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@@ -0,0 +1,378 @@
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+--- a/drivers/serial/amba-pl010.c
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++++ b/drivers/serial/amba-pl010.c
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+@@ -52,11 +52,10 @@
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+
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+ #include <asm/io.h>
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+
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+-#define UART_NR 8
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+-
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+ #define SERIAL_AMBA_MAJOR 204
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+ #define SERIAL_AMBA_MINOR 16
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+-#define SERIAL_AMBA_NR UART_NR
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++#define SERIAL_AMBA_NR CONFIG_SERIAL_AMBA_PL010_NUMPORTS
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++#define SERIAL_AMBA_NAME CONFIG_SERIAL_AMBA_PL010_PORTNAME
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+
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+ #define AMBA_ISR_PASS_LIMIT 256
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+
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+@@ -82,9 +81,9 @@
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+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
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+ unsigned int cr;
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+
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+- cr = readb(uap->port.membase + UART010_CR);
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++ cr = __raw_readl(uap->port.membase + UART010_CR);
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+ cr &= ~UART010_CR_TIE;
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+- writel(cr, uap->port.membase + UART010_CR);
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++ __raw_writel(cr, uap->port.membase + UART010_CR);
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+ }
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+
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+ static void pl010_start_tx(struct uart_port *port)
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+@@ -92,9 +91,9 @@
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+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
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+ unsigned int cr;
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+
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+- cr = readb(uap->port.membase + UART010_CR);
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++ cr = __raw_readl(uap->port.membase + UART010_CR);
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+ cr |= UART010_CR_TIE;
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+- writel(cr, uap->port.membase + UART010_CR);
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++ __raw_writel(cr, uap->port.membase + UART010_CR);
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+ }
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+
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+ static void pl010_stop_rx(struct uart_port *port)
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+@@ -102,9 +101,9 @@
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+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
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+ unsigned int cr;
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+
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+- cr = readb(uap->port.membase + UART010_CR);
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++ cr = __raw_readl(uap->port.membase + UART010_CR);
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+ cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
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+- writel(cr, uap->port.membase + UART010_CR);
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++ __raw_writel(cr, uap->port.membase + UART010_CR);
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+ }
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+
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+ static void pl010_enable_ms(struct uart_port *port)
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+@@ -112,9 +111,9 @@
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+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
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+ unsigned int cr;
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+
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+- cr = readb(uap->port.membase + UART010_CR);
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++ cr = __raw_readl(uap->port.membase + UART010_CR);
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+ cr |= UART010_CR_MSIE;
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+- writel(cr, uap->port.membase + UART010_CR);
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++ __raw_writel(cr, uap->port.membase + UART010_CR);
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+ }
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+
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+ static void pl010_rx_chars(struct uart_amba_port *uap)
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+@@ -122,9 +121,9 @@
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+ struct tty_struct *tty = uap->port.info->tty;
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+ unsigned int status, ch, flag, rsr, max_count = 256;
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+
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+- status = readb(uap->port.membase + UART01x_FR);
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++ status = __raw_readl(uap->port.membase + UART01x_FR);
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+ while (UART_RX_DATA(status) && max_count--) {
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+- ch = readb(uap->port.membase + UART01x_DR);
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++ ch = __raw_readl(uap->port.membase + UART01x_DR);
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+ flag = TTY_NORMAL;
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+
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+ uap->port.icount.rx++;
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+@@ -133,9 +132,9 @@
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+ * Note that the error handling code is
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+ * out of the main execution path
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+ */
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+- rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
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++ rsr = __raw_readl(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
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+ if (unlikely(rsr & UART01x_RSR_ANY)) {
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+- writel(0, uap->port.membase + UART01x_ECR);
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++ __raw_writel(0, uap->port.membase + UART01x_ECR);
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+
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+ if (rsr & UART01x_RSR_BE) {
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+ rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
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+@@ -165,7 +164,7 @@
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+ uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag);
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+
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+ ignore_char:
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+- status = readb(uap->port.membase + UART01x_FR);
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++ status = __raw_readl(uap->port.membase + UART01x_FR);
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+ }
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+ spin_unlock(&uap->port.lock);
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+ tty_flip_buffer_push(tty);
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+@@ -178,7 +177,7 @@
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+ int count;
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+
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+ if (uap->port.x_char) {
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+- writel(uap->port.x_char, uap->port.membase + UART01x_DR);
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++ __raw_writel(uap->port.x_char, uap->port.membase + UART01x_DR);
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+ uap->port.icount.tx++;
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+ uap->port.x_char = 0;
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+ return;
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+@@ -190,7 +189,7 @@
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+
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+ count = uap->port.fifosize >> 1;
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+ do {
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+- writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
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++ __raw_writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
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+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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+ uap->port.icount.tx++;
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+ if (uart_circ_empty(xmit))
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+@@ -208,9 +207,9 @@
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+ {
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+ unsigned int status, delta;
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+
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+- writel(0, uap->port.membase + UART010_ICR);
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++ __raw_writel(0, uap->port.membase + UART010_ICR);
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+
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+- status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
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++ status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
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+
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+ delta = status ^ uap->old_status;
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+ uap->old_status = status;
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+@@ -238,7 +237,7 @@
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+
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+ spin_lock(&uap->port.lock);
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+
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+- status = readb(uap->port.membase + UART010_IIR);
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++ status = __raw_readl(uap->port.membase + UART010_IIR);
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+ if (status) {
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+ do {
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+ if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
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+@@ -251,7 +250,7 @@
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+ if (pass_counter-- == 0)
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+ break;
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+
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+- status = readb(uap->port.membase + UART010_IIR);
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++ status = __raw_readl(uap->port.membase + UART010_IIR);
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+ } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
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+ UART010_IIR_TIS));
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+ handled = 1;
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+@@ -265,7 +264,7 @@
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+ static unsigned int pl010_tx_empty(struct uart_port *port)
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+ {
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+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
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+- unsigned int status = readb(uap->port.membase + UART01x_FR);
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++ unsigned int status = __raw_readl(uap->port.membase + UART01x_FR);
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+ return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
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+ }
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+
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+@@ -275,7 +274,7 @@
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+ unsigned int result = 0;
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+ unsigned int status;
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+
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+- status = readb(uap->port.membase + UART01x_FR);
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++ status = __raw_readl(uap->port.membase + UART01x_FR);
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+ if (status & UART01x_FR_DCD)
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+ result |= TIOCM_CAR;
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+ if (status & UART01x_FR_DSR)
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+@@ -301,12 +300,12 @@
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+ unsigned int lcr_h;
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+
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+ spin_lock_irqsave(&uap->port.lock, flags);
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+- lcr_h = readb(uap->port.membase + UART010_LCRH);
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++ lcr_h = __raw_readl(uap->port.membase + UART010_LCRH);
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+ if (break_state == -1)
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+ lcr_h |= UART01x_LCRH_BRK;
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+ else
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+ lcr_h &= ~UART01x_LCRH_BRK;
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+- writel(lcr_h, uap->port.membase + UART010_LCRH);
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++ __raw_writel(lcr_h, uap->port.membase + UART010_LCRH);
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+ spin_unlock_irqrestore(&uap->port.lock, flags);
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+ }
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+
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+@@ -334,12 +333,12 @@
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+ /*
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+ * initialise the old status of the modem signals
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+ */
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+- uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
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++ uap->old_status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
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+
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+ /*
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+ * Finally, enable interrupts
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+ */
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+- writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
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++ __raw_writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
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+ uap->port.membase + UART010_CR);
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+
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+ return 0;
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+@@ -362,10 +361,10 @@
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+ /*
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+ * disable all interrupts, disable the port
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+ */
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+- writel(0, uap->port.membase + UART010_CR);
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++ __raw_writel(0, uap->port.membase + UART010_CR);
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+
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+ /* disable break condition and fifos */
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+- writel(readb(uap->port.membase + UART010_LCRH) &
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++ __raw_writel(__raw_readl(uap->port.membase + UART010_LCRH) &
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+ ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
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+ uap->port.membase + UART010_LCRH);
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+
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+@@ -387,7 +386,7 @@
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+ /*
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+ * Ask the core to calculate the divisor for us.
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+ */
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+- baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
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++ baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
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+ quot = uart_get_divisor(port, baud);
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+
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+ switch (termios->c_cflag & CSIZE) {
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+@@ -450,25 +449,25 @@
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+ uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX;
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+
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+ /* first, disable everything */
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+- old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
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++ old_cr = __raw_readl(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
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+
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+ if (UART_ENABLE_MS(port, termios->c_cflag))
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+ old_cr |= UART010_CR_MSIE;
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+
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+- writel(0, uap->port.membase + UART010_CR);
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++ __raw_writel(0, uap->port.membase + UART010_CR);
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+
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+ /* Set baud rate */
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+ quot -= 1;
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+- writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
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+- writel(quot & 0xff, uap->port.membase + UART010_LCRL);
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++ __raw_writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
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++ __raw_writel(quot & 0xff, uap->port.membase + UART010_LCRL);
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+
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+ /*
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+ * ----------v----------v----------v----------v-----
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+ * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
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+ * ----------^----------^----------^----------^-----
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+ */
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+- writel(lcr_h, uap->port.membase + UART010_LCRH);
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+- writel(old_cr, uap->port.membase + UART010_CR);
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++ __raw_writel(lcr_h, uap->port.membase + UART010_LCRH);
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++ __raw_writel(old_cr, uap->port.membase + UART010_CR);
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+
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+ spin_unlock_irqrestore(&uap->port.lock, flags);
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+ }
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+@@ -540,7 +539,7 @@
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+ .verify_port = pl010_verify_port,
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+ };
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+
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+-static struct uart_amba_port *amba_ports[UART_NR];
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++static struct uart_amba_port *amba_ports[SERIAL_AMBA_NR];
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+
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+ #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
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+
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+@@ -550,10 +549,10 @@
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+ unsigned int status;
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+
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+ do {
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+- status = readb(uap->port.membase + UART01x_FR);
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++ status = __raw_readl(uap->port.membase + UART01x_FR);
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+ barrier();
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+ } while (!UART_TX_READY(status));
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+- writel(ch, uap->port.membase + UART01x_DR);
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++ __raw_writel(ch, uap->port.membase + UART01x_DR);
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+ }
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+
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+ static void
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+@@ -567,8 +566,8 @@
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+ /*
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+ * First save the CR then disable the interrupts
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+ */
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+- old_cr = readb(uap->port.membase + UART010_CR);
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+- writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
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++ old_cr = __raw_readl(uap->port.membase + UART010_CR);
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++ __raw_writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
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+
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+ uart_console_write(&uap->port, s, count, pl010_console_putchar);
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+
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+@@ -577,10 +576,10 @@
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+ * and restore the TCR
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+ */
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+ do {
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+- status = readb(uap->port.membase + UART01x_FR);
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++ status = __raw_readl(uap->port.membase + UART01x_FR);
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+ barrier();
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+ } while (status & UART01x_FR_BUSY);
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+- writel(old_cr, uap->port.membase + UART010_CR);
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++ __raw_writel(old_cr, uap->port.membase + UART010_CR);
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+
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+ clk_disable(uap->clk);
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+ }
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+@@ -589,9 +588,9 @@
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+ pl010_console_get_options(struct uart_amba_port *uap, int *baud,
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+ int *parity, int *bits)
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+ {
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+- if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
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++ if (__raw_readl(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
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+ unsigned int lcr_h, quot;
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+- lcr_h = readb(uap->port.membase + UART010_LCRH);
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++ lcr_h = __raw_readl(uap->port.membase + UART010_LCRH);
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+
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+ *parity = 'n';
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+ if (lcr_h & UART01x_LCRH_PEN) {
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+@@ -606,8 +605,8 @@
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+ else
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+ *bits = 8;
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+
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+- quot = readb(uap->port.membase + UART010_LCRL) |
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+- readb(uap->port.membase + UART010_LCRM) << 8;
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++ quot = __raw_readl(uap->port.membase + UART010_LCRL) |
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++ __raw_readl(uap->port.membase + UART010_LCRM) << 8;
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+ *baud = uap->port.uartclk / (16 * (quot + 1));
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+ }
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+ }
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+@@ -625,7 +624,7 @@
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+ * if so, search for the first available port that does have
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+ * console support.
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+ */
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+- if (co->index >= UART_NR)
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++ if (co->index >= SERIAL_AMBA_NR)
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+ co->index = 0;
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+ uap = amba_ports[co->index];
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+ if (!uap)
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+@@ -643,7 +642,7 @@
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+
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+ static struct uart_driver amba_reg;
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+ static struct console amba_console = {
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+- .name = "ttyAM",
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++ .name = SERIAL_AMBA_NAME,
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+ .write = pl010_console_write,
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+ .device = uart_console_device,
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+ .setup = pl010_console_setup,
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+@@ -659,11 +658,11 @@
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+
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+ static struct uart_driver amba_reg = {
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+ .owner = THIS_MODULE,
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+- .driver_name = "ttyAM",
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+- .dev_name = "ttyAM",
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++ .driver_name = SERIAL_AMBA_NAME,
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++ .dev_name = SERIAL_AMBA_NAME,
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+ .major = SERIAL_AMBA_MAJOR,
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+ .minor = SERIAL_AMBA_MINOR,
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+- .nr = UART_NR,
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++ .nr = SERIAL_AMBA_NR,
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+ .cons = AMBA_CONSOLE,
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+ };
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+
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+--- a/drivers/serial/Kconfig
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++++ b/drivers/serial/Kconfig
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+@@ -287,10 +287,25 @@
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+ help
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+ This selects the ARM(R) AMBA(R) PrimeCell PL010 UART. If you have
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+ an Integrator/AP or Integrator/PP2 platform, or if you have a
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+- Cirrus Logic EP93xx CPU, say Y or M here.
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++ Cirrus Logic EP93xx CPU or an Infineon ADM5120 SOC, say Y or M here.
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+
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+ If unsure, say N.
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+
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++config SERIAL_AMBA_PL010_NUMPORTS
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++ int "Maximum number of AMBA PL010 serial ports"
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++ depends on SERIAL_AMBA_PL010
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++ default "8"
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++ ---help---
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++ Set this to the number of serial ports you want the AMBA PL010 driver
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++ to support.
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++
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++config SERIAL_AMBA_PL010_PORTNAME
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++ string "Name of the AMBA PL010 serial ports"
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++ depends on SERIAL_AMBA_PL010
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++ default "ttyAM"
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++ ---help---
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++ ::: To be written :::
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++
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+ config SERIAL_AMBA_PL010_CONSOLE
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+ bool "Support for console on AMBA serial port"
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+ depends on SERIAL_AMBA_PL010=y
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