mediatek: switch to Linux version 6.1

Drop support for Linux 5.15 and switch to Linux 6.1.

Signed-off-by: Daniel Golle <[email protected]>

target/linux/mediatek/Makefile

@@ -8,8 +8,7 @@ BOARDNAME:=MediaTek Ralink ARM
 SUBTARGETS:=mt7622 mt7623 mt7629 filogic
 FEATURES:=dt-overlay emmc fpu gpio nand pci pcie rootfs-part separate_ramdisk squashfs usb
 
-KERNEL_PATCHVER:=5.15
-KERNEL_TESTING_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.1
 
 include $(INCLUDE_DIR)/target.mk
 DEFAULT_PACKAGES += \

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso

@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
-	fragment@0 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "2500base-x";
-			phy-handle = <&phy5>;
-		};
-	};
-
-	fragment@1 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <600>;
-			reset-post-delay-us = <20000>;
-
-			phy5: ethernet-phy@5 {
-				reg = <5>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				phy-mode = "2500base-x";
-			};
-		};
-	};
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso

@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
-	fragment@0 {
-		target = <&sw_p5>;
-		__overlay__ {
-			phy-mode = "2500base-x";
-			phy-handle = <&phy5>;
-			status = "okay";
-		};
-	};
-
-	fragment@1 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <600>;
-			reset-post-delay-us = <20000>;
-
-			phy5: ethernet-phy@5 {
-				reg = <5>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				phy-mode = "2500base-x";
-			};
-		};
-	};
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso

@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
-	fragment@0 {
-		target = <&spi0>;
-		__overlay__ {
-			status = "okay";
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			spi_nand: spi_nand@0 {
-				#address-cells = <1>;
-				#size-cells = <1>;
-				compatible = "spi-nand";
-				reg = <1>;
-				spi-max-frequency = <10000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "BL2";
-						reg = <0x00000 0x0100000>;
-						read-only;
-					};
-
-					partition@100000 {
-						label = "u-boot-env";
-						reg = <0x0100000 0x0080000>;
-					};
-
-					factory: partition@180000 {
-						label = "Factory";
-						reg = <0x180000 0x0200000>;
-					};
-
-					partition@380000 {
-						label = "FIP";
-						reg = <0x380000 0x0200000>;
-					};
-
-					partition@580000 {
-						label = "ubi";
-						reg = <0x580000 0x4000000>;
-					};
-				};
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&wifi>;
-		__overlay__ {
-			mediatek,mtd-eeprom = <&factory 0x0>;
-			status = "okay";
-		};
-	};
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts

@@ -1,188 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-/dts-v1/;
-#include "mt7981.dtsi"
-
-/ {
-	model = "MediaTek MT7981 RFB";
-	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory {
-		reg = <0 0x40000000 0 0x20000000>;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_5v: regulator-5v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-5V";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-		reset {
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
-		};
-		wps {
-			label = "wps";
-			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&eth {
-	status = "okay";
-
-	gmac0: mac@0 {
-		compatible = "mediatek,eth-mac";
-		reg = <0>;
-		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	gmac1: mac@1 {
-		compatible = "mediatek,eth-mac";
-		reg = <1>;
-		phy-mode = "gmii";
-		phy-handle = <&int_gbe_phy>;
-	};
-};
-
-&mdio_bus {
-	switch: switch@1f {
-		compatible = "mediatek,mt7531";
-		reg = <31>;
-		interrupt-controller;
-		#interrupt-cells = <1>;
-		interrupt-parent = <&pio>;
-		interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
-		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&crypto {
-	status = "okay";
-};
-
-&pio {
-	spi0_flash_pins: spi0-pins {
-		mux {
-			function = "spi";
-			groups = "spi0", "spi0_wp_hold";
-		};
-		conf-pu {
-			pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
-			drive-strength = <MTK_DRIVE_8mA>;
-			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
-		};
-		conf-pd {
-			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
-			drive-strength = <MTK_DRIVE_8mA>;
-			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
-		};
-	};
-
-};
-
-&spi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi0_flash_pins>;
-	cs-gpios = <0>, <0>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "disabled";
-};
-
-&switch {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-			label = "lan1";
-		};
-
-		port@1 {
-			reg = <1>;
-			label = "lan2";
-		};
-
-		port@2 {
-			reg = <2>;
-			label = "lan3";
-		};
-
-		port@3 {
-			reg = <3>;
-			label = "lan4";
-		};
-
-		sw_p5: port@5 {
-			reg = <5>;
-			label = "lan5";
-			status = "disabled";
-		};
-
-		port@6 {
-			reg = <6>;
-			ethernet = <&gmac0>;
-			phy-mode = "2500base-x";
-
-			fixed-link {
-				speed = <2500>;
-				full-duplex;
-				pause;
-			};
-		};
-	};
-};
-
-&xhci {
-	vusb33-supply = <&reg_3p3v>;
-	vbus-supply = <&reg_5v>;
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&usb_phy {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi

@@ -1,820 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (c) 2020 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- * Author: Jianhui Zhao <[email protected]>
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-#include <dt-bindings/reset/mt7986-resets.h>
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/mux/mux.h>
-
-/ {
-	compatible = "mediatek,mt7981";
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			enable-method = "psci";
-			reg = <0x0>;
-		};
-
-		cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			enable-method = "psci";
-			reg = <0x1>;
-		};
-	};
-
-	pwm: pwm@10048000 {
-		compatible = "mediatek,mt7981-pwm";
-		reg = <0 0x10048000 0 0x1000>;
-		#pwm-cells = <2>;
-		clocks = <&infracfg CLK_INFRA_PWM_STA>,
-			 <&infracfg CLK_INFRA_PWM_HCK>,
-			 <&infracfg CLK_INFRA_PWM1_CK>,
-			 <&infracfg CLK_INFRA_PWM2_CK>,
-			 <&infracfg CLK_INFRA_PWM3_CK>;
-		clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
-	};
-
-	fan: pwm-fan {
-		compatible = "pwm-fan";
-		/* cooling level (0, 1, 2, 3, 4, 5, 6, 7) : (0%/25%/37.5%/50%/62.5%/75%/87.5%/100% duty) */
-		cooling-levels = <0 63 95 127 159 191 223 255>;
-		#cooling-cells = <2>;
-		status = "disabled";
-	};
-
-	thermal-zones {
-		cpu_thermal: cpu-thermal {
-			polling-delay-passive = <1000>;
-			polling-delay = <1000>;
-			thermal-sensors = <&thermal 0>;
-			trips {
-				cpu_trip_active_highest: active-highest {
-					temperature = <70000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_high: active-high {
-					temperature = <60000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_med: active-med {
-					temperature = <50000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_low: active-low {
-					temperature = <45000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_lowest: active-lowest {
-					temperature = <40000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-			};
-
-			cooling-maps {
-				cpu-active-highest {
-					/* active: set fan to cooling level 7 */
-					cooling-device = <&fan 7 7>;
-					trip = <&cpu_trip_active_highest>;
-				};
-
-				cpu-active-high {
-					/* active: set fan to cooling level 5 */
-					cooling-device = <&fan 5 5>;
-					trip = <&cpu_trip_active_high>;
-				};
-
-				cpu-active-med {
-					/* active: set fan to cooling level 3 */
-					cooling-device = <&fan 3 3>;
-					trip = <&cpu_trip_active_med>;
-				};
-
-				cpu-active-low {
-					/* active: set fan to cooling level 2 */
-					cooling-device = <&fan 2 2>;
-					trip = <&cpu_trip_active_low>;
-				};
-
-				cpu-active-lowest {
-					/* active: set fan to cooling level 1 */
-					cooling-device = <&fan 1 1>;
-					trip = <&cpu_trip_active_lowest>;
-				};
-			};
-		};
-	};
-
-	thermal: thermal@1100c800 {
-		#thermal-sensor-cells = <1>;
-		compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
-		reg = <0 0x1100c800 0 0x800>;
-		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_THERM_CK>,
-			 <&infracfg CLK_INFRA_ADC_26M_CK>;
-		clock-names = "therm", "auxadc";
-		mediatek,auxadc = <&auxadc>;
-		mediatek,apmixedsys = <&apmixedsys>;
-		nvmem-cells = <&thermal_calibration>;
-		nvmem-cell-names = "calibration-data";
-	};
-
-	auxadc: adc@1100d000 {
-		compatible = "mediatek,mt7981-auxadc",
-			     "mediatek,mt7986-auxadc",
-			     "mediatek,mt7622-auxadc";
-		reg = <0 0x1100d000 0 0x1000>;
-		clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
-			 <&infracfg CLK_INFRA_ADC_FRC_CK>;
-		clock-names = "main", "32k";
-		#io-channel-cells = <1>;
-	};
-
-	wdma: wdma@15104800 {
-		compatible = "mediatek,wed-wdma";
-		reg = <0 0x15104800 0 0x400>,
-		      <0 0x15104c00 0 0x400>;
-	};
-
-	ap2woccif: ap2woccif@151a5000 {
-		compatible = "mediatek,ap2woccif";
-		reg = <0 0x151a5000 0 0x1000>,
-		      <0 0x151ad000 0 0x1000>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		/* 64 KiB reserved for ramoops/pstore */
-		ramoops@42ff0000 {
-			compatible = "ramoops";
-			reg = <0 0x42ff0000 0 0x10000>;
-			record-size = <0x1000>;
-		};
-
-		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
-		secmon_reserved: secmon@43000000 {
-			reg = <0 0x43000000 0 0x30000>;
-			no-map;
-		};
-
-		wmcpu_emi: wmcpu-reserved@47c80000 {
-			reg = <0 0x47c80000 0 0x100000>;
-			no-map;
-		};
-
-		wo_emi0: wo-emi@47d80000 {
-			reg = <0 0x47d80000 0 0x40000>;
-			no-map;
-		};
-
-		wo_data: wo-data@47dc0000 {
-			reg = <0 0x47dc0000 0 0x240000>;
-			no-map;
-		};
-	};
-
-	psci {
-		compatible  = "arm,psci-0.2";
-		method      = "smc";
-	};
-
-	trng {
-		compatible = "mediatek,mt7981-rng";
-	};
-
-	clk40m: oscillator@0 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <40000000>;
-		clock-output-names = "clkxtal";
-	};
-
-	infracfg: infracfg@10001000 {
-		compatible = "mediatek,mt7981-infracfg", "syscon";
-		reg = <0 0x10001000 0 0x1000>;
-		#clock-cells = <1>;
-	};
-
-	topckgen: topckgen@1001B000 {
-		compatible = "mediatek,mt7981-topckgen", "syscon";
-		reg = <0 0x1001B000 0 0x1000>;
-		#clock-cells = <1>;
-	};
-
-	apmixedsys: apmixedsys@1001E000 {
-		compatible = "mediatek,mt7981-apmixedsys", "mediatek,mt7986-apmixedsys", "syscon";
-		reg = <0 0x1001E000 0 0x1000>;
-		#clock-cells = <1>;
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupt-parent = <&gic>;
-		clock-frequency = <13000000>;
-		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-
-	};
-
-	watchdog: watchdog@1001c000 {
-		compatible = "mediatek,mt7986-wdt",
-			     "mediatek,mt6589-wdt";
-		reg = <0 0x1001c000 0 0x1000>;
-		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-		#reset-cells = <1>;
-		status = "disabled";
-	};
-
-	gic: interrupt-controller@c000000 {
-		compatible = "arm,gic-v3";
-		#interrupt-cells = <3>;
-		interrupt-parent = <&gic>;
-		interrupt-controller;
-		reg = <0 0x0c000000 0 0x40000>,  /* GICD */
-		      <0 0x0c080000 0 0x200000>; /* GICR */
-
-		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	uart0: serial@11002000 {
-		compatible = "mediatek,mt6577-uart";
-		reg = <0 0x11002000 0 0x400>;
-		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_UART0_SEL>,
-			<&infracfg CLK_INFRA_UART0_CK>;
-		clock-names = "baud", "bus";
-		assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-				  <&infracfg CLK_INFRA_UART0_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
-					 <&topckgen CLK_TOP_UART_SEL>;
-		pinctrl-0 = <&uart0_pins>;
-		pinctrl-names = "default";
-		status = "disabled";
-	};
-
-	uart1: serial@11003000 {
-		compatible = "mediatek,mt6577-uart";
-		reg = <0 0x11003000 0 0x400>;
-		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_UART1_SEL>,
-			<&infracfg CLK_INFRA_UART1_CK>;
-		clock-names = "baud", "bus";
-		assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-				  <&infracfg CLK_INFRA_UART1_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
-					 <&topckgen CLK_TOP_UART_SEL>;
-		status = "disabled";
-	};
-
-	uart2: serial@11004000 {
-		compatible = "mediatek,mt6577-uart";
-		reg = <0 0x11004000 0 0x400>;
-		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_UART2_SEL>,
-			<&infracfg CLK_INFRA_UART2_CK>;
-		clock-names = "baud", "bus";
-		assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-				  <&infracfg CLK_INFRA_UART2_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
-					 <&topckgen CLK_TOP_UART_SEL>;
-		status = "disabled";
-	};
-
-	i2c0: i2c@11007000 {
-		compatible = "mediatek,mt7981-i2c";
-		reg = <0 0x11007000 0 0x1000>,
-		      <0 0x10217080 0 0x80>;
-		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-		clock-div = <1>;
-		clocks = <&infracfg CLK_INFRA_I2C0_CK>,
-			 <&infracfg CLK_INFRA_AP_DMA_CK>,
-			 <&infracfg CLK_INFRA_I2C_MCK_CK>,
-			 <&infracfg CLK_INFRA_I2C_PCK_CK>;
-		clock-names = "main", "dma", "arb", "pmic";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	pcie: pcie@11280000 {
-		compatible = "mediatek,mt7981-pcie",
-			     "mediatek,mt7986-pcie";
-		device_type = "pci";
-		reg = <0 0x11280000 0 0x4000>;
-		reg-names = "pcie-mac";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-		bus-range = <0x00 0xff>;
-		ranges = <0x82000000 0 0x20000000
-			  0x0 0x20000000 0 0x10000000>;
-		status = "disabled";
-
-		clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
-			 <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
-			 <&infracfg CLK_INFRA_IPCIER_CK>,
-			 <&infracfg CLK_INFRA_IPCIEB_CK>;
-
-		phys = <&u3port0 PHY_TYPE_PCIE>;
-		phy-names = "pcie-phy";
-
-		#interrupt-cells = <1>;
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0 0 0 1 &pcie_intc 0>,
-				<0 0 0 2 &pcie_intc 1>,
-				<0 0 0 3 &pcie_intc 2>,
-				<0 0 0 4 &pcie_intc 3>;
-		pcie_intc: interrupt-controller {
-			interrupt-controller;
-			#address-cells = <0>;
-			#interrupt-cells = <1>;
-		};
-	};
-
-	crypto: crypto@10320000 {
-		compatible = "inside-secure,safexcel-eip97";
-		reg = <0 0x10320000 0 0x40000>;
-		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "ring0", "ring1", "ring2", "ring3";
-		clocks = <&topckgen CLK_TOP_EIP97B>;
-		clock-names = "top_eip97_ck";
-		assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
-	};
-
-	pio: pinctrl@11d00000 {
-		compatible = "mediatek,mt7981-pinctrl";
-		reg = <0 0x11d00000 0 0x1000>,
-		      <0 0x11c00000 0 0x1000>,
-		      <0 0x11c10000 0 0x1000>,
-		      <0 0x11d20000 0 0x1000>,
-		      <0 0x11e00000 0 0x1000>,
-		      <0 0x11e20000 0 0x1000>,
-		      <0 0x11f00000 0 0x1000>,
-		      <0 0x11f10000 0 0x1000>,
-		      <0 0x1000b000 0 0x1000>;
-		reg-names = "gpio", "iocfg_rt", "iocfg_rm",
-			    "iocfg_rb", "iocfg_lb", "iocfg_bl",
-			    "iocfg_tm", "iocfg_tl", "eint";
-		gpio-controller;
-		#gpio-cells = <2>;
-		gpio-ranges = <&pio 0 0 56>;
-		interrupt-controller;
-		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&gic>;
-		#interrupt-cells = <2>;
-
-		mdio_pins: mdc-mdio-pins {
-			mux {
-				function = "eth";
-				groups = "smi_mdc_mdio";
-			};
-		};
-
-		uart0_pins: uart0-pins {
-			mux {
-				function = "uart";
-				groups = "uart0";
-			};
-		};
-
-		wifi_dbdc_pins: wifi-dbdc-pins {
-			mux {
-				function = "eth";
-				groups = "wf0_mode1";
-			};
-			conf {
-				pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
-				       "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
-				       "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
-				       "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
-				       "WF_CBA_RESETB", "WF_DIG_RESETB";
-				drive-strength = <4>;
-			};
-		};
-
-		gbe_led0_pins: gbe-led0-pins {
-			mux {
-				function = "led";
-				groups = "gbe_led0";
-			};
-		};
-
-		gbe_led1_pins: gbe-led1-pins {
-			mux {
-				function = "led";
-				groups = "gbe_led1";
-			};
-		};
-	};
-
-	ethsys: syscon@15000000 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "mediatek,mt7981-ethsys",
-			     "mediatek,mt7986-ethsys",
-			     "syscon";
-		reg = <0 0x15000000 0 0x1000>;
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-	};
-
-	wed: wed@15010000 {
-		compatible = "mediatek,mt7981-wed",
-			     "mediatek,mt7986-wed",
-			     "syscon";
-		reg = <0 0x15010000 0 0x1000>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
-		memory-region = <&wo_emi0>, <&wo_data>;
-		memory-region-names = "wo-emi", "wo-data";
-		mediatek,wo-ccif = <&wo_ccif0>;
-		mediatek,wo-ilm = <&wo_ilm0>;
-		mediatek,wo-dlm = <&wo_dlm0>;
-		mediatek,wo-cpuboot = <&wo_cpuboot>;
-	};
-
-	eth: ethernet@15100000 {
-		compatible = "mediatek,mt7981-eth";
-		reg = <0 0x15100000 0 0x80000>;
-		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&ethsys CLK_ETH_FE_EN>,
-			<&ethsys CLK_ETH_GP2_EN>,
-			<&ethsys CLK_ETH_GP1_EN>,
-			<&ethsys CLK_ETH_WOCPU0_EN>,
-			<&sgmiisys0 CLK_SGM0_TX_EN>,
-			<&sgmiisys0 CLK_SGM0_RX_EN>,
-			<&sgmiisys0 CLK_SGM0_CK0_EN>,
-			<&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
-			<&sgmiisys1 CLK_SGM1_TX_EN>,
-			<&sgmiisys1 CLK_SGM1_RX_EN>,
-			<&sgmiisys1 CLK_SGM1_CK1_EN>,
-			<&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
-			<&topckgen CLK_TOP_SGM_REG>,
-			<&topckgen CLK_TOP_NETSYS_SEL>,
-			<&topckgen CLK_TOP_NETSYS_500M_SEL>;
-		clock-names = "fe", "gp2", "gp1", "wocpu0",
-					"sgmii_tx250m", "sgmii_rx250m",
-					"sgmii_cdr_ref", "sgmii_cdr_fb",
-					"sgmii2_tx250m", "sgmii2_rx250m",
-					"sgmii2_cdr_ref", "sgmii2_cdr_fb",
-					"sgmii_ck", "netsys0", "netsys1";
-		assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
-				  <&topckgen CLK_TOP_SGM_325M_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
-					 <&topckgen CLK_TOP_CB_SGM_325M>;
-		mediatek,ethsys = <&ethsys>;
-		mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
-		mediatek,infracfg = <&topmisc>;
-		mediatek,wed = <&wed>;
-		#reset-cells = <1>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-
-		mdio_bus: mdio-bus {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			int_gbe_phy: ethernet-phy@0 {
-				reg = <0>;
-				compatible = "ethernet-phy-ieee802.3-c22";
-				phy-mode = "gmii";
-				phy-is-integrated;
-				nvmem-cells = <&phy_calibration>;
-				nvmem-cell-names = "phy-cal-data";
-
-				leds {
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					int_gbe_phy_led0: int-gbe-phy-led0@0 {
-						reg = <0>;
-						function = LED_FUNCTION_LAN;
-						status = "disabled";
-					};
-
-					int_gbe_phy_led1: int-gbe-phy-led1@1 {
-						reg = <1>;
-						function = LED_FUNCTION_LAN;
-						status = "disabled";
-					};
-				};
-			};
-		};
-	};
-
-	wo_dlm0: syscon@151e8000 {
-		compatible = "mediatek,mt7986-wo-dlm", "syscon";
-		reg = <0 0x151e8000 0 0x2000>;
-	};
-
-	wo_ilm0: syscon@151e0000 {
-		compatible = "mediatek,mt7986-wo-ilm", "syscon";
-		reg = <0 0x151e0000 0 0x8000>;
-	};
-
-	wo_cpuboot: syscon@15194000 {
-		compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
-		reg = <0 0x15194000 0 0x1000>;
-	};
-
-	wo_ccif0: syscon@151a5000 {
-		compatible = "mediatek,mt7986-wo-ccif", "syscon";
-		reg = <0 0x151a5000 0 0x1000>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	sgmiisys0: syscon@10060000 {
-		compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon";
-		reg = <0 0x10060000 0 0x1000>;
-		mediatek,pnswap;
-		#clock-cells = <1>;
-	};
-
-	sgmiisys1: syscon@10070000 {
-		compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon";
-		reg = <0 0x10070000 0 0x1000>;
-		#clock-cells = <1>;
-	};
-
-	topmisc: topmisc@11d10000 {
-		compatible = "mediatek,mt7981-topmisc", "syscon";
-		reg = <0 0x11d10000 0 0x10000>;
-		#clock-cells = <1>;
-	};
-
-	snand: snfi@11005000 {
-		compatible = "mediatek,mt7986-snand";
-		reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
-		reg-names = "nfi", "ecc";
-		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
-			 <&infracfg CLK_INFRA_NFI1_CK>,
-			 <&infracfg CLK_INFRA_NFI_HCK_CK>;
-		clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
-		assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
-				  <&topckgen CLK_TOP_NFI1X_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
-					 <&topckgen CLK_TOP_CB_M_D8>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	mmc0: mmc@11230000 {
-		compatible = "mediatek,mt7986-mmc",
-					"mediatek,mt7981-mmc";
-		reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
-		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_MSDC_CK>,
-			 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
-			 <&infracfg CLK_INFRA_MSDC_66M_CK>,
-			 <&infracfg CLK_INFRA_MSDC_133M_CK>;
-		assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
-				  <&topckgen CLK_TOP_EMMC_400M_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
-					 <&topckgen CLK_TOP_CB_NET2_D2>;
-		clock-names = "source", "hclk", "axi_cg", "ahb_cg";
-		status = "disabled";
-	};
-
-	wed_pcie: wed_pcie@10003000 {
-		compatible = "mediatek,wed_pcie";
-		reg = <0 0x10003000 0 0x10>;
-	};
-
-	spi0: spi@1100a000 {
-		compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0 0x1100a000 0 0x100>;
-		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&topckgen CLK_TOP_CB_M_D2>,
-			 <&topckgen CLK_TOP_SPI_SEL>,
-			 <&infracfg CLK_INFRA_SPI0_CK>,
-			 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
-
-		clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-		status = "disabled";
-	};
-
-	spi1: spi@1100b000 {
-		compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0 0x1100b000 0 0x100>;
-		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&topckgen CLK_TOP_CB_M_D2>,
-			 <&topckgen CLK_TOP_SPIM_MST_SEL>,
-			 <&infracfg CLK_INFRA_SPI1_CK>,
-			 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
-		clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-		status = "disabled";
-	};
-
-	spi2: spi@11009000 {
-		compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0 0x11009000 0 0x100>;
-		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&topckgen CLK_TOP_CB_M_D2>,
-			 <&topckgen CLK_TOP_SPI_SEL>,
-			 <&infracfg CLK_INFRA_SPI2_CK>,
-			 <&infracfg CLK_INFRA_SPI2_HCK_CK>;
-		clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-		status = "disabled";
-	};
-
-	consys: consys@10000000 {
-		compatible = "mediatek,mt7981-consys";
-		reg = <0 0x10000000 0 0x8600000>;
-		memory-region = <&wmcpu_emi>;
-	};
-
-	xhci: usb@11200000 {
-		compatible = "mediatek,mt7986-xhci",
-			     "mediatek,mtk-xhci";
-		reg = <0 0x11200000 0 0x2e00>,
-		      <0 0x11203e00 0 0x0100>;
-		reg-names = "mac", "ippc";
-		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
-			 <&infracfg CLK_INFRA_IUSB_CK>,
-			 <&infracfg CLK_INFRA_IUSB_133_CK>,
-			 <&infracfg CLK_INFRA_IUSB_66M_CK>,
-			 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
-		clock-names = "sys_ck",
-			      "ref_ck",
-			      "mcu_ck",
-			      "dma_ck",
-			      "xhci_ck";
-		phys = <&u2port0 PHY_TYPE_USB2>,
-		       <&u3port0 PHY_TYPE_USB3>;
-		vusb33-supply = <&reg_3p3v>;
-		status = "disabled";
-	};
-
-	usb_phy: usb-phy@11e10000 {
-		compatible = "mediatek,mt7981",
-			     "mediatek,generic-tphy-v2";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0 0x11e10000 0x1700>;
-		status = "disabled";
-
-		u2port0: usb-phy@0 {
-			reg = <0x0 0x700>;
-			clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
-			clock-names = "ref";
-			#phy-cells = <1>;
-		};
-
-		u3port0: usb-phy@700 {
-			reg = <0x700 0x900>;
-			clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
-			clock-names = "ref";
-			#phy-cells = <1>;
-			mediatek,syscon-type = <&topmisc 0x218 0>;
-			status = "okay";
-		};
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	efuse: efuse@11f20000 {
-		compatible = "mediatek,mt7981-efuse",
-			     "mediatek,efuse";
-		reg = <0 0x11f20000 0 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		status = "okay";
-
-		thermal_calibration: thermal-calib@274 {
-			reg = <0x274 0xc>;
-		};
-
-		phy_calibration: phy-calib@8dc {
-			reg = <0x8dc 0x10>;
-		};
-
-		comb_rx_imp_p0: usb3-rx-imp@8c8 {
-			reg = <0x8c8 1>;
-			bits = <0 5>;
-		};
-
-		comb_tx_imp_p0: usb3-tx-imp@8c8 {
-			reg = <0x8c8 2>;
-			bits = <5 5>;
-		};
-
-		comb_intr_p0: usb3-intr@8c9 {
-			reg = <0x8c9 1>;
-			bits = <2 6>;
-		};
-	};
-
-	afe: audio-controller@11210000 {
-		compatible = "mediatek,mt79xx-audio";
-		reg = <0 0x11210000 0 0x9000>;
-		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
-			 <&infracfg CLK_INFRA_AUD_26M_CK>,
-			 <&infracfg CLK_INFRA_AUD_L_CK>,
-			 <&infracfg CLK_INFRA_AUD_AUD_CK>,
-			 <&infracfg CLK_INFRA_AUD_EG2_CK>,
-			 <&topckgen CLK_TOP_AUD_SEL>;
-		clock-names = "aud_bus_ck",
-			      "aud_26m_ck",
-			      "aud_l_ck",
-			      "aud_aud_ck",
-			      "aud_eg2_ck",
-			      "aud_sel";
-		assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
-				  <&topckgen CLK_TOP_A1SYS_SEL>,
-				  <&topckgen CLK_TOP_AUD_L_SEL>,
-				  <&topckgen CLK_TOP_A_TUNER_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
-					 <&topckgen CLK_TOP_APLL2_D4>,
-					 <&topckgen CLK_TOP_CB_APLL2_196M>,
-					 <&topckgen CLK_TOP_APLL2_D4>;
-		status = "disabled";
-	};
-
-	ice: ice_debug {
-		compatible = "mediatek,mt7981-ice_debug",
-			   "mediatek,mt2701-ice_debug";
-		clocks = <&infracfg CLK_INFRA_DBG_CK>;
-		clock-names = "ice_dbg";
-	};
-
-	wifi: wifi@18000000 {
-		compatible = "mediatek,mt7981-wmac";
-		resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
-		reset-names = "consys";
-		pinctrl-0 = <&wifi_dbdc_pins>;
-		pinctrl-names = "dbdc";
-		clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
-			 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
-		clock-names = "mcu", "ap2conn";
-		reg = <0 0x18000000 0 0x1000000>,
-		      <0 0x10003000 0 0x1000>,
-		      <0 0x11d10000 0 0x1000>;
-		interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
-		memory-region = <&wmcpu_emi>;
-		status = "disabled";
-	};
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso

@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
-	fragment@0 {
-		target-path = "/soc/mmc@11230000";
-		__overlay__ {
-			bus-width = <8>;
-			max-frequency = <200000000>;
-			cap-mmc-highspeed;
-			mmc-hs200-1_8v;
-			mmc-hs400-1_8v;
-			hs400-ds-delay = <0x14014>;
-			non-removable;
-			no-sd;
-			no-sdio;
-			status = "okay";
-		};
-	};
-};
-

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso

@@ -1,55 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/*
- * Authors: Daniel Golle <[email protected]>
- *          Frank Wunderlich <[email protected]>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
-	fragment@0 {
-		target-path = "/soc/spi@1100a000";
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			spi_nand: spi_nand@0 {
-				compatible = "spi-nand";
-				reg = <0>;
-				spi-max-frequency = <10000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "bl2";
-						reg = <0x0 0x80000>;
-						read-only;
-					};
-
-					partition@80000 {
-						label = "reserved";
-						reg = <0x80000 0x300000>;
-					};
-
-					partition@380000 {
-						label = "fip";
-						reg = <0x380000 0x200000>;
-						read-only;
-					};
-
-					partition@580000 {
-						label = "ubi";
-						reg = <0x580000 0x7a80000>;
-					};
-				};
-			};
-		};
-	};
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso

@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/*
- * Authors: Daniel Golle <[email protected]>
- *          Frank Wunderlich <[email protected]>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
-	fragment@0 {
-		target-path = "/soc/spi@1100a000";
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			flash@0 {
-				compatible = "jedec,spi-nor";
-				reg = <0>;
-				spi-max-frequency = <10000000>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "bl2";
-						reg = <0x0 0x40000>;
-						read-only;
-					};
-
-					partition@40000 {
-						label = "u-boot-env";
-						reg = <0x40000 0x40000>;
-					};
-
-					partition@80000 {
-						label = "reserved2";
-						reg = <0x80000 0x80000>;
-					};
-
-					partition@100000 {
-						label = "fip";
-						reg = <0x100000 0x80000>;
-						read-only;
-					};
-
-					partition@180000 {
-						label = "recovery";
-						reg = <0x180000 0xa80000>;
-					};
-
-					partition@c00000 {
-						label = "fit";
-						reg = <0xc00000 0x1400000>;
-					};
-				};
-			};
-		};
-	};
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso

@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
-	fragment@0 {
-		target-path = "/soc/mmc@11230000";
-		__overlay__ {
-			bus-width = <4>;
-			max-frequency = <52000000>;
-			cap-sd-highspeed;
-			status = "okay";
-		};
-	};
-};
-

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts

@@ -1,501 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Authors: Sam.Shih <[email protected]>
- *          Frank Wunderlich <[email protected]>
- *          Daniel Golle <[email protected]>
- */
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/mt65xx.h>
-
-#include "mt7986a.dtsi"
-
-/ {
-	model = "Bananapi BPI-R3";
-	chassis-type = "embedded";
-	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
-	aliases {
-		serial0 = &uart0;
-		ethernet0 = &gmac0;
-		ethernet1 = &gmac1;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	dcin: regulator-12vd {
-		compatible = "regulator-fixed";
-		regulator-name = "12vd";
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	fan: pwm-fan {
-		compatible = "pwm-fan";
-		#cooling-cells = <2>;
-		/* cooling level (0, 1, 2) - pwm inverted */
-		cooling-levels = <255 96 0>;
-		pwms = <&pwm 0 10000 0>;
-		status = "okay";
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-
-		reset-key {
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&pio 9 GPIO_ACTIVE_LOW>;
-		};
-
-		wps-key {
-			label = "wps";
-			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	/* i2c of the left SFP cage (wan) */
-	i2c_sfp1: i2c-gpio-0 {
-		compatible = "i2c-gpio";
-		sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		i2c-gpio,delay-us = <2>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	/* i2c of the right SFP cage (lan) */
-	i2c_sfp2: i2c-gpio-1 {
-		compatible = "i2c-gpio";
-		sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		i2c-gpio,delay-us = <2>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		green_led: led-0 {
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_POWER;
-			gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		blue_led: led-1 {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_STATUS;
-			gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-	};
-
-	reg_1p8v: regulator-1p8v {
-		compatible = "regulator-fixed";
-		regulator-name = "1.8vd";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-boot-on;
-		regulator-always-on;
-		vin-supply = <&dcin>;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "3.3vd";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-		vin-supply = <&dcin>;
-	};
-
-	/* left SFP cage (wan) */
-	sfp1: sfp-1 {
-		compatible = "sff,sfp";
-		i2c-bus = <&i2c_sfp1>;
-		los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
-		tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
-		maximum-power-milliwatt = <3000>;
-	};
-
-	/* right SFP cage (lan) */
-	sfp2: sfp-2 {
-		compatible = "sff,sfp";
-		i2c-bus = <&i2c_sfp2>;
-		los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
-		tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
-		maximum-power-milliwatt = <3000>;
-	};
-};
-
-&cpu_thermal {
-	cooling-maps {
-		cpu-active-high {
-			/* active: set fan to cooling level 2 */
-			cooling-device = <&fan 2 2>;
-			trip = <&cpu_trip_active_high>;
-		};
-
-		cpu-active-med {
-			/* active: set fan to cooling level 1 */
-			cooling-device = <&fan 1 1>;
-			trip = <&cpu_trip_active_med>;
-		};
-
-		cpu-active-low {
-			/* active: set fan to cooling level 0 */
-			cooling-device = <&fan 0 0>;
-			trip = <&cpu_trip_active_low>;
-		};
-	};
-};
-
-&crypto {
-	status = "okay";
-};
-
-&eth {
-	status = "okay";
-
-	gmac0: mac@0 {
-		compatible = "mediatek,eth-mac";
-		reg = <0>;
-		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	gmac1: mac@1 {
-		compatible = "mediatek,eth-mac";
-		reg = <1>;
-		phy-mode = "2500base-x";
-		sfp = <&sfp1>;
-		managed = "in-band-status";
-	};
-
-	mdio: mdio-bus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-};
-
-&mdio {
-	switch: switch@1f {
-		compatible = "mediatek,mt7531";
-		reg = <31>;
-		interrupt-controller;
-		#interrupt-cells = <1>;
-		interrupt-parent = <&pio>;
-		interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
-		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&mmc0 {
-	pinctrl-names = "default", "state_uhs";
-	pinctrl-0 = <&mmc0_pins_default>;
-	pinctrl-1 = <&mmc0_pins_uhs>;
-	vmmc-supply = <&reg_3p3v>;
-	vqmmc-supply = <&reg_1p8v>;
-};
-
-&i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c_pins>;
-	status = "okay";
-};
-
-&pcie {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie_pins>;
-	status = "okay";
-};
-
-&pcie_phy {
-	status = "okay";
-};
-
-&pio {
-	i2c_pins: i2c-pins {
-		mux {
-			function = "i2c";
-			groups = "i2c";
-		};
-	};
-
-	mmc0_pins_default: mmc0-pins {
-		mux {
-			function = "emmc";
-			groups = "emmc_51";
-		};
-		conf-cmd-dat {
-			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-			input-enable;
-			drive-strength = <4>;
-			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-		};
-		conf-clk {
-			pins = "EMMC_CK";
-			drive-strength = <6>;
-			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-		};
-		conf-ds {
-			pins = "EMMC_DSL";
-			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-		};
-		conf-rst {
-			pins = "EMMC_RSTB";
-			drive-strength = <4>;
-			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-		};
-	};
-
-	mmc0_pins_uhs: mmc0-uhs-pins {
-		mux {
-			function = "emmc";
-			groups = "emmc_51";
-		};
-		conf-cmd-dat {
-			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-			input-enable;
-			drive-strength = <4>;
-			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-		};
-		conf-clk {
-			pins = "EMMC_CK";
-			drive-strength = <6>;
-			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-		};
-		conf-ds {
-			pins = "EMMC_DSL";
-			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-		};
-		conf-rst {
-			pins = "EMMC_RSTB";
-			drive-strength = <4>;
-			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-		};
-	};
-
-	pcie_pins: pcie-pins {
-		mux {
-			function = "pcie";
-			groups = "pcie_clk", "pcie_pereset";
-		};
-	};
-
-	pwm_pins: pwm-pins {
-		mux {
-			function = "pwm";
-			groups = "pwm0", "pwm1_0";
-		};
-	};
-
-	spi_flash_pins: spi-flash-pins {
-		mux {
-			function = "spi";
-			groups = "spi0", "spi0_wp_hold";
-		};
-	};
-
-	spic_pins: spic-pins {
-		mux {
-			function = "spi";
-			groups = "spi1_0";
-		};
-	};
-
-	uart1_pins: uart1-pins {
-		mux {
-			function = "uart";
-			groups = "uart1_rx_tx";
-		};
-	};
-
-	uart2_pins: uart2-pins {
-		mux {
-			function = "uart";
-			groups = "uart2_0_rx_tx";
-		};
-	};
-
-	wf_2g_5g_pins: wf-2g-5g-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_2g", "wf_5g";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-
-	wf_dbdc_pins: wf-dbdc-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_dbdc";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-
-	wf_led_pins: wf-led-pins {
-		mux {
-			function = "led";
-			groups = "wifi_led";
-		};
-	};
-};
-
-&pwm {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pwm_pins>;
-	status = "okay";
-};
-
-&spi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi_flash_pins>;
-	status = "okay";
-};
-
-&spi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spic_pins>;
-	status = "okay";
-};
-
-&ssusb {
-	status = "okay";
-};
-
-&switch {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-			label = "wan";
-		};
-
-		port@1 {
-			reg = <1>;
-			label = "lan0";
-		};
-
-		port@2 {
-			reg = <2>;
-			label = "lan1";
-		};
-
-		port@3 {
-			reg = <3>;
-			label = "lan2";
-		};
-
-		port@4 {
-			reg = <4>;
-			label = "lan3";
-		};
-
-		port5: port@5 {
-			reg = <5>;
-			label = "lan4";
-			phy-mode = "2500base-x";
-			sfp = <&sfp2>;
-			managed = "in-band-status";
-		};
-
-		port@6 {
-			reg = <6>;
-			label = "cpu";
-			ethernet = <&gmac0>;
-			phy-mode = "2500base-x";
-
-			fixed-link {
-				speed = <2500>;
-				full-duplex;
-				pause;
-			};
-		};
-	};
-};
-
-&trng {
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_pins>;
-	status = "okay";
-};
-
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_pins>;
-	status = "okay";
-};
-
-&usb_phy {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&wifi {
-	status = "okay";
-	pinctrl-names = "default", "dbdc";
-	pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
-	pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
-
-	led {
-		led-active-low;
-	};
-};
-

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts

@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-
-#include "mt7986a-rfb.dtsi"
-
-/ {
-	compatible = "mediatek,mt7986a-rfb-snand";
-};
-
-&spi0 {
-	status = "okay";
-
-	spi_nand: spi_nand@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "spi-nand";
-		reg = <1>;
-		spi-max-frequency = <10000000>;
-		spi-tx-bus-width = <4>;
-		spi-rx-bus-width = <4>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			partition@0 {
-				label = "BL2";
-				reg = <0x00000 0x0100000>;
-				read-only;
-			};
-			partition@100000 {
-				label = "u-boot-env";
-				reg = <0x0100000 0x0080000>;
-			};
-			factory: partition@180000 {
-				label = "Factory";
-				reg = <0x180000 0x0200000>;
-			};
-			partition@380000 {
-				label = "FIP";
-				reg = <0x380000 0x0200000>;
-			};
-			partition@580000 {
-				label = "ubi";
-				reg = <0x580000 0x4000000>;
-			};
-		};
-	};
-};
-
-&wifi {
-	mediatek,mtd-eeprom = <&factory 0>;
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts

@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-
-#include "mt7986a-rfb.dtsi"
-
-/ {
-	compatible = "mediatek,mt7986a-rfb-snor";
-};
-
-&spi0 {
-	status = "okay";
-
-	spi_nor: spi_nor@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <52000000>;
-		spi-tx-bus-width = <4>;
-		spi-rx-bus-width = <4>;
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@00000 {
-				label = "BL2";
-				reg = <0x00000 0x0040000>;
-			};
-			partition@40000 {
-				label = "u-boot-env";
-				reg = <0x40000 0x0010000>;
-			};
-			factory: partition@50000 {
-				label = "Factory";
-				reg = <0x50000 0x00B0000>;
-			};
-			partition@100000 {
-				label = "FIP";
-				reg = <0x100000 0x0080000>;
-			};
-			partition@180000 {
-				label = "firmware";
-				reg = <0x180000 0xE00000>;
-			};
-		};
-	};
-};
-
-&wifi {
-	mediatek,mtd-eeprom = <&factory 0>;
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi

@@ -1,389 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-/dts-v1/;
-#include "mt7986a.dtsi"
-
-/ {
-	model = "MediaTek MT7986a RFB";
-	compatible = "mediatek,mt7986a-rfb";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory {
-		reg = <0 0x40000000 0 0x40000000>;
-	};
-
-	reg_1p8v: regulator-1p8v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-1.8V";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_5v: regulator-5v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-5V";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-};
-
-&eth {
-	status = "okay";
-
-	gmac0: mac@0 {
-		compatible = "mediatek,eth-mac";
-		reg = <0>;
-		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	gmac1: mac@1 {
-		compatible = "mediatek,eth-mac";
-		reg = <1>;
-		phy-mode = "2500base-x";
-	};
-
-	mdio: mdio-bus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-};
-
-&wifi {
-	status = "okay";
-	pinctrl-names = "default", "dbdc";
-	pinctrl-0 = <&wf_2g_5g_pins>;
-	pinctrl-1 = <&wf_dbdc_pins>;
-};
-
-&mdio {
-	phy5: phy@5 {
-		compatible = "ethernet-phy-id67c9.de0a";
-		reg = <5>;
-
-		reset-gpios = <&pio 6 1>;
-		reset-deassert-us = <20000>;
-	};
-
-	phy6: phy@6 {
-		compatible = "ethernet-phy-id67c9.de0a";
-		reg = <6>;
-	};
-
-	switch: switch@1f {
-		compatible = "mediatek,mt7531";
-		reg = <31>;
-		reset-gpios = <&pio 5 0>;
-	};
-};
-
-&crypto {
-	status = "okay";
-};
-
-&mmc0 {
-	pinctrl-names = "default", "state_uhs";
-	pinctrl-0 = <&mmc0_pins_default>;
-	pinctrl-1 = <&mmc0_pins_uhs>;
-	bus-width = <8>;
-	max-frequency = <200000000>;
-	cap-mmc-highspeed;
-	mmc-hs200-1_8v;
-	mmc-hs400-1_8v;
-	hs400-ds-delay = <0x14014>;
-	vmmc-supply = <&reg_3p3v>;
-	vqmmc-supply = <&reg_1p8v>;
-	non-removable;
-	no-sd;
-	no-sdio;
-	status = "okay";
-};
-
-&pcie {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie_pins>;
-	status = "okay";
-};
-
-&pcie_phy {
-	status = "okay";
-};
-
-&pio {
-	mmc0_pins_default: mmc0-pins {
-		mux {
-			function = "emmc";
-			groups = "emmc_51";
-		};
-		conf-cmd-dat {
-			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-			input-enable;
-			drive-strength = <4>;
-			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
-		};
-		conf-clk {
-			pins = "EMMC_CK";
-			drive-strength = <6>;
-			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
-		};
-		conf-ds {
-			pins = "EMMC_DSL";
-			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
-		};
-		conf-rst {
-			pins = "EMMC_RSTB";
-			drive-strength = <4>;
-			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
-		};
-	};
-
-	mmc0_pins_uhs: mmc0-uhs-pins {
-		mux {
-			function = "emmc";
-			groups = "emmc_51";
-		};
-		conf-cmd-dat {
-			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-			input-enable;
-			drive-strength = <4>;
-			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
-		};
-		conf-clk {
-			pins = "EMMC_CK";
-			drive-strength = <6>;
-			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
-		};
-		conf-ds {
-			pins = "EMMC_DSL";
-			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
-		};
-		conf-rst {
-			pins = "EMMC_RSTB";
-			drive-strength = <4>;
-			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
-		};
-	};
-
-	pcie_pins: pcie-pins {
-		mux {
-			function = "pcie";
-			groups = "pcie_clk", "pcie_wake", "pcie_pereset";
-		};
-	};
-
-	spic_pins_g2: spic-pins-29-to-32 {
-		mux {
-			function = "spi";
-			groups = "spi1_2";
-		};
-	};
-
-	spi_flash_pins: spi-flash-pins-33-to-38 {
-		mux {
-			function = "spi";
-			groups = "spi0", "spi0_wp_hold";
-		};
-		conf-pu {
-			pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
-			drive-strength = <8>;
-			mediatek,pull-up-adv = <0>;	/* bias-disable */
-		};
-		conf-pd {
-			pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
-			drive-strength = <8>;
-			mediatek,pull-down-adv = <0>;	/* bias-disable */
-		};
-	};
-
-	uart1_pins: uart1-pins {
-		mux {
-			function = "uart";
-			groups = "uart1";
-		};
-	};
-
-	uart2_pins: uart2-pins {
-		mux {
-			function = "uart";
-			groups = "uart2";
-		};
-	};
-
-	wf_2g_5g_pins: wf_2g_5g-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_2g", "wf_5g";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-
-	wf_dbdc_pins: wf_dbdc-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_dbdc";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-};
-
-&spi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi_flash_pins>;
-	cs-gpios = <0>, <0>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "disabled";
-};
-
-&spi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spic_pins_g2>;
-	status = "okay";
-
-	proslic_spi: proslic_spi@0 {
-		compatible = "silabs,proslic_spi";
-		reg = <0>;
-		spi-max-frequency = <10000000>;
-		spi-cpha = <1>;
-		spi-cpol = <1>;
-		channel_count = <1>;
-		debug_level = <4>;       /* 1 = TRC, 2 = DBG, 4 = ERR */
-		reset_gpio = <&pio 7 0>;
-		ig,enable-spi = <1>;     /* 1: Enable, 0: Disable */
-	};
-};
-
-&gmac1 {
-	phy-mode = "2500base-x";
-	phy-connection-type = "2500base-x";
-	phy-handle = <&phy6>;
-};
-
-&switch {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-			label = "lan1";
-		};
-
-		port@1 {
-			reg = <1>;
-			label = "lan2";
-		};
-
-		port@2 {
-			reg = <2>;
-			label = "lan3";
-		};
-
-		port@3 {
-			reg = <3>;
-			label = "lan4";
-		};
-
-		port@4 {
-			reg = <4>;
-			label = "wan";
-		};
-
-		port@5 {
-			reg = <5>;
-			label = "lan6";
-
-			phy-mode = "2500base-x";
-			phy-handle = <&phy5>;
-		};
-
-		port@6 {
-			reg = <6>;
-			ethernet = <&gmac0>;
-			phy-mode = "2500base-x";
-
-			fixed-link {
-				speed = <2500>;
-				full-duplex;
-				pause;
-			};
-		};
-	};
-};
-
-&ssusb {
-	vusb33-supply = <&reg_3p3v>;
-	vbus-supply = <&reg_5v>;
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_pins>;
-	status = "okay";
-};
-
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_pins>;
-	status = "okay";
-};
-
-&usb_phy {
-	status = "okay";
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi

@@ -1,645 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/mt7986-clk.h>
-#include <dt-bindings/reset/mt7986-resets.h>
-#include <dt-bindings/phy/phy.h>
-
-/ {
-	compatible = "mediatek,mt7986a";
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	clk40m: oscillator-40m {
-		compatible = "fixed-clock";
-		clock-frequency = <40000000>;
-		#clock-cells = <0>;
-		clock-output-names = "clkxtal";
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		cpu0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			enable-method = "psci";
-			reg = <0x0>;
-			#cooling-cells = <2>;
-		};
-
-		cpu1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			enable-method = "psci";
-			reg = <0x1>;
-			#cooling-cells = <2>;
-		};
-
-		cpu2: cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			enable-method = "psci";
-			reg = <0x2>;
-			#cooling-cells = <2>;
-		};
-
-		cpu3: cpu@3 {
-			device_type = "cpu";
-			enable-method = "psci";
-			compatible = "arm,cortex-a53";
-			reg = <0x3>;
-			#cooling-cells = <2>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
-		secmon_reserved: secmon@43000000 {
-			reg = <0 0x43000000 0 0x30000>;
-			no-map;
-		};
-
-		wmcpu_emi: wmcpu-reserved@4fc00000 {
-			no-map;
-			reg = <0 0x4fc00000 0 0x00100000>;
-		};
-
-		wo_emi0: wo-emi@4fd00000 {
-			reg = <0 0x4fd00000 0 0x40000>;
-			no-map;
-		};
-
-		wo_emi1: wo-emi@4fd40000 {
-			reg = <0 0x4fd40000 0 0x40000>;
-			no-map;
-		};
-
-		wo_ilm0: wo-ilm@151e0000 {
-			reg = <0 0x151e0000 0 0x8000>;
-			no-map;
-		};
-
-		wo_ilm1: wo-ilm@151f0000 {
-			reg = <0 0x151f0000 0 0x8000>;
-			no-map;
-		};
-
-		wo_data: wo-data@4fd80000 {
-			reg = <0 0x4fd80000 0 0x240000>;
-			no-map;
-		};
-
-		wo_dlm0: wo-dlm@151e8000 {
-			reg = <0 0x151e8000 0 0x2000>;
-			no-map;
-		};
-
-		wo_dlm1: wo-dlm@151f8000 {
-			reg = <0 0x151f8000 0 0x2000>;
-			no-map;
-		};
-
-		wo_boot: wo-boot@15194000 {
-			reg = <0 0x15194000 0 0x1000>;
-			no-map;
-		};
-
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-	};
-
-	soc {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		compatible = "simple-bus";
-		ranges;
-
-		gic: interrupt-controller@c000000 {
-			compatible = "arm,gic-v3";
-			#interrupt-cells = <3>;
-			interrupt-parent = <&gic>;
-			interrupt-controller;
-			reg = <0 0x0c000000 0 0x10000>,  /* GICD */
-			      <0 0x0c080000 0 0x80000>,  /* GICR */
-			      <0 0x0c400000 0 0x2000>,   /* GICC */
-			      <0 0x0c410000 0 0x1000>,   /* GICH */
-			      <0 0x0c420000 0 0x2000>;   /* GICV */
-			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		infracfg: infracfg@10001000 {
-			compatible = "mediatek,mt7986-infracfg", "syscon";
-			reg = <0 0x10001000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		wed_pcie: wed-pcie@10003000 {
-			compatible = "mediatek,mt7986-wed-pcie",
-				     "syscon";
-			reg = <0 0x10003000 0 0x10>;
-		};
-
-		topckgen: topckgen@1001b000 {
-			compatible = "mediatek,mt7986-topckgen", "syscon";
-			reg = <0 0x1001B000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		watchdog: watchdog@1001c000 {
-			compatible = "mediatek,mt7986-wdt";
-			reg = <0 0x1001c000 0 0x1000>;
-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-			#reset-cells = <1>;
-			status = "disabled";
-		};
-
-		apmixedsys: apmixedsys@1001e000 {
-			compatible = "mediatek,mt7986-apmixedsys";
-			reg = <0 0x1001E000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		pio: pinctrl@1001f000 {
-			compatible = "mediatek,mt7986a-pinctrl";
-			reg = <0 0x1001f000 0 0x1000>,
-			      <0 0x11c30000 0 0x1000>,
-			      <0 0x11c40000 0 0x1000>,
-			      <0 0x11e20000 0 0x1000>,
-			      <0 0x11e30000 0 0x1000>,
-			      <0 0x11f00000 0 0x1000>,
-			      <0 0x11f10000 0 0x1000>,
-			      <0 0x1000b000 0 0x1000>;
-			reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
-				    "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pio 0 0 100>;
-			interrupt-controller;
-			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-parent = <&gic>;
-			#interrupt-cells = <2>;
-		};
-
-		sgmiisys0: syscon@10060000 {
-			compatible = "mediatek,mt7986-sgmiisys_0",
-				     "syscon";
-			reg = <0 0x10060000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		sgmiisys1: syscon@10070000 {
-			compatible = "mediatek,mt7986-sgmiisys_1",
-				     "syscon";
-			reg = <0 0x10070000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		trng: rng@1020f000 {
-			compatible = "mediatek,mt7986-rng",
-				     "mediatek,mt7623-rng";
-			reg = <0 0x1020f000 0 0x100>;
-			clocks = <&infracfg CLK_INFRA_TRNG_CK>;
-			clock-names = "rng";
-			status = "disabled";
-		};
-
-		crypto: crypto@10320000 {
-			compatible = "inside-secure,safexcel-eip97";
-			reg = <0 0x10320000 0 0x40000>;
-			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "ring0", "ring1", "ring2", "ring3";
-			clocks = <&infracfg CLK_INFRA_EIP97_CK>;
-			clock-names = "infra_eip97_ck";
-			assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
-			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
-			status = "disabled";
-		};
-
-		pwm: pwm@10048000 {
-			compatible = "mediatek,mt7986-pwm";
-			reg = <0 0x10048000 0 0x1000>;
-			#clock-cells = <1>;
-			#pwm-cells = <2>;
-			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_PWM_SEL>,
-				 <&infracfg CLK_INFRA_PWM_STA>,
-				 <&infracfg CLK_INFRA_PWM1_CK>,
-				 <&infracfg CLK_INFRA_PWM2_CK>;
-			clock-names = "top", "main", "pwm1", "pwm2";
-			status = "disabled";
-		};
-
-		uart0: serial@11002000 {
-			compatible = "mediatek,mt7986-uart",
-				     "mediatek,mt6577-uart";
-			reg = <0 0x11002000 0 0x400>;
-			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_UART0_SEL>,
-				 <&infracfg CLK_INFRA_UART0_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-					  <&infracfg CLK_INFRA_UART0_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
-						 <&topckgen CLK_TOP_UART_SEL>;
-			status = "disabled";
-		};
-
-		uart1: serial@11003000 {
-			compatible = "mediatek,mt7986-uart",
-				     "mediatek,mt6577-uart";
-			reg = <0 0x11003000 0 0x400>;
-			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_UART1_SEL>,
-				 <&infracfg CLK_INFRA_UART1_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
-			status = "disabled";
-		};
-
-		uart2: serial@11004000 {
-			compatible = "mediatek,mt7986-uart",
-				     "mediatek,mt6577-uart";
-			reg = <0 0x11004000 0 0x400>;
-			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_UART2_SEL>,
-				 <&infracfg CLK_INFRA_UART2_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
-			status = "disabled";
-		};
-
-		i2c0: i2c@11008000 {
-			compatible = "mediatek,mt7986-i2c";
-			reg = <0 0x11008000 0 0x90>,
-			      <0 0x10217080 0 0x80>;
-			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-			clock-div = <5>;
-			clocks = <&infracfg CLK_INFRA_I2C0_CK>,
-				 <&infracfg CLK_INFRA_AP_DMA_CK>;
-			clock-names = "main", "dma";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		spi0: spi@1100a000 {
-			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0 0x1100a000 0 0x100>;
-			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-				 <&topckgen CLK_TOP_SPI_SEL>,
-				 <&infracfg CLK_INFRA_SPI0_CK>,
-				 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-			status = "disabled";
-		};
-
-		spi1: spi@1100b000 {
-			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0 0x1100b000 0 0x100>;
-			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-				 <&topckgen CLK_TOP_SPIM_MST_SEL>,
-				 <&infracfg CLK_INFRA_SPI1_CK>,
-				 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-			status = "disabled";
-		};
-
-		auxadc: adc@1100d000 {
-			compatible = "mediatek,mt7986-auxadc";
-			reg = <0 0x1100d000 0 0x1000>;
-			clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
-			clock-names = "main";
-			#io-channel-cells = <1>;
-			status = "disabled";
-		};
-
-		ssusb: usb@11200000 {
-			compatible = "mediatek,mt7986-xhci",
-				     "mediatek,mtk-xhci";
-			reg = <0 0x11200000 0 0x2e00>,
-			      <0 0x11203e00 0 0x0100>;
-			reg-names = "mac", "ippc";
-			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
-				 <&infracfg CLK_INFRA_IUSB_CK>,
-				 <&infracfg CLK_INFRA_IUSB_133_CK>,
-				 <&infracfg CLK_INFRA_IUSB_66M_CK>,
-				 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
-			clock-names = "sys_ck",
-				      "ref_ck",
-				      "mcu_ck",
-				      "dma_ck",
-				      "xhci_ck";
-			phys = <&u2port0 PHY_TYPE_USB2>,
-			       <&u3port0 PHY_TYPE_USB3>,
-			       <&u2port1 PHY_TYPE_USB2>;
-			status = "disabled";
-		};
-
-		mmc0: mmc@11230000 {
-			compatible = "mediatek,mt7986-mmc";
-			reg = <0 0x11230000 0 0x1000>,
-			      <0 0x11c20000 0 0x1000>;
-			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
-				 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
-				 <&infracfg CLK_INFRA_MSDC_CK>,
-				 <&infracfg CLK_INFRA_MSDC_133M_CK>,
-				 <&infracfg CLK_INFRA_MSDC_66M_CK>;
-			clock-names = "source", "hclk", "source_cg", "bus_clk",
-				      "sys_cg";
-			status = "disabled";
-		};
-
-		thermal: thermal@1100c800 {
-			#thermal-sensor-cells = <1>;
-			compatible = "mediatek,mt7986-thermal";
-			reg = <0 0x1100c800 0 0x800>;
-			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_THERM_CK>,
-				 <&infracfg CLK_INFRA_ADC_26M_CK>,
-				 <&infracfg CLK_INFRA_ADC_FRC_CK>;
-			clock-names = "therm", "auxadc", "adc_32k";
-			mediatek,auxadc = <&auxadc>;
-			mediatek,apmixedsys = <&apmixedsys>;
-			nvmem-cells = <&thermal_calibration>;
-			nvmem-cell-names = "calibration-data";
-		};
-
-		pcie: pcie@11280000 {
-			compatible = "mediatek,mt7986-pcie",
-				     "mediatek,mt8192-pcie";
-			device_type = "pci";
-			#address-cells = <3>;
-			#size-cells = <2>;
-			reg = <0x00 0x11280000 0x00 0x4000>;
-			reg-names = "pcie-mac";
-			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
-			ranges = <0x82000000 0x00 0x20000000 0x00
-				  0x20000000 0x00 0x10000000>;
-			clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
-				 <&infracfg CLK_INFRA_IPCIE_CK>,
-				 <&infracfg CLK_INFRA_IPCIER_CK>,
-				 <&infracfg CLK_INFRA_IPCIEB_CK>;
-			clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
-			status = "disabled";
-
-			phys = <&pcie_port PHY_TYPE_PCIE>;
-			phy-names = "pcie-phy";
-
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0x7>;
-			interrupt-map = <0 0 0 1 &pcie_intc 0>,
-					<0 0 0 2 &pcie_intc 1>,
-					<0 0 0 3 &pcie_intc 2>,
-					<0 0 0 4 &pcie_intc 3>;
-			pcie_intc: interrupt-controller {
-				#address-cells = <0>;
-				#interrupt-cells = <1>;
-				interrupt-controller;
-			};
-		};
-
-		pcie_phy: t-phy@11c00000 {
-			compatible = "mediatek,mt7986-tphy",
-				     "mediatek,generic-tphy-v2";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges;
-			status = "disabled";
-
-			pcie_port: pcie-phy@11c00000 {
-				reg = <0 0x11c00000 0 0x20000>;
-				clocks = <&clk40m>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-			};
-		};
-
-		efuse: efuse@11d00000 {
-			compatible = "mediatek,mt7986-efuse", "mediatek,efuse";
-			reg = <0 0x11d00000 0 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			thermal_calibration: calib@274 {
-				reg = <0x274 0xc>;
-			};
-		};
-
-		usb_phy: t-phy@11e10000 {
-			compatible = "mediatek,mt7986-tphy",
-				     "mediatek,generic-tphy-v2";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0 0x11e10000 0x1700>;
-			status = "disabled";
-
-			u2port0: usb-phy@0 {
-				reg = <0x0 0x700>;
-				clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
-					 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
-				clock-names = "ref", "da_ref";
-				#phy-cells = <1>;
-			};
-
-			u3port0: usb-phy@700 {
-				reg = <0x700 0x900>;
-				clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-			};
-
-			u2port1: usb-phy@1000 {
-				reg = <0x1000 0x700>;
-				clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
-					 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
-				clock-names = "ref", "da_ref";
-				#phy-cells = <1>;
-			};
-		};
-
-		ethsys: syscon@15000000 {
-			 #address-cells = <1>;
-			 #size-cells = <1>;
-			 compatible = "mediatek,mt7986-ethsys",
-				      "syscon";
-			 reg = <0 0x15000000 0 0x1000>;
-			 #clock-cells = <1>;
-			 #reset-cells = <1>;
-		};
-
-		wed0: wed@15010000 {
-			compatible = "mediatek,mt7986-wed",
-				     "syscon";
-			reg = <0 0x15010000 0 0x1000>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
-			memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
-					<&wo_data>, <&wo_boot>;
-			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
-					      "wo-data", "wo-boot";
-			mediatek,wo-ccif = <&wo_ccif0>;
-		};
-
-		wed1: wed@15011000 {
-			compatible = "mediatek,mt7986-wed",
-				     "syscon";
-			reg = <0 0x15011000 0 0x1000>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
-			memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
-					<&wo_data>, <&wo_boot>;
-			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
-					      "wo-data", "wo-boot";
-			mediatek,wo-ccif = <&wo_ccif1>;
-		};
-
-		wo_ccif0: syscon@151a5000 {
-			compatible = "mediatek,mt7986-wo-ccif", "syscon";
-			reg = <0 0x151a5000 0 0x1000>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		wo_ccif1: syscon@151ad000 {
-			compatible = "mediatek,mt7986-wo-ccif", "syscon";
-			reg = <0 0x151ad000 0 0x1000>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		eth: ethernet@15100000 {
-			compatible = "mediatek,mt7986-eth";
-			reg = <0 0x15100000 0 0x80000>;
-			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ethsys CLK_ETH_FE_EN>,
-				 <&ethsys CLK_ETH_GP2_EN>,
-				 <&ethsys CLK_ETH_GP1_EN>,
-				 <&ethsys CLK_ETH_WOCPU1_EN>,
-				 <&ethsys CLK_ETH_WOCPU0_EN>,
-				 <&sgmiisys0 CLK_SGMII0_TX250M_EN>,
-				 <&sgmiisys0 CLK_SGMII0_RX250M_EN>,
-				 <&sgmiisys0 CLK_SGMII0_CDR_REF>,
-				 <&sgmiisys0 CLK_SGMII0_CDR_FB>,
-				 <&sgmiisys1 CLK_SGMII1_TX250M_EN>,
-				 <&sgmiisys1 CLK_SGMII1_RX250M_EN>,
-				 <&sgmiisys1 CLK_SGMII1_CDR_REF>,
-				 <&sgmiisys1 CLK_SGMII1_CDR_FB>,
-				 <&topckgen CLK_TOP_NETSYS_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
-			clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
-				      "sgmii_tx250m", "sgmii_rx250m",
-				      "sgmii_cdr_ref", "sgmii_cdr_fb",
-				      "sgmii2_tx250m", "sgmii2_rx250m",
-				      "sgmii2_cdr_ref", "sgmii2_cdr_fb",
-				      "netsys0", "netsys1";
-			assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
-					  <&topckgen CLK_TOP_SGM_325M_SEL>;
-			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
-						 <&apmixedsys CLK_APMIXED_SGMPLL>;
-			mediatek,ethsys = <&ethsys>;
-			mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
-			mediatek,wed-pcie = <&wed_pcie>;
-			mediatek,wed = <&wed0>, <&wed1>;
-			#reset-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		wifi: wifi@18000000 {
-			compatible = "mediatek,mt7986-wmac";
-			resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
-			reset-names = "consys";
-			clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
-				 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
-			clock-names = "mcu", "ap2conn";
-			reg = <0 0x18000000 0 0x1000000>,
-			      <0 0x10003000 0 0x1000>,
-			      <0 0x11d10000 0 0x1000>;
-			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
-			memory-region = <&wmcpu_emi>;
-		};
-	};
-
-	thermal-zones {
-		cpu_thermal: cpu-thermal {
-			polling-delay-passive = <1000>;
-			polling-delay = <1000>;
-			thermal-sensors = <&thermal 0>;
-
-			trips {
-				cpu_trip_crit: crit {
-					temperature = <125000>;
-					hysteresis = <2000>;
-					type = "critical";
-				};
-
-				cpu_trip_hot: hot {
-					temperature = <120000>;
-					hysteresis = <2000>;
-					type = "hot";
-				};
-
-				cpu_trip_active_high: active-high {
-					temperature = <115000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_med: active-med {
-					temperature = <85000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_low: active-low {
-					temperature = <60000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-			};
-		};
-	};
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts

@@ -1,194 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-/dts-v1/;
-#include "mt7986b.dtsi"
-
-/ {
-	model = "MediaTek MT7986b RFB";
-	compatible = "mediatek,mt7986b-rfb";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory {
-		reg = <0 0x40000000 0 0x40000000>;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_5v: regulator-5v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-5V";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-};
-
-&ssusb {
-	vusb33-supply = <&reg_3p3v>;
-	vbus-supply = <&reg_5v>;
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&usb_phy {
-	status = "okay";
-};
-
-&wifi {
-	status = "okay";
-	pinctrl-names = "default", "dbdc";
-	pinctrl-0 = <&wf_2g_5g_pins>;
-	pinctrl-1 = <&wf_dbdc_pins>;
-};
-
-&eth {
-	status = "okay";
-
-	gmac0: mac@0 {
-		compatible = "mediatek,eth-mac";
-		reg = <0>;
-		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	gmac1: mac@1 {
-		compatible = "mediatek,eth-mac";
-		reg = <1>;
-		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	mdio: mdio-bus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		phy5: phy@5 {
-			compatible = "ethernet-phy-id67c9.de0a";
-			reg = <5>;
-			reset-gpios = <&pio 6 1>;
-			reset-deassert-us = <20000>;
-			phy-mode = "2500base-x";
-		};
-
-		phy6: phy@6 {
-			compatible = "ethernet-phy-id67c9.de0a";
-			reg = <6>;
-			phy-mode = "2500base-x";
-		};
-
-		switch@1f {
-			compatible = "mediatek,mt7531";
-			reg = <31>;
-			reset-gpios = <&pio 5 0>;
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@0 {
-					reg = <0>;
-					label = "lan0";
-				};
-
-				port@1 {
-					reg = <1>;
-					label = "lan1";
-				};
-
-				port@2 {
-					reg = <2>;
-					label = "lan2";
-				};
-
-				port@3 {
-					reg = <3>;
-					label = "lan3";
-				};
-
-				port@6 {
-					reg = <6>;
-					ethernet = <&gmac0>;
-					phy-mode = "2500base-x";
-
-					fixed-link {
-						speed = <2500>;
-						full-duplex;
-						pause;
-					};
-				};
-			};
-		};
-	};
-};
-
-&crypto {
-	status = "okay";
-};
-
-&pio {
-	wf_2g_5g_pins: wf_2g_5g-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_2g", "wf_5g";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-
-	wf_dbdc_pins: wf_dbdc-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_dbdc";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b.dtsi

@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-#include "mt7986a.dtsi"
-/ {
-	compatible = "mediatek,mt7986b";
-};
-
-&pio {
-	compatible = "mediatek,mt7986b-pinctrl";
-	gpio-ranges = <&pio 0 0 41>, <&pio 66 66 35>;
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso

@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Frank Wunderlich <[email protected]>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mmc0>;
-		__overlay__ {
-			pinctrl-names = "default", "state_uhs";
-			pinctrl-0 = <&mmc0_pins_emmc_51>;
-			pinctrl-1 = <&mmc0_pins_emmc_51>;
-			bus-width = <8>;
-			max-frequency = <200000000>;
-			cap-mmc-highspeed;
-			mmc-hs200-1_8v;
-			mmc-hs400-1_8v;
-			hs400-ds-delay = <0x12814>;
-			vqmmc-supply = <&reg_1p8v>;
-			vmmc-supply = <&reg_3p3v>;
-			non-removable;
-			no-sd;
-			no-sdio;
-			status = "okay";
-		};
-	};
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso

@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* external Aquantia AQR113C */
-			phy0: ethernet-phy@0 {
-				reg = <0>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>;
-				reset-assert-us = <100000>;
-				reset-deassert-us = <221000>;
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "usxgmii";
-			phy-connection-type = "usxgmii";
-			phy = <&phy0>;
-			status = "okay";
-		};
-	};
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "internal";
-			phy-connection-type = "internal";
-			phy = <&int_2p5g_phy>;
-			status = "okay";
-		};
-	};
-
-	fragment@1 {
-		target = <&int_2p5g_phy>;
-		__overlay__ {
-			pinctrl-names = "i2p5gbe-led";
-			pinctrl-0 = <&i2p5gbe_led0_pins>;
-		};
-	};
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso

@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* external Maxlinear GPY211C */
-			phy13: ethernet-phy@13 {
-				reg = <13>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				phy-mode = "2500base-x";
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "2500base-x";
-			phy-connection-type = "2500base-x";
-			phy = <&phy13>;
-			status = "okay";
-		};
-	};
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso

@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&i2c2>;
-		__overlay__ {
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c2_0_pins>;
-			status = "okay";
-		};
-	};
-
-	fragment@1 {
-		target-path = "/";
-		__overlay__ {
-			sfp_esp1: sfp@1 {
-				compatible = "sff,sfp";
-				i2c-bus = <&i2c2>;
-				mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
-				los-gpios = <&pio 81 GPIO_ACTIVE_HIGH>;
-				tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>;
-				maximum-power-milliwatt = <3000>;
-			};
-		};
-	};
-
-	fragment@2 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "10gbase-r";
-			managed = "in-band-status";
-			sfp = <&sfp_esp1>;
-			status = "okay";
-		};
-	};
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso

@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* external Aquantia AQR113C */
-			phy8: ethernet-phy@8 {
-				reg = <8>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>;
-				reset-assert-us = <100000>;
-				reset-deassert-us = <221000>;
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&gmac2>;
-		__overlay__ {
-			phy-mode = "usxgmii";
-			phy-connection-type = "usxgmii";
-			phy = <&phy8>;
-			status = "okay";
-		};
-	};
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso

@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* external Maxlinear GPY211C */
-			phy5: ethernet-phy@5 {
-				reg = <5>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				phy-mode = "2500base-x";
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&gmac2>;
-		__overlay__ {
-			phy-mode = "2500base-x";
-			phy-connection-type = "2500base-x";
-			phy = <&phy5>;
-			status = "okay";
-		};
-	};
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso

@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&i2c1>;
-		__overlay__ {
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c1_sfp_pins>;
-			status = "okay";
-		};
-	};
-
-	fragment@1 {
-		target-path = "/";
-		__overlay__ {
-			sfp_esp0: sfp@0 {
-				compatible = "sff,sfp";
-				i2c-bus = <&i2c1>;
-				mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>;
-				los-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
-				tx-disable-gpios = <&pio 29 GPIO_ACTIVE_HIGH>;
-				maximum-power-milliwatt = <3000>;
-			};
-		};
-	};
-
-	fragment@2 {
-		target = <&gmac2>;
-		__overlay__ {
-			phy-mode = "10gbase-r";
-			managed = "in-band-status";
-			sfp = <&sfp_esp0>;
-			status = "okay";
-		};
-	};
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso

@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2023 MediaTek Inc.
- * Author: Frank Wunderlich <[email protected]>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@1 {
-		target-path = <&mmc0>;
-		__overlay__ {
-			pinctrl-names = "default", "state_uhs";
-			pinctrl-0 = <&mmc0_pins_sdcard>;
-			pinctrl-1 = <&mmc0_pins_sdcard>;
-			cd-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
-			bus-width = <4>;
-			max-frequency = <52000000>;
-			cap-sd-highspeed;
-			vmmc-supply = <&reg_3p3v>;
-			vqmmc-supply = <&reg_3p3v>;
-			no-mmc;
-			status = "okay";
-		};
-	};
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso

@@ -1,69 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&snand>;
-		__overlay__ {
-			status = "okay";
-
-			flash@0 {
-				compatible = "spi-nand";
-				reg = <0>;
-				spi-max-frequency = <52000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-				mediatek,nmbm;
-				mediatek,bmt-max-ratio = <1>;
-				mediatek,bmt-max-reserved-blocks = <64>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "BL2";
-						reg = <0x00000 0x0100000>;
-						read-only;
-					};
-
-					partition@100000 {
-						label = "u-boot-env";
-						reg = <0x0100000 0x0080000>;
-					};
-
-					partition@180000 {
-						label = "Factory";
-						reg = <0x180000 0x0400000>;
-					};
-
-					partition@580000 {
-						label = "FIP";
-						reg = <0x580000 0x0200000>;
-					};
-
-					partition@780000 {
-						label = "ubi";
-						reg = <0x780000 0x7080000>;
-					};
-				};
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&bch>;
-		__overlay__ {
-			status = "okay";
-		};
-	};
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso

@@ -1,64 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&spi0>;
-		__overlay__ {
-			pinctrl-names = "default";
-			pinctrl-0 = <&spi0_flash_pins>;
-			status = "okay";
-
-			flash@0 {
-				compatible = "spi-nand";
-				reg = <0>;
-				spi-max-frequency = <52000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-				mediatek,nmbm;
-				mediatek,bmt-max-ratio = <1>;
-				mediatek,bmt-max-reserved-blocks = <64>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "BL2";
-						reg = <0x00000 0x0100000>;
-						read-only;
-					};
-
-					partition@100000 {
-						label = "u-boot-env";
-						reg = <0x0100000 0x0080000>;
-					};
-
-					partition@180000 {
-						label = "Factory";
-						reg = <0x180000 0x0400000>;
-					};
-
-					partition@580000 {
-						label = "FIP";
-						reg = <0x580000 0x0200000>;
-					};
-
-					partition@780000 {
-						label = "ubi";
-						reg = <0x780000 0x7080000>;
-					};
-				};
-			};
-		};
-	};
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso

@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&spi2>;
-		__overlay__ {
-			pinctrl-names = "default";
-			pinctrl-0 = <&spi2_flash_pins>;
-			status = "okay";
-
-			flash@0 {
-				#address-cells = <1>;
-				#size-cells = <1>;
-				compatible = "jedec,spi-nor";
-				spi-cal-enable;
-				spi-cal-mode = "read-data";
-				spi-cal-datalen = <7>;
-				spi-cal-data = /bits/ 8 <
-					0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */
-				spi-cal-addrlen = <1>;
-				spi-cal-addr = /bits/ 32 <0x0>;
-				reg = <0>;
-				spi-max-frequency = <52000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-
-				partition@00000 {
-					label = "BL2";
-					reg = <0x00000 0x0040000>;
-				};
-				partition@40000 {
-					label = "u-boot-env";
-					reg = <0x40000 0x0010000>;
-				};
-				partition@50000 {
-					label = "Factory";
-					reg = <0x50000 0x0200000>;
-				};
-				partition@250000 {
-					label = "FIP";
-					reg = <0x250000 0x0080000>;
-				};
-				partition@2D0000 {
-					label = "firmware";
-					reg = <0x2D0000 0x1D30000>;
-				};
-			};
-		};
-	};
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts

@@ -1,200 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-/dts-v1/;
-#include "mt7988a.dtsi"
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
-
-/ {
-	model = "MediaTek MT7988A Reference Board";
-	compatible = "mediatek,mt7988a-rfb",
-		     "mediatek,mt7988";
-
-	chosen {
-		bootargs = "console=ttyS0,115200n1 loglevel=8  \
-			    earlycon=uart8250,mmio32,0x11000000 \
-			    pci=pcie_bus_perf";
-	};
-
-	memory {
-		reg = <0 0x40000000 0 0x40000000>;
-	};
-};
-
-&eth {
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-};
-
-&gmac0 {
-	status = "okay";
-};
-
-&cpu0 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cpu1 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cpu2 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cpu3 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cci {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&eth {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&gsw_phy0 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe0_led0_pins>;
-};
-
-&gsw_phy0_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy1 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe1_led0_pins>;
-};
-
-&gsw_phy1_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy2 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe2_led0_pins>;
-};
-
-&gsw_phy2_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy3 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe3_led0_pins>;
-};
-
-&gsw_phy3_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins>;
-	status = "okay";
-
-	rt5190a_64: rt5190a@64 {
-		compatible = "richtek,rt5190a";
-		reg = <0x64>;
-		/*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/
-		vin2-supply = <&rt5190_buck1>;
-		vin3-supply = <&rt5190_buck1>;
-		vin4-supply = <&rt5190_buck1>;
-
-		regulators {
-			rt5190_buck1: buck1 {
-				regulator-name = "rt5190a-buck1";
-				regulator-min-microvolt = <5090000>;
-				regulator-max-microvolt = <5090000>;
-				regulator-allowed-modes =
-				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			buck2 {
-				regulator-name = "vcore";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <1400000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			rt5190_buck3: buck3 {
-				regulator-name = "vproc";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <1400000>;
-				regulator-boot-on;
-			};
-			buck4 {
-				regulator-name = "rt5190a-buck4";
-				regulator-min-microvolt = <850000>;
-				regulator-max-microvolt = <850000>;
-				regulator-allowed-modes =
-				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			ldo {
-				regulator-name = "rt5190a-ldo";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <1200000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-		};
-	};
-};
-
-&pcie0 {
-	status = "okay";
-};
-
-&pcie1 {
-	status = "okay";
-};
-
-&pcie2 {
-	status = "disabled";
-};
-
-&pcie3 {
-	status = "okay";
-};
-
-&ssusb0 {
-	status = "okay";
-};
-
-&ssusb1 {
-	status = "okay";
-};
-
-&tphy {
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&xphy {
-	status = "okay";
-};

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi

@@ -1,1456 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2023 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <dt-bindings/reset/ti-syscon.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
-	compatible = "mediatek,mt7988";
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	cci: cci {
-		compatible = "mediatek,mt7988-cci",
-			     "mediatek,mt8183-cci";
-		clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
-			 <&topckgen CLK_TOP_XTAL>;
-		clock-names = "cci", "intermediate";
-		operating-points-v2 = <&cci_opp>;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu0: cpu@0 {
-			compatible = "arm,cortex-a73";
-			reg = <0x0>;
-			device_type = "cpu";
-			enable-method = "psci";
-			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
-				 <&topckgen CLK_TOP_XTAL>;
-			clock-names = "cpu", "intermediate";
-			operating-points-v2 = <&cluster0_opp>;
-			mediatek,cci = <&cci>;
-		};
-
-		cpu1: cpu@1 {
-			compatible = "arm,cortex-a73";
-			reg = <0x1>;
-			device_type = "cpu";
-			enable-method = "psci";
-			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
-				 <&topckgen CLK_TOP_XTAL>;
-			clock-names = "cpu", "intermediate";
-			operating-points-v2 = <&cluster0_opp>;
-			mediatek,cci = <&cci>;
-		};
-
-		cpu2: cpu@2 {
-			compatible = "arm,cortex-a73";
-			reg = <0x2>;
-			device_type = "cpu";
-			enable-method = "psci";
-			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
-				 <&topckgen CLK_TOP_XTAL>;
-			clock-names = "cpu", "intermediate";
-			operating-points-v2 = <&cluster0_opp>;
-			mediatek,cci = <&cci>;
-		};
-
-		cpu3: cpu@3 {
-			compatible = "arm,cortex-a73";
-			reg = <0x3>;
-			device_type = "cpu";
-			enable-method = "psci";
-			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
-				 <&topckgen CLK_TOP_XTAL>;
-			clock-names = "cpu", "intermediate";
-			operating-points-v2 = <&cluster0_opp>;
-			mediatek,cci = <&cci>;
-		};
-
-		cluster0_opp: opp_table0 {
-			compatible = "operating-points-v2";
-			opp-shared;
-
-			opp00 {
-				opp-hz = /bits/ 64 <800000000>;
-				opp-microvolt = <850000>;
-			};
-
-			opp01 {
-				opp-hz = /bits/ 64 <1100000000>;
-				opp-microvolt = <850000>;
-			};
-
-			opp02 {
-				opp-hz = /bits/ 64 <1500000000>;
-				opp-microvolt = <850000>;
-			};
-
-			opp03 {
-				opp-hz = /bits/ 64 <1800000000>;
-				opp-microvolt = <900000>;
-			};
-		};
-	};
-
-	cci_opp: opp_table_cci {
-		compatible = "operating-points-v2";
-		opp-shared;
-
-		opp00 {
-			opp-hz = /bits/ 64 <480000000>;
-			opp-microvolt = <850000>;
-		};
-
-		opp01 {
-			opp-hz = /bits/ 64 <660000000>;
-			opp-microvolt = <850000>;
-		};
-
-		opp02 {
-			opp-hz = /bits/ 64 <900000000>;
-			opp-microvolt = <850000>;
-		};
-
-		opp03 {
-			opp-hz = /bits/ 64 <1080000000>;
-			opp-microvolt = <900000>;
-		};
-	};
-
-	clk40m: oscillator@0 {
-		compatible = "fixed-clock";
-		clock-frequency = <40000000>;
-		#clock-cells = <0>;
-		clock-output-names = "clkxtal";
-	};
-
-	pmu {
-		compatible = "arm,cortex-a73-pmu";
-		interrupt-parent = <&gic>;
-		interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	reg_1p8v: regulator-1p8v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-1.8V";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reserved-memory {
-		ranges;
-		#address-cells = <2>;
-		#size-cells = <2>;
-
-		/* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
-		secmon_reserved: secmon@43000000 {
-			reg = <0 0x43000000 0 0x50000>;
-			no-map;
-		};
-	};
-
-	soc {
-		compatible = "simple-bus";
-		ranges;
-		#address-cells = <2>;
-		#size-cells = <2>;
-
-		gic: interrupt-controller@c000000 {
-			compatible = "arm,gic-v3";
-			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
-			      <0 0x0c080000 0 0x200000>, /* GICR */
-			      <0 0x0c400000 0 0x2000>,   /* GICC */
-			      <0 0x0c410000 0 0x1000>,   /* GICH */
-			      <0 0x0c420000 0 0x2000>;   /* GICV */
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-controller;
-			#interrupt-cells = <3>;
-		};
-
-		phyfw: phy-firmware@f000000 {
-			compatible = "mediatek,2p5gphy-fw";
-			reg = <0 0x0f000000 0 0x8000>,
-			      <0 0x0f100000 0 0x20000>,
-			      <0 0x0f0f0000 0 0x200>;
-		};
-
-		infracfg: infracfg@10001000 {
-			compatible = "mediatek,mt7988-infracfg", "syscon";
-			reg = <0 0x10001000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		topckgen: topckgen@1001b000 {
-			compatible = "mediatek,mt7988-topckgen", "syscon";
-			reg = <0 0x1001b000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		watchdog: watchdog@1001c000 {
-			compatible = "mediatek,mt7988-wdt",
-				     "mediatek,mt6589-wdt",
-				     "syscon";
-			reg = <0 0x1001c000 0 0x1000>;
-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-			#reset-cells = <1>;
-		};
-
-		apmixedsys: apmixedsys@1001e000 {
-			compatible = "mediatek,mt7988-apmixedsys";
-			reg = <0 0x1001e000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		pio: pinctrl@1001f000 {
-			compatible = "mediatek,mt7988-pinctrl", "syscon";
-			reg = <0 0x1001f000 0 0x1000>,
-			      <0 0x11c10000 0 0x1000>,
-			      <0 0x11d00000 0 0x1000>,
-			      <0 0x11d20000 0 0x1000>,
-			      <0 0x11e00000 0 0x1000>,
-			      <0 0x11f00000 0 0x1000>,
-			      <0 0x1000b000 0 0x1000>;
-			reg-names = "gpio_base", "iocfg_tr_base",
-				    "iocfg_br_base", "iocfg_rb_base",
-				    "iocfg_lb_base", "iocfg_tl_base", "eint";
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pio 0 0 84>;
-			interrupt-controller;
-			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-parent = <&gic>;
-			#interrupt-cells = <2>;
-
-			mdio0_pins: mdio0-pins {
-				mux {
-					function = "eth";
-					groups = "mdc_mdio0";
-				};
-
-				conf {
-					groups = "mdc_mdio0";
-					drive-strength = <MTK_DRIVE_8mA>;
-				};
-			};
-
-			i2c0_pins: i2c0-pins-g0 {
-				mux {
-					function = "i2c";
-					groups = "i2c0_1";
-				};
-			};
-
-			i2c1_pins: i2c1-pins-g0 {
-				mux {
-					function = "i2c";
-					groups = "i2c1_0";
-				};
-			};
-
-			i2c1_sfp_pins: i2c1-sfp-pins-g0 {
-				mux {
-					function = "i2c";
-					groups = "i2c1_sfp";
-				};
-			};
-
-			i2c2_pins: i2c2-pins {
-				mux {
-					function = "i2c";
-					groups = "i2c2";
-				};
-			};
-
-			i2c2_0_pins: i2c2-pins-g0 {
-				mux {
-					function = "i2c";
-					groups = "i2c2_0";
-				};
-			};
-
-			i2c2_1_pins: i2c2-pins-g1 {
-				mux {
-					function = "i2c";
-					groups = "i2c2_1";
-				};
-			};
-
-			gbe0_led0_pins: gbe0-led0-pins {
-				mux {
-					function = "led";
-					groups = "gbe0_led0";
-				};
-			};
-
-			gbe1_led0_pins: gbe1-led0-pins {
-				mux {
-					function = "led";
-					groups = "gbe1_led0";
-				};
-			};
-
-			gbe2_led0_pins: gbe2-led0-pins {
-				mux {
-					function = "led";
-					groups = "gbe2_led0";
-				};
-			};
-
-			gbe3_led0_pins: gbe3-led0-pins {
-				mux {
-					function = "led";
-					groups = "gbe3_led0";
-				};
-			};
-
-			gbe0_led1_pins: gbe0-led1-pins {
-				mux {
-					function = "led";
-					groups = "gbe0_led1";
-				};
-			};
-
-			gbe1_led1_pins: gbe1-led1-pins {
-				mux {
-					function = "led";
-					groups = "gbe1_led1";
-				};
-			};
-
-			gbe2_led1_pins: gbe2-led1-pins {
-				mux {
-					function = "led";
-					groups = "gbe2_led1";
-				};
-			};
-
-			gbe3_led1_pins: gbe3-led1-pins {
-				mux {
-					function = "led";
-					groups = "gbe3_led1";
-				};
-			};
-
-			i2p5gbe_led0_pins: 2p5gbe-led0-pins {
-				mux {
-					function = "led";
-					groups = "2p5gbe_led0";
-				};
-			};
-
-			i2p5gbe_led1_pins: 2p5gbe-led1-pins {
-				mux {
-					function = "led";
-					groups = "2p5gbe_led1";
-				};
-			};
-
-			mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
-				mux {
-					function = "flash";
-					groups = "emmc_45";
-				};
-			};
-
-			mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
-				mux {
-					function = "flash";
-					groups = "emmc_51";
-				};
-			};
-
-			mmc0_pins_sdcard: mmc0-pins-sdcard {
-				mux {
-					function = "flash";
-					groups = "sdcard";
-				};
-			};
-
-			uart0_pins: uart0-pins {
-				mux {
-					function = "uart";
-					groups =  "uart0";
-				};
-			};
-
-			snfi_pins: snfi-pins {
-				mux {
-					function = "flash";
-					groups = "snfi";
-				};
-			};
-
-			spi0_pins: spi0-pins {
-				mux {
-					function = "spi";
-					groups = "spi0";
-				};
-			};
-
-			spi0_flash_pins: spi0-flash-pins {
-				mux {
-					function = "spi";
-					groups = "spi0", "spi0_wp_hold";
-				};
-			};
-
-			spi1_pins: spi1-pins {
-				mux {
-					function = "spi";
-					groups = "spi1";
-				};
-			};
-
-			spi2_pins: spi2-pins {
-				mux {
-					function = "spi";
-					groups = "spi2";
-				};
-			};
-
-			spi2_flash_pins: spi2-flash-pins {
-				mux {
-					function = "spi";
-					groups = "spi2", "spi2_wp_hold";
-				};
-			};
-
-			pcie0_pins: pcie0-pins {
-				mux {
-					function = "pcie";
-					groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
-						 "pcie_wake_n0_0";
-				};
-			};
-
-			pcie1_pins: pcie1-pins {
-				mux {
-					function = "pcie";
-					groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
-						 "pcie_wake_n1_0";
-				};
-			};
-
-			pcie2_pins: pcie2-pins {
-				mux {
-					function = "pcie";
-					groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
-						 "pcie_wake_n2_0";
-				};
-			};
-
-			pcie3_pins: pcie3-pins {
-				mux {
-					function = "pcie";
-					groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
-						 "pcie_wake_n3_0";
-				};
-			};
-		};
-
-		pwm: pwm@10048000 {
-			compatible = "mediatek,mt7988-pwm";
-			reg = <0 0x10048000 0 0x1000>;
-			#pwm-cells = <2>;
-			clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
-				 <&infracfg CLK_INFRA_66M_PWM_HCK>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK1>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK2>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK3>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK4>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK5>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK6>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK7>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK8>;
-			clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
-				      "pwm4","pwm5","pwm6","pwm7","pwm8";
-			status = "disabled";
-		};
-
-		sgmiisys0: syscon@10060000 {
-			compatible = "mediatek,mt7988-sgmiisys",
-				     "mediatek,mt7988-sgmiisys_0",
-				     "syscon";
-			reg = <0 0x10060000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		sgmiisys1: syscon@10070000 {
-			compatible = "mediatek,mt7988-sgmiisys",
-				     "mediatek,mt7988-sgmiisys_1",
-				     "syscon";
-			reg = <0 0x10070000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		usxgmiisys0: usxgmiisys@10080000 {
-			compatible = "mediatek,mt7988-usxgmiisys",
-				     "mediatek,mt7988-usxgmiisys_0",
-				     "syscon";
-			reg = <0 0x10080000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		usxgmiisys1: usxgmiisys@10081000 {
-			compatible = "mediatek,mt7988-usxgmiisys",
-				     "mediatek,mt7988-usxgmiisys_1",
-				     "syscon";
-			reg = <0 0x10081000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		mcusys: mcusys@100e0000 {
-			compatible = "mediatek,mt7988-mcusys", "syscon";
-			reg = <0 0x100e0000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		uart0: serial@11000000 {
-			compatible = "mediatek,mt7986-uart",
-				     "mediatek,mt6577-uart";
-			reg = <0 0x11000000 0 0x100>;
-			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-			/*
-			 * 8250-mtk driver don't control "baud" clock since commit
-			 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
-			 * still need to be passed to the driver to prevent probe fail
-			 */
-			clocks = <&topckgen CLK_TOP_UART_SEL>,
-				 <&infracfg CLK_INFRA_52M_UART0_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-					  <&infracfg CLK_INFRA_MUX_UART0_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
-						 <&topckgen CLK_TOP_UART_SEL>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&uart0_pins>;
-			status = "disabled";
-		};
-
-		snand: spi@11001000 {
-			compatible = "mediatek,mt7986-snand";
-			reg = <0 0x11001000 0 0x1000>;
-			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_SPINFI>,
-				 <&infracfg CLK_INFRA_NFI>;
-			clock-names = "pad_clk", "nfi_clk";
-			assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
-					  <&topckgen CLK_TOP_NFI1X_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
-						 <&topckgen CLK_TOP_MPLL_D8>;
-			nand-ecc-engine = <&bch>;
-			mediatek,quad-spi;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&snfi_pins>;
-			status = "disabled";
-		};
-
-		bch: ecc@11002000 {
-			compatible = "mediatek,mt7686-ecc";
-			reg = <0 0x11002000 0 0x1000>;
-			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_NFI1X_SEL>;
-			clock-names = "nfiecc_clk";
-			status = "disabled";
-		};
-
-		i2c0: i2c@11003000 {
-			compatible = "mediatek,mt7988-i2c",
-				     "mediatek,mt7981-i2c";
-			reg = <0 0x11003000 0 0x1000>,
-			      <0 0x10217080 0 0x80>;
-			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-			clock-div = <1>;
-			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
-				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
-			clock-names = "main", "dma";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		i2c1: i2c@11004000 {
-			compatible = "mediatek,mt7988-i2c",
-				     "mediatek,mt7981-i2c";
-			reg = <0 0x11004000 0 0x1000>,
-			      <0 0x10217100 0 0x80>;
-			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
-			clock-div = <1>;
-			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
-				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
-			clock-names = "main", "dma";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		i2c2: i2c@11005000 {
-			compatible = "mediatek,mt7988-i2c",
-				"mediatek,mt7981-i2c";
-			reg = <0 0x11005000 0 0x1000>,
-			      <0 0x10217180 0 0x80>;
-			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
-			clock-div = <1>;
-			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
-				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
-			clock-names = "main", "dma";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		spi0: spi@11007000 {
-			compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
-			reg = <0 0x11007000 0 0x100>;
-			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-				 <&topckgen CLK_TOP_SPI_SEL>,
-				 <&infracfg CLK_INFRA_104M_SPI0>,
-				 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk",
-				      "spi-hclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		spi1: spi@11008000 {
-			compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm";
-			reg = <0 0x11008000 0 0x100>;
-			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-				 <&topckgen CLK_TOP_SPI_SEL>,
-				 <&infracfg CLK_INFRA_104M_SPI1>,
-				 <&infracfg CLK_INFRA_66M_SPI1_HCK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk",
-				      "spi-hclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&spi1_pins>;
-			status = "disabled";
-		};
-
-		spi2: spi@11009000 {
-			compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
-			reg = <0 0x11009000 0 0x100>;
-			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-				 <&topckgen CLK_TOP_SPI_SEL>,
-				 <&infracfg CLK_INFRA_104M_SPI2_BCK>,
-				 <&infracfg CLK_INFRA_66M_SPI2_HCK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk",
-				      "spi-hclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		fan: pwm-fan {
-			compatible = "pwm-fan";
-			/* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
-			cooling-levels = <0 128 255>;
-			#cooling-cells = <2>;
-			#thermal-sensor-cells = <1>;
-			status = "disabled";
-		};
-
-		lvts: lvts@1100a000 {
-			compatible = "mediatek,mt7988-lvts";
-			reg = <0 0x1100a000 0 0x1000>;
-			clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
-			clock-names = "lvts_clk";
-			nvmem-cells = <&lvts_calibration>;
-			nvmem-cell-names = "e_data1";
-			#thermal-sensor-cells = <1>;
-		};
-
-		ssusb0: usb@11190000 {
-			compatible = "mediatek,mt7988-xhci",
-				     "mediatek,mtk-xhci";
-			reg = <0 0x11190000 0 0x2e00>,
-			      <0 0x11193e00 0 0x0100>;
-			reg-names = "mac", "ippc";
-			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
-			phys = <&xphyu2port0 PHY_TYPE_USB2>,
-			       <&xphyu3port0 PHY_TYPE_USB3>;
-			clocks = <&infracfg CLK_INFRA_USB_SYS>,
-				 <&infracfg CLK_INFRA_USB_XHCI>,
-				 <&infracfg CLK_INFRA_USB_REF>,
-				 <&infracfg CLK_INFRA_66M_USB_HCK>,
-				 <&infracfg CLK_INFRA_133M_USB_HCK>;
-			clock-names = "sys_ck",
-				      "xhci_ck",
-				      "ref_ck",
-				      "mcu_ck",
-				      "dma_ck";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			mediatek,p0_speed_fixup;
-			status = "disabled";
-		};
-
-		ssusb1: usb@11200000 {
-			compatible = "mediatek,mt7988-xhci",
-				     "mediatek,mtk-xhci";
-			reg = <0 0x11200000 0 0x2e00>,
-			      <0 0x11203e00 0 0x0100>;
-			reg-names = "mac", "ippc";
-			interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
-			phys = <&tphyu2port0 PHY_TYPE_USB2>,
-			       <&tphyu3port0 PHY_TYPE_USB3>;
-			clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
-				 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
-				 <&infracfg CLK_INFRA_USB_CK_P1>,
-				 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
-				 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
-			clock-names = "sys_ck",
-				      "xhci_ck",
-				      "ref_ck",
-				      "mcu_ck",
-				      "dma_ck";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			status = "disabled";
-		};
-
-		afe: audio-controller@11210000 {
-			compatible = "mediatek,mt79xx-audio";
-			reg = <0 0x11210000 0 0x9000>;
-			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
-				 <&infracfg CLK_INFRA_AUD_26M>,
-				 <&infracfg CLK_INFRA_AUD_L>,
-				 <&infracfg CLK_INFRA_AUD_AUD>,
-				 <&infracfg CLK_INFRA_AUD_EG2>,
-				 <&topckgen CLK_TOP_AUD_SEL>,
-				 <&topckgen CLK_TOP_AUD_I2S_M>;
-			clock-names = "aud_bus_ck",
-				      "aud_26m_ck",
-				      "aud_l_ck",
-				      "aud_aud_ck",
-				      "aud_eg2_ck",
-				      "aud_sel",
-				      "aud_i2s_m";
-			assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
-					  <&topckgen CLK_TOP_A1SYS_SEL>,
-					  <&topckgen CLK_TOP_AUD_L_SEL>,
-					  <&topckgen CLK_TOP_A_TUNER_SEL>;
-			assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>,
-						 <&topckgen CLK_TOP_APLL2_D4>,
-						 <&apmixedsys CLK_APMIXED_APLL2>,
-						 <&topckgen CLK_TOP_APLL2_D4>;
-			status = "disabled";
-		};
-
-		mmc0: mmc@11230000 {
-			compatible = "mediatek,mt7986-mmc",
-				     "mediatek,mt7981-mmc";
-			reg = <0 0x11230000 0 0x1000>,
-			      <0 0x11D60000 0 0x1000>;
-			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_MSDC400>,
-				 <&infracfg CLK_INFRA_MSDC2_HCK>,
-				 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
-				 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
-			assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
-					  <&topckgen CLK_TOP_EMMC_400M_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
-						 <&apmixedsys CLK_APMIXED_MSDCPLL>;
-			clock-names = "source",
-				      "hclk",
-				      "axi_cg",
-				      "ahb_cg";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		pcie2: pcie@11280000 {
-			compatible = "mediatek,mt7988-pcie",
-				     "mediatek,mt7986-pcie",
-				     "mediatek,mt8192-pcie";
-			reg = <0 0x11280000 0 0x2000>;
-			reg-names = "pcie-mac";
-			ranges = <0x81000000 0x00 0x20000000 0x00
-				  0x20000000 0x00 0x00200000>,
-				 <0x82000000 0x00 0x20200000 0x00
-				  0x20200000 0x00 0x07e00000>;
-			device_type = "pci";
-			linux,pci-domain = <3>;
-			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
-			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
-				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
-				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
-			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pcie2_pins>;
-			phys = <&xphyu3port0 PHY_TYPE_PCIE>;
-			phy-names = "pcie-phy";
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0x7>;
-			interrupt-map = <0 0 0 1 &pcie_intc2 0>,
-					<0 0 0 2 &pcie_intc2 1>,
-					<0 0 0 3 &pcie_intc2 2>,
-					<0 0 0 4 &pcie_intc2 3>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-			status = "disabled";
-
-			pcie_intc2: interrupt-controller {
-				#address-cells = <0>;
-				#interrupt-cells = <1>;
-				interrupt-controller;
-			};
-		};
-
-		pcie3: pcie@11290000 {
-			compatible = "mediatek,mt7988-pcie",
-				     "mediatek,mt7986-pcie",
-				     "mediatek,mt8192-pcie";
-			reg = <0 0x11290000 0 0x2000>;
-			reg-names = "pcie-mac";
-			ranges = <0x81000000 0x00 0x28000000 0x00
-				  0x28000000 0x00 0x00200000>,
-				 <0x82000000 0x00 0x28200000 0x00
-				  0x28200000 0x00 0x07e00000>;
-			device_type = "pci";
-			linux,pci-domain = <2>;
-			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
-			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
-				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
-				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
-			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pcie3_pins>;
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0x7>;
-			interrupt-map = <0 0 0 1 &pcie_intc3 0>,
-					<0 0 0 2 &pcie_intc3 1>,
-					<0 0 0 3 &pcie_intc3 2>,
-					<0 0 0 4 &pcie_intc3 3>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-			status = "disabled";
-
-			pcie_intc3: interrupt-controller {
-				#address-cells = <0>;
-				#interrupt-cells = <1>;
-				interrupt-controller;
-			};
-		};
-
-		pcie0: pcie@11300000 {
-			compatible = "mediatek,mt7988-pcie",
-				     "mediatek,mt7986-pcie",
-				     "mediatek,mt8192-pcie";
-			reg = <0 0x11300000 0 0x2000>;
-			reg-names = "pcie-mac";
-			ranges = <0x81000000 0x00 0x30000000 0x00
-				  0x30000000 0x00 0x00200000>,
-				 <0x82000000 0x00 0x30200000 0x00
-				  0x30200000 0x00 0x07e00000>;
-			device_type = "pci";
-			linux,pci-domain = <0>;
-			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
-			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
-				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
-				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
-			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pcie0_pins>;
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0x7>;
-			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
-					<0 0 0 2 &pcie_intc0 1>,
-					<0 0 0 3 &pcie_intc0 2>,
-					<0 0 0 4 &pcie_intc0 3>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-			status = "disabled";
-
-			pcie_intc0: interrupt-controller {
-				#address-cells = <0>;
-				#interrupt-cells = <1>;
-				interrupt-controller;
-			};
-		};
-
-		pcie1: pcie@11310000 {
-			compatible = "mediatek,mt7988-pcie",
-				     "mediatek,mt7986-pcie",
-				     "mediatek,mt8192-pcie";
-			reg = <0 0x11310000 0 0x2000>;
-			reg-names = "pcie-mac";
-			ranges = <0x81000000 0x00 0x38000000 0x00
-				  0x38000000 0x00 0x00200000>,
-				 <0x82000000 0x00 0x38200000 0x00
-				  0x38200000 0x00 0x07e00000>;
-			device_type = "pci";
-			linux,pci-domain = <1>;
-			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
-			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
-				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
-				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
-			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pcie1_pins>;
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0x7>;
-			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
-					<0 0 0 2 &pcie_intc1 1>,
-					<0 0 0 3 &pcie_intc1 2>,
-					<0 0 0 4 &pcie_intc1 3>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-			status = "disabled";
-
-			pcie_intc1: interrupt-controller {
-				#address-cells = <0>;
-				#interrupt-cells = <1>;
-				interrupt-controller;
-			};
-		};
-
-		tphy: tphy@11c50000 {
-			compatible = "mediatek,mt7988",
-				     "mediatek,generic-tphy-v2";
-			ranges;
-			#address-cells = <2>;
-			#size-cells = <2>;
-			status = "disabled";
-
-			tphyu2port0: usb-phy@11c50000 {
-				reg = <0 0x11c50000 0 0x700>;
-				clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-			};
-
-			tphyu3port0: usb-phy@11c50700 {
-				reg = <0 0x11c50700 0 0x900>;
-				clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-				mediatek,usb3-pll-ssc-delta;
-				mediatek,usb3-pll-ssc-delta1;
-			};
-		};
-
-		topmisc: topmisc@11d10000 {
-			compatible = "mediatek,mt7988-topmisc", "syscon",
-				     "mediatek,mt7988-power-controller";
-			reg = <0 0x11d10000 0 0x10000>;
-			#clock-cells = <1>;
-			#power-domain-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		xphy: xphy@11e10000 {
-			compatible = "mediatek,mt7988",
-				     "mediatek,xsphy";
-			ranges;
-			#address-cells = <2>;
-			#size-cells = <2>;
-			status = "disabled";
-
-			xphyu2port0: usb-phy@11e10000 {
-				reg = <0 0x11e10000 0 0x400>;
-				clocks = <&infracfg CLK_INFRA_USB_UTMI>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-			};
-
-			xphyu3port0: usb-phy@11e13000 {
-				reg = <0 0x11e13400 0 0x500>;
-				clocks = <&infracfg CLK_INFRA_USB_PIPE>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-				mediatek,syscon-type = <&topmisc 0x218 0>;
-			};
-		};
-
-		xfi_pextp0: xfi-pextp@11f20000 {
-			compatible = "mediatek,mt7988-xfi-pextp",
-				     "mediatek,mt7988-xfi-pextp_0",
-				     "syscon";
-			reg = <0 0x11f20000 0 0x10000>;
-			#clock-cells = <1>;
-		};
-
-		xfi_pextp1: xfi-pextp@11f30000 {
-			compatible = "mediatek,mt7988-xfi-pextp",
-				     "mediatek,mt7988-xfi-pextp_1",
-				     "syscon";
-			reg = <0 0x11f30000 0 0x10000>;
-			#clock-cells = <1>;
-		};
-
-		xfi_pll: xfi-pll@11f40000 {
-			compatible = "mediatek,mt7988-xfi-pll", "syscon";
-			reg = <0 0x11f40000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		efuse: efuse@11f50000 {
-			compatible = "mediatek,efuse";
-			reg = <0 0x11f50000 0 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			lvts_calibration: calib@918 {
-				reg = <0x918 0x28>;
-			};
-
-			phy_calibration_p0: calib@940 {
-				reg = <0x940 0x10>;
-			};
-
-			phy_calibration_p1: calib@954 {
-				reg = <0x954 0x10>;
-			};
-
-			phy_calibration_p2: calib@968 {
-				reg = <0x968 0x10>;
-			};
-
-			phy_calibration_p3: calib@97c {
-				reg = <0x97c 0x10>;
-			};
-
-			cpufreq_calibration: calib@278 {
-				reg = <0x278 0x1>;
-			};
-		};
-
-		ethsys: syscon@15000000 {
-			compatible = "mediatek,mt7988-ethsys", "syscon";
-			reg = <0 0x15000000 0 0x1000>;
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-		};
-
-		switch: switch@15020000 {
-			compatible = "mediatek,mt7988-switch";
-			reg = <0 0x15020000 0 0x8000>;
-			interrupt-controller;
-			#interrupt-cells = <1>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&ethrst 0>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@0 {
-					reg = <0>;
-					label = "lan0";
-					phy-mode = "internal";
-					phy-handle = <&gsw_phy0>;
-				};
-
-				port@1 {
-					reg = <1>;
-					label = "lan1";
-					phy-mode = "internal";
-					phy-handle = <&gsw_phy1>;
-				};
-
-				port@2 {
-					reg = <2>;
-					label = "lan2";
-					phy-mode = "internal";
-					phy-handle = <&gsw_phy2>;
-				};
-
-				port@3 {
-					reg = <3>;
-					label = "lan3";
-					phy-mode = "internal";
-					phy-handle = <&gsw_phy3>;
-				};
-
-				port@6 {
-					reg = <6>;
-					ethernet = <&gmac0>;
-					phy-mode = "internal";
-
-					fixed-link {
-						speed = <10000>;
-						full-duplex;
-						pause;
-					};
-				};
-			};
-
-			mdio {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				mediatek,pio = <&pio>;
-
-				gsw_phy0: ethernet-phy@0 {
-					compatible = "ethernet-phy-ieee802.3-c22";
-					reg = <0>;
-					phy-mode = "internal";
-					nvmem-cells = <&phy_calibration_p0>;
-					nvmem-cell-names = "phy-cal-data";
-
-					leds {
-						#address-cells = <1>;
-						#size-cells = <0>;
-
-						gsw_phy0_led0: gsw-phy0-led0@0 {
-							reg = <0>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-
-						gsw_phy0_led1: gsw-phy0-led1@1 {
-							reg = <1>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-					};
-				};
-
-				gsw_phy1: ethernet-phy@1 {
-					compatible = "ethernet-phy-ieee802.3-c22";
-					reg = <1>;
-					phy-mode = "internal";
-					nvmem-cells = <&phy_calibration_p1>;
-					nvmem-cell-names = "phy-cal-data";
-
-					leds {
-						#address-cells = <1>;
-						#size-cells = <0>;
-
-						gsw_phy1_led0: gsw-phy1-led0@0 {
-							reg = <0>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-
-						gsw_phy1_led1: gsw-phy1-led1@1 {
-							reg = <1>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-					};
-				};
-
-				gsw_phy2: ethernet-phy@2 {
-					compatible = "ethernet-phy-ieee802.3-c22";
-					reg = <2>;
-					phy-mode = "internal";
-					nvmem-cells = <&phy_calibration_p2>;
-					nvmem-cell-names = "phy-cal-data";
-
-					leds {
-						#address-cells = <1>;
-						#size-cells = <0>;
-
-						gsw_phy2_led0: gsw-phy2-led0@0 {
-							reg = <0>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-
-						gsw_phy2_led1: gsw-phy2-led1@1 {
-							reg = <1>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-					};
-				};
-
-				gsw_phy3: ethernet-phy@3 {
-					compatible = "ethernet-phy-ieee802.3-c22";
-					reg = <3>;
-					phy-mode = "internal";
-					nvmem-cells = <&phy_calibration_p3>;
-					nvmem-cell-names = "phy-cal-data";
-
-					leds {
-						#address-cells = <1>;
-						#size-cells = <0>;
-
-						gsw_phy3_led0: gsw-phy3-led0@0 {
-							reg = <0>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-
-						gsw_phy3_led1: gsw-phy3-led1@1 {
-							reg = <1>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-					};
-				};
-			};
-		};
-
-		ethwarp: syscon@15031000 {
-			compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
-			reg = <0 0x15031000 0 0x1000>;
-			#clock-cells = <1>;
-
-			ethrst: reset-controller {
-				compatible = "ti,syscon-reset";
-				#reset-cells = <1>;
-				ti,reset-bits = <
-					0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE)
-				>;
-			};
-		};
-
-		eth: ethernet@15100000 {
-			compatible = "mediatek,mt7988-eth";
-			reg = <0 0x15100000 0 0x80000>,
-			      <0 0x15400000 0 0x380000>;
-			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
-				 <&ethsys CLK_ETHDMA_XGP2_EN>,
-				 <&ethsys CLK_ETHDMA_XGP3_EN>,
-				 <&ethsys CLK_ETHDMA_FE_EN>,
-				 <&ethsys CLK_ETHDMA_GP2_EN>,
-				 <&ethsys CLK_ETHDMA_GP1_EN>,
-				 <&ethsys CLK_ETHDMA_GP3_EN>,
-				 <&ethsys CLK_ETHDMA_ESW_EN>,
-				 <&ethsys CLK_ETHDMA_CRYPT0_EN>,
-				 <&sgmiisys0 CLK_SGM0_TX_EN>,
-				 <&sgmiisys0 CLK_SGM0_RX_EN>,
-				 <&sgmiisys1 CLK_SGM1_TX_EN>,
-				 <&sgmiisys1 CLK_SGM1_RX_EN>,
-				 <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
-				 <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
-				 <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
-				 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
-				 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
-				 <&topckgen CLK_TOP_SGM_0_SEL>,
-				 <&topckgen CLK_TOP_SGM_1_SEL>,
-				 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>,
-				 <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>,
-				 <&topckgen CLK_TOP_ETH_GMII_SEL>,
-				 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
-				 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
-				 <&topckgen CLK_TOP_ETH_SYS_SEL>,
-				 <&topckgen CLK_TOP_ETH_XGMII_SEL>,
-				 <&topckgen CLK_TOP_ETH_MII_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_500M_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
-			clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
-				      "gp3", "esw", "crypto", "sgmii_tx250m",
-				      "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
-				      "ethwarp_wocpu2", "ethwarp_wocpu1",
-				      "ethwarp_wocpu0", "top_usxgmii0_sel",
-				      "top_usxgmii1_sel", "top_sgm0_sel",
-				      "top_sgm1_sel", "top_xfi_phy0_xtal_sel",
-				      "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel",
-				      "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
-				      "top_eth_sys_sel", "top_eth_xgmii_sel",
-				      "top_eth_mii_sel", "top_netsys_sel",
-				      "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
-				      "top_netsys_sync_250m_sel",
-				      "top_netsys_ppefb_250m_sel",
-				      "top_netsys_warp_sel";
-			assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
-					  <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
-					  <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
-					  <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
-					  <&topckgen CLK_TOP_SGM_0_SEL>,
-					  <&topckgen CLK_TOP_SGM_1_SEL>;
-			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
-						 <&topckgen CLK_TOP_NET1PLL_D4>,
-						 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
-						 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
-						 <&apmixedsys CLK_APMIXED_SGMPLL>,
-						 <&apmixedsys CLK_APMIXED_SGMPLL>;
-			mediatek,ethsys = <&ethsys>;
-			mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
-			mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
-			mediatek,xfi-pextp = <&xfi_pextp0>, <&xfi_pextp1>;
-			mediatek,xfi-pll = <&xfi_pll>;
-			mediatek,infracfg = <&topmisc>;
-			mediatek,toprgu = <&watchdog>;
-			#reset-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			gmac0: mac@0 {
-				compatible = "mediatek,eth-mac";
-				reg = <0>;
-				phy-mode = "internal";
-				status = "disabled";
-
-				fixed-link {
-					speed = <10000>;
-					full-duplex;
-					pause;
-				};
-			};
-
-			gmac1: mac@1 {
-				compatible = "mediatek,eth-mac";
-				reg = <1>;
-				status = "disabled";
-			};
-
-			gmac2: mac@2 {
-				compatible = "mediatek,eth-mac";
-				reg = <2>;
-				status = "disabled";
-			};
-
-			mdio_bus: mdio-bus {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				/* internal 2.5G PHY */
-				int_2p5g_phy: ethernet-phy@15 {
-					compatible = "ethernet-phy-ieee802.3-c45";
-					reg = <15>;
-					phy-mode = "internal";
-				};
-			};
-		};
-
-		crypto: crypto@15600000 {
-			compatible = "inside-secure,safexcel-eip197b";
-			reg = <0 0x15600000 0 0x180000>;
-			interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "ring0", "ring1", "ring2", "ring3";
-			status = "okay";
-		};
-	};
-
-	thermal-zones {
-		cpu_thermal: cpu-thermal {
-			polling-delay-passive = <1000>;
-			polling-delay = <1000>;
-			thermal-sensors = <&lvts 0>;
-
-			trips {
-				cpu_trip_crit: crit {
-					temperature = <125000>;
-					hysteresis = <2000>;
-					type = "critical";
-				};
-
-				cpu_trip_hot: hot {
-					temperature = <120000>;
-					hysteresis = <2000>;
-					type = "hot";
-				};
-
-				cpu_trip_active_high: active-high {
-					temperature = <115000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_med: active-med {
-					temperature = <85000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_low: active-low {
-					temperature = <40000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-			};
-
-			cooling-maps {
-				cpu-active-high {
-				/* active: set fan to cooling level 2 */
-					cooling-device = <&fan 3 3>;
-					trip = <&cpu_trip_active_high>;
-				};
-
-				cpu-active-low {
-				/* active: set fan to cooling level 1 */
-					cooling-device = <&fan 2 2>;
-					trip = <&cpu_trip_active_med>;
-				};
-
-				cpu-passive {
-				/* passive: set fan to cooling level 0 */
-					cooling-device = <&fan 1 1>;
-					trip = <&cpu_trip_active_low>;
-				};
-			};
-		};
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-	};
-};

target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-apmixed.c

@@ -1,102 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- * Author: Wenzhen Yu <[email protected]>
- * Author: Jianhui Zhao <[email protected]>
- * Author: Daniel Golle <[email protected]>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-#include <linux/clk.h>
-
-#define MT7981_PLL_FMAX (2500UL * MHZ)
-#define CON0_MT7981_RST_BAR BIT(27)
-
-#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \
-		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift,         \
-		 _div_table, _parent_name)                                     \
-	{                                                                      \
-		.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg,    \
-		.en_mask = _en_mask, .flags = _flags,                          \
-		.rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX,  \
-		.pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
-		.tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg,                  \
-		.pcw_shift = _pcw_shift, .div_table = _div_table,              \
-		.parent_name = _parent_name,                                   \
-	}
-
-#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,   \
-	    _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift)                       \
-	PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \
-		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL,   \
-		 "clkxtal")
-
-static const struct mtk_pll_data plls[] = {
-	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO,
-	    32, 0x0200, 4, 0, 0x0204, 0),
-	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
-	    0x0210, 4, 0, 0x0214, 0),
-	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
-	    0x0220, 4, 0, 0x0224, 0),
-	PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32,
-	    0x0230, 4, 0, 0x0234, 0),
-	PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32,
-	    0x0240, 4, 0, 0x0244, 0),
-	PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32,
-	    0x0250, 4, 0, 0x0254, 0),
-	PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32,
-	    0x0260, 4, 0, 0x0264, 0),
-	PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
-	    0x0278, 4, 0, 0x027C, 0),
-};
-
-static const struct of_device_id of_match_clk_mt7981_apmixed[] = {
-	{ .compatible = "mediatek,mt7981-apmixedsys", },
-	{}
-};
-
-static int clk_mt7981_apmixed_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-
-	clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_apmixed_data;
-	}
-	return r;
-
-free_apmixed_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static struct platform_driver clk_mt7981_apmixed_drv = {
-	.probe = clk_mt7981_apmixed_probe,
-	.driver = {
-		.name = "clk-mt7981-apmixed",
-		.of_match_table = of_match_clk_mt7981_apmixed,
-	},
-};
-builtin_platform_driver(clk_mt7981_apmixed_drv);

target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-eth.c

@@ -1,139 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- * Author: Wenzhen Yu <[email protected]>
- * Author: Jianhui Zhao <[email protected]>
- * Author: Daniel Golle <[email protected]>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-
-#include "clk-mtk.h"
-#include "clk-gate.h"
-
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-
-static const struct mtk_gate_regs sgmii0_cg_regs = {
-	.set_ofs = 0xE4,
-	.clr_ofs = 0xE4,
-	.sta_ofs = 0xE4,
-};
-
-#define GATE_SGMII0(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &sgmii0_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
-	}
-
-static const struct mtk_gate sgmii0_clks[] __initconst = {
-	GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2),
-	GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3),
-	GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4),
-	GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5),
-};
-
-static const struct mtk_gate_regs sgmii1_cg_regs = {
-	.set_ofs = 0xE4,
-	.clr_ofs = 0xE4,
-	.sta_ofs = 0xE4,
-};
-
-#define GATE_SGMII1(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &sgmii1_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
-	}
-
-static const struct mtk_gate sgmii1_clks[] __initconst = {
-	GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2),
-	GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3),
-	GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4),
-	GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5),
-};
-
-static const struct mtk_gate_regs eth_cg_regs = {
-	.set_ofs = 0x30,
-	.clr_ofs = 0x30,
-	.sta_ofs = 0x30,
-};
-
-#define GATE_ETH(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &eth_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
-	}
-
-static const struct mtk_gate eth_clks[] __initconst = {
-	GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6),
-	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7),
-	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8),
-	GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15),
-};
-
-static void __init mtk_sgmiisys_0_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
-
-	mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7981-sgmiisys_0",
-	       mtk_sgmiisys_0_init);
-
-static void __init mtk_sgmiisys_1_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
-
-	mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7981-sgmiisys_1",
-	       mtk_sgmiisys_1_init);
-
-static void __init mtk_ethsys_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
-
-	mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7981-ethsys", mtk_ethsys_init);

target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-infracfg.c

@@ -1,235 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- * Author: Wenzhen Yu <[email protected]>
- * Author: Jianhui Zhao <[email protected]>
- * Author: Daniel Golle <[email protected]>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-#include <linux/clk.h>
-
-static DEFINE_SPINLOCK(mt7981_clk_lock);
-
-static const struct mtk_fixed_factor infra_divs[] = {
-	FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2),
-};
-
-static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
-								"uart_sel" };
-
-static const char *const infra_spi0_parents[] __initconst = { "i2c_sel",
-							      "spi_sel" };
-
-static const char *const infra_spi1_parents[] __initconst = { "i2c_sel",
-							      "spim_mst_sel" };
-
-static const char *const infra_pwm1_parents[] __initconst = { "pwm_sel" };
-
-static const char *const infra_pwm_bsel_parents[] __initconst = {
-	"cb_rtc_32p7k", "csw_f26m_sel", "infra_66m_mck", "pwm_sel"
-};
-
-static const char *const infra_pcie_parents[] __initconst = {
-	"cb_rtc_32p7k", "csw_f26m_sel", "cb_cksq_40m", "pextp_tl_ck_sel"
-};
-
-static const struct mtk_mux infra_muxes[] = {
-	/* MODULE_CLK_SEL_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
-			     infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
-			     infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel",
-			     infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
-			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
-			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel",
-			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
-			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
-			     2, -1, -1, -1),
-	/* MODULE_CLK_SEL_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
-			     infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
-			     -1, -1, -1),
-};
-
-static const struct mtk_gate_regs infra0_cg_regs = {
-	.set_ofs = 0x40,
-	.clr_ofs = 0x44,
-	.sta_ofs = 0x48,
-};
-
-static const struct mtk_gate_regs infra1_cg_regs = {
-	.set_ofs = 0x50,
-	.clr_ofs = 0x54,
-	.sta_ofs = 0x58,
-};
-
-static const struct mtk_gate_regs infra2_cg_regs = {
-	.set_ofs = 0x60,
-	.clr_ofs = 0x64,
-	.sta_ofs = 0x68,
-};
-
-#define GATE_INFRA0(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra0_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-#define GATE_INFRA1(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra1_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-#define GATE_INFRA2(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra2_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-static const struct mtk_gate infra_clks[] = {
-	/* INFRA0 */
-	GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0),
-	GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1),
-	GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
-	GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
-	GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
-	GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi", 6),
-
-	GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi", 8),
-	GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
-	GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l", 10),
-	GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys", 11),
-	GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner", 13),
-	GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
-		    14),
-	GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15),
-	GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16),
-	GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24),
-	GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
-	GATE_INFRA0(CLK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27),
-	/* INFRA1 */
-	GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
-	GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_bck", 1),
-	GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
-	GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
-	GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
-	GATE_INFRA1(CLK_INFRA_SPI2_CK, "infra_spi2", "infra_spi2_sel", 6),
-	GATE_INFRA1(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7),
-	GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x", 8),
-	GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_bck", 9),
-	GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10),
-	GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
-	GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
-	GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck",
-		    13),
-	GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck",
-		    14),
-	GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "cb_rtc_32k", 15),
-	GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_400m", 16),
-	GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_208m", 17),
-	GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi", 18),
-	GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "sysaxi", 19),
-	GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
-	GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21),
-	GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x", 23),
-	GATE_INFRA1(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "sysaxi", 25),
-	GATE_INFRA1(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26),
-	/* INFRA2 */
-	GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi", 0),
-	GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "sysaxi", 1),
-	GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys", 2),
-	GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_ref", 3),
-	GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl", 12),
-	GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m",
-		    13),
-	GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m", 14),
-	GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi", 15),
-};
-
-static int clk_mt7981_infracfg_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) +
-		 ARRAY_SIZE(infra_clks);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
-	mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
-			       &mt7981_clk_lock, clk_data);
-	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_infracfg_data;
-	}
-	return r;
-
-free_infracfg_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct of_device_id of_match_clk_mt7981_infracfg[] = {
-	{ .compatible = "mediatek,mt7981-infracfg", },
-	{}
-};
-
-static struct platform_driver clk_mt7981_infracfg_drv = {
-	.probe = clk_mt7981_infracfg_probe,
-	.driver = {
-		.name = "clk-mt7981-infracfg",
-		.of_match_table = of_match_clk_mt7981_infracfg,
-	},
-};
-builtin_platform_driver(clk_mt7981_infracfg_drv);

target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-topckgen.c

@@ -1,450 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- * Author: Wenzhen Yu <[email protected]>
- * Author: Jianhui Zhao <[email protected]>
- */
-
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-#include <linux/clk.h>
-
-static DEFINE_SPINLOCK(mt7981_clk_lock);
-
-static const struct mtk_fixed_factor top_divs[] = {
-	FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1),
-	FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1),
-	FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2),
-	FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3),
-	FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2),
-	FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4),
-	FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8),
-	FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16),
-	FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1),
-	FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2),
-	FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3),
-	FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15),
-	FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4),
-	FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6),
-	FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12),
-	FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8),
-	FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1),
-	FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
-	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
-	FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1),
-	FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4),
-	FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5),
-	FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10),
-	FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20),
-	FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8),
-	FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16),
-	FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32),
-	FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1),
-	FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2),
-	FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4),
-	FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8),
-	FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16),
-	FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6),
-	FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1),
-	FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1),
-	FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2),
-	FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250),
-	FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220),
-	FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1),
-	FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1),
-	FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1),
-	FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1),
-	FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1),
-	FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1),
-	FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1),
-	FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1),
-	FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1),
-	FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1),
-	FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1),
-	FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1),
-	FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1),
-	FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1),
-	FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1),
-	FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1),
-	FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1),
-	FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1),
-	FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1),
-	FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1),
-	FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1),
-	FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1),
-	FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1),
-	FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1),
-	FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1),
-	FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1),
-	FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1),
-	FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1),
-	FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1),
-	FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1),
-	FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1),
-	FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1),
-	FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1),
-	FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1),
-	FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1),
-	FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1),
-	FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1),
-	FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1),
-};
-
-static const char * const nfi1x_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_mm_d4",
-	"net1_d8_d2",
-	"cb_net2_d6",
-	"cb_m_d4",
-	"cb_mm_d8",
-	"net1_d8_d4",
-	"cb_m_d8"
-};
-
-static const char * const spinfi_parents[] __initconst = {
-	"cksq_40m_d2",
-	"cb_cksq_40m",
-	"net1_d5_d4",
-	"cb_m_d4",
-	"cb_mm_d8",
-	"net1_d8_d4",
-	"mm_d6_d2",
-	"cb_m_d8"
-};
-
-static const char * const spi_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_m_d2",
-	"cb_mm_d4",
-	"net1_d8_d2",
-	"cb_net2_d6",
-	"net1_d5_d4",
-	"cb_m_d4",
-	"net1_d8_d4"
-};
-
-static const char * const uart_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_m_d8",
-	"m_d8_d2"
-};
-
-static const char * const pwm_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d8_d2",
-	"net1_d5_d4",
-	"cb_m_d4",
-	"m_d8_d2",
-	"cb_rtc_32k"
-};
-
-static const char * const i2c_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d5_d4",
-	"cb_m_d4",
-	"net1_d8_d4"
-};
-
-static const char * const pextp_tl_ck_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d5_d4",
-	"cb_m_d4",
-	"cb_rtc_32k"
-};
-
-static const char * const emmc_208m_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_m_d2",
-	"cb_net2_d4",
-	"cb_apll2_196m",
-	"cb_mm_d4",
-	"net1_d8_d2",
-	"cb_mm_d6"
-};
-
-static const char * const emmc_400m_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net2_d2",
-	"cb_mm_d2",
-	"cb_net2_d2"
-};
-
-static const char * const csw_f26m_parents[] __initconst = {
-	"cksq_40m_d2",
-	"m_d8_d2"
-};
-
-static const char * const dramc_md32_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_m_d2",
-	"cb_wedmcu_208m"
-};
-
-static const char * const sysaxi_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d8_d2"
-};
-
-static const char * const sysapb_parents[] __initconst = {
-	"cb_cksq_40m",
-	"m_d3_d2"
-};
-
-static const char * const arm_db_main_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net2_d6"
-};
-
-static const char * const ap2cnn_host_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d8_d4"
-};
-
-static const char * const netsys_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_mm_d2"
-};
-
-static const char * const netsys_500m_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net1_d5"
-};
-
-static const char * const netsys_mcu_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_mm_720m",
-	"cb_net1_d4",
-	"cb_net1_d5",
-	"cb_m_416m"
-};
-
-static const char * const netsys_2x_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net2_800m",
-	"cb_mm_720m"
-};
-
-static const char * const sgm_325m_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_sgm_325m"
-};
-
-static const char * const sgm_reg_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net2_d4"
-};
-
-static const char * const eip97b_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net1_d5",
-	"cb_m_416m",
-	"cb_mm_d2",
-	"net1_d5_d2"
-};
-
-static const char * const aud_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_apll2_196m"
-};
-
-static const char * const a1sys_parents[] __initconst = {
-	"cb_cksq_40m",
-	"apll2_d4"
-};
-
-static const char * const aud_l_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_apll2_196m",
-	"m_d8_d2"
-};
-
-static const char * const a_tuner_parents[] __initconst = {
-	"cb_cksq_40m",
-	"apll2_d4",
-	"m_d8_d2"
-};
-
-static const char * const u2u3_parents[] __initconst = {
-	"cb_cksq_40m",
-	"m_d8_d2"
-};
-
-static const char * const u2u3_sys_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d5_d4"
-};
-
-static const char * const usb_frmcnt_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_mm_d3_d5"
-};
-
-static const struct mtk_mux top_muxes[] = {
-	/* CLK_CFG_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
-			     0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
-			     0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
-			     0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
-			     0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
-	/* CLK_CFG_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
-			     0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
-			     0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
-			     0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
-			     pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31,
-			     0x1C0, 7),
-	/* CLK_CFG_2 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel",
-			     emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7,
-			     0x1C0, 8),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
-			     emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15,
-			     0x1C0, 9),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
-				   csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23,
-				   0x1C0, 10,
-				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
-				   csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1,
-				   31, 0x1C0, 11,
-				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-	/* CLK_CFG_3 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
-				   dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2,
-				   7, 0x1C0, 12,
-				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
-				   sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15,
-				   0x1C0, 13,
-				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
-				   sysapb_parents, 0x030, 0x034, 0x038, 16, 1,
-				   23, 0x1C0, 14,
-				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
-			     arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31,
-			     0x1C0, 15),
-	/* CLK_CFG_4 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
-			     ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7,
-			     0x1C0, 16),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
-			     0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
-			     netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23,
-			     0x1C0, 18),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
-			     netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
-			     0x1C0, 19),
-	/* CLK_CFG_5 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
-			     netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
-			     0x1C0, 20),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
-			     sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
-			     0x1C0, 21),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
-			     0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents,
-			     0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
-	/* CLK_CFG_6 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
-			     csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1,
-			     7, 0x1C0, 24),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x060,
-			     0x064, 0x068, 8, 1, 15, 0x1C0, 25),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
-			     0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
-			     0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27),
-	/* CLK_CFG_7 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
-			     a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7,
-			     0x1C0, 28),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x070,
-			     0x074, 0x078, 8, 1, 15, 0x1C0, 29),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
-			     u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23,
-			     0x1C0, 30),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
-			     u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31,
-			     0x1C4, 0),
-	/* CLK_CFG_8 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
-			     usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7,
-			     0x1C4, 1),
-};
-
-static struct mtk_composite top_aud_divs[] = {
-	DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud",
-		0x0420, 0, 0x0420, 8, 8),
-};
-
-static int clk_mt7981_topckgen_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(top_divs) + ARRAY_SIZE(top_muxes) +
-		 ARRAY_SIZE(top_aud_divs);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
-	mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
-			       &mt7981_clk_lock, clk_data);
-	mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), base,
-                        &mt7981_clk_lock, clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_topckgen_data;
-	}
-	return r;
-
-free_topckgen_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct of_device_id of_match_clk_mt7981_topckgen[] = {
-	{ .compatible = "mediatek,mt7981-topckgen", },
-	{}
-};
-
-static struct platform_driver clk_mt7981_topckgen_drv = {
-	.probe = clk_mt7981_topckgen_probe,
-	.driver = {
-		.name = "clk-mt7981-topckgen",
-		.of_match_table = of_match_clk_mt7981_topckgen,
-	},
-};
-builtin_platform_driver(clk_mt7981_topckgen_drv);

target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-apmixed.c

@@ -1,100 +0,0 @@
-// SPDX-License-Identifier: GPL-1.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- * Author: Wenzhen Yu <[email protected]>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mt7986-clk.h>
-#include <linux/clk.h>
-
-#define MT7986_PLL_FMAX (2500UL * MHZ)
-#define CON0_MT7986_RST_BAR BIT(27)
-
-#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \
-		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift,         \
-		 _div_table, _parent_name)                                     \
-	{                                                                      \
-		.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg,    \
-		.en_mask = _en_mask, .flags = _flags,                          \
-		.rst_bar_mask = CON0_MT7986_RST_BAR, .fmax = MT7986_PLL_FMAX,  \
-		.pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
-		.tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg,                  \
-		.pcw_shift = _pcw_shift, .div_table = _div_table,              \
-		.parent_name = _parent_name,                                   \
-	}
-
-#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,   \
-	    _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift)                       \
-	PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \
-		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL,   \
-		 "clkxtal")
-
-static const struct mtk_pll_data plls[] = {
-	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, 0, 32,
-	    0x0200, 4, 0, 0x0204, 0),
-	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
-	    0x0210, 4, 0, 0x0214, 0),
-	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
-	    0x0220, 4, 0, 0x0224, 0),
-	PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x00000001, 0, 32,
-	    0x0230, 4, 0, 0x0234, 0),
-	PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x00000001, 0,
-	    32, 0x0240, 4, 0, 0x0244, 0),
-	PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025c, 0x00000001, 0, 32,
-	    0x0250, 4, 0, 0x0254, 0),
-	PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, 0x0260,
-	    4, 0, 0x0264, 0),
-	PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
-	    0x0278, 4, 0, 0x027c, 0),
-};
-
-static const struct of_device_id of_match_clk_mt7986_apmixed[] = {
-	{ .compatible = "mediatek,mt7986-apmixedsys", },
-	{}
-};
-
-static int clk_mt7986_apmixed_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-
-	clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_apmixed_data;
-	}
-	return r;
-
-free_apmixed_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static struct platform_driver clk_mt7986_apmixed_drv = {
-	.probe = clk_mt7986_apmixed_probe,
-	.driver = {
-		.name = "clk-mt7986-apmixed",
-		.of_match_table = of_match_clk_mt7986_apmixed,
-	},
-};
-builtin_platform_driver(clk_mt7986_apmixed_drv);

target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-eth.c

@@ -1,132 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- * Author: Wenzhen Yu <[email protected]>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-
-#include "clk-mtk.h"
-#include "clk-gate.h"
-
-#include <dt-bindings/clock/mt7986-clk.h>
-
-static const struct mtk_gate_regs sgmii0_cg_regs = {
-	.set_ofs = 0xe4,
-	.clr_ofs = 0xe4,
-	.sta_ofs = 0xe4,
-};
-
-#define GATE_SGMII0(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &sgmii0_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                        \
-	}
-
-static const struct mtk_gate sgmii0_clks[] __initconst = {
-	GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en", "top_xtal", 2),
-	GATE_SGMII0(CLK_SGMII0_RX250M_EN, "sgmii0_rx250m_en", "top_xtal", 3),
-	GATE_SGMII0(CLK_SGMII0_CDR_REF, "sgmii0_cdr_ref", "top_xtal", 4),
-	GATE_SGMII0(CLK_SGMII0_CDR_FB, "sgmii0_cdr_fb", "top_xtal", 5),
-};
-
-static const struct mtk_gate_regs sgmii1_cg_regs = {
-	.set_ofs = 0xe4,
-	.clr_ofs = 0xe4,
-	.sta_ofs = 0xe4,
-};
-
-#define GATE_SGMII1(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &sgmii1_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                        \
-	}
-
-static const struct mtk_gate sgmii1_clks[] __initconst = {
-	GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en", "top_xtal", 2),
-	GATE_SGMII1(CLK_SGMII1_RX250M_EN, "sgmii1_rx250m_en", "top_xtal", 3),
-	GATE_SGMII1(CLK_SGMII1_CDR_REF, "sgmii1_cdr_ref", "top_xtal", 4),
-	GATE_SGMII1(CLK_SGMII1_CDR_FB, "sgmii1_cdr_fb", "top_xtal", 5),
-};
-
-static const struct mtk_gate_regs eth_cg_regs = {
-	.set_ofs = 0x30,
-	.clr_ofs = 0x30,
-	.sta_ofs = 0x30,
-};
-
-#define GATE_ETH(_id, _name, _parent, _shift)                                  \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &eth_cg_regs, .shift = _shift,                         \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                        \
-	}
-
-static const struct mtk_gate eth_clks[] __initconst = {
-	GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x_sel", 6),
-	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m_sel", 7),
-	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m_sel", 8),
-	GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en", "netsys_mcu_sel", 14),
-	GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_mcu_sel", 15),
-};
-
-static void __init mtk_sgmiisys_0_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
-
-	mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7986-sgmiisys_0",
-	       mtk_sgmiisys_0_init);
-
-static void __init mtk_sgmiisys_1_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
-
-	mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7986-sgmiisys_1",
-	       mtk_sgmiisys_1_init);
-
-static void __init mtk_ethsys_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
-
-	mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7986-ethsys", mtk_ethsys_init);

target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-infracfg.c

@@ -1,224 +0,0 @@
-// SPDX-License-Identifier: GPL-1.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- * Author: Wenzhen Yu <[email protected]>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mt7986-clk.h>
-#include <linux/clk.h>
-
-static DEFINE_SPINLOCK(mt7986_clk_lock);
-
-static const struct mtk_fixed_factor infra_divs[] = {
-	FACTOR(CLK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", "sysaxi_sel", 1, 2),
-};
-
-static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
-							     "uart_sel" };
-
-static const char *const infra_spi_parents[] __initconst = { "i2c_sel",
-							     "spi_sel" };
-
-static const char *const infra_pwm_bsel_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_f26m_sel", "infra_sysaxi_d2", "pwm_sel"
-};
-
-static const char *const infra_pcie_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_f26m_sel", "top_xtal", "pextp_tl_ck_sel"
-};
-
-static const struct mtk_mux infra_muxes[] = {
-	/* MODULE_CLK_SEL_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
-			     infra_spi_parents, 0x0018, 0x0010, 0x0014, 4, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
-			     infra_spi_parents, 0x0018, 0x0010, 0x0014, 5, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
-			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 9,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
-			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 11,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
-			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
-			     2, -1, -1, -1),
-	/* MODULE_CLK_SEL_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
-			     infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
-			     -1, -1, -1),
-};
-
-static const struct mtk_gate_regs infra0_cg_regs = {
-	.set_ofs = 0x40,
-	.clr_ofs = 0x44,
-	.sta_ofs = 0x48,
-};
-
-static const struct mtk_gate_regs infra1_cg_regs = {
-	.set_ofs = 0x50,
-	.clr_ofs = 0x54,
-	.sta_ofs = 0x58,
-};
-
-static const struct mtk_gate_regs infra2_cg_regs = {
-	.set_ofs = 0x60,
-	.clr_ofs = 0x64,
-	.sta_ofs = 0x68,
-};
-
-#define GATE_INFRA0(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra0_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-#define GATE_INFRA1(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra1_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-#define GATE_INFRA2(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra2_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-static const struct mtk_gate infra_clks[] = {
-	/* INFRA0 */
-	GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_sysaxi_d2", 0),
-	GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_sysaxi_d2", 1),
-	GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
-	GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
-	GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
-	GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi_sel", 6),
-	GATE_INFRA0(CLK_INFRA_EIP97_CK, "infra_eip97", "eip_b_sel", 7),
-	GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi_sel", 8),
-	GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
-	GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l_sel", 10),
-	GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys_sel", 11),
-	GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner_sel", 13),
-	GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
-		    14),
-	GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_sysaxi_d2", 15),
-	GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_sysaxi_d2", 16),
-	GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_sysaxi_d2", 24),
-	GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
-	GATE_INFRA0(CLK_INFRA_TRNG_CK, "infra_trng", "sysaxi_sel", 26),
-	/* INFRA1 */
-	GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
-	GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_sel", 1),
-	GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
-	GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
-	GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
-	GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x_sel", 8),
-	GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_sel", 9),
-	GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_sysaxi_d2",
-		    10),
-	GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
-	GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
-	GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_sysaxi_d2",
-		    13),
-	GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_sysaxi_d2",
-		    14),
-	GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "top_rtc_32k", 15),
-	GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_416m_sel", 16),
-	GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_250m_sel",
-		    17),
-	GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi_sel",
-		    18),
-	GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "infra_sysaxi_d2",
-		    19),
-	GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
-	GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m_sel", 21),
-	GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x_sel", 23),
-	/* INFRA2 */
-	GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi_sel", 0),
-	GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "infra_sysaxi_d2",
-		    1),
-	GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys_sel", 2),
-	GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_sel", 3),
-	GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl_ck_sel", 12),
-	GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "top_xtal",
-		    13),
-	GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m_sel", 14),
-	GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi_sel", 15),
-};
-
-static int clk_mt7986_infracfg_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) +
-		 ARRAY_SIZE(infra_clks);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
-	mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
-			       &mt7986_clk_lock, clk_data);
-	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_infracfg_data;
-	}
-	return r;
-
-free_infracfg_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-
-}
-
-static const struct of_device_id of_match_clk_mt7986_infracfg[] = {
-	{ .compatible = "mediatek,mt7986-infracfg", },
-	{}
-};
-
-static struct platform_driver clk_mt7986_infracfg_drv = {
-	.probe = clk_mt7986_infracfg_probe,
-	.driver = {
-		.name = "clk-mt7986-infracfg",
-		.of_match_table = of_match_clk_mt7986_infracfg,
-	},
-};
-builtin_platform_driver(clk_mt7986_infracfg_drv);

target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-topckgen.c

@@ -1,342 +0,0 @@
-// SPDX-License-Identifier: GPL-1.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- * Author: Wenzhen Yu <[email protected]>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mt7986-clk.h>
-#include <linux/clk.h>
-
-static DEFINE_SPINLOCK(mt7986_clk_lock);
-
-static const struct mtk_fixed_clk top_fixed_clks[] = {
-	FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
-	FIXED_CLK(CLK_TOP_JTAG, "top_jtag", "clkxtal", 50000000),
-};
-
-static const struct mtk_fixed_factor top_divs[] = {
-	/* XTAL */
-	FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
-	FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
-	FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
-	/* MPLL */
-	FACTOR(CLK_TOP_MPLL_D2, "top_mpll_d2", "mpll", 1, 2),
-	FACTOR(CLK_TOP_MPLL_D4, "top_mpll_d4", "mpll", 1, 4),
-	FACTOR(CLK_TOP_MPLL_D8, "top_mpll_d8", "mpll", 1, 8),
-	FACTOR(CLK_TOP_MPLL_D8_D2, "top_mpll_d8_d2", "mpll", 1, 16),
-	FACTOR(CLK_TOP_MPLL_D3_D2, "top_mpll_d3_d2", "mpll", 1, 6),
-	/* MMPLL */
-	FACTOR(CLK_TOP_MMPLL_D2, "top_mmpll_d2", "mmpll", 1, 2),
-	FACTOR(CLK_TOP_MMPLL_D4, "top_mmpll_d4", "mmpll", 1, 4),
-	FACTOR(CLK_TOP_MMPLL_D8, "top_mmpll_d8", "mmpll", 1, 8),
-	FACTOR(CLK_TOP_MMPLL_D8_D2, "top_mmpll_d8_d2", "mmpll", 1, 16),
-	FACTOR(CLK_TOP_MMPLL_D3_D8, "top_mmpll_d3_d8", "mmpll", 1, 24),
-	FACTOR(CLK_TOP_MMPLL_U2PHY, "top_mmpll_u2phy", "mmpll", 1, 30),
-	/* APLL2 */
-	FACTOR(CLK_TOP_APLL2_D4, "top_apll2_d4", "apll2", 1, 4),
-	/* NET1PLL */
-	FACTOR(CLK_TOP_NET1PLL_D4, "top_net1pll_d4", "net1pll", 1, 4),
-	FACTOR(CLK_TOP_NET1PLL_D5, "top_net1pll_d5", "net1pll", 1, 5),
-	FACTOR(CLK_TOP_NET1PLL_D5_D2, "top_net1pll_d5_d2", "net1pll", 1, 10),
-	FACTOR(CLK_TOP_NET1PLL_D5_D4, "top_net1pll_d5_d4", "net1pll", 1, 20),
-	FACTOR(CLK_TOP_NET1PLL_D8_D2, "top_net1pll_d8_d2", "net1pll", 1, 16),
-	FACTOR(CLK_TOP_NET1PLL_D8_D4, "top_net1pll_d8_d4", "net1pll", 1, 32),
-	/* NET2PLL */
-	FACTOR(CLK_TOP_NET2PLL_D4, "top_net2pll_d4", "net2pll", 1, 4),
-	FACTOR(CLK_TOP_NET2PLL_D4_D2, "top_net2pll_d4_d2", "net2pll", 1, 8),
-	FACTOR(CLK_TOP_NET2PLL_D3_D2, "top_net2pll_d3_d2", "net2pll", 1, 2),
-	/* WEDMCUPLL */
-	FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "top_wedmcupll_d5_d2", "wedmcupll", 1,
-	       10),
-};
-
-static const char *const nfi1x_parents[] __initconst = { "top_xtal",
-							 "top_mmpll_d8",
-							 "top_net1pll_d8_d2",
-							 "top_net2pll_d3_d2",
-							 "top_mpll_d4",
-							 "top_mmpll_d8_d2",
-							 "top_wedmcupll_d5_d2",
-							 "top_mpll_d8" };
-
-static const char *const spinfi_parents[] __initconst = {
-	"top_xtal_d2",     "top_xtal",	"top_net1pll_d5_d4",
-	"top_mpll_d4",     "top_mmpll_d8_d2", "top_wedmcupll_d5_d2",
-	"top_mmpll_d3_d8", "top_mpll_d8"
-};
-
-static const char *const spi_parents[] __initconst = {
-	"top_xtal",	  "top_mpll_d2",	"top_mmpll_d8",
-	"top_net1pll_d8_d2", "top_net2pll_d3_d2",  "top_net1pll_d5_d4",
-	"top_mpll_d4",       "top_wedmcupll_d5_d2"
-};
-
-static const char *const uart_parents[] __initconst = { "top_xtal",
-							"top_mpll_d8",
-							"top_mpll_d8_d2" };
-
-static const char *const pwm_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d8_d2", "top_net1pll_d5_d4", "top_mpll_d4"
-};
-
-static const char *const i2c_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d5_d4", "top_mpll_d4", "top_net1pll_d8_d4"
-};
-
-static const char *const pextp_tl_ck_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d5_d4", "top_net2pll_d4_d2", "top_rtc_32k"
-};
-
-static const char *const emmc_250m_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d5_d2"
-};
-
-static const char *const emmc_416m_parents[] __initconst = { "top_xtal",
-							     "mpll" };
-
-static const char *const f_26m_adc_parents[] __initconst = { "top_xtal",
-							     "top_mpll_d8_d2" };
-
-static const char *const dramc_md32_parents[] __initconst = { "top_xtal",
-							      "top_mpll_d2" };
-
-static const char *const sysaxi_parents[] __initconst = { "top_xtal",
-							  "top_net1pll_d8_d2",
-							  "top_net2pll_d4" };
-
-static const char *const sysapb_parents[] __initconst = { "top_xtal",
-							  "top_mpll_d3_d2",
-							  "top_net2pll_d4_d2" };
-
-static const char *const arm_db_main_parents[] __initconst = {
-	"top_xtal", "top_net2pll_d3_d2"
-};
-
-static const char *const arm_db_jtsel_parents[] __initconst = { "top_jtag",
-								"top_xtal" };
-
-static const char *const netsys_parents[] __initconst = { "top_xtal",
-							  "top_mmpll_d4" };
-
-static const char *const netsys_500m_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d5"
-};
-
-static const char *const netsys_mcu_parents[] __initconst = {
-	"top_xtal", "wedmcupll", "top_mmpll_d2", "top_net1pll_d4",
-	"top_net1pll_d5"
-};
-
-static const char *const netsys_2x_parents[] __initconst = {
-	"top_xtal", "net2pll", "wedmcupll", "top_mmpll_d2"
-};
-
-static const char *const sgm_325m_parents[] __initconst = { "top_xtal",
-							    "sgmpll" };
-
-static const char *const sgm_reg_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d8_d4"
-};
-
-static const char *const a1sys_parents[] __initconst = { "top_xtal",
-							 "top_apll2_d4" };
-
-static const char *const conn_mcusys_parents[] __initconst = { "top_xtal",
-							       "top_mmpll_d2" };
-
-static const char *const eip_b_parents[] __initconst = { "top_xtal",
-							 "net2pll" };
-
-static const char *const aud_l_parents[] __initconst = { "top_xtal", "apll2",
-							 "top_mpll_d8_d2" };
-
-static const char *const a_tuner_parents[] __initconst = { "top_xtal",
-							   "top_apll2_d4",
-							   "top_mpll_d8_d2" };
-
-static const char *const u2u3_sys_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d5_d4"
-};
-
-static const char *const da_u2_refsel_parents[] __initconst = {
-	"top_xtal", "top_mmpll_u2phy"
-};
-
-static const struct mtk_mux top_muxes[] = {
-	/* CLK_CFG_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
-			     0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
-			     0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
-			     0x004, 0x008, 16, 3, 23, 0x1C0, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
-			     0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
-	/* CLK_CFG_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
-			     0x014, 0x018, 0, 2, 7, 0x1C0, 4),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
-			     0x014, 0x018, 8, 2, 15, 0x1C0, 5),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
-			     0x014, 0x018, 16, 2, 23, 0x1C0, 6),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
-			     pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2,
-			     31, 0x1C0, 7),
-	/* CLK_CFG_2 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
-			     emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7,
-			     0x1C0, 8),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel",
-			     emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15,
-			     0x1C0, 9),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",
-			     f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23,
-			     0x1C0, 10),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents,
-			     0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11),
-	/* CLK_CFG_3 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
-			     dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7,
-			     0x1C0, 12),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents,
-			     0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents,
-			     0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
-			     arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1,
-			     31, 0x1C0, 15),
-	/* CLK_CFG_4 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel",
-			     arm_db_jtsel_parents, 0x040, 0x044, 0x048, 0, 1, 7,
-			     0x1C0, 16),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
-			     0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
-			     netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1,
-			     23, 0x1C0, 18),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
-			     netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
-			     0x1C0, 19),
-	/* CLK_CFG_5 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
-			     netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
-			     0x1C0, 20),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
-			     sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
-			     0x1C0, 21),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
-			     sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23,
-			     0x1C0, 22),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
-			     0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23),
-	/* CLK_CFG_6 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel",
-			     conn_mcusys_parents, 0x060, 0x064, 0x068, 0, 1, 7,
-			     0x1C0, 24),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents,
-			     0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel",
-			     f_26m_adc_parents, 0x060, 0x064, 0x068, 16, 1, 23,
-			     0x1C0, 26),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
-			     f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31,
-			     0x1C0, 27),
-	/* CLK_CFG_7 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel",
-			     f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7,
-			     0x1C0, 28),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
-			     0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
-			     a_tuner_parents, 0x070, 0x074, 0x078, 16, 2, 23,
-			     0x1C0, 30),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents,
-			     0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0),
-	/* CLK_CFG_8 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
-			     u2u3_sys_parents, 0x080, 0x084, 0x088, 0, 1, 7,
-			     0x1C4, 1),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
-			     u2u3_sys_parents, 0x080, 0x084, 0x088, 8, 1, 15,
-			     0x1C4, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel",
-			     da_u2_refsel_parents, 0x080, 0x084, 0x088, 16, 1,
-			     23, 0x1C4, 3),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel",
-			     da_u2_refsel_parents, 0x080, 0x084, 0x088, 24, 1,
-			     31, 0x1C4, 4),
-	/* CLK_CFG_9 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
-			     sgm_reg_parents, 0x090, 0x094, 0x098, 0, 1, 7,
-			     0x1C4, 5),
-};
-
-static int clk_mt7986_topckgen_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) +
-		 ARRAY_SIZE(top_muxes);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
-				    clk_data);
-	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
-	mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
-			       &mt7986_clk_lock, clk_data);
-
-	clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAXI_SEL]);
-	clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAPB_SEL]);
-	clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_SEL]);
-	clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_MD32_SEL]);
-	clk_prepare_enable(clk_data->clks[CLK_TOP_F26M_SEL]);
-	clk_prepare_enable(clk_data->clks[CLK_TOP_SGM_REG_SEL]);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_topckgen_data;
-	}
-	return r;
-
-free_topckgen_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct of_device_id of_match_clk_mt7986_topckgen[] = {
-	{ .compatible = "mediatek,mt7986-topckgen", },
-	{}
-};
-
-static struct platform_driver clk_mt7986_topckgen_drv = {
-	.probe = clk_mt7986_topckgen_probe,
-	.driver = {
-		.name = "clk-mt7986-topckgen",
-		.of_match_table = of_match_clk_mt7986_topckgen,
-	},
-};
-builtin_platform_driver(clk_mt7986_topckgen_drv);

target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-apmixed.c

@@ -1,113 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- * Author: Xiufeng Li <[email protected]>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-
-#define MT7988_PLL_FMAX (2500UL * MHZ)
-#define MT7988_PCW_CHG_SHIFT 2
-
-#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
-		 _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,     \
-		 _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg,           \
-		 _div_table)                                                  \
-	{                                                                     \
-		.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg,   \
-		.en_mask = _en_mask, .flags = _flags,                         \
-		.rst_bar_mask = BIT(_rst_bar_mask), .fmax = MT7988_PLL_FMAX,  \
-		.pcwbits = _pcwbits, .pd_reg = _pd_reg,                       \
-		.pd_shift = _pd_shift, .tuner_reg = _tuner_reg,               \
-		.tuner_en_reg = _tuner_en_reg, .tuner_en_bit = _tuner_en_bit, \
-		.pcw_reg = _pcw_reg, .pcw_shift = _pcw_shift,                 \
-		.pcw_chg_reg = _pcw_chg_reg,                                  \
-		.pcw_chg_shift = MT7988_PCW_CHG_SHIFT,                        \
-		.div_table = _div_table, .parent_name = "clkxtal",            \
-	}
-
-#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask,      \
-	    _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,          \
-	    _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg)                \
-	PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
-		 _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,     \
-		 _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, NULL)
-
-static const struct mtk_pll_data plls[] = {
-	PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0,
-	    0, 32, 0x0104, 4, 0, 0, 0, 0x0108, 0, 0x0104),
-	PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR,
-	    23, 32, 0x0114, 4, 0, 0, 0, 0x0118, 0, 0x0114),
-	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001,
-	    HAVE_RST_BAR, 23, 32, 0x0124, 4, 0, 0, 0, 0x0128, 0, 0x0124),
-	PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32,
-	    0x0134, 4, 0x0704, 0x0700, 1, 0x0138, 0, 0x0134),
-	PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001,
-	    HAVE_RST_BAR, 23, 32, 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
-	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001,
-	    (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0154, 4, 0, 0, 0, 0x0158, 0,
-	    0x0154),
-	PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0,
-	    0, 32, 0x0164, 4, 0, 0, 0, 0x0168, 0, 0x0164),
-	PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32,
-	    0x0174, 4, 0, 0, 0, 0x0178, 0, 0x0174),
-	PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001,
-	    (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0204, 4, 0, 0, 0, 0x0208, 0,
-	    0x0204),
-	PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001,
-	    HAVE_RST_BAR, 23, 32, 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214),
-	PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001,
-	    HAVE_RST_BAR, 23, 32, 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304),
-	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0,
-	    32, 0x0314, 4, 0, 0, 0, 0x0318, 0, 0x0314),
-};
-
-static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
-	{
-		.compatible = "mediatek,mt7988-apmixedsys",
-	},
-	{}
-};
-
-static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_apmixed_data;
-	}
-	return r;
-
-free_apmixed_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static struct platform_driver clk_mt7988_apmixed_drv = {
-	.probe = clk_mt7988_apmixed_probe,
-	.driver = {
-		.name = "clk-mt7988-apmixed",
-		.of_match_table = of_match_clk_mt7988_apmixed,
-	},
-};
-builtin_platform_driver(clk_mt7988_apmixed_drv);

target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-eth.c

@@ -1,299 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- * Author: Xiufeng Li <[email protected]>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-
-static const struct mtk_gate_regs ethdma_cg_regs = {
-	.set_ofs = 0x30,
-	.clr_ofs = 0x30,
-	.sta_ofs = 0x30,
-};
-
-#define GATE_ETHDMA(_id, _name, _parent, _shift)                              \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &ethdma_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
-	}
-
-static const struct mtk_gate ethdma_clks[] = {
-	GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0),
-	GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1),
-	GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2),
-	GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6),
-	GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7),
-	GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8),
-	GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10),
-	GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16),
-	GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel",
-		    29),
-};
-
-static int clk_mt7988_ethsys_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(ethdma_clks));
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_gates(node, ethdma_clks, ARRAY_SIZE(ethdma_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_data;
-	}
-	return r;
-
-free_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct mtk_gate_regs sgmii0_cg_regs = {
-	.set_ofs = 0xe4,
-	.clr_ofs = 0xe4,
-	.sta_ofs = 0xe4,
-};
-
-#define GATE_SGMII0(_id, _name, _parent, _shift)                              \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &sgmii0_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
-	}
-
-static const struct mtk_gate sgmii0_clks[] = {
-	GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2),
-	GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3),
-};
-
-static int clk_mt7988_sgmii0_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_data;
-	}
-	return r;
-
-free_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct mtk_gate_regs sgmii1_cg_regs = {
-	.set_ofs = 0xe4,
-	.clr_ofs = 0xe4,
-	.sta_ofs = 0xe4,
-};
-
-#define GATE_SGMII1(_id, _name, _parent, _shift)                              \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &sgmii1_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
-	}
-
-static const struct mtk_gate sgmii1_clks[] = {
-	GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2),
-	GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3),
-};
-
-static int clk_mt7988_sgmii1_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_data;
-	}
-	return r;
-
-free_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct mtk_gate_regs ethwarp_cg_regs = {
-	.set_ofs = 0x14,
-	.clr_ofs = 0x14,
-	.sta_ofs = 0x14,
-};
-
-#define GATE_ETHWARP(_id, _name, _parent, _shift)                             \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &ethwarp_cg_regs, .shift = _shift,                    \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
-	}
-
-static const struct mtk_gate ethwarp_clks[] = {
-	GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
-		     "netsys_mcu_sel", 13),
-	GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
-		     "netsys_mcu_sel", 14),
-	GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
-		     "netsys_mcu_sel", 15),
-};
-
-static int clk_mt7988_ethwarp_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(ethwarp_clks));
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_gates(node, ethwarp_clks, ARRAY_SIZE(ethwarp_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_data;
-	}
-	return r;
-
-free_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct of_device_id of_match_clk_mt7988_ethsys[] = {
-	{
-		.compatible = "mediatek,mt7988-ethsys",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_ethsys_drv = {
-	.probe = clk_mt7988_ethsys_probe,
-	.driver = {
-		.name = "clk-mt7988-ethsys",
-		.of_match_table = of_match_clk_mt7988_ethsys,
-	},
-};
-builtin_platform_driver(clk_mt7988_ethsys_drv);
-
-static const struct of_device_id of_match_clk_mt7988_sgmii0[] = {
-	{
-		.compatible = "mediatek,mt7988-sgmiisys_0",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_sgmii0_drv = {
-	.probe = clk_mt7988_sgmii0_probe,
-	.driver = {
-		.name = "clk-mt7988-sgmiisys_0",
-		.of_match_table = of_match_clk_mt7988_sgmii0,
-	},
-};
-builtin_platform_driver(clk_mt7988_sgmii0_drv);
-
-static const struct of_device_id of_match_clk_mt7988_sgmii1[] = {
-	{
-		.compatible = "mediatek,mt7988-sgmiisys_1",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_sgmii1_drv = {
-	.probe = clk_mt7988_sgmii1_probe,
-	.driver = {
-		.name = "clk-mt7988-sgmiisys_1",
-		.of_match_table = of_match_clk_mt7988_sgmii1,
-	},
-};
-builtin_platform_driver(clk_mt7988_sgmii1_drv);
-
-static const struct of_device_id of_match_clk_mt7988_ethwarp[] = {
-	{
-		.compatible = "mediatek,mt7988-ethwarp",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_ethwarp_drv = {
-	.probe = clk_mt7988_ethwarp_probe,
-	.driver = {
-		.name = "clk-mt7988-ethwarp",
-		.of_match_table = of_match_clk_mt7988_ethwarp,
-	},
-};
-builtin_platform_driver(clk_mt7988_ethwarp_drv);

target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-infracfg.c

@@ -1,406 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- * Author: Xiufeng Li <[email protected]>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-
-static DEFINE_SPINLOCK(mt7988_clk_lock);
-
-static const char *const infra_mux_uart0_parents[] __initconst = {
-	"csw_infra_f26m_sel", "uart_sel"
-};
-
-static const char *const infra_mux_uart1_parents[] __initconst = {
-	"csw_infra_f26m_sel", "uart_sel"
-};
-
-static const char *const infra_mux_uart2_parents[] __initconst = {
-	"csw_infra_f26m_sel", "uart_sel"
-};
-
-static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel",
-								  "spi_sel" };
-
-static const char *const infra_mux_spi1_parents[] __initconst = {
-	"i2c_sel", "spim_mst_sel"
-};
-
-static const char *const infra_pwm_bck_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "sysaxi_sel", "pwm_sel"
-};
-
-static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
-	"pextp_tl_sel"
-};
-
-static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
-	"pextp_tl_p1_sel"
-};
-
-static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
-	"pextp_tl_p2_sel"
-};
-
-static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
-	"pextp_tl_p3_sel"
-};
-
-static const struct mtk_mux infra_muxes[] = {
-	/* MODULE_CLK_SEL_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
-			     infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014,
-			     0, 1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
-			     infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014,
-			     1, 1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
-			     infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014,
-			     2, 1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
-			     infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4,
-			     1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
-			     infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5,
-			     1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
-			     infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 6,
-			     1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 16,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 18,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 20,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 22,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 24,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 26,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 28,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 30,
-			     2, -1, -1, -1),
-	/* MODULE_CLK_SEL_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
-			     "infra_pcie_gfmux_tl_o_p0_sel",
-			     infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028,
-			     0x0020, 0x0024, 0, 2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
-			     "infra_pcie_gfmux_tl_o_p1_sel",
-			     infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028,
-			     0x0020, 0x0024, 2, 2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
-			     "infra_pcie_gfmux_tl_o_p2_sel",
-			     infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028,
-			     0x0020, 0x0024, 4, 2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
-			     "infra_pcie_gfmux_tl_o_p3_sel",
-			     infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028,
-			     0x0020, 0x0024, 6, 2, -1, -1, -1),
-};
-
-static const struct mtk_gate_regs infra0_cg_regs = {
-	.set_ofs = 0x10,
-	.clr_ofs = 0x14,
-	.sta_ofs = 0x18,
-};
-
-static const struct mtk_gate_regs infra1_cg_regs = {
-	.set_ofs = 0x40,
-	.clr_ofs = 0x44,
-	.sta_ofs = 0x48,
-};
-
-static const struct mtk_gate_regs infra2_cg_regs = {
-	.set_ofs = 0x50,
-	.clr_ofs = 0x54,
-	.sta_ofs = 0x58,
-};
-
-static const struct mtk_gate_regs infra3_cg_regs = {
-	.set_ofs = 0x60,
-	.clr_ofs = 0x64,
-	.sta_ofs = 0x68,
-};
-
-#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags)                \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &infra0_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_setclr, .flags = _flags,             \
-	}
-
-#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags)                \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &infra1_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_setclr, .flags = _flags,             \
-	}
-
-#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags)                \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &infra2_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_setclr, .flags = _flags,             \
-	}
-
-#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags)                \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &infra3_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_setclr, .flags = _flags,             \
-	}
-
-#define GATE_INFRA0(_id, _name, _parent, _shift)                              \
-	GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0)
-
-#define GATE_INFRA1(_id, _name, _parent, _shift)                              \
-	GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
-
-#define GATE_INFRA2(_id, _name, _parent, _shift)                              \
-	GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0)
-
-#define GATE_INFRA3(_id, _name, _parent, _shift)                              \
-	GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
-
-#define GATE_CRITICAL(_id, _name, _parent, _regs, _shift) {                   \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = _regs, .shift = _shift,                               \
-		.flags = CLK_IS_CRITICAL,                                     \
-		.ops = &mtk_clk_gate_ops_setclr,                              \
-	}
-
-static const struct mtk_gate infra_clks[] = {
-	/* INFRA0 */
-	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0,
-		    "infra_pcie_peri_ck_26m_ck_p0", "csw_infra_f26m_sel", 7),
-	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1,
-		    "infra_pcie_peri_ck_26m_ck_p1", "csw_infra_f26m_sel", 8),
-	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2,
-		    "infra_pcie_peri_ck_26m_ck_p2", "csw_infra_f26m_sel", 9),
-	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3,
-		    "infra_pcie_peri_ck_26m_ck_p3", "csw_infra_f26m_sel", 10),
-	/* INFRA1 */
-	GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
-		    "sysaxi_sel", 0),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
-		    "sysaxi_sel", 1),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
-		    "infra_pwm_sel", 2),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
-		    "infra_pwm_ck1_sel", 3),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
-		    "infra_pwm_ck2_sel", 4),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
-		    "infra_pwm_ck3_sel", 5),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
-		    "infra_pwm_ck4_sel", 6),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
-		    "infra_pwm_ck5_sel", 7),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
-		    "infra_pwm_ck6_sel", 8),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
-		    "infra_pwm_ck7_sel", 9),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
-		    "infra_pwm_ck8_sel", 10),
-	GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
-		    "sysaxi_sel", 12),
-	GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
-		    "sysaxi_sel", 13),
-	GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m",
-		    "csw_infra_f26m_sel", 14),
-	GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15),
-	GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16),
-	GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18),
-	GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
-			  "csw_infra_f26m_sel", 19, CLK_IS_CRITICAL),
-	// JTAG
-	GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
-			  "sysaxi_sel", 20, CLK_IS_CRITICAL),
-	GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
-		    "sysaxi_sel", 21),
-	GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
-		    "sysaxi_sel", 29),
-	GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
-		    "csw_infra_f26m_sel", 30),
-	/* INFRA2 */
-	GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
-		    "csw_infra_f26m_sel", 0),
-	GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1),
-	GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
-		    "infra_mux_uart0_sel", 3),
-	GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
-		    "infra_mux_uart1_sel", 4),
-	GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
-		    "infra_mux_uart2_sel", 5),
-	GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9),
-	GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),
-	GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
-			  "sysaxi_sel", 11, CLK_IS_CRITICAL),
-	GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
-			  "infra_mux_spi0_sel", 12, CLK_IS_CRITICAL),
-	GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
-		    "infra_mux_spi1_sel", 13),
-	GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
-		    "infra_mux_spi2_sel", 14),
-	GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
-			  "sysaxi_sel", 15, CLK_IS_CRITICAL),
-	GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
-		    "sysaxi_sel", 16),
-	GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
-		    "sysaxi_sel", 17),
-	GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
-		    "sysaxi_sel", 18),
-	GATE_CRITICAL(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", &infra2_cg_regs, 19),
-	GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
-		    "csw_infra_f26m_sel", 20),
-	GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck",
-		    21),
-	GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel",
-		    22),
-	GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel",
-		    23),
-	GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
-		    "sysaxi_sel", 24),
-	GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
-		    "sysaxi_sel", 25),
-	GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
-		    "sysaxi_sel", 26),
-	GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27),
-	GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1,
-		    "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29),
-	GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1,
-		    "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31),
-	/* INFRA3 */
-	GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel",
-		    0),
-	GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
-		    "sysaxi_sel", 1),
-	GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel",
-		    2),
-	GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
-		    "sysaxi_sel", 3),
-	GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4),
-	GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
-		    "usb_sys_p1_sel", 5),
-	GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6),
-	GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7),
-	GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
-			  "usb_frmcnt_sel", 8, CLK_IS_CRITICAL),
-	GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
-			  "usb_frmcnt_p1_sel", 9, CLK_IS_CRITICAL),
-	GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10),
-	GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
-		    "usb_phy_sel", 11),
-	GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12),
-	GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
-		    "top_xtal", 13),
-	GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14),
-	GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
-		    "usb_xhci_p1_sel", 15),
-	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
-		    "infra_pcie_gfmux_tl_o_p0_sel", 20),
-	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
-		    "infra_pcie_gfmux_tl_o_p1_sel", 21),
-	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
-		    "infra_pcie_gfmux_tl_o_p2_sel", 22),
-	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
-		    "infra_pcie_gfmux_tl_o_p3_sel", 23),
-	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
-		    "top_xtal", 24),
-	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
-		    "top_xtal", 25),
-	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
-		    "top_xtal", 26),
-	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
-		    "top_xtal", 27),
-	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
-		    "sysaxi_sel", 28),
-	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
-		    "sysaxi_sel", 29),
-	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
-		    "sysaxi_sel", 30),
-	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
-		    "sysaxi_sel", 31),
-};
-
-static int clk_mt7988_infracfg_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(infra_muxes) + ARRAY_SIZE(infra_clks);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
-			       &mt7988_clk_lock, clk_data);
-
-	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_infracfg_data;
-	}
-	return r;
-
-free_infracfg_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
-	{
-		.compatible = "mediatek,mt7988-infracfg",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_infracfg_drv = {
-	.probe = clk_mt7988_infracfg_probe,
-	.driver = {
-		.name = "clk-mt7988-infracfg",
-		.of_match_table = of_match_clk_mt7988_infracfg,
-	},
-};
-builtin_platform_driver(clk_mt7988_infracfg_drv);

target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-topckgen.c

@@ -1,522 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- * Author: Xiufeng Li <[email protected]>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-
-static DEFINE_SPINLOCK(mt7988_clk_lock);
-
-static const struct mtk_fixed_clk top_fixed_clks[] = {
-	FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
-};
-
-static const struct mtk_fixed_factor top_divs[] = {
-	FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
-	FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
-	FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
-	FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2),
-	FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2),
-	FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4),
-	FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8),
-	FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16),
-	FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
-	FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15),
-	FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
-	FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12),
-	FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8),
-	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
-	FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4),
-	FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5),
-	FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10),
-	FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20),
-	FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8),
-	FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16),
-	FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32),
-	FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64),
-	FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128),
-	FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2),
-	FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4),
-	FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16),
-	FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32),
-	FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6),
-	FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8),
-};
-
-static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2",
-					      "mmpll_d2" };
-
-static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5",
-						   "net1pll_d5_d2" };
-
-static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll",
-						 "mmpll" };
-
-static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4",
-						  "net1pll_d5" };
-
-static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" };
-
-static const char *const netsys_mcu_parents[] = { "top_xtal",	"net2pll",
-						  "mmpll",	"net1pll_d4",
-						  "net1pll_d5", "mpll" };
-
-static const char *const eip197_parents[] = { "top_xtal",   "netsyspll",
-					      "net2pll",    "mmpll",
-					      "net1pll_d4", "net1pll_d5" };
-
-static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" };
-
-static const char *const uart_parents[] = { "top_xtal", "mpll_d8",
-					    "mpll_d8_d2" };
-
-static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2",
-						 "mmpll_d4" };
-
-static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll",
-						 "mmpll_d2", "mpll_d2",
-						 "mmpll_d4", "net1pll_d8_d2" };
-
-static const char *const spi_parents[] = { "top_xtal",	 "mpll_d2",
-					   "mmpll_d4",	 "net1pll_d8_d2",
-					   "net2pll_d6", "net1pll_d5_d4",
-					   "mpll_d4",	 "net1pll_d8_d4" };
-
-static const char *const nfi1x_parents[] = { "top_xtal",      "mmpll_d4",
-					     "net1pll_d8_d2", "net2pll_d6",
-					     "mpll_d4",	      "mmpll_d8",
-					     "net1pll_d8_d4", "mpll_d8" };
-
-static const char *const spinfi_parents[] = { "top_xtal_d2",   "top_xtal",
-					      "net1pll_d5_d4", "mpll_d4",
-					      "mmpll_d8",      "net1pll_d8_d4",
-					      "mmpll_d6_d2",   "mpll_d8" };
-
-static const char *const pwm_parents[] = { "top_xtal",	    "net1pll_d8_d2",
-					   "net1pll_d5_d4", "mpll_d4",
-					   "mpll_d8_d2",    "top_rtc_32k" };
-
-static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4",
-					   "mpll_d4", "net1pll_d8_d4" };
-
-static const char *const pcie_mbist_250m_parents[] = { "top_xtal",
-						       "net1pll_d5_d2" };
-
-static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6",
-						   "mmpll_d8", "mpll_d8_d2",
-						   "top_rtc_32k" };
-
-static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" };
-
-static const char *const aud_parents[] = { "top_xtal", "apll2" };
-
-static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" };
-
-static const char *const aud_l_parents[] = { "top_xtal", "apll2",
-					     "mpll_d8_d2" };
-
-static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" };
-
-static const char *const usxgmii_sbus_0_parents[] = { "top_xtal",
-						      "net1pll_d8_d4" };
-
-static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" };
-
-static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" };
-
-static const char *const eth_refck_50m_parents[] = { "top_xtal",
-						     "net2pll_d4_d4" };
-
-static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" };
-
-static const char *const eth_xgmii_parents[] = { "top_xtal_d2",
-						 "net1pll_d8_d8",
-						 "net1pll_d8_d16" };
-
-static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5",
-						"net2pll_d2" };
-
-static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" };
-
-static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2",
-						  "wedmcupll" };
-
-static const char *const da_xtp_glb_p0_parents[] = { "top_xtal",
-						     "net2pll_d8" };
-
-static const char *const mcusys_backup_625m_parents[] = { "top_xtal",
-							  "net1pll_d4" };
-
-static const char *const macsec_parents[] = { "top_xtal", "sgmpll",
-					      "net1pll_d8" };
-
-static const char *const netsys_tops_400m_parents[] = { "top_xtal",
-							"net2pll_d2" };
-
-static const char *const eth_mii_parents[] = { "top_xtal_d2",
-					       "net2pll_d4_d8" };
-
-static const struct mtk_mux top_muxes[] = {
-	/* CLK_CFG_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
-			     0x000, 0x004, 0x008, 0, 2, 7, 0x1c0, 0),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
-			     netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2,
-			     15, 0x1C0, 1),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
-			     netsys_2x_parents, 0x000, 0x004, 0x008, 16, 2, 23,
-			     0x1C0, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel",
-			     netsys_gsw_parents, 0x000, 0x004, 0x008, 24, 2,
-			     31, 0x1C0, 3),
-	/* CLK_CFG_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel",
-			     eth_gmii_parents, 0x010, 0x014, 0x018, 0, 1, 7,
-			     0x1C0, 4),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
-			     netsys_mcu_parents, 0x010, 0x014, 0x018, 8, 3, 15,
-			     0x1C0, 5),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
-			     netsys_mcu_parents, 0x010, 0x014, 0x018, 16, 3,
-			     23, 0x1C0, 6),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents,
-			     0x010, 0x014, 0x018, 24, 3, 31, 0x1c0, 7),
-	/* CLK_CFG_2 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel",
-				   axi_infra_parents, 0x020, 0x024, 0x028, 0,
-				   1, 7, 0x1C0, 8, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020,
-			     0x024, 0x028, 8, 2, 15, 0x1c0, 9),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
-			     emmc_250m_parents, 0x020, 0x024, 0x028, 16, 2, 23,
-			     0x1C0, 10),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
-			     emmc_400m_parents, 0x020, 0x024, 0x028, 24, 3, 31,
-			     0x1C0, 11),
-	/* CLK_CFG_3 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030,
-			     0x034, 0x038, 0, 3, 7, 0x1c0, 12),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
-			     0x030, 0x034, 0x038, 8, 3, 15, 0x1c0, 13),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
-			     0x030, 0x034, 0x038, 16, 3, 23, 0x1c0, 14),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
-			     0x030, 0x034, 0x038, 24, 3, 31, 0x1c0, 15),
-	/* CLK_CFG_4 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040,
-			     0x044, 0x048, 0, 3, 7, 0x1c0, 16),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040,
-			     0x044, 0x048, 8, 2, 15, 0x1c0, 17),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL,
-			     "pcie_mbist_250m_sel", pcie_mbist_250m_parents,
-			     0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel",
-			     pextp_tl_ck_parents, 0x040, 0x044, 0x048, 24, 3,
-			     31, 0x1C0, 19),
-	/* CLK_CFG_5 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel",
-			     pextp_tl_ck_parents, 0x050, 0x054, 0x058, 0, 3, 7,
-			     0x1C0, 20),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel",
-			     pextp_tl_ck_parents, 0x050, 0x054, 0x058, 8, 3,
-			     15, 0x1C0, 21),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel",
-			     pextp_tl_ck_parents, 0x050, 0x054, 0x058, 16, 3,
-			     23, 0x1C0, 22),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel",
-			     eth_gmii_parents, 0x050, 0x054, 0x058, 24, 1, 31,
-			     0x1C0, 23),
-	/* CLK_CFG_6 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel",
-			     eth_gmii_parents, 0x060, 0x064, 0x068, 0, 1, 7,
-			     0x1C0, 24),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel",
-			     eth_gmii_parents, 0x060, 0x064, 0x068, 8, 1, 15,
-			     0x1C0, 25),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel",
-			     eth_gmii_parents, 0x060, 0x064, 0x068, 16, 1, 23,
-			     0x1C0, 26),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
-			     usb_frmcnt_parents, 0x060, 0x064, 0x068, 24, 1,
-			     31, 0x1C0, 27),
-	/* CLK_CFG_7 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
-			     usb_frmcnt_parents, 0x070, 0x074, 0x078, 0, 1, 7,
-			     0x1C0, 28),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070,
-			     0x074, 0x078, 8, 1, 15, 0x1c0, 29),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
-			     0x070, 0x074, 0x078, 16, 1, 23, 0x1c0, 30),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
-			     0x070, 0x074, 0x078, 24, 2, 31, 0x1c4, 0),
-	/* CLK_CFG_8 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents,
-			     0x080, 0x084, 0x088, 0, 1, 7, 0x1c4, 1),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents,
-			     0x080, 0x084, 0x088, 8, 1, 15, 0x1c4, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel",
-			     sspxtp_parents, 0x080, 0x084, 0x088, 16, 1, 23,
-			     0x1c4, 3),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
-			     usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24,
-			     1, 31, 0x1C4, 4),
-	/* CLK_CFG_9 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
-			     usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1,
-			     7, 0x1C4, 5),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents,
-			     0x090, 0x094, 0x098, 8, 1, 15, 0x1c4, 6),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel",
-				   usxgmii_sbus_0_parents, 0x090, 0x094, 0x098,
-				   16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents,
-			     0x090, 0x094, 0x098, 24, 1, 31, 0x1c4, 8),
-	/* CLK_CFG_10 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel",
-				   usxgmii_sbus_0_parents, 0x0a0, 0x0a4, 0x0a8,
-				   0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel",
-			     sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15,
-			     0x1C4, 10),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel",
-			     sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 16, 1, 23,
-			     0x1C4, 11),
-	/* CLK_CFG_11 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
-				   axi_infra_parents, 0x0a0, 0x0a4, 0x0a8, 24,
-				   1, 31, 0x1C4, 12, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
-				   sysapb_parents, 0x0b0, 0x0b4, 0x0b8, 0, 1,
-				   7, 0x1c4, 13, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
-			     eth_refck_50m_parents, 0x0b0, 0x0b4, 0x0b8, 8, 1,
-			     15, 0x1C4, 14),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
-			     eth_sys_200m_parents, 0x0b0, 0x0b4, 0x0b8, 16, 1,
-			     23, 0x1C4, 15),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel",
-			     pcie_mbist_250m_parents, 0x0b0, 0x0b4, 0x0b8, 24,
-			     1, 31, 0x1C4, 16),
-	/* CLK_CFG_12 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel",
-			     eth_xgmii_parents, 0x0c0, 0x0c4, 0x0c8, 0, 2, 7,
-			     0x1C4, 17),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel",
-			     bus_tops_parents, 0x0c0, 0x0c4, 0x0c8, 8, 2, 15,
-			     0x1C4, 18),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel",
-			     npu_tops_parents, 0x0c0, 0x0c4, 0x0c8, 16, 1, 23,
-			     0x1C4, 19),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
-				   sspxtp_parents, 0x0c0, 0x0c4, 0x0c8, 24, 1,
-				   31, 0x1C4, 20, CLK_IS_CRITICAL),
-	/* CLK_CFG_13 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
-				   dramc_md32_parents, 0x0d0, 0x0d4, 0x0d8, 0,
-				   2, 7, 0x1C4, 21, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD_FLAGS(
-		CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
-		0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel",
-			     sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 16, 1, 23,
-			     0x1C4, 23),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel",
-			     sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 24, 1, 31,
-			     0x1C4, 24),
-	/* CLK_CFG_14 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel",
-			     sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7,
-			     0x1C4, 25),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel",
-			     sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15,
-			     0x1C4, 26),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
-			     da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 16, 1,
-			     23, 0x1C4, 27),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
-			     da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 24, 1,
-			     31, 0x1C4, 28),
-	/* CLK_CFG_15 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
-			     da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 0, 1,
-			     7, 0x1C4, 29),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
-			     da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 8, 1,
-			     15, 0x1C4, 30),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0,
-			     0x0f4, 0x0f8, 16, 1, 23, 0x1c8, 0),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0,
-			     0x0f4, 0x0f8, 24, 1, 31, 0x1C8, 1),
-	/* CLK_CFG_16 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents,
-			     0x0100, 0x104, 0x108, 0, 1, 7, 0x1c8, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel",
-			     sspxtp_parents, 0x0100, 0x104, 0x108, 8, 1, 15,
-			     0x1C8, 3),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL,
-			     "mcusys_backup_625m_sel",
-			     mcusys_backup_625m_parents, 0x0100, 0x104, 0x108,
-			     16, 1, 23, 0x1C8, 4),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL,
-			     "netsys_sync_250m_sel", pcie_mbist_250m_parents,
-			     0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5),
-	/* CLK_CFG_17 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents,
-			     0x0110, 0x114, 0x118, 0, 2, 7, 0x1c8, 6),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL,
-			     "netsys_tops_400m_sel", netsys_tops_400m_parents,
-			     0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL,
-			     "netsys_ppefb_250m_sel", pcie_mbist_250m_parents,
-			     0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel",
-			     netsys_parents, 0x0110, 0x114, 0x118, 24, 2, 31,
-			     0x1C8, 9),
-	/* CLK_CFG_18 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel",
-			     eth_mii_parents, 0x0120, 0x124, 0x128, 0, 1, 7,
-			     0x1c8, 10),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents,
-			     0x0120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11),
-};
-
-static const struct mtk_composite top_aud_divs[] = {
-	DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420,
-		 8, 8),
-};
-
-static int clk_mt7988_topckgen_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) +
-		 ARRAY_SIZE(top_muxes) + ARRAY_SIZE(top_aud_divs);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
-				    clk_data);
-
-	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
-
-	mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
-			       &mt7988_clk_lock, clk_data);
-
-	mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
-				    base, &mt7988_clk_lock, clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_topckgen_data;
-	}
-	return r;
-
-free_topckgen_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b",
-						   "net1pll_d4" };
-
-static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b",
-						   "net1pll_d4" };
-
-static struct mtk_composite mcu_muxes[] = {
-	/* bus_pll_divider_cfg */
-	MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel",
-		       mcu_bus_div_parents, 0x7C0, 9, 2, -1, CLK_IS_CRITICAL),
-	/* mp2_pll_divider_cfg */
-	MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel",
-		       mcu_arm_div_parents, 0x7A8, 9, 2, -1, CLK_IS_CRITICAL),
-};
-
-static int clk_mt7988_mcusys_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(mcu_muxes);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
-				    &mt7988_clk_lock, clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_mcusys_data;
-	}
-	return r;
-
-free_mcusys_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct of_device_id of_match_clk_mt7988_topckgen[] = {
-	{
-		.compatible = "mediatek,mt7988-topckgen",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_topckgen_drv = {
-	.probe = clk_mt7988_topckgen_probe,
-	.driver = {
-		.name = "clk-mt7988-topckgen",
-		.of_match_table = of_match_clk_mt7988_topckgen,
-	},
-};
-builtin_platform_driver(clk_mt7988_topckgen_drv);
-
-static const struct of_device_id of_match_clk_mt7988_mcusys[] = {
-	{
-		.compatible = "mediatek,mt7988-mcusys",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_mcusys_drv = {
-	.probe = clk_mt7988_mcusys_probe,
-	.driver = {
-		.name = "clk-mt7988-mcusys",
-		.of_match_table = of_match_clk_mt7988_mcusys,
-	},
-};
-builtin_platform_driver(clk_mt7988_mcusys_drv);

target/linux/mediatek/files-5.15/drivers/net/phy/mediatek-2p5ge.c

@@ -1,262 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-#include <linux/bitfield.h>
-#include <linux/firmware.h>
-#include <linux/module.h>
-#include <linux/nvmem-consumer.h>
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/phy.h>
-
-#define MEDAITEK_2P5GE_PHY_DMB_FW "mediatek/mediatek-2p5ge-phy-dmb.bin"
-#define MEDIATEK_2P5GE_PHY_PMB_FW "mediatek/mediatek-2p5ge-phy-pmb.bin"
-
-#define MD32_EN_CFG			0x18
-#define   MD32_EN			BIT(0)
-
-#define BASE100T_STATUS_EXTEND		0x10
-#define BASE1000T_STATUS_EXTEND		0x11
-#define EXTEND_CTRL_AND_STATUS		0x16
-
-#define PHY_AUX_CTRL_STATUS		0x1d
-#define   PHY_AUX_DPX_MASK		GENMASK(5, 5)
-#define   PHY_AUX_SPEED_MASK		GENMASK(4, 2)
-
-/* Registers on MDIO_MMD_VEND1 */
-#define MTK_PHY_LINK_STATUS_MISC	0xa2
-#define   MTK_PHY_FDX_ENABLE		BIT(5)
-
-/* Registers on MDIO_MMD_VEND2 */
-#define MTK_PHY_LED0_ON_CTRL		0x24
-#define   MTK_PHY_LED0_ON_LINK1000	BIT(0)
-#define   MTK_PHY_LED0_ON_LINK100	BIT(1)
-#define   MTK_PHY_LED0_ON_LINK10	BIT(2)
-#define   MTK_PHY_LED0_ON_LINK2500	BIT(7)
-#define   MTK_PHY_LED0_POLARITY		BIT(14)
-
-#define MTK_PHY_LED1_ON_CTRL		0x26
-#define   MTK_PHY_LED1_ON_FDX		BIT(4)
-#define   MTK_PHY_LED1_ON_HDX		BIT(5)
-#define   MTK_PHY_LED1_POLARITY		BIT(14)
-
-enum {
-	PHY_AUX_SPD_10 = 0,
-	PHY_AUX_SPD_100,
-	PHY_AUX_SPD_1000,
-	PHY_AUX_SPD_2500,
-};
-
-static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
-{
-	int ret;
-	int i;
-	const struct firmware *fw;
-	struct device *dev = &phydev->mdio.dev;
-	struct device_node *np;
-	void __iomem *dmb_addr;
-	void __iomem *pmb_addr;
-	void __iomem *mcucsr_base;
-	u16 reg;
-	struct pinctrl *pinctrl;
-
-	np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw");
-	if (!np)
-		return -ENOENT;
-
-	dmb_addr = of_iomap(np, 0);
-	if (!dmb_addr)
-		return -ENOMEM;
-	pmb_addr = of_iomap(np, 1);
-	if (!pmb_addr)
-		return -ENOMEM;
-	mcucsr_base = of_iomap(np, 2);
-	if (!mcucsr_base)
-		return -ENOMEM;
-
-	ret = request_firmware(&fw, MEDAITEK_2P5GE_PHY_DMB_FW, dev);
-	if (ret) {
-		dev_err(dev, "failed to load firmware: %s, ret: %d\n",
-			MEDAITEK_2P5GE_PHY_DMB_FW, ret);
-		return ret;
-	}
-	for (i = 0; i < fw->size - 1; i += 4)
-		writel(*((uint32_t *)(fw->data + i)), dmb_addr + i);
-	release_firmware(fw);
-
-	ret = request_firmware(&fw, MEDIATEK_2P5GE_PHY_PMB_FW, dev);
-	if (ret) {
-		dev_err(dev, "failed to load firmware: %s, ret: %d\n",
-			MEDIATEK_2P5GE_PHY_PMB_FW, ret);
-		return ret;
-	}
-	for (i = 0; i < fw->size - 1; i += 4)
-		writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
-	release_firmware(fw);
-
-	reg = readw(mcucsr_base + MD32_EN_CFG);
-	writew(reg | MD32_EN, mcucsr_base + MD32_EN_CFG);
-	dev_dbg(dev, "Firmware loading/trigger ok.\n");
-
-	/* Setup LED */
-	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
-			   MTK_PHY_LED0_POLARITY);
-
-	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
-			 MTK_PHY_LED0_ON_LINK10 |
-			 MTK_PHY_LED0_ON_LINK100 |
-			 MTK_PHY_LED0_ON_LINK1000 |
-			 MTK_PHY_LED0_ON_LINK2500);
-
-	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
-			 MTK_PHY_LED1_ON_FDX | MTK_PHY_LED1_ON_HDX);
-
-	pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led");
-	if (IS_ERR(pinctrl)) {
-		dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n");
-		return PTR_ERR(pinctrl);
-	}
-
-	return 0;
-}
-
-static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev)
-{
-	bool changed = false;
-	u32 adv;
-	int ret;
-
-	if (phydev->autoneg == AUTONEG_DISABLE) {
-		/* Configure half duplex with genphy_setup_forced,
-		 * because genphy_c45_pma_setup_forced does not support.
-		 */
-		return phydev->duplex != DUPLEX_FULL
-			? genphy_setup_forced(phydev)
-			: genphy_c45_pma_setup_forced(phydev);
-	}
-
-	ret = genphy_c45_an_config_aneg(phydev);
-	if (ret < 0)
-		return ret;
-	if (ret > 0)
-		changed = true;
-
-	adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
-	ret = phy_modify_changed(phydev, MII_CTRL1000,
-				 ADVERTISE_1000FULL | ADVERTISE_1000HALF,
-				 adv);
-	if (ret < 0)
-		return ret;
-	if (ret > 0)
-		changed = true;
-
-	return genphy_c45_check_and_restart_aneg(phydev, changed);
-}
-
-static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev)
-{
-	int ret;
-
-	ret = genphy_read_abilities(phydev);
-	if (ret)
-		return ret;
-
-	/* We don't support HDX at MAC layer on mt798x.
-	 * So mask phy's HDX capabilities, too.
-	 */
-	linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
-			 phydev->supported);
-	linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
-			 phydev->supported);
-	linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
-			 phydev->supported);
-	linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
-			 phydev->supported);
-	linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
-
-	return 0;
-}
-
-static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
-{
-	int ret;
-
-	ret = genphy_update_link(phydev);
-	if (ret)
-		return ret;
-
-	phydev->speed = SPEED_UNKNOWN;
-	phydev->duplex = DUPLEX_UNKNOWN;
-	phydev->pause = 0;
-	phydev->asym_pause = 0;
-
-	if (!phydev->link)
-		return 0;
-
-	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
-		ret = genphy_c45_read_lpa(phydev);
-		if (ret < 0)
-			return ret;
-
-		/* Read the link partner's 1G advertisement */
-		ret = phy_read(phydev, MII_STAT1000);
-		if (ret < 0)
-			return ret;
-		mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
-	} else if (phydev->autoneg == AUTONEG_DISABLE) {
-		linkmode_zero(phydev->lp_advertising);
-	}
-
-	ret = phy_read(phydev, PHY_AUX_CTRL_STATUS);
-	if (ret < 0)
-		return ret;
-
-	switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) {
-	case PHY_AUX_SPD_10:
-		phydev->speed = SPEED_10;
-		break;
-	case PHY_AUX_SPD_100:
-		phydev->speed = SPEED_100;
-		break;
-	case PHY_AUX_SPD_1000:
-		phydev->speed = SPEED_1000;
-		break;
-	case PHY_AUX_SPD_2500:
-		phydev->speed = SPEED_2500;
-		phydev->duplex = DUPLEX_FULL; /* 2.5G must be FDX */
-		break;
-	}
-
-	ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_MISC);
-	if (ret < 0)
-		return ret;
-
-	phydev->duplex = (ret & MTK_PHY_FDX_ENABLE) ? DUPLEX_FULL : DUPLEX_HALF;
-
-	return 0;
-}
-
-static struct phy_driver mtk_gephy_driver[] = {
-	{
-		PHY_ID_MATCH_EXACT(0x00339c11),
-		.name		= "MediaTek MT798x 2.5GbE PHY",
-		.config_init	= mt798x_2p5ge_phy_config_init,
-		.config_aneg    = mt798x_2p5ge_phy_config_aneg,
-		.get_features	= mt798x_2p5ge_phy_get_features,
-		.read_status	= mt798x_2p5ge_phy_read_status,
-	},
-};
-
-module_phy_driver(mtk_gephy_driver);
-
-static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = {
-	{ PHY_ID_MATCH_VENDOR(0x00339c00) },
-	{ }
-};
-
-MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver");
-MODULE_AUTHOR("SkyLake Huang <[email protected]>");
-MODULE_LICENSE("GPL");
-
-MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl);
-MODULE_FIRMWARE(MEDAITEK_2P5GE_PHY_DMB_FW);
-MODULE_FIRMWARE(MEDIATEK_2P5GE_PHY_PMB_FW);

target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7981.c

@@ -1,1041 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * The MT7981 driver based on Linux generic pinctrl binding.
- *
- * Copyright (C) 2020 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- */
-
-#include "pinctrl-moore.h"
-
-#define MT7981_PIN(_number, _name)				\
-	MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
-
-#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits)	\
-	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
-		       _x_bits, 32, 0)
-
-#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits)	\
-	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
-		      _x_bits, 32, 1)
-
-static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = {
-	PIN_FIELD(0, 56, 0x300, 0x10, 0, 4),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = {
-	PIN_FIELD(0, 56, 0x0, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_di_range[] = {
-	PIN_FIELD(0, 56, 0x200, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_do_range[] = {
-	PIN_FIELD(0, 56, 0x100, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1),
-	PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1),
-	PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1),
-	PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1),
-	PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1),
-	PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1),
-	PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1),
-	PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1),
-	PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1),
-	PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1),
-	PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1),
-	PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1),
-	PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1),
-	PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1),
-	PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1),
-	PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1),
-	PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1),
-	PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1),
-	PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1),
-	PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1),
-	PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1),
-	PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1),
-	PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1),
-	PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1),
-	PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1),
-	PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1),
-	PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1),
-	PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1),
-	PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1),
-	PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x90, 0x10, 9, 1),
-	PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1),
-	PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1),
-	PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1),
-	PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1),
-	PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1),
-	PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1),
-	PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
-	PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1),
-	PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1),
-	PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1),
-	PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1),
-	PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1),
-	PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1),
-	PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1),
-	PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1),
-	PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1),
-	PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1),
-	PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1),
-	PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1),
-	PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1),
-	PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1),
-	PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1),
-	PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1),
-	PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = {
-	PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1),
-	PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = {
-	PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1),
-	PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1),
-	PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1),
-	PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1),
-	PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1),
-	PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3),
-
-	PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3),
-
-	PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3),
-
-	PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3),
-
-	PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1),
-	PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1),
-	PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
-	PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1),
-	PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1),
-	PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1),
-	PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1),
-	PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1),
-	PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1),
-};
-
-static const unsigned int mt7981_pull_type[] = {
-	MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
-	MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/
-	MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/
-	MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/
-	MTK_PULL_PU_PD_TYPE,/*46*/ MTK_PULL_PU_PD_TYPE,/*47*/
-	MTK_PULL_PU_PD_TYPE,/*48*/ MTK_PULL_PU_PD_TYPE,/*49*/
-	MTK_PULL_PU_PD_TYPE,/*50*/ MTK_PULL_PU_PD_TYPE,/*51*/
-	MTK_PULL_PU_PD_TYPE,/*52*/ MTK_PULL_PU_PD_TYPE,/*53*/
-	MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/
-	MTK_PULL_PU_PD_TYPE,/*56*/
-};
-
-static const struct mtk_pin_reg_calc mt7981_reg_cals[] = {
-	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range),
-	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range),
-	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range),
-	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range),
-	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range),
-	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range),
-	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range),
-	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range),
-	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range),
-	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range),
-	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range),
-	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range),
-};
-
-static const struct mtk_pin_desc mt7981_pins[] = {
-	MT7981_PIN(0, "GPIO_WPS"),
-	MT7981_PIN(1, "GPIO_RESET"),
-	MT7981_PIN(2, "SYS_WATCHDOG"),
-	MT7981_PIN(3, "PCIE_PERESET_N"),
-	MT7981_PIN(4, "JTAG_JTDO"),
-	MT7981_PIN(5, "JTAG_JTDI"),
-	MT7981_PIN(6, "JTAG_JTMS"),
-	MT7981_PIN(7, "JTAG_JTCLK"),
-	MT7981_PIN(8, "JTAG_JTRST_N"),
-	MT7981_PIN(9, "WO_JTAG_JTDO"),
-	MT7981_PIN(10, "WO_JTAG_JTDI"),
-	MT7981_PIN(11, "WO_JTAG_JTMS"),
-	MT7981_PIN(12, "WO_JTAG_JTCLK"),
-	MT7981_PIN(13, "WO_JTAG_JTRST_N"),
-	MT7981_PIN(14, "USB_VBUS"),
-	MT7981_PIN(15, "PWM0"),
-	MT7981_PIN(16, "SPI0_CLK"),
-	MT7981_PIN(17, "SPI0_MOSI"),
-	MT7981_PIN(18, "SPI0_MISO"),
-	MT7981_PIN(19, "SPI0_CS"),
-	MT7981_PIN(20, "SPI0_HOLD"),
-	MT7981_PIN(21, "SPI0_WP"),
-	MT7981_PIN(22, "SPI1_CLK"),
-	MT7981_PIN(23, "SPI1_MOSI"),
-	MT7981_PIN(24, "SPI1_MISO"),
-	MT7981_PIN(25, "SPI1_CS"),
-	MT7981_PIN(26, "SPI2_CLK"),
-	MT7981_PIN(27, "SPI2_MOSI"),
-	MT7981_PIN(28, "SPI2_MISO"),
-	MT7981_PIN(29, "SPI2_CS"),
-	MT7981_PIN(30, "SPI2_HOLD"),
-	MT7981_PIN(31, "SPI2_WP"),
-	MT7981_PIN(32, "UART0_RXD"),
-	MT7981_PIN(33, "UART0_TXD"),
-	MT7981_PIN(34, "PCIE_CLK_REQ"),
-	MT7981_PIN(35, "PCIE_WAKE_N"),
-	MT7981_PIN(36, "SMI_MDC"),
-	MT7981_PIN(37, "SMI_MDIO"),
-	MT7981_PIN(38, "GBE_INT"),
-	MT7981_PIN(39, "GBE_RESET"),
-	MT7981_PIN(40, "WF_DIG_RESETB"),
-	MT7981_PIN(41, "WF_CBA_RESETB"),
-	MT7981_PIN(42, "WF_XO_REQ"),
-	MT7981_PIN(43, "WF_TOP_CLK"),
-	MT7981_PIN(44, "WF_TOP_DATA"),
-	MT7981_PIN(45, "WF_HB1"),
-	MT7981_PIN(46, "WF_HB2"),
-	MT7981_PIN(47, "WF_HB3"),
-	MT7981_PIN(48, "WF_HB4"),
-	MT7981_PIN(49, "WF_HB0"),
-	MT7981_PIN(50, "WF_HB0_B"),
-	MT7981_PIN(51, "WF_HB5"),
-	MT7981_PIN(52, "WF_HB6"),
-	MT7981_PIN(53, "WF_HB7"),
-	MT7981_PIN(54, "WF_HB8"),
-	MT7981_PIN(55, "WF_HB9"),
-	MT7981_PIN(56, "WF_HB10"),
-};
-
-/* List all groups consisting of these pins dedicated to the enablement of
- * certain hardware block and the corresponding mode for all of the pins.
- * The hardware probably has multiple combinations of these pinouts.
- */
-
-/* WA_AICE */
-static int mt7981_wa_aice1_pins[] = { 0, 1, };
-static int mt7981_wa_aice1_funcs[] = { 2, 2, };
-
-static int mt7981_wa_aice2_pins[] = { 0, 1, };
-static int mt7981_wa_aice2_funcs[] = { 3, 3, };
-
-static int mt7981_wa_aice3_pins[] = { 28, 29, };
-static int mt7981_wa_aice3_funcs[] = { 3, 3, };
-
-static int mt7981_wm_aice1_pins[] = { 9, 10, };
-static int mt7981_wm_aice1_funcs[] = { 2, 2, };
-
-static int mt7981_wm_aice2_pins[] = { 30, 31, };
-static int mt7981_wm_aice2_funcs[] = { 5, 5, };
-
-/* WM_UART */
-static int mt7981_wm_uart_0_pins[] = { 0, 1, };
-static int mt7981_wm_uart_0_funcs[] = { 5, 5, };
-
-static int mt7981_wm_uart_1_pins[] = { 20, 21, };
-static int mt7981_wm_uart_1_funcs[] = { 4, 4, };
-
-static int mt7981_wm_uart_2_pins[] = { 30, 31, };
-static int mt7981_wm_uart_2_funcs[] = { 3, 3, };
-
-/* DFD */
-static int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
-static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
-
-/* SYS_WATCHDOG */
-static int mt7981_watchdog_pins[] = { 2, };
-static int mt7981_watchdog_funcs[] = { 1, };
-
-static int mt7981_watchdog1_pins[] = { 13, };
-static int mt7981_watchdog1_funcs[] = { 5, };
-
-/* PCIE_PERESET_N */
-static int mt7981_pcie_pereset_pins[] = { 3, };
-static int mt7981_pcie_pereset_funcs[] = { 1, };
-
-/* JTAG */
-static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
-static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
-
-/* WM_JTAG */
-static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
-static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
-
-static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
-static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
-
-/* WO0_JTAG */
-static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
-static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
-
-static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
-static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
-
-/* UART2 */
-static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
-static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, };
-static int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, };
-
-/* GBE_LED0 */
-static int mt7981_gbe_led0_pins[] = { 8, };
-static int mt7981_gbe_led0_funcs[] = { 3, };
-
-/* PTA_EXT */
-static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
-static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
-
-static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
-static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
-
-/* PWM2 */
-static int mt7981_pwm2_pins[] = { 7, };
-static int mt7981_pwm2_funcs[] = { 4, };
-
-/* NET_WO0_UART_TXD */
-static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
-static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
-
-static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
-static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
-
-static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
-static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
-
-/* SPI1 */
-static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
-static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
-
-/* I2C */
-static int mt7981_i2c0_0_pins[] = { 6, 7, };
-static int mt7981_i2c0_0_funcs[] = { 6, 6, };
-
-static int mt7981_i2c0_1_pins[] = { 30, 31, };
-static int mt7981_i2c0_1_funcs[] = { 4, 4, };
-
-static int mt7981_i2c0_2_pins[] = { 36, 37, };
-static int mt7981_i2c0_2_funcs[] = { 2, 2, };
-
-static int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
-static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
-
-static int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
-static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
-
-static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
-static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
-
-static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
-static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
-
-/* DFD_NTRST */
-static int mt7981_dfd_ntrst_pins[] = { 8, };
-static int mt7981_dfd_ntrst_funcs[] = { 6, };
-
-/* PWM0 */
-static int mt7981_pwm0_0_pins[] = { 13, };
-static int mt7981_pwm0_0_funcs[] = { 2, };
-
-static int mt7981_pwm0_1_pins[] = { 15, };
-static int mt7981_pwm0_1_funcs[] = { 1, };
-
-/* PWM1 */
-static int mt7981_pwm1_0_pins[] = { 14, };
-static int mt7981_pwm1_0_funcs[] = { 2, };
-
-static int mt7981_pwm1_1_pins[] = { 15, };
-static int mt7981_pwm1_1_funcs[] = { 3, };
-
-/* GBE_LED1 */
-static int mt7981_gbe_led1_pins[] = { 13, };
-static int mt7981_gbe_led1_funcs[] = { 3, };
-
-/* PCM */
-static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
-static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
-
-/* UDI */
-static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
-static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
-
-/* DRV_VBUS */
-static int mt7981_drv_vbus_pins[] = { 14, };
-static int mt7981_drv_vbus_funcs[] = { 1, };
-
-/* EMMC */
-static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
-static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-
-/* SNFI */
-static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
-static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
-
-/* SPI0 */
-static int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
-static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
-
-/* SPI0 */
-static int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
-static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
-
-/* SPI1 */
-static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
-static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
-
-/* SPI2 */
-static int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
-static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
-
-/* SPI2 */
-static int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
-static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
-
-/* UART1 */
-static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
-static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
-
-static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
-static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
-
-static int mt7981_uart1_2_pins[] = { 9, 10, };
-static int mt7981_uart1_2_funcs[] = { 2, 2, };
-
-/* UART2 */
-static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
-static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
-
-/* UART0 */
-static int mt7981_uart0_pins[] = { 32, 33, };
-static int mt7981_uart0_funcs[] = { 1, 1, };
-
-/* PCIE_CLK_REQ */
-static int mt7981_pcie_clk_pins[] = { 34, };
-static int mt7981_pcie_clk_funcs[] = { 2, };
-
-/* PCIE_WAKE_N */
-static int mt7981_pcie_wake_pins[] = { 35, };
-static int mt7981_pcie_wake_funcs[] = { 2, };
-
-/* MDC_MDIO */
-static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
-static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
-
-static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
-static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
-
-/* WF0_MODE1 */
-static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 };
-static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
-
-/* WF0_MODE3 */
-static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
-static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
-
-/* WF2G_LED */
-static int mt7981_wf2g_led0_pins[] = { 30, };
-static int mt7981_wf2g_led0_funcs[] = { 2, };
-
-static int mt7981_wf2g_led1_pins[] = { 34, };
-static int mt7981_wf2g_led1_funcs[] = { 1, };
-
-/* WF5G_LED */
-static int mt7981_wf5g_led0_pins[] = { 31, };
-static int mt7981_wf5g_led0_funcs[] = { 2, };
-
-static int mt7981_wf5g_led1_pins[] = { 35, };
-static int mt7981_wf5g_led1_funcs[] = { 1, };
-
-/* MT7531_INT */
-static int mt7981_mt7531_int_pins[] = { 38, };
-static int mt7981_mt7531_int_funcs[] = { 1, };
-
-/* ANT_SEL */
-static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
-static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
-
-static const struct group_desc mt7981_groups[] = {
-	/* @GPIO(0,1): WA_AICE(2) */
-	PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1),
-	/* @GPIO(0,1): WA_AICE(3) */
-	PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2),
-	/* @GPIO(0,1): WM_UART(5) */
-	PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0),
-	/* @GPIO(0,1,4,5): DFD(6) */
-	PINCTRL_PIN_GROUP("dfd", mt7981_dfd),
-	/* @GPIO(2): SYS_WATCHDOG(1) */
-	PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog),
-	/* @GPIO(3): PCIE_PERESET_N(1) */
-	PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset),
-	/* @GPIO(4,8) JTAG(1) */
-	PINCTRL_PIN_GROUP("jtag", mt7981_jtag),
-	/* @GPIO(4,8) WM_JTAG(2) */
-	PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0),
-	/* @GPIO(9,13) WO0_JTAG(1) */
-	PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
-	/* @GPIO(4,7) WM_JTAG(3) */
-	PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
-	/* @GPIO(4,5) WM_JTAG(4) */
-	PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx),
-	/* @GPIO(8) GBE_LED0(3) */
-	PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
-	/* @GPIO(4,6) PTA_EXT(4) */
-	PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0),
-	/* @GPIO(7) PWM2(4) */
-	PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2),
-	/* @GPIO(8) NET_WO0_UART_TXD(4) */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0),
-	/* @GPIO(4,7) SPI1(5) */
-	PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0),
-	/* @GPIO(6,7) I2C(5) */
-	PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0),
-	/* @GPIO(0,1,4,5): DFD_NTRST(6) */
-	PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst),
-	/* @GPIO(9,10): WM_AICE(2) */
-	PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1),
-	/* @GPIO(13): PWM0(2) */
-	PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0),
-	/* @GPIO(15): PWM0(1) */
-	PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1),
-	/* @GPIO(14): PWM1(2) */
-	PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0),
-	/* @GPIO(15): PWM1(3) */
-	PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1),
-	/* @GPIO(14) NET_WO0_UART_TXD(3) */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1),
-	/* @GPIO(15) NET_WO0_UART_TXD(4) */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2),
-	/* @GPIO(13) GBE_LED0(3) */
-	PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1),
-	/* @GPIO(9,13) PCM(4) */
-	PINCTRL_PIN_GROUP("pcm", mt7981_pcm),
-	/* @GPIO(13): SYS_WATCHDOG1(5) */
-	PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1),
-	/* @GPIO(9,13) UDI(4) */
-	PINCTRL_PIN_GROUP("udi", mt7981_udi),
-	/* @GPIO(14) DRV_VBUS(1) */
-	PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus),
-	/* @GPIO(15,25): EMMC(2) */
-	PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45),
-	/* @GPIO(16,21): SNFI(3) */
-	PINCTRL_PIN_GROUP("snfi", mt7981_snfi),
-	/* @GPIO(16,19): SPI0(1) */
-	PINCTRL_PIN_GROUP("spi0", mt7981_spi0),
-	/* @GPIO(20,21): SPI0(1) */
-	PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold),
-	/* @GPIO(22,25) SPI1(1) */
-	PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1),
-	/* @GPIO(26,29): SPI2(1) */
-	PINCTRL_PIN_GROUP("spi2", mt7981_spi2),
-	/* @GPIO(30,31): SPI0(1) */
-	PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold),
-	/* @GPIO(16,19): UART1(4) */
-	PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
-	/* @GPIO(26,29): UART1(2) */
-	PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
-	/* @GPIO(9,10): UART1(2) */
-	PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2),
-	/* @GPIO(22,25): UART1(3) */
-	PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
-	/* @GPIO(22,24) PTA_EXT(4) */
-	PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1),
-	/* @GPIO(20,21): WM_UART(4) */
-	PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1),
-	/* @GPIO(30,31): WM_UART(3) */
-	PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2),
-	/* @GPIO(20,24) WM_JTAG(5) */
-	PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1),
-	/* @GPIO(25,29) WO0_JTAG(5) */
-	PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1),
-	/* @GPIO(28,29): WA_AICE(3) */
-	PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3),
-	/* @GPIO(30,31): WM_AICE(5) */
-	PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2),
-	/* @GPIO(30,31): I2C(4) */
-	PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1),
-	/* @GPIO(30,31): I2C(6) */
-	PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c),
-	/* @GPIO(32,33): I2C(1) */
-	PINCTRL_PIN_GROUP("uart0", mt7981_uart0),
-	/* @GPIO(32,33): I2C(2) */
-	PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c),
-	/* @GPIO(32,33): I2C(3) */
-	PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c),
-	/* @GPIO(32,33): I2C(5) */
-	PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c),
-	/* @GPIO(34): PCIE_CLK_REQ(2) */
-	PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk),
-	/* @GPIO(35): PCIE_WAKE_N(2) */
-	PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake),
-	/* @GPIO(36,37): I2C(2) */
-	PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2),
-	/* @GPIO(36,37): MDC_MDIO(1) */
-	PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio),
-	/* @GPIO(36,37): MDC_MDIO(3) */
-	PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio),
-	/* @GPIO(69,85): WF0_MODE1(1) */
-	PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1),
-	/* @GPIO(74,80): WF0_MODE3(3) */
-	PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3),
-	/* @GPIO(30): WF2G_LED(2) */
-	PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0),
-	/* @GPIO(34): WF2G_LED(1) */
-	PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1),
-	/* @GPIO(31): WF5G_LED(2) */
-	PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0),
-	/* @GPIO(35): WF5G_LED(1) */
-	PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1),
-	/* @GPIO(38): MT7531_INT(1) */
-	PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int),
-	/* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */
-	PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel),
-};
-
-/* Joint those groups owning the same capability in user point of view which
- * allows that people tend to use through the device tree.
- */
-static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
-	"wa_aice3", "wm_aice1_2", };
-static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
-	"uart1_2", "uart2_0_tx_rx",
-	"net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
-	"uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", };
-static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
-static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
-static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", };
-static const char *mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", "wo0_jtag_0",
-	"wo0_jtag_1", "wm_jtag_1", };
-static const char *mt7981_led_groups[] = { "gbe_led0", "gbe_led1", "wf2g_led0",
-	"wf2g_led1", "wf5g_led0", "wf5g_led1", };
-static const char *mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", };
-static const char *mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1",
-	"pwm1_0", "pwm1_1", };
-static const char *mt7981_spi_groups[] = { "spi1_0", "spi0", "spi0_wp_hold", "spi1_1", "spi2",
-	"spi2_wp_hold", };
-static const char *mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", "u2_phy_i2c",
-	"sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", "i2c0_2", };
-static const char *mt7981_pcm_groups[] = { "pcm", };
-static const char *mt7981_udi_groups[] = { "udi", };
-static const char *mt7981_usb_groups[] = { "drv_vbus", };
-static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", };
-static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio",
-	"wf0_mode1", "wf0_mode3", "mt7531_int", };
-static const char *mt7981_ant_groups[] = { "ant_sel", };
-
-static const struct function_desc mt7981_functions[] = {
-	{"wa_aice",	mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)},
-	{"dfd",	mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)},
-	{"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)},
-	{"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)},
-	{"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)},
-	{"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)},
-	{"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)},
-	{"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)},
-	{"eth",	mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)},
-	{"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)},
-	{"led",	mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)},
-	{"pwm",	mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)},
-	{"spi",	mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)},
-	{"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)},
-	{"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)},
-	{"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)},
-	{"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)},
-};
-
-static const struct mtk_eint_hw mt7981_eint_hw = {
-	.port_mask = 7,
-	.ports     = 7,
-	.ap_num    = ARRAY_SIZE(mt7981_pins),
-	.db_cnt    = 16,
-};
-
-static const char * const mt7981_pinctrl_register_base_names[] = {
-	"gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb",
-	"iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl",
-};
-
-static struct mtk_pin_soc mt7981_data = {
-	.reg_cal = mt7981_reg_cals,
-	.pins = mt7981_pins,
-	.npins = ARRAY_SIZE(mt7981_pins),
-	.grps = mt7981_groups,
-	.ngrps = ARRAY_SIZE(mt7981_groups),
-	.funcs = mt7981_functions,
-	.nfuncs = ARRAY_SIZE(mt7981_functions),
-	.eint_hw = &mt7981_eint_hw,
-	.gpio_m = 0,
-	.ies_present = false,
-	.base_names = mt7981_pinctrl_register_base_names,
-	.nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names),
-	.bias_disable_set = mtk_pinconf_bias_disable_set,
-	.bias_disable_get = mtk_pinconf_bias_disable_get,
-	.bias_set = mtk_pinconf_bias_set,
-	.bias_get = mtk_pinconf_bias_get,
-	.pull_type = mt7981_pull_type,
-	.bias_set_combo = mtk_pinconf_bias_set_combo,
-	.bias_get_combo = mtk_pinconf_bias_get_combo,
-	.drive_set = mtk_pinconf_drive_set_rev1,
-	.drive_get = mtk_pinconf_drive_get_rev1,
-	.adv_pull_get = mtk_pinconf_adv_pull_get,
-	.adv_pull_set = mtk_pinconf_adv_pull_set,
-};
-
-static const struct of_device_id mt7981_pinctrl_of_match[] = {
-	{ .compatible = "mediatek,mt7981-pinctrl", },
-	{}
-};
-
-static int mt7981_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_moore_pinctrl_probe(pdev, &mt7981_data);
-}
-
-static struct platform_driver mt7981_pinctrl_driver = {
-	.driver = {
-		.name = "mt7981-pinctrl",
-		.of_match_table = mt7981_pinctrl_of_match,
-	},
-	.probe = mt7981_pinctrl_probe,
-};
-
-static int __init mt7981_pinctrl_init(void)
-{
-	return platform_driver_register(&mt7981_pinctrl_driver);
-}
-arch_initcall(mt7981_pinctrl_init);

target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7986.c

@@ -1,1011 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * The MT7986 driver based on Linux generic pinctrl binding.
- *
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- */
-
-#include "pinctrl-moore.h"
-
-#define MT7986_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
-#define MT7986_NOT_BALLOUT_PIN(_number) { .number = _number, .name = NULL }
-
-#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
-			_x_bits)	\
-		PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
-			_x_bits, 32, 0)
-
-/**
- * enum - Locking variants of the iocfg bases
- *
- * MT7986 have multiple bases to program pin configuration listed as the below:
- * iocfg_rt:0x11c30000, iocfg_rb:0x11c40000, iocfg_lt:0x11e20000,
- * iocfg_lb:0x11e30000, iocfg_tr:0x11f00000, iocfg_tl:0x11f10000,
- * _i_based could be used to indicate what base the pin should be mapped into.
- *
- * Each iocfg register base control different group of pads on the SoC
- *
- *
- *  chip carrier
- *
- *      A  B  C  D  E  F  G  H
- *    +------------------------+
- *  8 | o  o  o  o  o  o  o  o |
- *  7 | o  o  o  o  o  o  o  o |
- *  6 | o  o  o  o  o  o  o  o |
- *  5 | o  o  o  o  o  o  o  o |
- *  4 | o  o  o  o  o  o  o  o |
- *  3 | o  o  o  o  o  o  o  o |
- *  2 | o  o  o  o  o  o  o  o |
- *  1 | o  o  o  o  o  o  o  o |
- *    +------------------------+
- *
- *  inside Chip carrier
- *
- *      A  B  C  D  E  F  G  H
- *    +------------------------+
- *  8 |                        |
- *  7 |        TL  TR          |
- *  6 |      +---------+       |
- *  5 |   LT |         | RT    |
- *  4 |      |         |       |
- *  3 |   LB |         | RB    |
- *  2 |      +---------+       |
- *  1 |                        |
- *    +------------------------+
- *
- */
-
-enum {
-	GPIO_BASE,
-	IOCFG_RT_BASE,
-	IOCFG_RB_BASE,
-	IOCFG_LT_BASE,
-	IOCFG_LB_BASE,
-	IOCFG_TR_BASE,
-	IOCFG_TL_BASE,
-};
-
-static const char *const mt7986_pinctrl_register_base_names[] = {
-	"gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", "iocfg_lb", "iocfg_tr",
-	"iocfg_tl",
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_mode_range[] = {
-	PIN_FIELD(0, 100, 0x300, 0x10, 0, 4),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_dir_range[] = {
-	PIN_FIELD(0, 100, 0x0, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_di_range[] = {
-	PIN_FIELD(0, 100, 0x200, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_do_range[] = {
-	PIN_FIELD(0, 100, 0x100, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_ies_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x20, 0x10, 10, 1),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x40, 0x10, 8, 1),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x30, 0x10, 12, 1),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x30, 0x10, 18, 1),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x30, 0x10, 17, 1),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x30, 0x10, 15, 1),
-	PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x30, 0x10, 19, 1),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x30, 0x10, 23, 1),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x30, 0x10, 22, 1),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x30, 0x10, 21, 1),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x20, 0x10, 4, 1),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x20, 0x10, 8, 1),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x20, 0x10, 7, 1),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x20, 0x10, 5, 1),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x20, 0x10, 9, 1),
-	PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x40, 0x10, 18, 1),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x40, 0x10, 12, 1),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x40, 0x10, 22, 1),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x40, 0x10, 20, 1),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x40, 0x10, 26, 1),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x40, 0x10, 24, 1),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x30, 0x10, 10, 1),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x40, 0x10, 15, 1),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x40, 0x10, 14, 1),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x40, 0x10, 13, 1),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x40, 0x10, 16, 1),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x30, 0x10, 16, 1),
-	PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x30, 0x10, 14, 1),
-	PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x30, 0x10, 14, 1),
-	PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x30, 0x10, 12, 1),
-	PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x30, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_smt_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0xf0, 0x10, 17, 1),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x90, 0x10, 10, 1),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0xf0, 0x10, 0, 1),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0xf0, 0x10, 8, 1),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0xf0, 0x10, 2, 1),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0xc0, 0x10, 12, 1),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0xc0, 0x10, 18, 1),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0xc0, 0x10, 17, 1),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0xc0, 0x10, 15, 1),
-	PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0xc0, 0x10, 19, 1),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0xc0, 0x10, 23, 1),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0xc0, 0x10, 22, 1),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0xc0, 0x10, 21, 1),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x90, 0x10, 4, 1),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x90, 0x10, 8, 1),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x90, 0x10, 7, 1),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x90, 0x10, 5, 1),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x90, 0x10, 9, 1),
-	PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0xf0, 0x10, 18, 1),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xf0, 0x10, 12, 1),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0xf0, 0x10, 22, 1),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0xf0, 0x10, 20, 1),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0xf0, 0x10, 26, 1),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0xf0, 0x10, 24, 1),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0xc0, 0x10, 2, 1),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0xc0, 0x10, 1, 1),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0xc0, 0x10, 0, 1),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0xc0, 0x10, 10, 1),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0xf0, 0x10, 15, 1),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0xf0, 0x10, 14, 1),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0xf0, 0x10, 13, 1),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0xf0, 0x10, 16, 1),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x90, 0x10, 2, 1),
-	PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x80, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x80, 0x10, 0, 1),
-	PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x80, 0x10, 16, 1),
-	PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x80, 0x10, 14, 1),
-	PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x80, 0x10, 4, 1),
-	PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x80, 0x10, 6, 1),
-	PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x80, 0x10, 2, 1),
-	PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x80, 0x10, 9, 1),
-	PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x80, 0x10, 5, 1),
-	PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x70, 0x10, 1, 1),
-	PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x70, 0x10, 14, 1),
-	PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x70, 0x10, 12, 1),
-	PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x70, 0x10, 4, 1),
-	PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x70, 0x10, 2, 1),
-	PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x70, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_pu_range[] = {
-	PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x50, 0x10, 16, 1),
-	PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x50, 0x10, 14, 1),
-	PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x50, 0x10, 14, 1),
-	PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x50, 0x10, 12, 1),
-	PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x50, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_pd_range[] = {
-	PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x40, 0x10, 16, 1),
-	PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x40, 0x10, 14, 1),
-	PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x40, 0x10, 14, 1),
-	PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x40, 0x10, 12, 1),
-	PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x40, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_drv_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x10, 0x10, 21, 3),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x00, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(11, 12, IOCFG_RB_BASE, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(13, 14, IOCFG_RB_BASE, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x10, 0x10, 6, 3),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x10, 0x10, 24, 3),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x10, 0x10, 21, 3),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x10, 0x10, 15, 3),
-	PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x10, 0x10, 27, 3),
-	PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x20, 0x10, 0, 3),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x20, 0x10, 9, 3),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x20, 0x10, 6, 3),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x20, 0x10, 3, 3),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 27, 3),
-	PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x20, 0x10, 0, 3),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x10, 0x10, 6, 3),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x20, 0x10, 9, 3),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x20, 0x10, 3, 3),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x20, 0x10, 21, 3),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x20, 0x10, 15, 3),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x10, 0x10, 15, 3),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x10, 0x10, 12, 3),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x10, 0x10, 9, 3),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x10, 0x10, 18, 3),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x00, 0x10, 2, 3),
-	PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x10, 0x10, 18, 3),
-	PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x10, 0x10, 12, 3),
-	PIN_FIELD_BASE(74, 77, IOCFG_TR_BASE, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(81, 84, IOCFG_TR_BASE, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x10, 0x10, 12, 3),
-	PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x10, 0x10, 6, 3),
-	PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(97, 98, IOCFG_TL_BASE, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(99, 100, IOCFG_TL_BASE, 0x10, 0x10, 2, 3),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_pupd_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x60, 0x10, 17, 1),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x30, 0x10, 10, 1),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x60, 0x10, 8, 1),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x60, 0x10, 2, 1),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x40, 0x10, 12, 1),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x40, 0x10, 18, 1),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x40, 0x10, 17, 1),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x40, 0x10, 15, 1),
-	PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x40, 0x10, 19, 1),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x40, 0x10, 23, 1),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x40, 0x10, 22, 1),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x40, 0x10, 21, 1),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x60, 0x10, 18, 1),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x60, 0x10, 12, 1),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x60, 0x10, 23, 1),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x60, 0x10, 21, 1),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x60, 0x10, 27, 1),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x60, 0x10, 25, 1),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x60, 0x10, 15, 1),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x60, 0x10, 14, 1),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x60, 0x10, 13, 1),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x60, 0x10, 16, 1),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x40, 0x10, 2, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_r0_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x70, 0x10, 17, 1),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x70, 0x10, 8, 1),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x70, 0x10, 2, 1),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x50, 0x10, 12, 1),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x50, 0x10, 18, 1),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x50, 0x10, 17, 1),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x50, 0x10, 15, 1),
-	PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x50, 0x10, 19, 1),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x50, 0x10, 23, 1),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x50, 0x10, 22, 1),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x50, 0x10, 21, 1),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x40, 0x10, 8, 1),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x70, 0x10, 18, 1),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 12, 1),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x70, 0x10, 23, 1),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x70, 0x10, 21, 1),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x70, 0x10, 27, 1),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x70, 0x10, 25, 1),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x50, 0x10, 10, 1),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x70, 0x10, 15, 1),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x70, 0x10, 14, 1),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x70, 0x10, 13, 1),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x70, 0x10, 16, 1),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x50, 0x10, 2, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_r1_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x80, 0x10, 17, 1),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x50, 0x10, 10, 1),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x80, 0x10, 0, 1),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x80, 0x10, 8, 1),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x80, 0x10, 2, 1),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x60, 0x10, 12, 1),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x60, 0x10, 18, 1),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x60, 0x10, 17, 1),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x60, 0x10, 15, 1),
-	PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x60, 0x10, 19, 1),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x60, 0x10, 23, 1),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x60, 0x10, 22, 1),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x60, 0x10, 21, 1),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x50, 0x10, 8, 1),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x80, 0x10, 18, 1),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x80, 0x10, 12, 1),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x80, 0x10, 23, 1),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x80, 0x10, 21, 1),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x80, 0x10, 27, 1),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x80, 0x10, 25, 1),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x60, 0x10, 2, 1),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x60, 0x10, 10, 1),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x80, 0x10, 15, 1),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x80, 0x10, 14, 1),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x80, 0x10, 13, 1),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x80, 0x10, 16, 1),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
-};
-
-static const unsigned int mt7986_pull_type[] = {
-	MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
-	MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
-	MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
-	MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
-	MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
-	MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
-	MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
-	MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
-	MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
-	MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
-	MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
-	MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
-	MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
-	MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
-	MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
-	MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
-	MTK_PULL_PU_PD_TYPE,/*100*/
-};
-
-static const struct mtk_pin_reg_calc mt7986_reg_cals[] = {
-	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range),
-	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range),
-	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7986_pin_di_range),
-	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7986_pin_do_range),
-	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7986_pin_smt_range),
-	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7986_pin_ies_range),
-	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7986_pin_drv_range),
-	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7986_pin_pu_range),
-	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7986_pin_pd_range),
-	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7986_pin_pupd_range),
-	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7986_pin_r0_range),
-	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7986_pin_r1_range),
-};
-
-static const struct mtk_pin_desc mt7986a_pins[] = {
-	MT7986_PIN(0, "SYS_WATCHDOG"),
-	MT7986_PIN(1, "WF2G_LED"),
-	MT7986_PIN(2, "WF5G_LED"),
-	MT7986_PIN(3, "I2C_SCL"),
-	MT7986_PIN(4, "I2C_SDA"),
-	MT7986_PIN(5, "GPIO_0"),
-	MT7986_PIN(6, "GPIO_1"),
-	MT7986_PIN(7, "GPIO_2"),
-	MT7986_PIN(8, "GPIO_3"),
-	MT7986_PIN(9, "GPIO_4"),
-	MT7986_PIN(10, "GPIO_5"),
-	MT7986_PIN(11, "GPIO_6"),
-	MT7986_PIN(12, "GPIO_7"),
-	MT7986_PIN(13, "GPIO_8"),
-	MT7986_PIN(14, "GPIO_9"),
-	MT7986_PIN(15, "GPIO_10"),
-	MT7986_PIN(16, "GPIO_11"),
-	MT7986_PIN(17, "GPIO_12"),
-	MT7986_PIN(18, "GPIO_13"),
-	MT7986_PIN(19, "GPIO_14"),
-	MT7986_PIN(20, "GPIO_15"),
-	MT7986_PIN(21, "PWM0"),
-	MT7986_PIN(22, "PWM1"),
-	MT7986_PIN(23, "SPI0_CLK"),
-	MT7986_PIN(24, "SPI0_MOSI"),
-	MT7986_PIN(25, "SPI0_MISO"),
-	MT7986_PIN(26, "SPI0_CS"),
-	MT7986_PIN(27, "SPI0_HOLD"),
-	MT7986_PIN(28, "SPI0_WP"),
-	MT7986_PIN(29, "SPI1_CLK"),
-	MT7986_PIN(30, "SPI1_MOSI"),
-	MT7986_PIN(31, "SPI1_MISO"),
-	MT7986_PIN(32, "SPI1_CS"),
-	MT7986_PIN(33, "SPI2_CLK"),
-	MT7986_PIN(34, "SPI2_MOSI"),
-	MT7986_PIN(35, "SPI2_MISO"),
-	MT7986_PIN(36, "SPI2_CS"),
-	MT7986_PIN(37, "SPI2_HOLD"),
-	MT7986_PIN(38, "SPI2_WP"),
-	MT7986_PIN(39, "UART0_RXD"),
-	MT7986_PIN(40, "UART0_TXD"),
-	MT7986_PIN(41, "PCIE_PERESET_N"),
-	MT7986_PIN(42, "UART1_RXD"),
-	MT7986_PIN(43, "UART1_TXD"),
-	MT7986_PIN(44, "UART1_CTS"),
-	MT7986_PIN(45, "UART1_RTS"),
-	MT7986_PIN(46, "UART2_RXD"),
-	MT7986_PIN(47, "UART2_TXD"),
-	MT7986_PIN(48, "UART2_CTS"),
-	MT7986_PIN(49, "UART2_RTS"),
-	MT7986_PIN(50, "EMMC_DATA_0"),
-	MT7986_PIN(51, "EMMC_DATA_1"),
-	MT7986_PIN(52, "EMMC_DATA_2"),
-	MT7986_PIN(53, "EMMC_DATA_3"),
-	MT7986_PIN(54, "EMMC_DATA_4"),
-	MT7986_PIN(55, "EMMC_DATA_5"),
-	MT7986_PIN(56, "EMMC_DATA_6"),
-	MT7986_PIN(57, "EMMC_DATA_7"),
-	MT7986_PIN(58, "EMMC_CMD"),
-	MT7986_PIN(59, "EMMC_CK"),
-	MT7986_PIN(60, "EMMC_DSL"),
-	MT7986_PIN(61, "EMMC_RSTB"),
-	MT7986_PIN(62, "PCM_DTX"),
-	MT7986_PIN(63, "PCM_DRX"),
-	MT7986_PIN(64, "PCM_CLK"),
-	MT7986_PIN(65, "PCM_FS"),
-	MT7986_PIN(66, "MT7531_INT"),
-	MT7986_PIN(67, "SMI_MDC"),
-	MT7986_PIN(68, "SMI_MDIO"),
-	MT7986_PIN(69, "WF0_DIG_RESETB"),
-	MT7986_PIN(70, "WF0_CBA_RESETB"),
-	MT7986_PIN(71, "WF0_XO_REQ"),
-	MT7986_PIN(72, "WF0_TOP_CLK"),
-	MT7986_PIN(73, "WF0_TOP_DATA"),
-	MT7986_PIN(74, "WF0_HB1"),
-	MT7986_PIN(75, "WF0_HB2"),
-	MT7986_PIN(76, "WF0_HB3"),
-	MT7986_PIN(77, "WF0_HB4"),
-	MT7986_PIN(78, "WF0_HB0"),
-	MT7986_PIN(79, "WF0_HB0_B"),
-	MT7986_PIN(80, "WF0_HB5"),
-	MT7986_PIN(81, "WF0_HB6"),
-	MT7986_PIN(82, "WF0_HB7"),
-	MT7986_PIN(83, "WF0_HB8"),
-	MT7986_PIN(84, "WF0_HB9"),
-	MT7986_PIN(85, "WF0_HB10"),
-	MT7986_PIN(86, "WF1_DIG_RESETB"),
-	MT7986_PIN(87, "WF1_CBA_RESETB"),
-	MT7986_PIN(88, "WF1_XO_REQ"),
-	MT7986_PIN(89, "WF1_TOP_CLK"),
-	MT7986_PIN(90, "WF1_TOP_DATA"),
-	MT7986_PIN(91, "WF1_HB1"),
-	MT7986_PIN(92, "WF1_HB2"),
-	MT7986_PIN(93, "WF1_HB3"),
-	MT7986_PIN(94, "WF1_HB4"),
-	MT7986_PIN(95, "WF1_HB0"),
-	MT7986_PIN(96, "WF1_HB0_B"),
-	MT7986_PIN(97, "WF1_HB5"),
-	MT7986_PIN(98, "WF1_HB6"),
-	MT7986_PIN(99, "WF1_HB7"),
-	MT7986_PIN(100, "WF1_HB8"),
-};
-
-static const struct mtk_pin_desc mt7986b_pins[] = {
-	MT7986_PIN(0, "SYS_WATCHDOG"),
-	MT7986_PIN(1, "WF2G_LED"),
-	MT7986_PIN(2, "WF5G_LED"),
-	MT7986_PIN(3, "I2C_SCL"),
-	MT7986_PIN(4, "I2C_SDA"),
-	MT7986_PIN(5, "GPIO_0"),
-	MT7986_PIN(6, "GPIO_1"),
-	MT7986_PIN(7, "GPIO_2"),
-	MT7986_PIN(8, "GPIO_3"),
-	MT7986_PIN(9, "GPIO_4"),
-	MT7986_PIN(10, "GPIO_5"),
-	MT7986_PIN(11, "GPIO_6"),
-	MT7986_PIN(12, "GPIO_7"),
-	MT7986_PIN(13, "GPIO_8"),
-	MT7986_PIN(14, "GPIO_9"),
-	MT7986_PIN(15, "GPIO_10"),
-	MT7986_PIN(16, "GPIO_11"),
-	MT7986_PIN(17, "GPIO_12"),
-	MT7986_PIN(18, "GPIO_13"),
-	MT7986_PIN(19, "GPIO_14"),
-	MT7986_PIN(20, "GPIO_15"),
-	MT7986_PIN(21, "PWM0"),
-	MT7986_PIN(22, "PWM1"),
-	MT7986_PIN(23, "SPI0_CLK"),
-	MT7986_PIN(24, "SPI0_MOSI"),
-	MT7986_PIN(25, "SPI0_MISO"),
-	MT7986_PIN(26, "SPI0_CS"),
-	MT7986_PIN(27, "SPI0_HOLD"),
-	MT7986_PIN(28, "SPI0_WP"),
-	MT7986_PIN(29, "SPI1_CLK"),
-	MT7986_PIN(30, "SPI1_MOSI"),
-	MT7986_PIN(31, "SPI1_MISO"),
-	MT7986_PIN(32, "SPI1_CS"),
-	MT7986_PIN(33, "SPI2_CLK"),
-	MT7986_PIN(34, "SPI2_MOSI"),
-	MT7986_PIN(35, "SPI2_MISO"),
-	MT7986_PIN(36, "SPI2_CS"),
-	MT7986_PIN(37, "SPI2_HOLD"),
-	MT7986_PIN(38, "SPI2_WP"),
-	MT7986_PIN(39, "UART0_RXD"),
-	MT7986_PIN(40, "UART0_TXD"),
-	MT7986_NOT_BALLOUT_PIN(41),
-	MT7986_NOT_BALLOUT_PIN(42),
-	MT7986_NOT_BALLOUT_PIN(43),
-	MT7986_NOT_BALLOUT_PIN(44),
-	MT7986_NOT_BALLOUT_PIN(45),
-	MT7986_NOT_BALLOUT_PIN(46),
-	MT7986_NOT_BALLOUT_PIN(47),
-	MT7986_NOT_BALLOUT_PIN(48),
-	MT7986_NOT_BALLOUT_PIN(49),
-	MT7986_NOT_BALLOUT_PIN(50),
-	MT7986_NOT_BALLOUT_PIN(51),
-	MT7986_NOT_BALLOUT_PIN(52),
-	MT7986_NOT_BALLOUT_PIN(53),
-	MT7986_NOT_BALLOUT_PIN(54),
-	MT7986_NOT_BALLOUT_PIN(55),
-	MT7986_NOT_BALLOUT_PIN(56),
-	MT7986_NOT_BALLOUT_PIN(57),
-	MT7986_NOT_BALLOUT_PIN(58),
-	MT7986_NOT_BALLOUT_PIN(59),
-	MT7986_NOT_BALLOUT_PIN(60),
-	MT7986_NOT_BALLOUT_PIN(61),
-	MT7986_NOT_BALLOUT_PIN(62),
-	MT7986_NOT_BALLOUT_PIN(63),
-	MT7986_NOT_BALLOUT_PIN(64),
-	MT7986_NOT_BALLOUT_PIN(65),
-	MT7986_PIN(66, "MT7531_INT"),
-	MT7986_PIN(67, "SMI_MDC"),
-	MT7986_PIN(68, "SMI_MDIO"),
-	MT7986_PIN(69, "WF0_DIG_RESETB"),
-	MT7986_PIN(70, "WF0_CBA_RESETB"),
-	MT7986_PIN(71, "WF0_XO_REQ"),
-	MT7986_PIN(72, "WF0_TOP_CLK"),
-	MT7986_PIN(73, "WF0_TOP_DATA"),
-	MT7986_PIN(74, "WF0_HB1"),
-	MT7986_PIN(75, "WF0_HB2"),
-	MT7986_PIN(76, "WF0_HB3"),
-	MT7986_PIN(77, "WF0_HB4"),
-	MT7986_PIN(78, "WF0_HB0"),
-	MT7986_PIN(79, "WF0_HB0_B"),
-	MT7986_PIN(80, "WF0_HB5"),
-	MT7986_PIN(81, "WF0_HB6"),
-	MT7986_PIN(82, "WF0_HB7"),
-	MT7986_PIN(83, "WF0_HB8"),
-	MT7986_PIN(84, "WF0_HB9"),
-	MT7986_PIN(85, "WF0_HB10"),
-	MT7986_PIN(86, "WF1_DIG_RESETB"),
-	MT7986_PIN(87, "WF1_CBA_RESETB"),
-	MT7986_PIN(88, "WF1_XO_REQ"),
-	MT7986_PIN(89, "WF1_TOP_CLK"),
-	MT7986_PIN(90, "WF1_TOP_DATA"),
-	MT7986_PIN(91, "WF1_HB1"),
-	MT7986_PIN(92, "WF1_HB2"),
-	MT7986_PIN(93, "WF1_HB3"),
-	MT7986_PIN(94, "WF1_HB4"),
-	MT7986_PIN(95, "WF1_HB0"),
-	MT7986_PIN(96, "WF1_HB0_B"),
-	MT7986_PIN(97, "WF1_HB5"),
-	MT7986_PIN(98, "WF1_HB6"),
-	MT7986_PIN(99, "WF1_HB7"),
-	MT7986_PIN(100, "WF1_HB8"),
-};
-
-/* List all groups consisting of these pins dedicated to the enablement of
- * certain hardware block and the corresponding mode for all of the pins.
- * The hardware probably has multiple combinations of these pinouts.
- */
-
-static int mt7986_watchdog_pins[] = { 0, };
-static int mt7986_watchdog_funcs[] = { 1, };
-
-static int mt7986_wifi_led_pins[] = { 1, 2, };
-static int mt7986_wifi_led_funcs[] = { 1, 1, };
-
-static int mt7986_i2c_pins[] = { 3, 4, };
-static int mt7986_i2c_funcs[] = { 1, 1, };
-
-static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, };
-static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, };
-static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7986_pwm1_1_pins[] = { 20, };
-static int mt7986_pwm1_1_funcs[] = { 2, };
-
-static int mt7986_pwm0_pins[] = { 21, };
-static int mt7986_pwm0_funcs[] = { 1, };
-
-static int mt7986_pwm1_0_pins[] = { 22, };
-static int mt7986_pwm1_0_funcs[] = { 1, };
-
-static int mt7986_emmc_45_pins[] = {
-	22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, };
-static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-
-static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, };
-static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, };
-
-static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, };
-static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, };
-static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, };
-
-static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
-static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, };
-static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, };
-
-static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, };
-static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, };
-
-static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, };
-static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, };
-
-static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, };
-static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, };
-
-static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
-static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_spi0_wp_hold_pins[] = { 37, 38, };
-static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, };
-
-static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, };
-static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, };
-static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, };
-
-static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, };
-static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, };
-
-static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, };
-static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, };
-
-static int mt7986_uart0_pins[] = { 39, 40, };
-static int mt7986_uart0_funcs[] = { 1, 1, };
-
-static int mt7986_pcie_reset_pins[] = { 41, };
-static int mt7986_pcie_reset_funcs[] = { 1, };
-
-static int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
-static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_uart1_rx_tx_pins[] = { 42, 43, };
-static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, };
-
-static int mt7986_uart1_cts_rts_pins[] = { 44, 45, };
-static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, };
-
-static int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
-static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_emmc_51_pins[] = {
-	50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, };
-static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-
-static int mt7986_pcm_pins[] = { 62, 63, 64, 65, };
-static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_i2s_pins[] = { 62, 63, 64, 65, };
-static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_switch_int_pins[] = { 66, };
-static int mt7986_switch_int_funcs[] = { 1, };
-
-static int mt7986_mdc_mdio_pins[] = { 67, 68, };
-static int mt7986_mdc_mdio_funcs[] = { 1, 1, };
-
-static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, };
-static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-
-static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, };
-static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-
-static int mt7986_wf_dbdc_pins[] = {
-	74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, };
-static int mt7986_wf_dbdc_funcs[] = {
-	2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-
-static int mt7986_pcie_clk_pins[] = { 9, };
-static int mt7986_pcie_clk_funcs[] = { 1, };
-
-static int mt7986_pcie_wake_pins[] = { 10, };
-static int mt7986_pcie_wake_funcs[] = { 1, };
-
-static const struct group_desc mt7986_groups[] = {
-	PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog),
-	PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led),
-	PINCTRL_PIN_GROUP("i2c", mt7986_i2c),
-	PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0),
-	PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx),
-	PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts),
-	PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk),
-	PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake),
-	PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0),
-	PINCTRL_PIN_GROUP("pwm1_1", mt7986_pwm1_1),
-	PINCTRL_PIN_GROUP("pwm0", mt7986_pwm0),
-	PINCTRL_PIN_GROUP("pwm1_0", mt7986_pwm1_0),
-	PINCTRL_PIN_GROUP("emmc_45", mt7986_emmc_45),
-	PINCTRL_PIN_GROUP("snfi", mt7986_snfi),
-	PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1),
-	PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1),
-	PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2),
-	PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx),
-	PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts),
-	PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx),
-	PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts),
-	PINCTRL_PIN_GROUP("spi0", mt7986_spi0),
-	PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold),
-	PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1),
-	PINCTRL_PIN_GROUP("uart1_3_rx_tx", mt7986_uart1_3_rx_tx),
-	PINCTRL_PIN_GROUP("uart1_3_cts_rts", mt7986_uart1_3_cts_rts),
-	PINCTRL_PIN_GROUP("spi1_3", mt7986_spi1_3),
-	PINCTRL_PIN_GROUP("uart0", mt7986_uart0),
-	PINCTRL_PIN_GROUP("switch_int", mt7986_switch_int),
-	PINCTRL_PIN_GROUP("mdc_mdio", mt7986_mdc_mdio),
-	PINCTRL_PIN_GROUP("pcie_pereset", mt7986_pcie_reset),
-	PINCTRL_PIN_GROUP("uart1", mt7986_uart1),
-	PINCTRL_PIN_GROUP("uart2", mt7986_uart2),
-	PINCTRL_PIN_GROUP("emmc_51", mt7986_emmc_51),
-	PINCTRL_PIN_GROUP("pcm", mt7986_pcm),
-	PINCTRL_PIN_GROUP("i2s", mt7986_i2s),
-	PINCTRL_PIN_GROUP("wf_2g", mt7986_wf_2g),
-	PINCTRL_PIN_GROUP("wf_5g", mt7986_wf_5g),
-	PINCTRL_PIN_GROUP("wf_dbdc", mt7986_wf_dbdc),
-};
-
-/* Joint those groups owning the same capability in user point of view which
- * allows that people tend to use through the device tree.
- */
-
-static const char *mt7986_audio_groups[] = { "pcm", "i2s" };
-static const char *mt7986_emmc_groups[] = {
-	"emmc_45", "emmc_51", };
-static const char *mt7986_ethernet_groups[] = {
-	"switch_int", "mdc_mdio", };
-static const char *mt7986_i2c_groups[] = { "i2c", };
-static const char *mt7986_led_groups[] = { "wifi_led", };
-static const char *mt7986_flash_groups[] = { "snfi", };
-static const char *mt7986_pcie_groups[] = {
-	"pcie_clk", "pcie_wake", "pcie_pereset" };
-static const char *mt7986_pwm_groups[] = { "pwm0", "pwm1_0", "pwm1_1", };
-static const char *mt7986_spi_groups[] = {
-	"spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", };
-static const char *mt7986_uart_groups[] = {
-	"uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts",
-	"uart1_2_rx_tx", "uart1_2_cts_rts",
-	"uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts",
-	"uart2_0", "uart2_1", "uart0", "uart1", "uart2",
-};
-static const char *mt7986_wdt_groups[] = { "watchdog", };
-static const char *mt7986_wf_groups[] = { "wf_2g", "wf_5g", "wf_dbdc", };
-
-static const struct function_desc mt7986_functions[] = {
-	{"audio", mt7986_audio_groups, ARRAY_SIZE(mt7986_audio_groups)},
-	{"emmc", mt7986_emmc_groups, ARRAY_SIZE(mt7986_emmc_groups)},
-	{"eth", mt7986_ethernet_groups, ARRAY_SIZE(mt7986_ethernet_groups)},
-	{"i2c", mt7986_i2c_groups, ARRAY_SIZE(mt7986_i2c_groups)},
-	{"led", mt7986_led_groups, ARRAY_SIZE(mt7986_led_groups)},
-	{"flash", mt7986_flash_groups, ARRAY_SIZE(mt7986_flash_groups)},
-	{"pcie", mt7986_pcie_groups, ARRAY_SIZE(mt7986_pcie_groups)},
-	{"pwm", mt7986_pwm_groups, ARRAY_SIZE(mt7986_pwm_groups)},
-	{"spi", mt7986_spi_groups, ARRAY_SIZE(mt7986_spi_groups)},
-	{"uart", mt7986_uart_groups, ARRAY_SIZE(mt7986_uart_groups)},
-	{"watchdog", mt7986_wdt_groups, ARRAY_SIZE(mt7986_wdt_groups)},
-	{"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)},
-};
-
-static const struct mtk_eint_hw mt7986a_eint_hw = {
-	.port_mask = 7,
-	.ports = 7,
-	.ap_num = ARRAY_SIZE(mt7986a_pins),
-	.db_cnt = 16,
-	.db_time = debounce_time_mt6765,
-};
-
-static const struct mtk_eint_hw mt7986b_eint_hw = {
-	.port_mask = 7,
-	.ports = 7,
-	.ap_num = ARRAY_SIZE(mt7986b_pins),
-	.db_cnt = 16,
-	.db_time = debounce_time_mt6765,
-};
-
-static struct mtk_pin_soc mt7986a_data = {
-	.reg_cal = mt7986_reg_cals,
-	.pins = mt7986a_pins,
-	.npins = ARRAY_SIZE(mt7986a_pins),
-	.grps = mt7986_groups,
-	.ngrps = ARRAY_SIZE(mt7986_groups),
-	.funcs = mt7986_functions,
-	.nfuncs = ARRAY_SIZE(mt7986_functions),
-	.eint_hw = &mt7986a_eint_hw,
-	.gpio_m = 0,
-	.ies_present = false,
-	.base_names = mt7986_pinctrl_register_base_names,
-	.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
-	.bias_disable_set = mtk_pinconf_bias_disable_set,
-	.bias_disable_get = mtk_pinconf_bias_disable_get,
-	.bias_set = mtk_pinconf_bias_set,
-	.bias_get = mtk_pinconf_bias_get,
-	.pull_type = mt7986_pull_type,
-	.bias_set_combo = mtk_pinconf_bias_set_combo,
-	.bias_get_combo = mtk_pinconf_bias_get_combo,
-	.drive_set = mtk_pinconf_drive_set_rev1,
-	.drive_get = mtk_pinconf_drive_get_rev1,
-	.adv_pull_get = mtk_pinconf_adv_pull_get,
-	.adv_pull_set = mtk_pinconf_adv_pull_set,
-};
-
-static struct mtk_pin_soc mt7986b_data = {
-	.reg_cal = mt7986_reg_cals,
-	.pins = mt7986b_pins,
-	.npins = ARRAY_SIZE(mt7986b_pins),
-	.grps = mt7986_groups,
-	.ngrps = ARRAY_SIZE(mt7986_groups),
-	.funcs = mt7986_functions,
-	.nfuncs = ARRAY_SIZE(mt7986_functions),
-	.eint_hw = &mt7986b_eint_hw,
-	.gpio_m = 0,
-	.ies_present = false,
-	.base_names = mt7986_pinctrl_register_base_names,
-	.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
-	.bias_disable_set = mtk_pinconf_bias_disable_set,
-	.bias_disable_get = mtk_pinconf_bias_disable_get,
-	.bias_set = mtk_pinconf_bias_set,
-	.bias_get = mtk_pinconf_bias_get,
-	.pull_type = mt7986_pull_type,
-	.bias_set_combo = mtk_pinconf_bias_set_combo,
-	.bias_get_combo = mtk_pinconf_bias_get_combo,
-	.drive_set = mtk_pinconf_drive_set_rev1,
-	.drive_get = mtk_pinconf_drive_get_rev1,
-	.adv_pull_get = mtk_pinconf_adv_pull_get,
-	.adv_pull_set = mtk_pinconf_adv_pull_set,
-};
-
-static const struct of_device_id mt7986a_pinctrl_of_match[] = {
-	{.compatible = "mediatek,mt7986a-pinctrl",},
-	{}
-};
-
-static const struct of_device_id mt7986b_pinctrl_of_match[] = {
-	{.compatible = "mediatek,mt7986b-pinctrl",},
-	{}
-};
-
-static int mt7986a_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_moore_pinctrl_probe(pdev, &mt7986a_data);
-}
-
-static int mt7986b_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_moore_pinctrl_probe(pdev, &mt7986b_data);
-}
-
-static struct platform_driver mt7986a_pinctrl_driver = {
-	.driver = {
-		.name = "mt7986a-pinctrl",
-		.of_match_table = mt7986a_pinctrl_of_match,
-	},
-	.probe = mt7986a_pinctrl_probe,
-};
-
-static struct platform_driver mt7986b_pinctrl_driver = {
-	.driver = {
-		.name = "mt7986b-pinctrl",
-		.of_match_table = mt7986b_pinctrl_of_match,
-	},
-	.probe = mt7986b_pinctrl_probe,
-};
-
-static int __init mt7986a_pinctrl_init(void)
-{
-	return platform_driver_register(&mt7986a_pinctrl_driver);
-}
-
-static int __init mt7986b_pinctrl_init(void)
-{
-	return platform_driver_register(&mt7986b_pinctrl_driver);
-}
-
-arch_initcall(mt7986a_pinctrl_init);
-arch_initcall(mt7986b_pinctrl_init);

target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c

@@ -1,1466 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * The MT7988 driver based on Linux generic pinctrl binding.
- *
- * Copyright (C) 2020 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- */
-
-#include "pinctrl-moore.h"
-
-enum MT7988_PINCTRL_REG_PAGE {
-	GPIO_BASE,
-	IOCFG_TR_BASE,
-	IOCFG_BR_BASE,
-	IOCFG_RB_BASE,
-	IOCFG_LB_BASE,
-	IOCFG_TL_BASE,
-};
-
-#define MT7988_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
-
-#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,     \
-		       _x_bits)                                                \
-	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,     \
-		       _x_bits, 32, 0)
-
-#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,    \
-			_x_bits)                                               \
-	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,     \
-		       _x_bits, 32, 1)
-
-static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = {
-	PIN_FIELD(0, 83, 0x300, 0x10, 0, 4),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = {
-	PIN_FIELD(0, 83, 0x0, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_di_range[] = {
-	PIN_FIELD(0, 83, 0x200, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_do_range[] = {
-	PIN_FIELD(0, 83, 0x100, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1),
-	PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1),
-	PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1),
-	PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1),
-
-	PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1),
-	PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1),
-	PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1),
-	PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1),
-	PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1),
-	PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1),
-	PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1),
-	PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1),
-	PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1),
-	PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1),
-	PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1),
-	PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1),
-	PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1),
-	PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(45, 45, 3, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(46, 46, 3, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(47, 47, 3, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1),
-	PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1),
-	PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1),
-	PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1),
-
-	PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1),
-	PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1),
-	PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1),
-	PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1),
-	PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1),
-	PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1),
-	PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1),
-
-	PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1),
-
-	PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1),
-	PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1),
-	PIN_FIELD_BASE(76, 76, 4, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1),
-
-	PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1),
-	PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1),
-	PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1),
-	PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1),
-	PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1),
-	PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1),
-	PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1),
-	PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1),
-
-	PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1),
-	PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1),
-	PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1),
-	PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1),
-	PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1),
-	PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1),
-	PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1),
-	PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1),
-	PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1),
-	PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1),
-	PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1),
-	PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1),
-	PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1),
-	PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1),
-	PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1),
-	PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1),
-	PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1),
-	PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1),
-	PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1),
-	PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1),
-	PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1),
-	PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1),
-	PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1),
-	PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1),
-	PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1),
-	PIN_FIELD_BASE(45, 45, 3, 0x140, 0x10, 6, 1),
-	PIN_FIELD_BASE(46, 46, 3, 0x140, 0x10, 5, 1),
-	PIN_FIELD_BASE(47, 47, 3, 0x140, 0x10, 4, 1),
-	PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1),
-	PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1),
-	PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1),
-	PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1),
-	PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1),
-	PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1),
-
-	PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1),
-	PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1),
-	PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1),
-	PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1),
-	PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1),
-	PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1),
-	PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1),
-	PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1),
-	PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1),
-	PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1),
-	PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1),
-	PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1),
-	PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1),
-	PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1),
-
-	PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1),
-	PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1),
-	PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1),
-
-	PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1),
-	PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1),
-	PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1),
-	PIN_FIELD_BASE(76, 76, 4, 0xb0, 0x10, 9, 1),
-	PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1),
-	PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1),
-	PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1),
-
-	PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1),
-	PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1),
-	PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1),
-	PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
-	PIN_FIELD_BASE(7, 7, 4, 0x60, 0x10, 5, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1),
-	PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1),
-	PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1),
-	PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1),
-	PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1),
-	PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(78, 78, 4, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(79, 79, 4, 0x60, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
-	PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(78, 78, 4, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(79, 79, 4, 0x40, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3),
-
-	PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3),
-	PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3),
-
-	PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3),
-	PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3),
-
-	PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3),
-
-	PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3),
-	PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3),
-	PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3),
-	PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3),
-	PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3),
-	PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3),
-	PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3),
-	PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3),
-	PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3),
-	PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3),
-	PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3),
-	PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3),
-	PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3),
-	PIN_FIELD_BASE(34, 34, 3, 0x30, 0x10, 3, 3),
-	PIN_FIELD_BASE(35, 35, 3, 0x20, 0x10, 27, 3),
-	PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 0, 3),
-	PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3),
-	PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3),
-	PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(45, 45, 3, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(46, 46, 3, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(47, 47, 3, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3),
-	PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3),
-	PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3),
-	PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3),
-	PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3),
-
-	PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3),
-	PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3),
-	PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3),
-	PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3),
-	PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3),
-	PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3),
-
-	PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3),
-
-	PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3),
-	PIN_FIELD_BASE(76, 76, 4, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3),
-
-	PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3),
-	PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3),
-	PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3),
-	PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1),
-
-	PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1),
-	PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1),
-	PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1),
-	PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1),
-	PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1),
-	PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1),
-	PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1),
-	PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1),
-	PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1),
-	PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1),
-	PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1),
-	PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1),
-	PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1),
-	PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1),
-	PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1),
-	PIN_FIELD_BASE(45, 45, 3, 0x70, 0x10, 6, 1),
-	PIN_FIELD_BASE(46, 46, 3, 0x70, 0x10, 5, 1),
-	PIN_FIELD_BASE(47, 47, 3, 0x70, 0x10, 4, 1),
-	PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1),
-	PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1),
-	PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1),
-	PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1),
-	PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1),
-	PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1),
-
-	PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1),
-	PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1),
-	PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1),
-	PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1),
-	PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1),
-	PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1),
-	PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1),
-	PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1),
-	PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1),
-	PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1),
-	PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1),
-	PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1),
-
-	PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1),
-
-	PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1),
-	PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1),
-	PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1),
-	PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1),
-	PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1),
-	PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1),
-	PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1),
-	PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1),
-
-	PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1),
-	PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1),
-	PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1),
-	PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1),
-	PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1),
-	PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1),
-	PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1),
-	PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1),
-	PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1),
-	PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1),
-	PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1),
-	PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1),
-	PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1),
-	PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1),
-	PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1),
-	PIN_FIELD_BASE(45, 45, 3, 0x90, 0x10, 6, 1),
-	PIN_FIELD_BASE(46, 46, 3, 0x90, 0x10, 5, 1),
-	PIN_FIELD_BASE(47, 47, 3, 0x90, 0x10, 4, 1),
-	PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1),
-	PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1),
-	PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1),
-	PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1),
-	PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1),
-	PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1),
-
-	PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1),
-	PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1),
-	PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1),
-	PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1),
-	PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1),
-	PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1),
-	PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1),
-	PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1),
-	PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1),
-	PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1),
-	PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1),
-	PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1),
-	PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1),
-
-	PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1),
-	PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1),
-
-	PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1),
-	PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1),
-	PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1),
-	PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1),
-	PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1),
-	PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1),
-	PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1),
-
-	PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1),
-	PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1),
-	PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1),
-	PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1),
-	PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1),
-	PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1),
-	PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1),
-	PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1),
-	PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1),
-	PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1),
-	PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1),
-	PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1),
-	PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1),
-	PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1),
-	PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1),
-	PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1),
-	PIN_FIELD_BASE(45, 45, 3, 0xb0, 0x10, 6, 1),
-	PIN_FIELD_BASE(46, 46, 3, 0xb0, 0x10, 5, 1),
-	PIN_FIELD_BASE(47, 47, 3, 0xb0, 0x10, 4, 1),
-	PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1),
-	PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1),
-	PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1),
-	PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1),
-	PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1),
-	PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1),
-
-	PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1),
-	PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1),
-	PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1),
-	PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1),
-	PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1),
-	PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1),
-	PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1),
-	PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1),
-	PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1),
-	PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1),
-	PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1),
-	PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1),
-	PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1),
-
-	PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1),
-	PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1),
-
-	PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1),
-	PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1),
-	PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1),
-	PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1),
-};
-
-static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {
-	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range),
-	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range),
-	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range),
-	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range),
-	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range),
-	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range),
-	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range),
-	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range),
-	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range),
-	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range),
-	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range),
-	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range),
-};
-
-static const struct mtk_pin_desc mt7988_pins[] = {
-	MT7988_PIN(0, "UART2_RXD"),
-	MT7988_PIN(1, "UART2_TXD"),
-	MT7988_PIN(2, "UART2_CTS"),
-	MT7988_PIN(3, "UART2_RTS"),
-	MT7988_PIN(4, "GPIO_A"),
-	MT7988_PIN(5, "SMI_0_MDC"),
-	MT7988_PIN(6, "SMI_0_MDIO"),
-	MT7988_PIN(7, "PCIE30_2L_0_WAKE_N"),
-	MT7988_PIN(8, "PCIE30_2L_0_CLKREQ_N"),
-	MT7988_PIN(9, "PCIE30_1L_1_WAKE_N"),
-	MT7988_PIN(10, "PCIE30_1L_1_CLKREQ_N"),
-	MT7988_PIN(11, "GPIO_P"),
-	MT7988_PIN(12, "WATCHDOG"),
-	MT7988_PIN(13, "GPIO_RESET"),
-	MT7988_PIN(14, "GPIO_WPS"),
-	MT7988_PIN(15, "PMIC_I2C_SCL"),
-	MT7988_PIN(16, "PMIC_I2C_SDA"),
-	MT7988_PIN(17, "I2C_1_SCL"),
-	MT7988_PIN(18, "I2C_1_SDA"),
-	MT7988_PIN(19, "PCIE30_2L_0_PRESET_N"),
-	MT7988_PIN(20, "PCIE30_1L_1_PRESET_N"),
-	MT7988_PIN(21, "PWMD1"),
-	MT7988_PIN(22, "SPI0_WP"),
-	MT7988_PIN(23, "SPI0_HOLD"),
-	MT7988_PIN(24, "SPI0_CSB"),
-	MT7988_PIN(25, "SPI0_MISO"),
-	MT7988_PIN(26, "SPI0_MOSI"),
-	MT7988_PIN(27, "SPI0_CLK"),
-	MT7988_PIN(28, "SPI1_CSB"),
-	MT7988_PIN(29, "SPI1_MISO"),
-	MT7988_PIN(30, "SPI1_MOSI"),
-	MT7988_PIN(31, "SPI1_CLK"),
-	MT7988_PIN(32, "SPI2_CLK"),
-	MT7988_PIN(33, "SPI2_MOSI"),
-	MT7988_PIN(34, "SPI2_MISO"),
-	MT7988_PIN(35, "SPI2_CSB"),
-	MT7988_PIN(36, "SPI2_HOLD"),
-	MT7988_PIN(37, "SPI2_WP"),
-	MT7988_PIN(38, "EMMC_RSTB"),
-	MT7988_PIN(39, "EMMC_DSL"),
-	MT7988_PIN(40, "EMMC_CK"),
-	MT7988_PIN(41, "EMMC_CMD"),
-	MT7988_PIN(42, "EMMC_DATA_7"),
-	MT7988_PIN(43, "EMMC_DATA_6"),
-	MT7988_PIN(44, "EMMC_DATA_5"),
-	MT7988_PIN(45, "EMMC_DATA_4"),
-	MT7988_PIN(46, "EMMC_DATA_3"),
-	MT7988_PIN(47, "EMMC_DATA_2"),
-	MT7988_PIN(48, "EMMC_DATA_1"),
-	MT7988_PIN(49, "EMMC_DATA_0"),
-	MT7988_PIN(50, "PCM_FS_I2S_LRCK"),
-	MT7988_PIN(51, "PCM_CLK_I2S_BCLK"),
-	MT7988_PIN(52, "PCM_DRX_I2S_DIN"),
-	MT7988_PIN(53, "PCM_DTX_I2S_DOUT"),
-	MT7988_PIN(54, "PCM_MCK_I2S_MCLK"),
-	MT7988_PIN(55, "UART0_RXD"),
-	MT7988_PIN(56, "UART0_TXD"),
-	MT7988_PIN(57, "PWMD0"),
-	MT7988_PIN(58, "JTAG_JTDI"),
-	MT7988_PIN(59, "JTAG_JTDO"),
-	MT7988_PIN(60, "JTAG_JTMS"),
-	MT7988_PIN(61, "JTAG_JTCLK"),
-	MT7988_PIN(62, "JTAG_JTRST_N"),
-	MT7988_PIN(63, "USB_DRV_VBUS_P1"),
-	MT7988_PIN(64, "LED_A"),
-	MT7988_PIN(65, "LED_B"),
-	MT7988_PIN(66, "LED_C"),
-	MT7988_PIN(67, "LED_D"),
-	MT7988_PIN(68, "LED_E"),
-	MT7988_PIN(69, "GPIO_B"),
-	MT7988_PIN(70, "GPIO_C"),
-	MT7988_PIN(71, "I2C_2_SCL"),
-	MT7988_PIN(72, "I2C_2_SDA"),
-	MT7988_PIN(73, "PCIE30_2L_1_PRESET_N"),
-	MT7988_PIN(74, "PCIE30_1L_0_PRESET_N"),
-	MT7988_PIN(75, "PCIE30_2L_1_WAKE_N"),
-	MT7988_PIN(76, "PCIE30_2L_1_CLKREQ_N"),
-	MT7988_PIN(77, "PCIE30_1L_0_WAKE_N"),
-	MT7988_PIN(78, "PCIE30_1L_0_CLKREQ_N"),
-	MT7988_PIN(79, "USB_DRV_VBUS_P0"),
-	MT7988_PIN(80, "UART1_RXD"),
-	MT7988_PIN(81, "UART1_TXD"),
-	MT7988_PIN(82, "UART1_CTS"),
-	MT7988_PIN(83, "UART1_RTS"),
-};
-
-/* jtag */
-static int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 };
-static int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 };
-
-static int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 };
-static int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 };
-
-static int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 };
-static int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 };
-
-static int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 };
-static int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 };
-
-static int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 };
-static int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 };
-
-static int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 };
-static int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 };
-
-/* int_usxgmii */
-static int mt7988_int_usxgmii_pins[] = { 2, 3 };
-static int mt7988_int_usxgmii_funcs[] = { 3, 3 };
-
-/* pwm */
-static int mt7988_pwm0_pins[] = { 57 };
-static int mt7988_pwm0_funcs[] = { 1 };
-
-static int mt7988_pwm1_pins[] = { 21 };
-static int mt7988_pwm1_funcs[] = { 1 };
-
-static int mt7988_pwm2_pins[] = { 80 };
-static int mt7988_pwm2_funcs[] = { 2 };
-
-static int mt7988_pwm3_pins[] = { 81 };
-static int mt7988_pwm3_funcs[] = { 2 };
-
-static int mt7988_pwm4_pins[] = { 82 };
-static int mt7988_pwm4_funcs[] = { 2 };
-
-static int mt7988_pwm5_pins[] = { 83 };
-static int mt7988_pwm5_funcs[] = { 2 };
-
-static int mt7988_pwm6_pins[] = { 69 };
-static int mt7988_pwm6_funcs[] = { 3 };
-
-static int mt7988_pwm7_pins[] = { 70 };
-static int mt7988_pwm7_funcs[] = { 3 };
-
-/* dfd */
-static int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 };
-static int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 };
-
-/* i2c */
-static int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 };
-static int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 };
-
-static int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 };
-static int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 };
-
-static int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 };
-static int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 };
-
-static int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 };
-static int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 };
-
-static int mt7988_i2c0_0_pins[] = { 5, 6 };
-static int mt7988_i2c0_0_funcs[] = { 2, 2 };
-
-static int mt7988_i2c1_sfp_pins[] = { 5, 6 };
-static int mt7988_i2c1_sfp_funcs[] = { 4, 4 };
-
-static int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 };
-static int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 };
-
-static int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 };
-static int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 };
-
-static int mt7988_i2c0_1_pins[] = { 15, 16 };
-static int mt7988_i2c0_1_funcs[] = { 1, 1 };
-
-static int mt7988_u30_phy_i2c0_pins[] = { 15, 16 };
-static int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 };
-
-static int mt7988_u32_phy_i2c0_pins[] = { 15, 16 };
-static int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 };
-
-static int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 };
-static int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 };
-
-static int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 };
-static int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 };
-
-static int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 };
-static int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 };
-
-static int mt7988_i2c1_0_pins[] = { 17, 18 };
-static int mt7988_i2c1_0_funcs[] = { 1, 1 };
-
-static int mt7988_u30_phy_i2c1_pins[] = { 17, 18 };
-static int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 };
-
-static int mt7988_u32_phy_i2c1_pins[] = { 17, 18 };
-static int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 };
-
-static int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 };
-static int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 };
-
-static int mt7988_sgmii0_i2c_pins[] = { 17, 18 };
-static int mt7988_sgmii0_i2c_funcs[] = { 5, 5 };
-
-static int mt7988_sgmii1_i2c_pins[] = { 17, 18 };
-static int mt7988_sgmii1_i2c_funcs[] = { 6, 6 };
-
-static int mt7988_i2c1_2_pins[] = { 69, 70 };
-static int mt7988_i2c1_2_funcs[] = { 2, 2 };
-
-static int mt7988_i2c2_0_pins[] = { 69, 70 };
-static int mt7988_i2c2_0_funcs[] = { 4, 4 };
-
-static int mt7988_i2c2_1_pins[] = { 71, 72 };
-static int mt7988_i2c2_1_funcs[] = { 1, 1 };
-
-/* eth */
-static int mt7988_mdc_mdio0_pins[] = { 5, 6 };
-static int mt7988_mdc_mdio0_funcs[] = { 1, 1 };
-
-static int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 };
-static int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 };
-
-static int mt7988_gbe_ext_mdio_pins[] = { 30, 31 };
-static int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 };
-
-static int mt7988_mdc_mdio1_pins[] = { 69, 70 };
-static int mt7988_mdc_mdio1_funcs[] = { 1, 1 };
-
-/* pcie */
-static int mt7988_pcie_wake_n0_0_pins[] = { 7 };
-static int mt7988_pcie_wake_n0_0_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n0_0_pins[] = { 8 };
-static int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 };
-
-static int mt7988_pcie_wake_n3_0_pins[] = { 9 };
-static int mt7988_pcie_wake_n3_0_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n3_pins[] = { 10 };
-static int mt7988_pcie_clk_req_n3_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n0_1_pins[] = { 10 };
-static int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 };
-
-static int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 };
-static int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 };
-
-static int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 };
-static int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 };
-
-static int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 };
-static int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 };
-
-static int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 };
-static int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 };
-
-static int mt7988_ckm_phy_i2c_pins[] = { 9, 10 };
-static int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 };
-
-static int mt7988_pcie_wake_n0_1_pins[] = { 13 };
-static int mt7988_pcie_wake_n0_1_funcs[] = { 2 };
-
-static int mt7988_pcie_wake_n3_1_pins[] = { 14 };
-static int mt7988_pcie_wake_n3_1_funcs[] = { 2 };
-
-static int mt7988_pcie_2l_0_pereset_pins[] = { 19 };
-static int mt7988_pcie_2l_0_pereset_funcs[] = { 1 };
-
-static int mt7988_pcie_1l_1_pereset_pins[] = { 20 };
-static int mt7988_pcie_1l_1_pereset_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n2_1_pins[] = { 63 };
-static int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 };
-
-static int mt7988_pcie_2l_1_pereset_pins[] = { 73 };
-static int mt7988_pcie_2l_1_pereset_funcs[] = { 1 };
-
-static int mt7988_pcie_1l_0_pereset_pins[] = { 74 };
-static int mt7988_pcie_1l_0_pereset_funcs[] = { 1 };
-
-static int mt7988_pcie_wake_n1_0_pins[] = { 75 };
-static int mt7988_pcie_wake_n1_0_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n1_pins[] = { 76 };
-static int mt7988_pcie_clk_req_n1_funcs[] = { 1 };
-
-static int mt7988_pcie_wake_n2_0_pins[] = { 77 };
-static int mt7988_pcie_wake_n2_0_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n2_0_pins[] = { 78 };
-static int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 };
-
-static int mt7988_pcie_wake_n2_1_pins[] = { 79 };
-static int mt7988_pcie_wake_n2_1_funcs[] = { 2 };
-
-/* pmic */
-static int mt7988_pmic_pins[] = { 11 };
-static int mt7988_pmic_funcs[] = { 1 };
-
-/* watchdog */
-static int mt7988_watchdog_pins[] = { 12 };
-static int mt7988_watchdog_funcs[] = { 1 };
-
-/* spi */
-static int mt7988_spi0_wp_hold_pins[] = { 22, 23 };
-static int mt7988_spi0_wp_hold_funcs[] = { 1, 1 };
-
-static int mt7988_spi0_pins[] = { 24, 25, 26, 27 };
-static int mt7988_spi0_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_spi1_pins[] = { 28, 29, 30, 31 };
-static int mt7988_spi1_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_spi2_pins[] = { 32, 33, 34, 35 };
-static int mt7988_spi2_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_spi2_wp_hold_pins[] = { 36, 37 };
-static int mt7988_spi2_wp_hold_funcs[] = { 1, 1 };
-
-/* flash */
-static int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 };
-static int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
-
-static int mt7988_emmc_45_pins[] = {
-	21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37
-};
-static int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 };
-
-static int mt7988_sdcard_pins[] = { 32, 33, 34, 35, 36, 37 };
-static int mt7988_sdcard_funcs[] = { 5, 5, 5, 5, 5, 5 };
-
-static int mt7988_emmc_51_pins[] = { 38, 39, 40, 41, 42, 43,
-				     44, 45, 46, 47, 48, 49 };
-static int mt7988_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
-
-/* uart */
-static int mt7988_uart2_pins[] = { 0, 1, 2, 3 };
-static int mt7988_uart2_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_tops_uart0_0_pins[] = { 22, 23 };
-static int mt7988_tops_uart0_0_funcs[] = { 3, 3 };
-
-static int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 };
-static int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 };
-
-static int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 };
-static int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 };
-
-static int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 };
-static int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 };
-
-static int mt7988_net_wo0_uart_txd_0_pins[] = { 28 };
-static int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 };
-
-static int mt7988_net_wo1_uart_txd_0_pins[] = { 29 };
-static int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 };
-
-static int mt7988_net_wo2_uart_txd_0_pins[] = { 30 };
-static int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 };
-
-static int mt7988_tops_uart1_0_pins[] = { 28, 29 };
-static int mt7988_tops_uart1_0_funcs[] = { 4, 4 };
-
-static int mt7988_tops_uart0_1_pins[] = { 30, 31 };
-static int mt7988_tops_uart0_1_funcs[] = { 4, 4 };
-
-static int mt7988_tops_uart1_1_pins[] = { 36, 37 };
-static int mt7988_tops_uart1_1_funcs[] = { 3, 3 };
-
-static int mt7988_uart0_pins[] = { 55, 56 };
-static int mt7988_uart0_funcs[] = { 1, 1 };
-
-static int mt7988_tops_uart0_2_pins[] = { 55, 56 };
-static int mt7988_tops_uart0_2_funcs[] = { 2, 2 };
-
-static int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 };
-static int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 };
-
-static int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 };
-static int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 };
-
-static int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 };
-static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 };
-
-static int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 };
-static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_tops_uart1_2_pins[] = { 80, 81 };
-static int mt7988_tops_uart1_2_funcs[] = {
-	4,
-	4,
-};
-
-static int mt7988_net_wo0_uart_txd_1_pins[] = { 80 };
-static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 };
-
-static int mt7988_net_wo1_uart_txd_1_pins[] = { 81 };
-static int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 };
-
-static int mt7988_net_wo2_uart_txd_1_pins[] = { 82 };
-static int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 };
-
-/* udi */
-static int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 };
-static int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 };
-
-/* i2s */
-static int mt7988_i2s_pins[] = { 50, 51, 52, 53, 54 };
-static int mt7988_i2s_funcs[] = { 1, 1, 1, 1, 1 };
-
-/* pcm */
-static int mt7988_pcm_pins[] = { 50, 51, 52, 53 };
-static int mt7988_pcm_funcs[] = { 1, 1, 1, 1 };
-
-/* led */
-static int mt7988_gbe0_led1_pins[] = { 58 };
-static int mt7988_gbe0_led1_funcs[] = { 6 };
-static int mt7988_gbe1_led1_pins[] = { 59 };
-static int mt7988_gbe1_led1_funcs[] = { 6 };
-static int mt7988_gbe2_led1_pins[] = { 60 };
-static int mt7988_gbe2_led1_funcs[] = { 6 };
-static int mt7988_gbe3_led1_pins[] = { 61 };
-static int mt7988_gbe3_led1_funcs[] = { 6 };
-
-static int mt7988_2p5gbe_led1_pins[] = { 62 };
-static int mt7988_2p5gbe_led1_funcs[] = { 6 };
-
-static int mt7988_gbe0_led0_pins[] = { 64 };
-static int mt7988_gbe0_led0_funcs[] = { 1 };
-static int mt7988_gbe1_led0_pins[] = { 65 };
-static int mt7988_gbe1_led0_funcs[] = { 1 };
-static int mt7988_gbe2_led0_pins[] = { 66 };
-static int mt7988_gbe2_led0_funcs[] = { 1 };
-static int mt7988_gbe3_led0_pins[] = { 67 };
-static int mt7988_gbe3_led0_funcs[] = { 1 };
-
-static int mt7988_2p5gbe_led0_pins[] = { 68 };
-static int mt7988_2p5gbe_led0_funcs[] = { 1 };
-
-/* usb */
-static int mt7988_drv_vbus_p1_pins[] = { 63 };
-static int mt7988_drv_vbus_p1_funcs[] = { 1 };
-
-static int mt7988_drv_vbus_pins[] = { 79 };
-static int mt7988_drv_vbus_funcs[] = { 1 };
-
-static const struct group_desc mt7988_groups[] = {
-	/*  @GPIO(0,1,2,3): uart2 */
-	PINCTRL_PIN_GROUP("uart2", mt7988_uart2),
-	/*  @GPIO(0,1,2,3,4): tops_jtag0_0 */
-	PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0),
-	/*  @GPIO(2,3): int_usxgmii */
-	PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii),
-	/*  @GPIO(0,1,2,3,4): dfd */
-	PINCTRL_PIN_GROUP("dfd", mt7988_dfd),
-	/*  @GPIO(0,1): xfi_phy0_i2c0 */
-	PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0),
-	/*  @GPIO(0,1): xfi_phy1_i2c0 */
-	PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0),
-	/*  @GPIO(3,4): xfi_phy_pll_i2c0 */
-	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0),
-	/*  @GPIO(3,4): xfi_phy_pll_i2c1 */
-	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1),
-	/*  @GPIO(5,6) i2c0_0 */
-	PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0),
-	/*  @GPIO(5,6) i2c1_sfp */
-	PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp),
-	/*  @GPIO(5,6) xfi_pextp_phy0_i2c */
-	PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c),
-	/*  @GPIO(5,6) xfi_pextp_phy1_i2c */
-	PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c),
-	/*  @GPIO(5,6) mdc_mdio0 */
-	PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0),
-	/*  @GPIO(7): pcie_wake_n0_0 */
-	PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0),
-	/*  @GPIO(8): pcie_clk_req_n0_0 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0),
-	/*  @GPIO(9): pcie_wake_n3_0 */
-	PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0),
-	/*  @GPIO(10): pcie_clk_req_n3 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3),
-	/*  @GPIO(10): pcie_clk_req_n0_1 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1),
-	/*  @GPIO(7,8) pcie_p0_phy_i2c */
-	PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c),
-	/*  @GPIO(7,8) pcie_p1_phy_i2c */
-	PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c),
-	/*  @GPIO(7,8) pcie_p2_phy_i2c */
-	PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c),
-	/*  @GPIO(9,10) pcie_p3_phy_i2c */
-	PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c),
-	/*  @GPIO(9,10) ckm_phy_i2c */
-	PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c),
-	/*  @GPIO(11): pmic */
-	PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic),
-	/*  @GPIO(12): watchdog */
-	PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog),
-	/*  @GPIO(13): pcie_wake_n0_1 */
-	PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1),
-	/*  @GPIO(14): pcie_wake_n3_1 */
-	PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1),
-	/*  @GPIO(15,16) i2c0_1 */
-	PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1),
-	/*  @GPIO(15,16) u30_phy_i2c0 */
-	PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0),
-	/*  @GPIO(15,16) u32_phy_i2c0 */
-	PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0),
-	/*  @GPIO(15,16) xfi_phy0_i2c1 */
-	PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1),
-	/*  @GPIO(15,16) xfi_phy1_i2c1 */
-	PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1),
-	/*  @GPIO(15,16) xfi_phy_pll_i2c2 */
-	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2),
-	/*  @GPIO(17,18) i2c1_0 */
-	PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0),
-	/*  @GPIO(17,18) u30_phy_i2c1 */
-	PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1),
-	/*  @GPIO(17,18) u32_phy_i2c1 */
-	PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1),
-	/*  @GPIO(17,18) xfi_phy_pll_i2c3 */
-	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3),
-	/*  @GPIO(17,18) sgmii0_i2c */
-	PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c),
-	/*  @GPIO(17,18) sgmii1_i2c */
-	PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c),
-	/*  @GPIO(19): pcie_2l_0_pereset */
-	PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset),
-	/*  @GPIO(20): pcie_1l_1_pereset */
-	PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset),
-	/*  @GPIO(21): pwm1 */
-	PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1),
-	/*  @GPIO(22,23) spi0_wp_hold */
-	PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold),
-	/*  @GPIO(24,25,26,27) spi0 */
-	PINCTRL_PIN_GROUP("spi0", mt7988_spi0),
-	/*  @GPIO(28,29,30,31) spi1 */
-	PINCTRL_PIN_GROUP("spi1", mt7988_spi1),
-	/*  @GPIO(32,33,34,35) spi2 */
-	PINCTRL_PIN_GROUP("spi2", mt7988_spi2),
-	/*  @GPIO(36,37) spi2_wp_hold */
-	PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold),
-	/*  @GPIO(22,23,24,25,26,27) snfi */
-	PINCTRL_PIN_GROUP("snfi", mt7988_snfi),
-	/*  @GPIO(22,23) tops_uart0_0 */
-	PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0),
-	/*  @GPIO(28,29,30,31) uart2_0 */
-	PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0),
-	/*  @GPIO(32,33,34,35) uart1_0 */
-	PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0),
-	/*  @GPIO(32,33,34,35) uart2_1 */
-	PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1),
-	/*  @GPIO(28) net_wo0_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
-	/*  @GPIO(29) net_wo1_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
-	/*  @GPIO(30) net_wo2_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
-	/*  @GPIO(28,29) tops_uart1_0 */
-	PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0),
-	/*  @GPIO(30,31) tops_uart0_1 */
-	PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1),
-	/*  @GPIO(36,37) tops_uart1_1 */
-	PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1),
-	/*  @GPIO(32,33,34,35,36) udi */
-	PINCTRL_PIN_GROUP("udi", mt7988_udi),
-	/*  @GPIO(21,28,29,30,31,32,33,34,35,36,37) emmc_45 */
-	PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45),
-	/*  @GPIO(32,33,34,35,36,37) sdcard */
-	PINCTRL_PIN_GROUP("sdcard", mt7988_sdcard),
-	/*  @GPIO(38,39,40,41,42,43,44,45,46,47,48,49) emmc_51 */
-	PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51),
-	/*  @GPIO(28,29) 2p5g_ext_mdio */
-	PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio),
-	/*  @GPIO(30,31) gbe_ext_mdio */
-	PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio),
-	/*  @GPIO(50,51,52,53,54) i2s */
-	PINCTRL_PIN_GROUP("i2s", mt7988_i2s),
-	/*  @GPIO(50,51,52,53) pcm */
-	PINCTRL_PIN_GROUP("pcm", mt7988_pcm),
-	/*  @GPIO(55,56) uart0 */
-	PINCTRL_PIN_GROUP("uart0", mt7988_uart0),
-	/*  @GPIO(55,56) tops_uart0_2 */
-	PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2),
-	/*  @GPIO(50,51,52,53) uart2_2 */
-	PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2),
-	/*  @GPIO(50,51,52,53,54) wo0_jtag */
-	PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag),
-	/*  @GPIO(50,51,52,53,54) wo1-wo1_jtag */
-	PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag),
-	/*  @GPIO(50,51,52,53,54) wo2_jtag */
-	PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag),
-	/*  @GPIO(57) pwm0 */
-	PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0),
-	/*  @GPIO(58,59,60,61,62) jtag */
-	PINCTRL_PIN_GROUP("jtag", mt7988_jtag),
-	/*  @GPIO(58,59,60,61,62) tops_jtag0_1 */
-	PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1),
-	/*  @GPIO(58,59,60,61) uart2_3 */
-	PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3),
-	/*  @GPIO(58,59,60,61) uart1_1 */
-	PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1),
-	/*  @GPIO(58,59,60,61) gbe_led1 */
-	PINCTRL_PIN_GROUP("gbe0_led1", mt7988_gbe0_led1),
-	PINCTRL_PIN_GROUP("gbe1_led1", mt7988_gbe1_led1),
-	PINCTRL_PIN_GROUP("gbe2_led1", mt7988_gbe2_led1),
-	PINCTRL_PIN_GROUP("gbe3_led1", mt7988_gbe3_led1),
-	/*  @GPIO(62) 2p5gbe_led1 */
-	PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1),
-	/*  @GPIO(64,65,66,67) gbe_led0 */
-	PINCTRL_PIN_GROUP("gbe0_led0", mt7988_gbe0_led0),
-	PINCTRL_PIN_GROUP("gbe1_led0", mt7988_gbe1_led0),
-	PINCTRL_PIN_GROUP("gbe2_led0", mt7988_gbe2_led0),
-	PINCTRL_PIN_GROUP("gbe3_led0", mt7988_gbe3_led0),
-	/*  @GPIO(68) 2p5gbe_led0 */
-	PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0),
-	/*  @GPIO(63) drv_vbus_p1 */
-	PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1),
-	/*  @GPIO(63) pcie_clk_req_n2_1 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1),
-	/*  @GPIO(69, 70) mdc_mdio1 */
-	PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1),
-	/*  @GPIO(69, 70) i2c1_2 */
-	PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2),
-	/*  @GPIO(69) pwm6 */
-	PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6),
-	/*  @GPIO(70) pwm7 */
-	PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7),
-	/*  @GPIO(69,70) i2c2_0 */
-	PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0),
-	/*  @GPIO(71,72) i2c2_1 */
-	PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1),
-	/*  @GPIO(73) pcie_2l_1_pereset */
-	PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset),
-	/*  @GPIO(74) pcie_1l_0_pereset */
-	PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset),
-	/*  @GPIO(75) pcie_wake_n1_0 */
-	PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0),
-	/*  @GPIO(76) pcie_clk_req_n1 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1),
-	/*  @GPIO(77) pcie_wake_n2_0 */
-	PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0),
-	/*  @GPIO(78) pcie_clk_req_n2_0 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0),
-	/*  @GPIO(79) drv_vbus */
-	PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus),
-	/*  @GPIO(79) pcie_wake_n2_1 */
-	PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1),
-	/*  @GPIO(80,81,82,83) uart1_2 */
-	PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2),
-	/*  @GPIO(80) pwm2 */
-	PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2),
-	/*  @GPIO(81) pwm3 */
-	PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3),
-	/*  @GPIO(82) pwm4 */
-	PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4),
-	/*  @GPIO(83) pwm5 */
-	PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5),
-	/*  @GPIO(80) net_wo0_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
-	/*  @GPIO(81) net_wo1_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
-	/*  @GPIO(82) net_wo2_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
-	/*  @GPIO(80,81) tops_uart1_2 */
-	PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2),
-	/*  @GPIO(80) net_wo0_uart_txd_1 */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1),
-	/*  @GPIO(81) net_wo1_uart_txd_1 */
-	PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1),
-	/*  @GPIO(82) net_wo2_uart_txd_1 */
-	PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1),
-};
-
-/* Joint those groups owning the same capability in user point of view which
- * allows that people tend to use through the device tree.
- */
-static const char *mt7988_jtag_groups[] = {
-	"tops_jtag0_0", "wo0_jtag", "wo1_jtag",
-	"wo2_jtag",	"jtag",	    "tops_jtag0_1",
-};
-static const char *mt7988_int_usxgmii_groups[] = {
-	"int_usxgmii",
-};
-static const char *mt7988_pwm_groups[] = {
-	"pwm0", "pwm1", "pwm2", "pwm3", "pwm4",	"pwm5",	"pwm6", "pwm7"
-};
-static const char *mt7988_dfd_groups[] = {
-	"dfd",
-};
-static const char *mt7988_i2c_groups[] = {
-	"xfi_phy0_i2c0",
-	"xfi_phy1_i2c0",
-	"xfi_phy_pll_i2c0",
-	"xfi_phy_pll_i2c1",
-	"i2c0_0",
-	"i2c1_sfp",
-	"xfi_pextp_phy0_i2c",
-	"xfi_pextp_phy1_i2c",
-	"i2c0_1",
-	"u30_phy_i2c0",
-	"u32_phy_i2c0",
-	"xfi_phy0_i2c1",
-	"xfi_phy1_i2c1",
-	"xfi_phy_pll_i2c2",
-	"i2c1_0",
-	"u30_phy_i2c1",
-	"u32_phy_i2c1",
-	"xfi_phy_pll_i2c3",
-	"sgmii0_i2c",
-	"sgmii1_i2c",
-	"i2c1_2",
-	"i2c2_0",
-	"i2c2_1",
-};
-static const char *mt7988_ethernet_groups[] = {
-	"mdc_mdio0",
-	"2p5g_ext_mdio",
-	"gbe_ext_mdio",
-	"mdc_mdio1",
-};
-static const char *mt7988_pcie_groups[] = {
-	"pcie_wake_n0_0",    "pcie_clk_req_n0_0", "pcie_wake_n3_0",
-	"pcie_clk_req_n3",   "pcie_p0_phy_i2c",	  "pcie_p1_phy_i2c",
-	"pcie_p3_phy_i2c",   "pcie_p2_phy_i2c",	  "ckm_phy_i2c",
-	"pcie_wake_n0_1",    "pcie_wake_n3_1",	  "pcie_2l_0_pereset",
-	"pcie_1l_1_pereset", "pcie_clk_req_n2_1", "pcie_2l_1_pereset",
-	"pcie_1l_0_pereset", "pcie_wake_n1_0",	  "pcie_clk_req_n1",
-	"pcie_wake_n2_0",    "pcie_clk_req_n2_0", "pcie_wake_n2_1",
-	"pcie_clk_req_n0_1"
-};
-static const char *mt7988_pmic_groups[] = {
-	"pmic",
-};
-static const char *mt7988_wdt_groups[] = {
-	"watchdog",
-};
-static const char *mt7988_spi_groups[] = {
-	"spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold",
-};
-static const char *mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi",
-						    "emmc_51" };
-static const char *mt7988_uart_groups[] = {
-	"uart2",
-	"tops_uart0_0",
-	"uart2_0",
-	"uart1_0",
-	"uart2_1",
-	"net_wo0_uart_txd_0",
-	"net_wo1_uart_txd_0",
-	"net_wo2_uart_txd_0",
-	"tops_uart1_0",
-	"ops_uart0_1",
-	"ops_uart1_1",
-	"uart0",
-	"tops_uart0_2",
-	"uart1_1",
-	"uart2_3",
-	"uart1_2",
-	"tops_uart1_2",
-	"net_wo0_uart_txd_1",
-	"net_wo1_uart_txd_1",
-	"net_wo2_uart_txd_1",
-};
-static const char *mt7988_udi_groups[] = {
-	"udi",
-};
-static const char *mt7988_audio_groups[] = {
-	"i2s", "pcm",
-};
-static const char *mt7988_led_groups[] = {
-	"gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1",
-	"gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0",
-	"wf5g_led0",   "wf5g_led1",
-};
-static const char *mt7988_usb_groups[] = {
-	"drv_vbus",
-	"drv_vbus_p1",
-};
-
-static const struct function_desc mt7988_functions[] = {
-	{ "audio", mt7988_audio_groups, ARRAY_SIZE(mt7988_audio_groups) },
-	{ "jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups) },
-	{ "int_usxgmii", mt7988_int_usxgmii_groups,
-	  ARRAY_SIZE(mt7988_int_usxgmii_groups) },
-	{ "pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups) },
-	{ "dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups) },
-	{ "i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups) },
-	{ "eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups) },
-	{ "pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups) },
-	{ "pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups) },
-	{ "watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups) },
-	{ "spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups) },
-	{ "flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups) },
-	{ "uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups) },
-	{ "udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups) },
-	{ "usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups) },
-	{ "led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups) },
-};
-
-static const struct mtk_eint_hw mt7988_eint_hw = {
-	.port_mask = 7,
-	.ports = 7,
-	.ap_num = ARRAY_SIZE(mt7988_pins),
-	.db_cnt = 16,
-};
-
-static const char *mt7988_pinctrl_register_base_names[] = {
-	"gpio_base",	 "iocfg_tr_base", "iocfg_br_base",
-	"iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
-};
-
-static struct mtk_pin_soc mt7988_data = {
-	.reg_cal = mt7988_reg_cals,
-	.pins = mt7988_pins,
-	.npins = ARRAY_SIZE(mt7988_pins),
-	.grps = mt7988_groups,
-	.ngrps = ARRAY_SIZE(mt7988_groups),
-	.funcs = mt7988_functions,
-	.nfuncs = ARRAY_SIZE(mt7988_functions),
-	.eint_hw = &mt7988_eint_hw,
-	.gpio_m = 0,
-	.ies_present = false,
-	.base_names = mt7988_pinctrl_register_base_names,
-	.nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names),
-	.bias_disable_set = mtk_pinconf_bias_disable_set,
-	.bias_disable_get = mtk_pinconf_bias_disable_get,
-	.bias_set = mtk_pinconf_bias_set,
-	.bias_get = mtk_pinconf_bias_get,
-	.drive_set = mtk_pinconf_drive_set_rev1,
-	.drive_get = mtk_pinconf_drive_get_rev1,
-	.adv_pull_get = mtk_pinconf_adv_pull_get,
-	.adv_pull_set = mtk_pinconf_adv_pull_set,
-};
-
-static const struct of_device_id mt7988_pinctrl_of_match[] = {
-	{
-		.compatible = "mediatek,mt7988-pinctrl",
-	},
-	{}
-};
-
-static int mt7988_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_moore_pinctrl_probe(pdev, &mt7988_data);
-}
-
-static struct platform_driver mt7988_pinctrl_driver = {
-	.driver = {
-		.name = "mt7988-pinctrl",
-		.of_match_table = mt7988_pinctrl_of_match,
-	},
-	.probe = mt7988_pinctrl_probe,
-};
-
-static int __init mt7988_pinctrl_init(void)
-{
-	return platform_driver_register(&mt7988_pinctrl_driver);
-}
-arch_initcall(mt7988_pinctrl_init);

target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7981-clk.h

@@ -1,215 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Wenzhen.Yu <[email protected]>
- * Author: Jianhui Zhao <[email protected]>
- * Author: Daniel Golle <[email protected]>
- */
-
-#ifndef _DT_BINDINGS_CLK_MT7981_H
-#define _DT_BINDINGS_CLK_MT7981_H
-
-/* TOPCKGEN */
-#define CLK_TOP_CB_CKSQ_40M		0
-#define CLK_TOP_CB_M_416M		1
-#define CLK_TOP_CB_M_D2			2
-#define CLK_TOP_CB_M_D3			3
-#define CLK_TOP_M_D3_D2			4
-#define CLK_TOP_CB_M_D4			5
-#define CLK_TOP_CB_M_D8			6
-#define CLK_TOP_M_D8_D2			7
-#define CLK_TOP_CB_MM_720M		8
-#define CLK_TOP_CB_MM_D2		9
-#define CLK_TOP_CB_MM_D3		10
-#define CLK_TOP_CB_MM_D3_D5		11
-#define CLK_TOP_CB_MM_D4		12
-#define CLK_TOP_CB_MM_D6		13
-#define CLK_TOP_MM_D6_D2		14
-#define CLK_TOP_CB_MM_D8		15
-#define CLK_TOP_CB_APLL2_196M		16
-#define CLK_TOP_APLL2_D2		17
-#define CLK_TOP_APLL2_D4		18
-#define CLK_TOP_NET1_2500M		19
-#define CLK_TOP_CB_NET1_D4		20
-#define CLK_TOP_CB_NET1_D5		21
-#define CLK_TOP_NET1_D5_D2		22
-#define CLK_TOP_NET1_D5_D4		23
-#define CLK_TOP_CB_NET1_D8		24
-#define CLK_TOP_NET1_D8_D2		25
-#define CLK_TOP_NET1_D8_D4		26
-#define CLK_TOP_CB_NET2_800M		27
-#define CLK_TOP_CB_NET2_D2		28
-#define CLK_TOP_CB_NET2_D4		29
-#define CLK_TOP_NET2_D4_D2		30
-#define CLK_TOP_NET2_D4_D4		31
-#define CLK_TOP_CB_NET2_D6		32
-#define CLK_TOP_CB_WEDMCU_208M		33
-#define CLK_TOP_CB_SGM_325M		34
-#define CLK_TOP_CKSQ_40M_D2		35
-#define CLK_TOP_CB_RTC_32K		36
-#define CLK_TOP_CB_RTC_32P7K		37
-#define CLK_TOP_USB_TX250M		38
-#define CLK_TOP_FAUD			39
-#define CLK_TOP_NFI1X			40
-#define CLK_TOP_USB_EQ_RX250M		41
-#define CLK_TOP_USB_CDR_CK		42
-#define CLK_TOP_USB_LN0_CK		43
-#define CLK_TOP_SPINFI_BCK		44
-#define CLK_TOP_SPI			45
-#define CLK_TOP_SPIM_MST		46
-#define CLK_TOP_UART_BCK		47
-#define CLK_TOP_PWM_BCK			48
-#define CLK_TOP_I2C_BCK			49
-#define CLK_TOP_PEXTP_TL		50
-#define CLK_TOP_EMMC_208M		51
-#define CLK_TOP_EMMC_400M		52
-#define CLK_TOP_DRAMC_REF		53
-#define CLK_TOP_DRAMC_MD32		54
-#define CLK_TOP_SYSAXI			55
-#define CLK_TOP_SYSAPB			56
-#define CLK_TOP_ARM_DB_MAIN		57
-#define CLK_TOP_AP2CNN_HOST		58
-#define CLK_TOP_NETSYS			59
-#define CLK_TOP_NETSYS_500M		60
-#define CLK_TOP_NETSYS_WED_MCU		61
-#define CLK_TOP_NETSYS_2X		62
-#define CLK_TOP_SGM_325M		63
-#define CLK_TOP_SGM_REG			64
-#define CLK_TOP_F26M			65
-#define CLK_TOP_EIP97B			66
-#define CLK_TOP_USB3_PHY		67
-#define CLK_TOP_AUD			68
-#define CLK_TOP_A1SYS			69
-#define CLK_TOP_AUD_L			70
-#define CLK_TOP_A_TUNER			71
-#define CLK_TOP_U2U3_REF		72
-#define CLK_TOP_U2U3_SYS		73
-#define CLK_TOP_U2U3_XHCI		74
-#define CLK_TOP_USB_FRMCNT		75
-#define CLK_TOP_NFI1X_SEL		76
-#define CLK_TOP_SPINFI_SEL		77
-#define CLK_TOP_SPI_SEL			78
-#define CLK_TOP_SPIM_MST_SEL		79
-#define CLK_TOP_UART_SEL		80
-#define CLK_TOP_PWM_SEL			81
-#define CLK_TOP_I2C_SEL			82
-#define CLK_TOP_PEXTP_TL_SEL		83
-#define CLK_TOP_EMMC_208M_SEL		84
-#define CLK_TOP_EMMC_400M_SEL		85
-#define CLK_TOP_F26M_SEL		86
-#define CLK_TOP_DRAMC_SEL		87
-#define CLK_TOP_DRAMC_MD32_SEL		88
-#define CLK_TOP_SYSAXI_SEL		89
-#define CLK_TOP_SYSAPB_SEL		90
-#define CLK_TOP_ARM_DB_MAIN_SEL		91
-#define CLK_TOP_AP2CNN_HOST_SEL		92
-#define CLK_TOP_NETSYS_SEL		93
-#define CLK_TOP_NETSYS_500M_SEL		94
-#define CLK_TOP_NETSYS_MCU_SEL		95
-#define CLK_TOP_NETSYS_2X_SEL		96
-#define CLK_TOP_SGM_325M_SEL		97
-#define CLK_TOP_SGM_REG_SEL		98
-#define CLK_TOP_EIP97B_SEL		99
-#define CLK_TOP_USB3_PHY_SEL		100
-#define CLK_TOP_AUD_SEL			101
-#define CLK_TOP_A1SYS_SEL		102
-#define CLK_TOP_AUD_L_SEL		103
-#define CLK_TOP_A_TUNER_SEL		104
-#define CLK_TOP_U2U3_SEL		105
-#define CLK_TOP_U2U3_SYS_SEL		106
-#define CLK_TOP_U2U3_XHCI_SEL		107
-#define CLK_TOP_USB_FRMCNT_SEL		108
-#define CLK_TOP_AUD_I2S_M		109
-
-/* INFRACFG */
-#define CLK_INFRA_66M_MCK		0
-#define CLK_INFRA_UART0_SEL		1
-#define CLK_INFRA_UART1_SEL		2
-#define CLK_INFRA_UART2_SEL		3
-#define CLK_INFRA_SPI0_SEL		4
-#define CLK_INFRA_SPI1_SEL		5
-#define CLK_INFRA_SPI2_SEL		6
-#define CLK_INFRA_PWM1_SEL		7
-#define CLK_INFRA_PWM2_SEL		8
-#define CLK_INFRA_PWM3_SEL		9
-#define CLK_INFRA_PWM_BSEL		10
-#define CLK_INFRA_PCIE_SEL		11
-#define CLK_INFRA_GPT_STA		12
-#define CLK_INFRA_PWM_HCK		13
-#define CLK_INFRA_PWM_STA		14
-#define CLK_INFRA_PWM1_CK		15
-#define CLK_INFRA_PWM2_CK		16
-#define CLK_INFRA_PWM3_CK		17
-#define CLK_INFRA_CQ_DMA_CK		18
-#define CLK_INFRA_AUD_BUS_CK		19
-#define CLK_INFRA_AUD_26M_CK		20
-#define CLK_INFRA_AUD_L_CK		21
-#define CLK_INFRA_AUD_AUD_CK		22
-#define CLK_INFRA_AUD_EG2_CK		23
-#define CLK_INFRA_DRAMC_26M_CK		24
-#define CLK_INFRA_DBG_CK		25
-#define CLK_INFRA_AP_DMA_CK		26
-#define CLK_INFRA_SEJ_CK		27
-#define CLK_INFRA_SEJ_13M_CK		28
-#define CLK_INFRA_THERM_CK		29
-#define CLK_INFRA_I2C0_CK		30
-#define CLK_INFRA_UART0_CK		31
-#define CLK_INFRA_UART1_CK		32
-#define CLK_INFRA_UART2_CK		33
-#define CLK_INFRA_SPI2_CK		34
-#define CLK_INFRA_SPI2_HCK_CK		35
-#define CLK_INFRA_NFI1_CK		36
-#define CLK_INFRA_SPINFI1_CK		37
-#define CLK_INFRA_NFI_HCK_CK		38
-#define CLK_INFRA_SPI0_CK		39
-#define CLK_INFRA_SPI1_CK		40
-#define CLK_INFRA_SPI0_HCK_CK		41
-#define CLK_INFRA_SPI1_HCK_CK		42
-#define CLK_INFRA_FRTC_CK		43
-#define CLK_INFRA_MSDC_CK		44
-#define CLK_INFRA_MSDC_HCK_CK		45
-#define CLK_INFRA_MSDC_133M_CK		46
-#define CLK_INFRA_MSDC_66M_CK		47
-#define CLK_INFRA_ADC_26M_CK		48
-#define CLK_INFRA_ADC_FRC_CK		49
-#define CLK_INFRA_FBIST2FPC_CK		50
-#define CLK_INFRA_I2C_MCK_CK		51
-#define CLK_INFRA_I2C_PCK_CK		52
-#define CLK_INFRA_IUSB_133_CK		53
-#define CLK_INFRA_IUSB_66M_CK		54
-#define CLK_INFRA_IUSB_SYS_CK		55
-#define CLK_INFRA_IUSB_CK		56
-#define CLK_INFRA_IPCIE_CK		57
-#define CLK_INFRA_IPCIE_PIPE_CK		58
-#define CLK_INFRA_IPCIER_CK		59
-#define CLK_INFRA_IPCIEB_CK		60
-
-/* APMIXEDSYS */
-#define CLK_APMIXED_ARMPLL		0
-#define CLK_APMIXED_NET2PLL		1
-#define CLK_APMIXED_MMPLL		2
-#define CLK_APMIXED_SGMPLL		3
-#define CLK_APMIXED_WEDMCUPLL		4
-#define CLK_APMIXED_NET1PLL		5
-#define CLK_APMIXED_MPLL		6
-#define CLK_APMIXED_APLL2		7
-
-/* SGMIISYS_0 */
-#define CLK_SGM0_TX_EN			0
-#define CLK_SGM0_RX_EN			1
-#define CLK_SGM0_CK0_EN			2
-#define CLK_SGM0_CDR_CK0_EN		3
-
-/* SGMIISYS_1 */
-#define CLK_SGM1_TX_EN			0
-#define CLK_SGM1_RX_EN			1
-#define CLK_SGM1_CK1_EN			2
-#define CLK_SGM1_CDR_CK1_EN		3
-
-/* ETHSYS */
-#define CLK_ETH_FE_EN			0
-#define CLK_ETH_GP2_EN			1
-#define CLK_ETH_GP1_EN			2
-#define CLK_ETH_WOCPU0_EN		3
-
-#endif /* _DT_BINDINGS_CLK_MT7981_H */

target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7988-clk.h

@@ -1,276 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- * Author: Xiufeng Li <[email protected]>
- */
-
-#ifndef _DT_BINDINGS_CLK_MT7988_H
-#define _DT_BINDINGS_CLK_MT7988_H
-
-/* APMIXEDSYS */
-
-#define CLK_APMIXED_NETSYSPLL  0
-#define CLK_APMIXED_MPLL       1
-#define CLK_APMIXED_MMPLL      2
-#define CLK_APMIXED_APLL2      3
-#define CLK_APMIXED_NET1PLL    4
-#define CLK_APMIXED_NET2PLL    5
-#define CLK_APMIXED_WEDMCUPLL  6
-#define CLK_APMIXED_SGMPLL     7
-#define CLK_APMIXED_ARM_B      8
-#define CLK_APMIXED_CCIPLL2_B  9
-#define CLK_APMIXED_USXGMIIPLL 10
-#define CLK_APMIXED_MSDCPLL    11
-
-/* TOPCKGEN */
-
-#define CLK_TOP_XTAL		       0
-#define CLK_TOP_XTAL_D2		       1
-#define CLK_TOP_RTC_32K		       2
-#define CLK_TOP_RTC_32P7K	       3
-#define CLK_TOP_MPLL_D2		       4
-#define CLK_TOP_MPLL_D3_D2	       5
-#define CLK_TOP_MPLL_D4		       6
-#define CLK_TOP_MPLL_D8		       7
-#define CLK_TOP_MPLL_D8_D2	       8
-#define CLK_TOP_MMPLL_D2	       9
-#define CLK_TOP_MMPLL_D3_D5	       10
-#define CLK_TOP_MMPLL_D4	       11
-#define CLK_TOP_MMPLL_D6_D2	       12
-#define CLK_TOP_MMPLL_D8	       13
-#define CLK_TOP_APLL2_D4	       14
-#define CLK_TOP_NET1PLL_D4	       15
-#define CLK_TOP_NET1PLL_D5	       16
-#define CLK_TOP_NET1PLL_D5_D2	       17
-#define CLK_TOP_NET1PLL_D5_D4	       18
-#define CLK_TOP_NET1PLL_D8	       19
-#define CLK_TOP_NET1PLL_D8_D2	       20
-#define CLK_TOP_NET1PLL_D8_D4	       21
-#define CLK_TOP_NET1PLL_D8_D8	       22
-#define CLK_TOP_NET1PLL_D8_D16	       23
-#define CLK_TOP_NET2PLL_D2	       24
-#define CLK_TOP_NET2PLL_D4	       25
-#define CLK_TOP_NET2PLL_D4_D4	       26
-#define CLK_TOP_NET2PLL_D4_D8	       27
-#define CLK_TOP_NET2PLL_D6	       28
-#define CLK_TOP_NET2PLL_D8	       29
-#define CLK_TOP_NETSYS_SEL	       30
-#define CLK_TOP_NETSYS_500M_SEL	       31
-#define CLK_TOP_NETSYS_2X_SEL	       32
-#define CLK_TOP_NETSYS_GSW_SEL	       33
-#define CLK_TOP_ETH_GMII_SEL	       34
-#define CLK_TOP_NETSYS_MCU_SEL	       35
-#define CLK_TOP_NETSYS_PAO_2X_SEL      36
-#define CLK_TOP_EIP197_SEL	       37
-#define CLK_TOP_AXI_INFRA_SEL	       38
-#define CLK_TOP_UART_SEL	       39
-#define CLK_TOP_EMMC_250M_SEL	       40
-#define CLK_TOP_EMMC_400M_SEL	       41
-#define CLK_TOP_SPI_SEL		       42
-#define CLK_TOP_SPIM_MST_SEL	       43
-#define CLK_TOP_NFI1X_SEL	       44
-#define CLK_TOP_SPINFI_SEL	       45
-#define CLK_TOP_PWM_SEL		       46
-#define CLK_TOP_I2C_SEL		       47
-#define CLK_TOP_PCIE_MBIST_250M_SEL    48
-#define CLK_TOP_PEXTP_TL_SEL	       49
-#define CLK_TOP_PEXTP_TL_P1_SEL	       50
-#define CLK_TOP_PEXTP_TL_P2_SEL	       51
-#define CLK_TOP_PEXTP_TL_P3_SEL	       52
-#define CLK_TOP_USB_SYS_SEL	       53
-#define CLK_TOP_USB_SYS_P1_SEL	       54
-#define CLK_TOP_USB_XHCI_SEL	       55
-#define CLK_TOP_USB_XHCI_P1_SEL	       56
-#define CLK_TOP_USB_FRMCNT_SEL	       57
-#define CLK_TOP_USB_FRMCNT_P1_SEL      58
-#define CLK_TOP_AUD_SEL		       59
-#define CLK_TOP_A1SYS_SEL	       60
-#define CLK_TOP_AUD_L_SEL	       61
-#define CLK_TOP_A_TUNER_SEL	       62
-#define CLK_TOP_SSPXTP_SEL	       63
-#define CLK_TOP_USB_PHY_SEL	       64
-#define CLK_TOP_USXGMII_SBUS_0_SEL     65
-#define CLK_TOP_USXGMII_SBUS_1_SEL     66
-#define CLK_TOP_SGM_0_SEL	       67
-#define CLK_TOP_SGM_SBUS_0_SEL	       68
-#define CLK_TOP_SGM_1_SEL	       69
-#define CLK_TOP_SGM_SBUS_1_SEL	       70
-#define CLK_TOP_XFI_PHY_0_XTAL_SEL     71
-#define CLK_TOP_XFI_PHY_1_XTAL_SEL     72
-#define CLK_TOP_SYSAXI_SEL	       73
-#define CLK_TOP_SYSAPB_SEL	       74
-#define CLK_TOP_ETH_REFCK_50M_SEL      75
-#define CLK_TOP_ETH_SYS_200M_SEL       76
-#define CLK_TOP_ETH_SYS_SEL	       77
-#define CLK_TOP_ETH_XGMII_SEL	       78
-#define CLK_TOP_BUS_TOPS_SEL	       79
-#define CLK_TOP_NPU_TOPS_SEL	       80
-#define CLK_TOP_DRAMC_SEL	       81
-#define CLK_TOP_DRAMC_MD32_SEL	       82
-#define CLK_TOP_INFRA_F26M_SEL	       83
-#define CLK_TOP_PEXTP_P0_SEL	       84
-#define CLK_TOP_PEXTP_P1_SEL	       85
-#define CLK_TOP_PEXTP_P2_SEL	       86
-#define CLK_TOP_PEXTP_P3_SEL	       87
-#define CLK_TOP_DA_XTP_GLB_P0_SEL      88
-#define CLK_TOP_DA_XTP_GLB_P1_SEL      89
-#define CLK_TOP_DA_XTP_GLB_P2_SEL      90
-#define CLK_TOP_DA_XTP_GLB_P3_SEL      91
-#define CLK_TOP_CKM_SEL		       92
-#define CLK_TOP_DA_SEL		       93
-#define CLK_TOP_PEXTP_SEL	       94
-#define CLK_TOP_TOPS_P2_26M_SEL	       95
-#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96
-#define CLK_TOP_NETSYS_SYNC_250M_SEL   97
-#define CLK_TOP_MACSEC_SEL	       98
-#define CLK_TOP_NETSYS_TOPS_400M_SEL   99
-#define CLK_TOP_NETSYS_PPEFB_250M_SEL  100
-#define CLK_TOP_NETSYS_WARP_SEL	       101
-#define CLK_TOP_ETH_MII_SEL	       102
-#define CLK_TOP_NPU_SEL		       103
-#define CLK_TOP_AUD_I2S_M	       104
-
-/* MCUSYS */
-
-#define CLK_MCU_BUS_DIV_SEL 0
-#define CLK_MCU_ARM_DIV_SEL 1
-
-/* INFRACFG_AO */
-
-#define CLK_INFRA_MUX_UART0_SEL		 0
-#define CLK_INFRA_MUX_UART1_SEL		 1
-#define CLK_INFRA_MUX_UART2_SEL		 2
-#define CLK_INFRA_MUX_SPI0_SEL		 3
-#define CLK_INFRA_MUX_SPI1_SEL		 4
-#define CLK_INFRA_MUX_SPI2_SEL		 5
-#define CLK_INFRA_PWM_SEL		 6
-#define CLK_INFRA_PWM_CK1_SEL		 7
-#define CLK_INFRA_PWM_CK2_SEL		 8
-#define CLK_INFRA_PWM_CK3_SEL		 9
-#define CLK_INFRA_PWM_CK4_SEL		 10
-#define CLK_INFRA_PWM_CK5_SEL		 11
-#define CLK_INFRA_PWM_CK6_SEL		 12
-#define CLK_INFRA_PWM_CK7_SEL		 13
-#define CLK_INFRA_PWM_CK8_SEL		 14
-#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
-#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
-#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
-#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
-
-/* INFRACFG */
-
-#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19
-#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20
-#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21
-#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22
-#define CLK_INFRA_66M_GPT_BCK	      23
-#define CLK_INFRA_66M_PWM_HCK	      24
-#define CLK_INFRA_66M_PWM_BCK	      25
-#define CLK_INFRA_66M_PWM_CK1	      26
-#define CLK_INFRA_66M_PWM_CK2	      27
-#define CLK_INFRA_66M_PWM_CK3	      28
-#define CLK_INFRA_66M_PWM_CK4	      29
-#define CLK_INFRA_66M_PWM_CK5	      30
-#define CLK_INFRA_66M_PWM_CK6	      31
-#define CLK_INFRA_66M_PWM_CK7	      32
-#define CLK_INFRA_66M_PWM_CK8	      33
-#define CLK_INFRA_133M_CQDMA_BCK      34
-#define CLK_INFRA_66M_AUD_SLV_BCK     35
-#define CLK_INFRA_AUD_26M	      36
-#define CLK_INFRA_AUD_L		      37
-#define CLK_INFRA_AUD_AUD	      38
-#define CLK_INFRA_AUD_EG2	      39
-#define CLK_INFRA_DRAMC_F26M	      40
-#define CLK_INFRA_133M_DBG_ACKM	      41
-#define CLK_INFRA_66M_AP_DMA_BCK      42
-#define CLK_INFRA_66M_SEJ_BCK	      43
-#define CLK_INFRA_PRE_CK_SEJ_F13M     44
-#define CLK_INFRA_26M_THERM_SYSTEM    45
-#define CLK_INFRA_I2C_BCK	      46
-#define CLK_INFRA_52M_UART0_CK	      47
-#define CLK_INFRA_52M_UART1_CK	      48
-#define CLK_INFRA_52M_UART2_CK	      49
-#define CLK_INFRA_NFI		      50
-#define CLK_INFRA_SPINFI	      51
-#define CLK_INFRA_66M_NFI_HCK	      52
-#define CLK_INFRA_104M_SPI0	      53
-#define CLK_INFRA_104M_SPI1	      54
-#define CLK_INFRA_104M_SPI2_BCK	      55
-#define CLK_INFRA_66M_SPI0_HCK	      56
-#define CLK_INFRA_66M_SPI1_HCK	      57
-#define CLK_INFRA_66M_SPI2_HCK	      58
-#define CLK_INFRA_66M_FLASHIF_AXI     59
-#define CLK_INFRA_RTC		      60
-#define CLK_INFRA_26M_ADC_BCK	      61
-#define CLK_INFRA_RC_ADC	      62
-#define CLK_INFRA_MSDC400	      63
-#define CLK_INFRA_MSDC2_HCK	      64
-#define CLK_INFRA_133M_MSDC_0_HCK     65
-#define CLK_INFRA_66M_MSDC_0_HCK      66
-#define CLK_INFRA_133M_CPUM_BCK	      67
-#define CLK_INFRA_BIST2FPC	      68
-#define CLK_INFRA_I2C_X16W_MCK_CK_P1  69
-#define CLK_INFRA_I2C_X16W_PCK_CK_P1  70
-#define CLK_INFRA_133M_USB_HCK	      71
-#define CLK_INFRA_133M_USB_HCK_CK_P1  72
-#define CLK_INFRA_66M_USB_HCK	      73
-#define CLK_INFRA_66M_USB_HCK_CK_P1   74
-#define CLK_INFRA_USB_SYS	      75
-#define CLK_INFRA_USB_SYS_CK_P1	      76
-#define CLK_INFRA_USB_REF	      77
-#define CLK_INFRA_USB_CK_P1	      78
-#define CLK_INFRA_USB_FRMCNT	      79
-#define CLK_INFRA_USB_FRMCNT_CK_P1    80
-#define CLK_INFRA_USB_PIPE	      81
-#define CLK_INFRA_USB_PIPE_CK_P1      82
-#define CLK_INFRA_USB_UTMI	      83
-#define CLK_INFRA_USB_UTMI_CK_P1      84
-#define CLK_INFRA_USB_XHCI	      85
-#define CLK_INFRA_USB_XHCI_CK_P1      86
-#define CLK_INFRA_PCIE_GFMUX_TL_P0    87
-#define CLK_INFRA_PCIE_GFMUX_TL_P1    88
-#define CLK_INFRA_PCIE_GFMUX_TL_P2    89
-#define CLK_INFRA_PCIE_GFMUX_TL_P3    90
-#define CLK_INFRA_PCIE_PIPE_P0	      91
-#define CLK_INFRA_PCIE_PIPE_P1	      92
-#define CLK_INFRA_PCIE_PIPE_P2	      93
-#define CLK_INFRA_PCIE_PIPE_P3	      94
-#define CLK_INFRA_133M_PCIE_CK_P0     95
-#define CLK_INFRA_133M_PCIE_CK_P1     96
-#define CLK_INFRA_133M_PCIE_CK_P2     97
-#define CLK_INFRA_133M_PCIE_CK_P3     98
-
-/* ETHDMA */
-
-#define CLK_ETHDMA_XGP1_EN   0
-#define CLK_ETHDMA_XGP2_EN   1
-#define CLK_ETHDMA_XGP3_EN   2
-#define CLK_ETHDMA_FE_EN     3
-#define CLK_ETHDMA_GP2_EN    4
-#define CLK_ETHDMA_GP1_EN    5
-#define CLK_ETHDMA_GP3_EN    6
-#define CLK_ETHDMA_ESW_EN    7
-#define CLK_ETHDMA_CRYPT0_EN 8
-#define CLK_ETHDMA_NR_CLK    9
-
-/* SGMIISYS_0 */
-
-#define CLK_SGM0_TX_EN	  0
-#define CLK_SGM0_RX_EN	  1
-#define CLK_SGMII0_NR_CLK 2
-
-/* SGMIISYS_1 */
-
-#define CLK_SGM1_TX_EN	  0
-#define CLK_SGM1_RX_EN	  1
-#define CLK_SGMII1_NR_CLK 2
-
-/* ETHWARP */
-
-#define CLK_ETHWARP_WOCPU2_EN 0
-#define CLK_ETHWARP_WOCPU1_EN 1
-#define CLK_ETHWARP_WOCPU0_EN 2
-#define CLK_ETHWARP_NR_CLK    3
-
-#endif /* _DT_BINDINGS_CLK_MT7988_H */

target/linux/mediatek/files-5.15/include/dt-bindings/clock/mt7986-clk.h

@@ -1,169 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- */
-
-#ifndef _DT_BINDINGS_CLK_MT7986_H
-#define _DT_BINDINGS_CLK_MT7986_H
-
-/* APMIXEDSYS */
-
-#define CLK_APMIXED_ARMPLL		0
-#define CLK_APMIXED_NET2PLL		1
-#define CLK_APMIXED_MMPLL		2
-#define CLK_APMIXED_SGMPLL		3
-#define CLK_APMIXED_WEDMCUPLL		4
-#define CLK_APMIXED_NET1PLL		5
-#define CLK_APMIXED_MPLL		6
-#define CLK_APMIXED_APLL2		7
-
-/* TOPCKGEN */
-
-#define CLK_TOP_XTAL			0
-#define CLK_TOP_XTAL_D2			1
-#define CLK_TOP_RTC_32K			2
-#define CLK_TOP_RTC_32P7K		3
-#define CLK_TOP_MPLL_D2			4
-#define CLK_TOP_MPLL_D4			5
-#define CLK_TOP_MPLL_D8			6
-#define CLK_TOP_MPLL_D8_D2		7
-#define CLK_TOP_MPLL_D3_D2		8
-#define CLK_TOP_MMPLL_D2		9
-#define CLK_TOP_MMPLL_D4		10
-#define CLK_TOP_MMPLL_D8		11
-#define CLK_TOP_MMPLL_D8_D2		12
-#define CLK_TOP_MMPLL_D3_D8		13
-#define CLK_TOP_MMPLL_U2PHY		14
-#define CLK_TOP_APLL2_D4		15
-#define CLK_TOP_NET1PLL_D4		16
-#define CLK_TOP_NET1PLL_D5		17
-#define CLK_TOP_NET1PLL_D5_D2		18
-#define CLK_TOP_NET1PLL_D5_D4		19
-#define CLK_TOP_NET1PLL_D8_D2		20
-#define CLK_TOP_NET1PLL_D8_D4		21
-#define CLK_TOP_NET2PLL_D4		22
-#define CLK_TOP_NET2PLL_D4_D2		23
-#define CLK_TOP_NET2PLL_D3_D2		24
-#define CLK_TOP_WEDMCUPLL_D5_D2		25
-#define CLK_TOP_NFI1X_SEL		26
-#define CLK_TOP_SPINFI_SEL		27
-#define CLK_TOP_SPI_SEL			28
-#define CLK_TOP_SPIM_MST_SEL		29
-#define CLK_TOP_UART_SEL		30
-#define CLK_TOP_PWM_SEL			31
-#define CLK_TOP_I2C_SEL			32
-#define CLK_TOP_PEXTP_TL_SEL		33
-#define CLK_TOP_EMMC_250M_SEL		34
-#define CLK_TOP_EMMC_416M_SEL		35
-#define CLK_TOP_F_26M_ADC_SEL		36
-#define CLK_TOP_DRAMC_SEL		37
-#define CLK_TOP_DRAMC_MD32_SEL		38
-#define CLK_TOP_SYSAXI_SEL		39
-#define CLK_TOP_SYSAPB_SEL		40
-#define CLK_TOP_ARM_DB_MAIN_SEL		41
-#define CLK_TOP_ARM_DB_JTSEL		42
-#define CLK_TOP_NETSYS_SEL		43
-#define CLK_TOP_NETSYS_500M_SEL		44
-#define CLK_TOP_NETSYS_MCU_SEL		45
-#define CLK_TOP_NETSYS_2X_SEL		46
-#define CLK_TOP_SGM_325M_SEL		47
-#define CLK_TOP_SGM_REG_SEL		48
-#define CLK_TOP_A1SYS_SEL		49
-#define CLK_TOP_CONN_MCUSYS_SEL		50
-#define CLK_TOP_EIP_B_SEL		51
-#define CLK_TOP_PCIE_PHY_SEL		52
-#define CLK_TOP_USB3_PHY_SEL		53
-#define CLK_TOP_F26M_SEL		54
-#define CLK_TOP_AUD_L_SEL		55
-#define CLK_TOP_A_TUNER_SEL		56
-#define CLK_TOP_U2U3_SEL		57
-#define CLK_TOP_U2U3_SYS_SEL		58
-#define CLK_TOP_U2U3_XHCI_SEL		59
-#define CLK_TOP_DA_U2_REFSEL		60
-#define CLK_TOP_DA_U2_CK_1P_SEL		61
-#define CLK_TOP_AP2CNN_HOST_SEL		62
-#define CLK_TOP_JTAG			63
-
-/* INFRACFG */
-
-#define CLK_INFRA_SYSAXI_D2		0
-#define CLK_INFRA_UART0_SEL		1
-#define CLK_INFRA_UART1_SEL		2
-#define CLK_INFRA_UART2_SEL		3
-#define CLK_INFRA_SPI0_SEL		4
-#define CLK_INFRA_SPI1_SEL		5
-#define CLK_INFRA_PWM1_SEL		6
-#define CLK_INFRA_PWM2_SEL		7
-#define CLK_INFRA_PWM_BSEL		8
-#define CLK_INFRA_PCIE_SEL		9
-#define CLK_INFRA_GPT_STA		10
-#define CLK_INFRA_PWM_HCK		11
-#define CLK_INFRA_PWM_STA		12
-#define CLK_INFRA_PWM1_CK		13
-#define CLK_INFRA_PWM2_CK		14
-#define CLK_INFRA_CQ_DMA_CK		15
-#define CLK_INFRA_EIP97_CK		16
-#define CLK_INFRA_AUD_BUS_CK		17
-#define CLK_INFRA_AUD_26M_CK		18
-#define CLK_INFRA_AUD_L_CK		19
-#define CLK_INFRA_AUD_AUD_CK		20
-#define CLK_INFRA_AUD_EG2_CK		21
-#define CLK_INFRA_DRAMC_26M_CK		22
-#define CLK_INFRA_DBG_CK		23
-#define CLK_INFRA_AP_DMA_CK		24
-#define CLK_INFRA_SEJ_CK		25
-#define CLK_INFRA_SEJ_13M_CK		26
-#define CLK_INFRA_THERM_CK		27
-#define CLK_INFRA_I2C0_CK		28
-#define CLK_INFRA_UART0_CK		29
-#define CLK_INFRA_UART1_CK		30
-#define CLK_INFRA_UART2_CK		31
-#define CLK_INFRA_NFI1_CK		32
-#define CLK_INFRA_SPINFI1_CK		33
-#define CLK_INFRA_NFI_HCK_CK		34
-#define CLK_INFRA_SPI0_CK		35
-#define CLK_INFRA_SPI1_CK		36
-#define CLK_INFRA_SPI0_HCK_CK		37
-#define CLK_INFRA_SPI1_HCK_CK		38
-#define CLK_INFRA_FRTC_CK		39
-#define CLK_INFRA_MSDC_CK		40
-#define CLK_INFRA_MSDC_HCK_CK		41
-#define CLK_INFRA_MSDC_133M_CK		42
-#define CLK_INFRA_MSDC_66M_CK		43
-#define CLK_INFRA_ADC_26M_CK		44
-#define CLK_INFRA_ADC_FRC_CK		45
-#define CLK_INFRA_FBIST2FPC_CK		46
-#define CLK_INFRA_IUSB_133_CK		47
-#define CLK_INFRA_IUSB_66M_CK		48
-#define CLK_INFRA_IUSB_SYS_CK		49
-#define CLK_INFRA_IUSB_CK		50
-#define CLK_INFRA_IPCIE_CK		51
-#define CLK_INFRA_IPCIE_PIPE_CK		52
-#define CLK_INFRA_IPCIER_CK		53
-#define CLK_INFRA_IPCIEB_CK		54
-#define CLK_INFRA_TRNG_CK		55
-
-/* SGMIISYS_0 */
-
-#define CLK_SGMII0_TX250M_EN		0
-#define CLK_SGMII0_RX250M_EN		1
-#define CLK_SGMII0_CDR_REF		2
-#define CLK_SGMII0_CDR_FB		3
-
-/* SGMIISYS_1 */
-
-#define CLK_SGMII1_TX250M_EN		0
-#define CLK_SGMII1_RX250M_EN		1
-#define CLK_SGMII1_CDR_REF		2
-#define CLK_SGMII1_CDR_FB		3
-
-/* ETHSYS */
-
-#define CLK_ETH_FE_EN			0
-#define CLK_ETH_GP2_EN			1
-#define CLK_ETH_GP1_EN			2
-#define CLK_ETH_WOCPU1_EN		3
-#define CLK_ETH_WOCPU0_EN		4
-
-#endif /* _DT_BINDINGS_CLK_MT7986_H */

target/linux/mediatek/files-5.15/include/dt-bindings/reset/mt7986-resets.h

@@ -1,55 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
-/*
- * Copyright (c) 2022 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- */
-
-#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7986
-#define _DT_BINDINGS_RESET_CONTROLLER_MT7986
-
-/* INFRACFG resets */
-#define MT7986_INFRACFG_PEXTP_MAC_SW_RST	6
-#define MT7986_INFRACFG_SSUSB_SW_RST		7
-#define MT7986_INFRACFG_EIP97_SW_RST		8
-#define MT7986_INFRACFG_AUDIO_SW_RST		13
-#define MT7986_INFRACFG_CQ_DMA_SW_RST		14
-
-#define MT7986_INFRACFG_TRNG_SW_RST		17
-#define MT7986_INFRACFG_AP_DMA_SW_RST		32
-#define MT7986_INFRACFG_I2C_SW_RST		33
-#define MT7986_INFRACFG_NFI_SW_RST		34
-#define MT7986_INFRACFG_SPI0_SW_RST		35
-#define MT7986_INFRACFG_SPI1_SW_RST		36
-#define MT7986_INFRACFG_UART0_SW_RST		37
-#define MT7986_INFRACFG_UART1_SW_RST		38
-#define MT7986_INFRACFG_UART2_SW_RST		39
-#define MT7986_INFRACFG_AUXADC_SW_RST		43
-
-#define MT7986_INFRACFG_APXGPT_SW_RST		66
-#define MT7986_INFRACFG_PWM_SW_RST		68
-
-#define MT7986_INFRACFG_SW_RST_NUM		69
-
-/* TOPRGU resets */
-#define MT7986_TOPRGU_APMIXEDSYS_SW_RST		0
-#define MT7986_TOPRGU_SGMII0_SW_RST		1
-#define MT7986_TOPRGU_SGMII1_SW_RST		2
-#define MT7986_TOPRGU_INFRA_SW_RST		3
-#define MT7986_TOPRGU_U2PHY_SW_RST		5
-#define MT7986_TOPRGU_PCIE_SW_RST		6
-#define MT7986_TOPRGU_SSUSB_SW_RST		7
-#define MT7986_TOPRGU_ETHDMA_SW_RST		20
-#define MT7986_TOPRGU_CONSYS_SW_RST		23
-
-#define MT7986_TOPRGU_SW_RST_NUM		24
-
-/* ETHSYS Subsystem resets */
-#define MT7986_ETHSYS_FE_SW_RST			6
-#define MT7986_ETHSYS_PMTR_SW_RST		8
-#define MT7986_ETHSYS_GMAC_SW_RST		23
-#define MT7986_ETHSYS_PPE0_SW_RST		30
-#define MT7986_ETHSYS_PPE1_SW_RST		31
-
-#define MT7986_ETHSYS_SW_RST_NUM		32
-
-#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */

target/linux/mediatek/filogic/config-5.15

@@ -1,443 +0,0 @@
-CONFIG_64BIT=y
-# CONFIG_AHCI_MTK is not set
-CONFIG_AQUANTIA_PHY=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_CRYPTO=y
-CONFIG_ARM64_ERRATUM_843419=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-CONFIG_ARM_MEDIATEK_CPUFREQ=y
-CONFIG_ARM_PMU=y
-CONFIG_ARM_PSCI_FW=y
-CONFIG_ATA=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE_OVERRIDE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-# CONFIG_COMMON_CLK_MT2712 is not set
-# CONFIG_COMMON_CLK_MT6779 is not set
-# CONFIG_COMMON_CLK_MT6797 is not set
-# CONFIG_COMMON_CLK_MT7622 is not set
-CONFIG_COMMON_CLK_MT7981=y
-CONFIG_COMMON_CLK_MT7981_ETHSYS=y
-CONFIG_COMMON_CLK_MT7986=y
-CONFIG_COMMON_CLK_MT7986_ETHSYS=y
-CONFIG_COMMON_CLK_MT7988=y
-# CONFIG_COMMON_CLK_MT8173 is not set
-# CONFIG_COMMON_CLK_MT8183 is not set
-# CONFIG_COMMON_CLK_MT8516 is not set
-# CONFIG_COMPAT_32BIT_TIME is not set
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
-# CONFIG_CPUFREQ_DT is not set
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_CMAC=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ECC=y
-CONFIG_CRYPTO_ECDH=y
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA256_ARM64=y
-CONFIG_CRYPTO_SHA2_ARM64_CE=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_MISC=y
-CONFIG_DIMLIB=y
-CONFIG_DMADEVICES=y
-CONFIG_DMATEST=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_ENGINE_RAID=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EINT_MTK=y
-CONFIG_EXT4_FS=y
-CONFIG_F2FS_FS=y
-CONFIG_FIT_PARTITION=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_WATCHDOG=y
-CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HWMON=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MT65XX=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_JUMP_LABEL=y
-CONFIG_LEDS_SMARTRG_LED=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAXLINEAR_GPHY=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEDIATEK_2P5G_PHY=y
-CONFIG_MEDIATEK_GE_PHY=y
-CONFIG_MEDIATEK_GE_SOC_PHY=y
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_MTK=y
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_MTK=y
-CONFIG_MTD_NAND_MTK_BMT=y
-CONFIG_MTD_PARSER_TRX=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-# CONFIG_MTK_CMDQ is not set
-# CONFIG_MTK_CQDMA is not set
-CONFIG_MTK_HSDMA=y
-CONFIG_MTK_INFRACFG=y
-CONFIG_MTK_PMIC_WRAP=y
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-CONFIG_MTK_THERMAL=y
-CONFIG_MTK_TIMER=y
-# CONFIG_MTK_UART_APDMA is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_MT7530_MDIO=y
-CONFIG_NET_DSA_MT7530_MMIO=y
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_MEDIATEK_SOC_USXGMII=y
-CONFIG_NET_MEDIATEK_SOC_WED=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NLS=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_NVMEM_MTK_EFUSE=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_RESOLVE=y
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-# CONFIG_PCIEASPM_DEFAULT is not set
-CONFIG_PCIEASPM_PERFORMANCE=y
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-# CONFIG_PCIE_MEDIATEK is not set
-CONFIG_PCIE_MEDIATEK_GEN3=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DEBUG=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_MTK_LYNXI=y
-CONFIG_PERF_EVENTS=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_MTK_TPHY=y
-# CONFIG_PHY_MTK_UFS is not set
-CONFIG_PHY_MTK_XSPHY=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_MT2712 is not set
-# CONFIG_PINCTRL_MT6765 is not set
-# CONFIG_PINCTRL_MT6797 is not set
-# CONFIG_PINCTRL_MT7622 is not set
-CONFIG_PINCTRL_MT7981=y
-CONFIG_PINCTRL_MT7986=y
-CONFIG_PINCTRL_MT7988=y
-# CONFIG_PINCTRL_MT8173 is not set
-# CONFIG_PINCTRL_MT8183 is not set
-CONFIG_PINCTRL_MT8516=y
-CONFIG_PINCTRL_MTK=y
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MTK_V2=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PSTORE=y
-CONFIG_PSTORE_COMPRESS=y
-CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
-CONFIG_PSTORE_CONSOLE=y
-CONFIG_PSTORE_DEFLATE_COMPRESS=y
-CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
-CONFIG_PSTORE_PMSG=y
-CONFIG_PSTORE_RAM=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-# CONFIG_RAVE_SP_CORE is not set
-CONFIG_REALTEK_PHY=y
-CONFIG_REED_SOLOMON=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_MT6380=y
-CONFIG_REGULATOR_RT5190A=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_TI_SYSCON=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_MT7622=y
-CONFIG_RTC_I2C_AND_SPI=y
-# CONFIG_RTL8367S_GSW is not set
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCHED_MC=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT65XX=y
-CONFIG_SPI_MTK_NOR=y
-CONFIG_SPI_MTK_SNFI=y
-CONFIG_SRCU=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_BANG_BANG=y
-CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-# CONFIG_UCLAMP_TASK is not set
-# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_VMAP_STACK=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
-# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
-CONFIG_WATCHDOG_SYSFS=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y

target/linux/mediatek/mt7622/config-5.15

@@ -1,444 +0,0 @@
-CONFIG_64BIT=y
-# CONFIG_AHCI_MTK is not set
-CONFIG_AQUANTIA_PHY=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_CRYPTO=y
-CONFIG_ARM64_ERRATUM_843419=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-CONFIG_ARM_MEDIATEK_CPUFREQ=y
-CONFIG_ARM_PMU=y
-CONFIG_ARM_PSCI_FW=y
-CONFIG_ATA=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-CONFIG_COMMON_CLK_MT2712=y
-# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set
-# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set
-# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set
-# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set
-# CONFIG_COMMON_CLK_MT2712_MMSYS is not set
-# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set
-# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set
-# CONFIG_COMMON_CLK_MT6779 is not set
-# CONFIG_COMMON_CLK_MT6797 is not set
-CONFIG_COMMON_CLK_MT7622=y
-CONFIG_COMMON_CLK_MT7622_AUDSYS=y
-CONFIG_COMMON_CLK_MT7622_ETHSYS=y
-CONFIG_COMMON_CLK_MT7622_HIFSYS=y
-# CONFIG_COMMON_CLK_MT7981 is not set
-# CONFIG_COMMON_CLK_MT7986 is not set
-# CONFIG_COMMON_CLK_MT7988 is not set
-# CONFIG_COMMON_CLK_MT8173 is not set
-# CONFIG_COMMON_CLK_MT8183 is not set
-# CONFIG_COMMON_CLK_MT8516 is not set
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
-# CONFIG_CPUFREQ_DT is not set
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_CMAC=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ECC=y
-CONFIG_CRYPTO_ECDH=y
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA256_ARM64=y
-CONFIG_CRYPTO_SHA2_ARM64_CE=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_MISC=y
-CONFIG_DIMLIB=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EINT_MTK=y
-CONFIG_EXT4_FS=y
-CONFIG_F2FS_FS=y
-CONFIG_FIT_PARTITION=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MT65XX=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_JUMP_LABEL=y
-# CONFIG_LEDS_SMARTRG_LED is not set
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-# CONFIG_MEDIATEK_2P5G_PHY is not set
-CONFIG_MEDIATEK_GE_PHY=y
-# CONFIG_MEDIATEK_GE_SOC_PHY is not set
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_MTK=y
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_MTK=y
-CONFIG_MTD_NAND_MTK_BMT=y
-CONFIG_MTD_PARSER_TRX=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-# CONFIG_MTK_CMDQ is not set
-# CONFIG_MTK_CQDMA is not set
-CONFIG_MTK_HSDMA=y
-CONFIG_MTK_INFRACFG=y
-CONFIG_MTK_PMIC_WRAP=y
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-CONFIG_MTK_THERMAL=y
-CONFIG_MTK_TIMER=y
-# CONFIG_MTK_UART_APDMA is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_MT7530_MDIO=y
-# CONFIG_NET_DSA_MT7530_MMIO is not set
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-# CONFIG_NET_MEDIATEK_SOC_USXGMII is not set
-CONFIG_NET_MEDIATEK_SOC_WED=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NLS=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=2
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_NVMEM_MTK_EFUSE=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_RESOLVE=y
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-# CONFIG_PCIEASPM_DEFAULT is not set
-CONFIG_PCIEASPM_PERFORMANCE=y
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_MEDIATEK=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DEBUG=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_MTK_LYNXI=y
-CONFIG_PERF_EVENTS=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_MTK_TPHY=y
-# CONFIG_PHY_MTK_UFS is not set
-# CONFIG_PHY_MTK_XSPHY is not set
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_MT2712 is not set
-# CONFIG_PINCTRL_MT6765 is not set
-# CONFIG_PINCTRL_MT6797 is not set
-CONFIG_PINCTRL_MT7622=y
-# CONFIG_PINCTRL_MT7981 is not set
-# CONFIG_PINCTRL_MT7986 is not set
-# CONFIG_PINCTRL_MT7988 is not set
-# CONFIG_PINCTRL_MT8173 is not set
-# CONFIG_PINCTRL_MT8183 is not set
-CONFIG_PINCTRL_MT8516=y
-CONFIG_PINCTRL_MTK=y
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MTK_V2=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PSTORE=y
-CONFIG_PSTORE_COMPRESS=y
-CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
-CONFIG_PSTORE_CONSOLE=y
-CONFIG_PSTORE_DEFLATE_COMPRESS=y
-CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
-CONFIG_PSTORE_PMSG=y
-CONFIG_PSTORE_RAM=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-# CONFIG_RAVE_SP_CORE is not set
-CONFIG_REALTEK_PHY=y
-CONFIG_REED_SOLOMON=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_MT6380=y
-# CONFIG_REGULATOR_RT5190A is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_MT7622=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTL8367S_GSW=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCHED_MC=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT65XX=y
-CONFIG_SPI_MTK_NOR=y
-CONFIG_SPI_MTK_SNFI=y
-CONFIG_SRCU=y
-CONFIG_SWCONFIG=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_EMULATION=y
-CONFIG_THERMAL_GOV_BANG_BANG=y
-CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_THERMAL_OF=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-# CONFIG_UCLAMP_TASK is not set
-# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_VMAP_STACK=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
-# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
-CONFIG_WATCHDOG_SYSFS=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y

target/linux/mediatek/mt7623/config-5.15

@@ -1,577 +0,0 @@
-# CONFIG_AIO is not set
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
-CONFIG_ARM_CPU_SUSPEND=y
-# CONFIG_ARM_CPU_TOPOLOGY is not set
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8
-CONFIG_ARM_DMA_USE_IOMMU=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_MEDIATEK_CPUFREQ=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_THUMBEE=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_GPIO=y
-CONFIG_BACKLIGHT_LED=y
-CONFIG_BACKLIGHT_PWM=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BOUNCE=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CLEANCACHE=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CMDLINE_PARTITION=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-CONFIG_COMMON_CLK_MT2701=y
-CONFIG_COMMON_CLK_MT2701_AUDSYS=y
-CONFIG_COMMON_CLK_MT2701_BDPSYS=y
-CONFIG_COMMON_CLK_MT2701_ETHSYS=y
-CONFIG_COMMON_CLK_MT2701_G3DSYS=y
-CONFIG_COMMON_CLK_MT2701_HIFSYS=y
-CONFIG_COMMON_CLK_MT2701_IMGSYS=y
-CONFIG_COMMON_CLK_MT2701_MMSYS=y
-CONFIG_COMMON_CLK_MT2701_VDECSYS=y
-# CONFIG_COMMON_CLK_MT7622 is not set
-# CONFIG_COMMON_CLK_MT7629 is not set
-# CONFIG_COMMON_CLK_MT7981 is not set
-# CONFIG_COMMON_CLK_MT7986 is not set
-# CONFIG_COMMON_CLK_MT7988 is not set
-# CONFIG_COMMON_CLK_MT8135 is not set
-# CONFIG_COMMON_CLK_MT8173 is not set
-CONFIG_COMMON_CLK_MT8516=y
-# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_COREDUMP=y
-# CONFIG_CPUFREQ_DT is not set
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_ALIGN_RODATA=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_GPIO=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
-CONFIG_DEBUG_MISC=y
-CONFIG_DEBUG_MT6589_UART0=y
-# CONFIG_DEBUG_MT8127_UART0 is not set
-# CONFIG_DEBUG_MT8135_UART3 is not set
-CONFIG_DEBUG_PREEMPT=y
-CONFIG_DEBUG_UART_8250=y
-CONFIG_DEBUG_UART_8250_SHIFT=2
-CONFIG_DEBUG_UART_PHYS=0x11004000
-CONFIG_DEBUG_UART_VIRT=0xf1004000
-CONFIG_DEBUG_UNCOMPRESS=y
-# CONFIG_DEVFREQ_GOV_PASSIVE is not set
-# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
-# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
-CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
-# CONFIG_DEVFREQ_GOV_USERSPACE is not set
-# CONFIG_DEVFREQ_THERMAL is not set
-CONFIG_DIMLIB=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DRM=y
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_DISPLAY_CONNECTOR=y
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-CONFIG_DRM_GEM_CMA_HELPER=y
-CONFIG_DRM_GEM_SHMEM_HELPER=y
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_LIMA=y
-CONFIG_DRM_LVDS_CODEC=y
-CONFIG_DRM_MEDIATEK=y
-CONFIG_DRM_MEDIATEK_HDMI=y
-CONFIG_DRM_MIPI_DSI=y
-CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y
-CONFIG_DRM_SCHED=y
-CONFIG_DRM_SIMPLE_BRIDGE=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EINT_MTK=y
-CONFIG_ELF_CORE=y
-CONFIG_EXT4_FS=y
-CONFIG_EXTCON=y
-CONFIG_F2FS_FS=y
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_FOPS=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-CONFIG_FIT_PARTITION=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FREEZER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_CACHE=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HDMI=y
-CONFIG_HID=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HWMON=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MT65XX=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_IIO=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_IOMMU_API=y
-# CONFIG_IOMMU_DEBUGFS is not set
-CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
-CONFIG_IOMMU_IO_PGTABLE=y
-CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_KALLSYMS=y
-CONFIG_KCMP=y
-CONFIG_KEYBOARD_MTK_PMIC=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_LCD_PLATFORM=y
-CONFIG_LEDS_MT6323=y
-# CONFIG_LEDS_SMARTRG_LED is not set
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-# CONFIG_MACH_MT2701 is not set
-# CONFIG_MACH_MT6589 is not set
-# CONFIG_MACH_MT6592 is not set
-CONFIG_MACH_MT7623=y
-# CONFIG_MACH_MT7629 is not set
-# CONFIG_MACH_MT8127 is not set
-# CONFIG_MACH_MT8135 is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAILBOX=y
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_GPIO=y
-CONFIG_MEDIATEK_GE_PHY=y
-CONFIG_MEDIATEK_MT6577_AUXADC=y
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_HI6421_SPMI is not set
-CONFIG_MFD_MT6397=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_MTK=y
-CONFIG_MMC_SDHCI=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_NAND_ECC_MEDIATEK is not set
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTK_CMDQ=y
-CONFIG_MTK_CMDQ_MBOX=y
-CONFIG_MTK_CQDMA=y
-# CONFIG_MTK_HSDMA is not set
-CONFIG_MTK_INFRACFG=y
-CONFIG_MTK_IOMMU=y
-CONFIG_MTK_IOMMU_V1=y
-CONFIG_MTK_MMSYS=y
-CONFIG_MTK_PMIC_WRAP=y
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-CONFIG_MTK_SMI=y
-CONFIG_MTK_THERMAL=y
-CONFIG_MTK_TIMER=y
-# CONFIG_MTK_UART_APDMA is not set
-# CONFIG_MUSB_PIO_ONLY is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NEON=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_MT7530_MDIO=y
-# CONFIG_NET_DSA_MT7530_MMIO is not set
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_MEDIATEK_SOC_WED=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-# CONFIG_NET_VENDOR_WIZNET is not set
-CONFIG_NLS=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVMEM_MTK_EFUSE=y
-# CONFIG_NVMEM_SPMI_SDAM is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IOMMU=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_RESOLVE=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_MEDIATEK=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_MTK_LYNXI=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHY_MTK_HDMI=y
-CONFIG_PHY_MTK_MIPI_DSI=y
-CONFIG_PHY_MTK_TPHY=y
-# CONFIG_PHY_MTK_UFS is not set
-# CONFIG_PHY_MTK_XSPHY is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_MT2701=y
-CONFIG_PINCTRL_MT6397=y
-CONFIG_PINCTRL_MT7623=y
-CONFIG_PINCTRL_MTK=y
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MTK_V2=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_DEVFREQ=y
-# CONFIG_PM_DEVFREQ_EVENT is not set
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
-CONFIG_PM_OPP=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_POWER_RESET=y
-# CONFIG_POWER_RESET_MT6323 is not set
-CONFIG_POWER_SUPPLY=y
-CONFIG_POWER_SUPPLY_HWMON=y
-CONFIG_PREEMPT=y
-CONFIG_PREEMPTION=y
-CONFIG_PREEMPT_COUNT=y
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_RCU=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_REGULATOR_MT6323=y
-# CONFIG_REGULATOR_MT6358 is not set
-# CONFIG_REGULATOR_MT6380 is not set
-# CONFIG_REGULATOR_MT6397 is not set
-# CONFIG_REGULATOR_RT5190A is not set
-# CONFIG_REGULATOR_QCOM_LABIBB is not set
-# CONFIG_REGULATOR_QCOM_SPMI is not set
-# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_MT6397 is not set
-# CONFIG_RTC_DRV_MT7622 is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-# CONFIG_RTL8367S_GSW is not set
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SERIAL_8250_DMA is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT65XX=y
-# CONFIG_SPI_MTK_NOR is not set
-CONFIG_SPMI=y
-# CONFIG_SPMI_HISI3670 is not set
-CONFIG_SRCU=y
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYNC_FILE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TOUCHSCREEN_EDT_FT5X06=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-# CONFIG_UACCE is not set
-CONFIG_UBIFS_FS=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_F_ACM=y
-CONFIG_USB_F_ECM=y
-CONFIG_USB_F_MASS_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GPIO_VBUS=y
-CONFIG_USB_G_MULTI=y
-CONFIG_USB_G_MULTI_CDC=y
-# CONFIG_USB_G_MULTI_RNDIS is not set
-CONFIG_USB_HID=y
-CONFIG_USB_HIDDEV=y
-CONFIG_USB_INVENTRA_DMA=y
-CONFIG_USB_LIBCOMPOSITE=y
-CONFIG_USB_MUSB_DUAL_ROLE=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_MEDIATEK=y
-CONFIG_USB_OTG=y
-CONFIG_USB_PHY=y
-CONFIG_USB_ROLE_SWITCH=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_U_ETHER=y
-CONFIG_USB_U_SERIAL=y
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VIDEOMODE_HELPERS=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y

target/linux/mediatek/mt7629/config-5.15

@@ -1,327 +0,0 @@
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_CACHE_L2X0=y
-# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CHR_DEV_SCH=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_CMDLINE_OVERRIDE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-# CONFIG_COMMON_CLK_MT2701 is not set
-# CONFIG_COMMON_CLK_MT7622 is not set
-CONFIG_COMMON_CLK_MT7629=y
-CONFIG_COMMON_CLK_MT7629_ETHSYS=y
-CONFIG_COMMON_CLK_MT7629_HIFSYS=y
-# CONFIG_COMMON_CLK_MT7981 is not set
-# CONFIG_COMMON_CLK_MT7986 is not set
-# CONFIG_COMMON_CLK_MT7988 is not set
-# CONFIG_COMMON_CLK_MT8135 is not set
-# CONFIG_COMMON_CLK_MT8173 is not set
-CONFIG_COMMON_CLK_MT8516=y
-# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MISC=y
-CONFIG_DEFAULT_HOSTNAME="(mt7629)"
-CONFIG_DIMLIB=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DTC=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EINT_MTK=y
-# CONFIG_FIT_PARTITION is not set
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_HZ_FIXED=0
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
-# CONFIG_LEDS_SMARTRG_LED is not set
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-# CONFIG_MACH_MT2701 is not set
-# CONFIG_MACH_MT6589 is not set
-# CONFIG_MACH_MT6592 is not set
-# CONFIG_MACH_MT7623 is not set
-CONFIG_MACH_MT7629=y
-# CONFIG_MACH_MT8127 is not set
-# CONFIG_MACH_MT8135 is not set
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEDIATEK_GE_PHY=y
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_MTK_BMT=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-# CONFIG_MTK_CMDQ is not set
-CONFIG_MTK_INFRACFG=y
-# CONFIG_MTK_PMIC_WRAP is not set
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-CONFIG_MTK_TIMER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NETFILTER=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_MT7530_MDIO=y
-# CONFIG_NET_DSA_MT7530_MMIO is not set
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_MEDIATEK_SOC_WED=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NLS=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=2
-CONFIG_NVMEM=y
-# CONFIG_NVMEM_MTK_EFUSE is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_MEDIATEK=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_MTK_LYNXI=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHY_MTK_TPHY=y
-# CONFIG_PHY_MTK_UFS is not set
-# CONFIG_PHY_MTK_XSPHY is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_MT7629=y
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MTK_V2=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-# CONFIG_RTL8367S_GSW is not set
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT65XX=y
-CONFIG_SPI_MTK_NOR=y
-CONFIG_SPI_MTK_SNFI=y
-CONFIG_SRCU=y
-CONFIG_STACKTRACE=y
-# CONFIG_SWAP is not set
-CONFIG_SWCONFIG=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_MTK=y
-# CONFIG_USB_XHCI_PLATFORM is not set
-CONFIG_USE_OF=y
-# CONFIG_VFP is not set
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y

target/linux/mediatek/patches-5.15/041-block-fit-partition-parser.patch

@@ -1,214 +0,0 @@
-From 69357074558daf6ff24c9f58714935e9e095a865 Mon Sep 17 00:00:00 2001
-From: OpenWrt community <[email protected]>
-Date: Wed, 13 Jul 2022 13:37:33 +0200
-Subject: [PATCH] kernel: add block fit partition parser
-
----
- block/blk.h                     |  2 ++
- block/partitions/Kconfig        |  7 +++++++
- block/partitions/Makefile       |  1 +
- block/partitions/check.h        |  3 +++
- block/partitions/core.c         | 17 +++++++++++++++++
- block/partitions/efi.c          |  8 ++++++++
- block/partitions/efi.h          |  3 +++
- block/partitions/msdos.c        | 10 ++++++++++
- drivers/mtd/mtd_blkdevs.c       |  2 ++
- drivers/mtd/ubi/block.c         |  3 +++
- include/linux/msdos_partition.h |  1 +
- 11 files changed, 57 insertions(+)
-
---- a/block/blk.h
-+++ b/block/blk.h
-@@ -354,6 +354,8 @@ void blk_free_ext_minor(unsigned int min
- #define ADDPART_FLAG_NONE	0
- #define ADDPART_FLAG_RAID	1
- #define ADDPART_FLAG_WHOLEDISK	2
-+#define ADDPART_FLAG_READONLY	4
-+#define ADDPART_FLAG_ROOTDEV	8
- int bdev_add_partition(struct gendisk *disk, int partno, sector_t start,
- 		sector_t length);
- int bdev_del_partition(struct gendisk *disk, int partno);
---- a/block/partitions/Kconfig
-+++ b/block/partitions/Kconfig
-@@ -101,6 +101,13 @@ config ATARI_PARTITION
- 	  Say Y here if you would like to use hard disks under Linux which
- 	  were partitioned under the Atari OS.
- 
-+config FIT_PARTITION
-+	bool "Flattened-Image-Tree (FIT) partition support" if PARTITION_ADVANCED
-+	default n
-+	help
-+	  Say Y here if your system needs to mount the filesystem part of
-+	  a Flattened-Image-Tree (FIT) image commonly used with Das U-Boot.
-+
- config IBM_PARTITION
- 	bool "IBM disk label and partition support"
- 	depends on PARTITION_ADVANCED && S390
---- a/block/partitions/Makefile
-+++ b/block/partitions/Makefile
-@@ -8,6 +8,7 @@ obj-$(CONFIG_ACORN_PARTITION) += acorn.o
- obj-$(CONFIG_AMIGA_PARTITION) += amiga.o
- obj-$(CONFIG_ATARI_PARTITION) += atari.o
- obj-$(CONFIG_AIX_PARTITION) += aix.o
-+obj-$(CONFIG_FIT_PARTITION) += fit.o
- obj-$(CONFIG_CMDLINE_PARTITION) += cmdline.o
- obj-$(CONFIG_MAC_PARTITION) += mac.o
- obj-$(CONFIG_LDM_PARTITION) += ldm.o
---- a/block/partitions/check.h
-+++ b/block/partitions/check.h
-@@ -58,6 +58,7 @@ int amiga_partition(struct parsed_partit
- int atari_partition(struct parsed_partitions *state);
- int cmdline_partition(struct parsed_partitions *state);
- int efi_partition(struct parsed_partitions *state);
-+int fit_partition(struct parsed_partitions *state);
- int ibm_partition(struct parsed_partitions *);
- int karma_partition(struct parsed_partitions *state);
- int ldm_partition(struct parsed_partitions *state);
-@@ -68,3 +69,5 @@ int sgi_partition(struct parsed_partitio
- int sun_partition(struct parsed_partitions *state);
- int sysv68_partition(struct parsed_partitions *state);
- int ultrix_partition(struct parsed_partitions *state);
-+
-+int parse_fit_partitions(struct parsed_partitions *state, u64 start_sector, u64 nr_sectors, int *slot, int add_remain);
---- a/block/partitions/core.c
-+++ b/block/partitions/core.c
-@@ -12,6 +12,10 @@
- #include <linux/vmalloc.h>
- #include <linux/blktrace_api.h>
- #include <linux/raid/detect.h>
-+#ifdef CONFIG_FIT_PARTITION
-+#include <linux/root_dev.h>
-+#endif
-+
- #include "check.h"
- 
- static int (*check_part[])(struct parsed_partitions *) = {
-@@ -48,6 +52,9 @@ static int (*check_part[])(struct parsed
- #ifdef CONFIG_EFI_PARTITION
- 	efi_partition,		/* this must come before msdos */
- #endif
-+#ifdef CONFIG_FIT_PARTITION
-+	fit_partition,
-+#endif
- #ifdef CONFIG_SGI_PARTITION
- 	sgi_partition,
- #endif
-@@ -408,6 +415,11 @@ static struct block_device *add_partitio
- 			goto out_del;
- 	}
- 
-+#ifdef CONFIG_FIT_PARTITION
-+	if (flags & ADDPART_FLAG_READONLY)
-+		bdev->bd_read_only = true;
-+#endif
-+
- 	/* everything is up and running, commence */
- 	err = xa_insert(&disk->part_tbl, partno, bdev, GFP_KERNEL);
- 	if (err)
-@@ -595,6 +607,11 @@ static bool blk_add_partition(struct gen
- 	    (state->parts[p].flags & ADDPART_FLAG_RAID))
- 		md_autodetect_dev(part->bd_dev);
- 
-+#ifdef CONFIG_FIT_PARTITION
-+	if ((state->parts[p].flags & ADDPART_FLAG_ROOTDEV) && ROOT_DEV == 0)
-+		ROOT_DEV = part->bd_dev;
-+#endif
-+
- 	return true;
- }
- 
---- a/block/partitions/efi.c
-+++ b/block/partitions/efi.c
-@@ -716,6 +716,9 @@ int efi_partition(struct parsed_partitio
- 	gpt_entry *ptes = NULL;
- 	u32 i;
- 	unsigned ssz = queue_logical_block_size(state->disk->queue) / 512;
-+#ifdef CONFIG_FIT_PARTITION
-+	u32 extra_slot = 64;
-+#endif
- 
- 	if (!find_valid_gpt(state, &gpt, &ptes) || !gpt || !ptes) {
- 		kfree(gpt);
-@@ -749,6 +752,11 @@ int efi_partition(struct parsed_partitio
- 				ARRAY_SIZE(ptes[i].partition_name));
- 		utf16_le_to_7bit(ptes[i].partition_name, label_max, info->volname);
- 		state->parts[i + 1].has_info = true;
-+#ifdef CONFIG_FIT_PARTITION
-+		/* If this is a U-Boot FIT volume it may have subpartitions */
-+		if (!efi_guidcmp(ptes[i].partition_type_guid, PARTITION_LINUX_FIT_GUID))
-+			(void) parse_fit_partitions(state, start * ssz, size * ssz, &extra_slot, 1);
-+#endif
- 	}
- 	kfree(ptes);
- 	kfree(gpt);
---- a/block/partitions/efi.h
-+++ b/block/partitions/efi.h
-@@ -52,6 +52,9 @@
- #define PARTITION_LINUX_LVM_GUID \
-     EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \
-               0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)
-+#define PARTITION_LINUX_FIT_GUID \
-+    EFI_GUID( 0xcae9be83, 0xb15f, 0x49cc, \
-+              0x86, 0x3f, 0x08, 0x1b, 0x74, 0x4a, 0x2d, 0x93)
- 
- typedef struct _gpt_header {
- 	__le64 signature;
---- a/block/partitions/msdos.c
-+++ b/block/partitions/msdos.c
-@@ -564,6 +564,15 @@ static void parse_minix(struct parsed_pa
- #endif /* CONFIG_MINIX_SUBPARTITION */
- }
- 
-+static void parse_fit_mbr(struct parsed_partitions *state,
-+			  sector_t offset, sector_t size, int origin)
-+{
-+#ifdef CONFIG_FIT_PARTITION
-+	u32 extra_slot = 64;
-+	(void) parse_fit_partitions(state, offset, size, &extra_slot, 1);
-+#endif /* CONFIG_FIT_PARTITION */
-+}
-+
- static struct {
- 	unsigned char id;
- 	void (*parse)(struct parsed_partitions *, sector_t, sector_t, int);
-@@ -575,6 +584,7 @@ static struct {
- 	{UNIXWARE_PARTITION, parse_unixware},
- 	{SOLARIS_X86_PARTITION, parse_solaris_x86},
- 	{NEW_SOLARIS_X86_PARTITION, parse_solaris_x86},
-+	{FIT_PARTITION, parse_fit_mbr},
- 	{0, NULL},
- };
- 
---- a/drivers/mtd/mtd_blkdevs.c
-+++ b/drivers/mtd/mtd_blkdevs.c
-@@ -345,6 +345,8 @@ int add_mtd_blktrans_dev(struct mtd_blkt
- 	gd->first_minor = (new->devnum) << tr->part_bits;
- 	gd->minors = 1 << tr->part_bits;
- 	gd->fops = &mtd_block_ops;
-+	if (IS_ENABLED(CONFIG_FIT_PARTITION) && !mtd_type_is_nand(new->mtd))
-+		gd->flags |= GENHD_FL_EXT_DEVT;
- 
- 	if (tr->part_bits)
- 		if (new->devnum < 26)
---- a/drivers/mtd/ubi/block.c
-+++ b/drivers/mtd/ubi/block.c
-@@ -428,6 +428,9 @@ int ubiblock_create(struct ubi_volume_in
- 		goto out_cleanup_disk;
- 	}
- 	gd->private_data = dev;
-+#ifdef CONFIG_FIT_PARTITION
-+	gd->flags |= GENHD_FL_EXT_DEVT;
-+#endif
- 	sprintf(gd->disk_name, "ubiblock%d_%d", dev->ubi_num, dev->vol_id);
- 	set_capacity(gd, disk_capacity);
- 	dev->gd = gd;
---- a/include/linux/msdos_partition.h
-+++ b/include/linux/msdos_partition.h
-@@ -31,6 +31,7 @@ enum msdos_sys_ind {
- 	LINUX_LVM_PARTITION = 0x8e,
- 	LINUX_RAID_PARTITION = 0xfd,	/* autodetect RAID partition */
- 
-+	FIT_PARTITION = 0x2e,		/* U-Boot uImage.FIT */
- 	SOLARIS_X86_PARTITION =	0x82,	/* also Linux swap partitions */
- 	NEW_SOLARIS_X86_PARTITION = 0xbf,
- 

target/linux/mediatek/patches-5.15/100-dts-update-mt7622-rfb1.patch

@@ -1,119 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -1,7 +1,6 @@
- /*
-- * Copyright (c) 2017 MediaTek Inc.
-- * Author: Ming Huang <[email protected]>
-- *	   Sean Wang <[email protected]>
-+ * Copyright (c) 2018 MediaTek Inc.
-+ * Author: Ryder Lee <[email protected]>
-  *
-  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
-  */
-@@ -23,7 +22,7 @@
- 
- 	chosen {
- 		stdout-path = "serial0:115200n8";
--		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
-+		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
- 	};
- 
- 	cpus {
-@@ -40,23 +39,22 @@
- 
- 	gpio-keys {
- 		compatible = "gpio-keys";
--		poll-interval = <100>;
- 
- 		factory {
- 			label = "factory";
- 			linux,code = <BTN_0>;
--			gpios = <&pio 0 0>;
-+			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
- 		};
- 
- 		wps {
- 			label = "wps";
- 			linux,code = <KEY_WPS_BUTTON>;
--			gpios = <&pio 102 0>;
-+			gpios = <&pio 102 GPIO_ACTIVE_LOW>;
- 		};
- 	};
- 
- 	memory@40000000 {
--		reg = <0 0x40000000 0 0x20000000>;
-+		reg = <0 0x40000000 0 0x40000000>;
- 	};
- 
- 	reg_1p8v: regulator-1p8v {
-@@ -132,22 +130,22 @@
- 
- 				port@0 {
- 					reg = <0>;
--					label = "lan0";
-+					label = "lan1";
- 				};
- 
- 				port@1 {
- 					reg = <1>;
--					label = "lan1";
-+					label = "lan2";
- 				};
- 
- 				port@2 {
- 					reg = <2>;
--					label = "lan2";
-+					label = "lan3";
- 				};
- 
- 				port@3 {
- 					reg = <3>;
--					label = "lan3";
-+					label = "lan4";
- 				};
- 
- 				port@4 {
-@@ -236,15 +234,28 @@
- 
- &pcie {
- 	pinctrl-names = "default";
--	pinctrl-0 = <&pcie0_pins>;
-+	pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
- 	status = "okay";
- 
- 	pcie@0,0 {
- 		status = "okay";
- 	};
-+
-+	pcie@1,0 {
-+		status = "okay";
-+	};
- };
- 
- &pio {
-+	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
-+	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
-+	 */
-+	asm_sel {
-+		gpio-hog;
-+		gpios = <90 GPIO_ACTIVE_HIGH>;
-+		output-high;
-+	};
-+
- 	/* eMMC is shared pin with parallel NAND */
- 	emmc_pins_default: emmc-pins-default {
- 		mux {
-@@ -521,11 +532,11 @@
- };
- 
- &sata {
--	status = "okay";
-+	status = "disabled";
- };
- 
- &sata_phy {
--	status = "okay";
-+	status = "disabled";
- };
- 
- &spi0 {

target/linux/mediatek/patches-5.15/101-dts-update-mt7629-rfb.patch

@@ -1,60 +0,0 @@
---- a/arch/arm/boot/dts/mt7629-rfb.dts
-+++ b/arch/arm/boot/dts/mt7629-rfb.dts
-@@ -18,6 +18,7 @@
- 
- 	chosen {
- 		stdout-path = "serial0:115200n8";
-+		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8";
- 	};
- 
- 	gpio-keys {
-@@ -70,6 +71,10 @@
- 		compatible = "mediatek,eth-mac";
- 		reg = <0>;
- 		phy-mode = "2500base-x";
-+
-+		nvmem-cells = <&macaddr_factory_2a>;
-+		nvmem-cell-names = "mac-address";
-+
- 		fixed-link {
- 			speed = <2500>;
- 			full-duplex;
-@@ -82,6 +87,9 @@
- 		reg = <1>;
- 		phy-mode = "gmii";
- 		phy-handle = <&phy0>;
-+
-+		nvmem-cells = <&macaddr_factory_24>;
-+		nvmem-cell-names = "mac-address";
- 	};
- 
- 	mdio: mdio-bus {
-@@ -133,8 +141,9 @@
- 			};
- 
- 			partition@b0000 {
--				label = "kernel";
-+				label = "firmware";
- 				reg = <0xb0000 0xb50000>;
-+				compatible = "denx,fit";
- 			};
- 		};
- 	};
-@@ -272,3 +281,17 @@
- 	pinctrl-0 = <&watchdog_pins>;
- 	status = "okay";
- };
-+
-+&factory {
-+	compatible = "nvmem-cells";
-+	#address-cells = <1>;
-+	#size-cells = <1>;
-+
-+	macaddr_factory_24: macaddr@24 {
-+		reg = <0x24 0x6>;
-+	};
-+
-+	macaddr_factory_2a: macaddr@2a {
-+		reg = <0x2a 0x6>;
-+	};
-+};

target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch

@@ -1,20 +0,0 @@
-From d6a596012150960f0f3a214d31bbac4b607dbd1e Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <[email protected]>
-Date: Fri, 29 Apr 2022 10:40:56 +0800
-Subject: [PATCH] arm: mediatek: select arch timer for mt7623
-
-Signed-off-by: Chuanhong Guo <[email protected]>
----
- arch/arm/mach-mediatek/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm/mach-mediatek/Kconfig
-+++ b/arch/arm/mach-mediatek/Kconfig
-@@ -26,6 +26,7 @@ config MACH_MT6592
- config MACH_MT7623
- 	bool "MediaTek MT7623 SoCs support"
- 	default ARCH_MEDIATEK
-+	select HAVE_ARM_ARCH_TIMER
- 
- config MACH_MT7629
- 	bool "MediaTek MT7629 SoCs support"

target/linux/mediatek/patches-5.15/104-mt7622-add-snor-irq.patch

@@ -1,10 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -559,6 +559,7 @@
- 		compatible = "mediatek,mt7622-nor",
- 			     "mediatek,mt8173-nor";
- 		reg = <0 0x11014000 0 0xe0>;
-+		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
- 		clocks = <&pericfg CLK_PERI_FLASH_PD>,
- 			 <&topckgen CLK_TOP_FLASH_SEL>;
- 		clock-names = "spi", "sf";

target/linux/mediatek/patches-5.15/105-dts-mt7622-enable-pstore.patch

@@ -1,25 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -111,7 +111,7 @@
- 	};
- 
- 	psci {
--		compatible  = "arm,psci-0.2";
-+		compatible  = "arm,psci-1.0";
- 		method      = "smc";
- 	};
- 
-@@ -127,6 +127,13 @@
- 		#size-cells = <2>;
- 		ranges;
- 
-+		/* 64 KiB reserved for ramoops/pstore */
-+		ramoops@42ff0000 {
-+			compatible = "ramoops";
-+			reg = <0 0x42ff0000 0 0x10000>;
-+			record-size = <0x1000>;
-+		};
-+
- 		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
- 		secmon_reserved: secmon@43000000 {
- 			reg = <0 0x43000000 0 0x30000>;

target/linux/mediatek/patches-5.15/110-dts-fix-bpi2-console.patch

@@ -1,10 +0,0 @@
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -19,6 +19,7 @@
- 
- 	chosen {
- 		stdout-path = "serial2:115200n8";
-+		bootargs = "console=ttyS2,115200n8 console=tty1";
- 	};
- 
- 	connector {

target/linux/mediatek/patches-5.15/111-dts-fix-bpi64-console.patch

@@ -1,11 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -22,7 +22,7 @@
- 
- 	chosen {
- 		stdout-path = "serial0:115200n8";
--		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
-+		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
- 	};
- 
- 	cpus {

target/linux/mediatek/patches-5.15/112-dts-fix-bpi64-lan-names.patch

@@ -1,37 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -18,6 +18,7 @@
- 
- 	aliases {
- 		serial0 = &uart0;
-+		ethernet0 = &gmac0;
- 	};
- 
- 	chosen {
-@@ -160,22 +161,22 @@
- 
- 				port@1 {
- 					reg = <1>;
--					label = "lan0";
-+					label = "lan1";
- 				};
- 
- 				port@2 {
- 					reg = <2>;
--					label = "lan1";
-+					label = "lan2";
- 				};
- 
- 				port@3 {
- 					reg = <3>;
--					label = "lan2";
-+					label = "lan3";
- 				};
- 
- 				port@4 {
- 					reg = <4>;
--					label = "lan3";
-+					label = "lan4";
- 				};
- 
- 				port@6 {

target/linux/mediatek/patches-5.15/113-dts-fix-bpi64-leds-and-buttons.patch

@@ -1,56 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -19,6 +19,10 @@
- 	aliases {
- 		serial0 = &uart0;
- 		ethernet0 = &gmac0;
-+		led-boot = &led_system_green;
-+		led-failsafe = &led_system_blue;
-+		led-running = &led_system_green;
-+		led-upgrade = &led_system_blue;
- 	};
- 
- 	chosen {
-@@ -42,8 +46,8 @@
- 		compatible = "gpio-keys";
- 
- 		factory {
--			label = "factory";
--			linux,code = <BTN_0>;
-+			label = "reset";
-+			linux,code = <KEY_RESTART>;
- 			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
- 		};
- 
-@@ -57,17 +61,25 @@
- 	leds {
- 		compatible = "gpio-leds";
- 
--		green {
--			label = "bpi-r64:pio:green";
--			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
-+		led_system_blue: blue {
-+			label = "bpi-r64:pio:blue";
-+			gpios = <&pio 85 GPIO_ACTIVE_HIGH>;
- 			default-state = "off";
- 		};
- 
--		red {
--			label = "bpi-r64:pio:red";
--			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
-+		led_system_green: green {
-+			label = "bpi-r64:pio:green";
-+			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
- 			default-state = "off";
- 		};
-+
-+/*
-+ *		red {
-+ *			label = "bpi-r64:pio:red";
-+ *			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
-+ *			default-state = "off";
-+ *		};
-+ */
- 	};
- 
- 	memory@40000000 {

target/linux/mediatek/patches-5.15/114-dts-bpi64-disable-rtc.patch

@@ -1,21 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -564,12 +564,16 @@
- 	status = "okay";
- };
- 
-+&rtc {
-+	status = "disabled";
-+};
-+
- &sata {
--	status = "disable";
-+	status = "disabled";
- };
- 
- &sata_phy {
--	status = "disable";
-+	status = "disabled";
- };
- 
- &spi0 {

target/linux/mediatek/patches-5.15/115-dts-bpi64-add-snand-support.patch

@@ -1,50 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -259,14 +259,42 @@
- 	status = "disabled";
- };
- 
--&nor_flash {
--	pinctrl-names = "default";
--	pinctrl-0 = <&spi_nor_pins>;
--	status = "disabled";
-+&bch {
-+	status = "okay";
-+};
- 
-+&snfi {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&serial_nand_pins>;
-+	status = "okay";
- 	flash@0 {
--		compatible = "jedec,spi-nor";
-+		compatible = "spi-nand";
- 		reg = <0>;
-+		spi-tx-bus-width = <4>;
-+		spi-rx-bus-width = <4>;
-+		nand-ecc-engine = <&snfi>;
-+		partitions {
-+			compatible = "fixed-partitions";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			partition@0 {
-+				label = "bl2";
-+				reg = <0x0 0x80000>;
-+				read-only;
-+			};
-+
-+			partition@80000 {
-+				label = "fip";
-+				reg = <0x80000 0x200000>;
-+				read-only;
-+			};
-+
-+			partition@280000 {
-+				label = "ubi";
-+				reg = <0x280000 0x7d80000>;
-+			};
-+		};
- 	};
- };
- 

target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch

@@ -1,214 +0,0 @@
-From ad4944aa0b02cb043afe20bc2a018c161e65c992 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <[email protected]>
-Date: Thu, 16 Dec 2021 12:16:38 +0100
-Subject: [PATCH 01/15] mtd: nand: ecc: Add infrastructure to support hardware
- engines
-
-Add the necessary helpers to register/unregister hardware ECC engines
-that will be called from ECC engine drivers.
-
-Also add helpers to get the right engine from the user
-perspective. Keep a reference of the in use ECC engine in order to
-prevent modules to be unloaded. Put the reference when the engine gets
-retired.
-
-A static list of hardware (only) ECC engines is setup to keep track of
-the registered engines.
-
-Signed-off-by: Miquel Raynal <[email protected]>
-Link: https://lore.kernel.org/linux-mtd/[email protected]
-(cherry picked from commit 96489c1c0b53131b0e1ec33e2060538379ad6152)
----
- drivers/mtd/nand/core.c  | 10 +++--
- drivers/mtd/nand/ecc.c   | 88 ++++++++++++++++++++++++++++++++++++++++
- include/linux/mtd/nand.h | 28 +++++++++++++
- 3 files changed, 123 insertions(+), 3 deletions(-)
-
---- a/drivers/mtd/nand/core.c
-+++ b/drivers/mtd/nand/core.c
-@@ -232,7 +232,9 @@ static int nanddev_get_ecc_engine(struct
- 		nand->ecc.engine = nand_ecc_get_on_die_hw_engine(nand);
- 		break;
- 	case NAND_ECC_ENGINE_TYPE_ON_HOST:
--		pr_err("On-host hardware ECC engines not supported yet\n");
-+		nand->ecc.engine = nand_ecc_get_on_host_hw_engine(nand);
-+		if (PTR_ERR(nand->ecc.engine) == -EPROBE_DEFER)
-+			return -EPROBE_DEFER;
- 		break;
- 	default:
- 		pr_err("Missing ECC engine type\n");
-@@ -252,7 +254,7 @@ static int nanddev_put_ecc_engine(struct
- {
- 	switch (nand->ecc.ctx.conf.engine_type) {
- 	case NAND_ECC_ENGINE_TYPE_ON_HOST:
--		pr_err("On-host hardware ECC engines not supported yet\n");
-+		nand_ecc_put_on_host_hw_engine(nand);
- 		break;
- 	case NAND_ECC_ENGINE_TYPE_NONE:
- 	case NAND_ECC_ENGINE_TYPE_SOFT:
-@@ -297,7 +299,9 @@ int nanddev_ecc_engine_init(struct nand_
- 	/* Look for the ECC engine to use */
- 	ret = nanddev_get_ecc_engine(nand);
- 	if (ret) {
--		pr_err("No ECC engine found\n");
-+		if (ret != -EPROBE_DEFER)
-+			pr_err("No ECC engine found\n");
-+
- 		return ret;
- 	}
- 
---- a/drivers/mtd/nand/ecc.c
-+++ b/drivers/mtd/nand/ecc.c
-@@ -96,6 +96,12 @@
- #include <linux/module.h>
- #include <linux/mtd/nand.h>
- #include <linux/slab.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_platform.h>
-+
-+static LIST_HEAD(on_host_hw_engines);
-+static DEFINE_MUTEX(on_host_hw_engines_mutex);
- 
- /**
-  * nand_ecc_init_ctx - Init the ECC engine context
-@@ -611,6 +617,88 @@ struct nand_ecc_engine *nand_ecc_get_on_
- }
- EXPORT_SYMBOL(nand_ecc_get_on_die_hw_engine);
- 
-+int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine)
-+{
-+	struct nand_ecc_engine *item;
-+
-+	if (!engine)
-+		return -EINVAL;
-+
-+	/* Prevent multiple registrations of one engine */
-+	list_for_each_entry(item, &on_host_hw_engines, node)
-+		if (item == engine)
-+			return 0;
-+
-+	mutex_lock(&on_host_hw_engines_mutex);
-+	list_add_tail(&engine->node, &on_host_hw_engines);
-+	mutex_unlock(&on_host_hw_engines_mutex);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(nand_ecc_register_on_host_hw_engine);
-+
-+int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine)
-+{
-+	if (!engine)
-+		return -EINVAL;
-+
-+	mutex_lock(&on_host_hw_engines_mutex);
-+	list_del(&engine->node);
-+	mutex_unlock(&on_host_hw_engines_mutex);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(nand_ecc_unregister_on_host_hw_engine);
-+
-+static struct nand_ecc_engine *nand_ecc_match_on_host_hw_engine(struct device *dev)
-+{
-+	struct nand_ecc_engine *item;
-+
-+	list_for_each_entry(item, &on_host_hw_engines, node)
-+		if (item->dev == dev)
-+			return item;
-+
-+	return NULL;
-+}
-+
-+struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand)
-+{
-+	struct nand_ecc_engine *engine = NULL;
-+	struct device *dev = &nand->mtd.dev;
-+	struct platform_device *pdev;
-+	struct device_node *np;
-+
-+	if (list_empty(&on_host_hw_engines))
-+		return NULL;
-+
-+	/* Check for an explicit nand-ecc-engine property */
-+	np = of_parse_phandle(dev->of_node, "nand-ecc-engine", 0);
-+	if (np) {
-+		pdev = of_find_device_by_node(np);
-+		if (!pdev)
-+			return ERR_PTR(-EPROBE_DEFER);
-+
-+		engine = nand_ecc_match_on_host_hw_engine(&pdev->dev);
-+		platform_device_put(pdev);
-+		of_node_put(np);
-+
-+		if (!engine)
-+			return ERR_PTR(-EPROBE_DEFER);
-+	}
-+
-+	if (engine)
-+		get_device(engine->dev);
-+
-+	return engine;
-+}
-+EXPORT_SYMBOL(nand_ecc_get_on_host_hw_engine);
-+
-+void nand_ecc_put_on_host_hw_engine(struct nand_device *nand)
-+{
-+	put_device(nand->ecc.engine->dev);
-+}
-+EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine);
-+
- MODULE_LICENSE("GPL");
- MODULE_AUTHOR("Miquel Raynal <[email protected]>");
- MODULE_DESCRIPTION("Generic ECC engine");
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -264,11 +264,35 @@ struct nand_ecc_engine_ops {
- };
- 
- /**
-+ * enum nand_ecc_engine_integration - How the NAND ECC engine is integrated
-+ * @NAND_ECC_ENGINE_INTEGRATION_INVALID: Invalid value
-+ * @NAND_ECC_ENGINE_INTEGRATION_PIPELINED: Pipelined engine, performs on-the-fly
-+ *                                         correction, does not need to copy
-+ *                                         data around
-+ * @NAND_ECC_ENGINE_INTEGRATION_EXTERNAL: External engine, needs to bring the
-+ *                                        data into its own area before use
-+ */
-+enum nand_ecc_engine_integration {
-+	NAND_ECC_ENGINE_INTEGRATION_INVALID,
-+	NAND_ECC_ENGINE_INTEGRATION_PIPELINED,
-+	NAND_ECC_ENGINE_INTEGRATION_EXTERNAL,
-+};
-+
-+/**
-  * struct nand_ecc_engine - ECC engine abstraction for NAND devices
-+ * @dev: Host device
-+ * @node: Private field for registration time
-  * @ops: ECC engine operations
-+ * @integration: How the engine is integrated with the host
-+ *               (only relevant on %NAND_ECC_ENGINE_TYPE_ON_HOST engines)
-+ * @priv: Private data
-  */
- struct nand_ecc_engine {
-+	struct device *dev;
-+	struct list_head node;
- 	struct nand_ecc_engine_ops *ops;
-+	enum nand_ecc_engine_integration integration;
-+	void *priv;
- };
- 
- void of_get_nand_ecc_user_config(struct nand_device *nand);
-@@ -279,8 +303,12 @@ int nand_ecc_prepare_io_req(struct nand_
- int nand_ecc_finish_io_req(struct nand_device *nand,
- 			   struct nand_page_io_req *req);
- bool nand_ecc_is_strong_enough(struct nand_device *nand);
-+int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine);
-+int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine);
- struct nand_ecc_engine *nand_ecc_get_sw_engine(struct nand_device *nand);
- struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand);
-+struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand);
-+void nand_ecc_put_on_host_hw_engine(struct nand_device *nand);
- 
- #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING)
- struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void);

target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch

@@ -1,31 +0,0 @@
-From 840b2f8dd2d0579e517140e1f9bbc482eaf4ed07 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <[email protected]>
-Date: Thu, 16 Dec 2021 12:16:39 +0100
-Subject: [PATCH 02/15] mtd: nand: Add a new helper to retrieve the ECC context
-
-Introduce nand_to_ecc_ctx() which will allow to easily jump to the
-private pointer of an ECC context given a NAND device. This is very
-handy, from the prepare or finish ECC hook, to get the internal context
-out of the NAND device object.
-
-Signed-off-by: Miquel Raynal <[email protected]>
-Link: https://lore.kernel.org/linux-mtd/[email protected]
-(cherry picked from commit cda32a618debd3fad8e42757b198719ae180f8f4)
----
- include/linux/mtd/nand.h | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -990,6 +990,11 @@ int nanddev_markbad(struct nand_device *
- int nanddev_ecc_engine_init(struct nand_device *nand);
- void nanddev_ecc_engine_cleanup(struct nand_device *nand);
- 
-+static inline void *nand_to_ecc_ctx(struct nand_device *nand)
-+{
-+	return nand->ecc.ctx.priv;
-+}
-+
- /* BBT related functions */
- enum nand_bbt_block_status {
- 	NAND_BBT_BLOCK_STATUS_UNKNOWN,

target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch

@@ -1,73 +0,0 @@
-From 784866bc4f9f25e0494b77750f95af2a2619e498 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <[email protected]>
-Date: Thu, 16 Dec 2021 12:16:41 +0100
-Subject: [PATCH 03/15] mtd: nand: ecc: Provide a helper to retrieve a
- pilelined engine device
-
-In a pipelined engine situation, we might either have the host which
-internally has support for error correction, or have it using an
-external hardware block for this purpose. In the former case, the host
-is also the ECC engine. In the latter case, it is not. In order to get
-the right pointers on the right devices (for example: in order to devm_*
-allocate variables), let's introduce this helper which can safely be
-called by pipelined ECC engines in order to retrieve the right device
-structure.
-
-Signed-off-by: Miquel Raynal <[email protected]>
-Link: https://lore.kernel.org/linux-mtd/[email protected]
-(cherry picked from commit 5145abeb0649acf810a32e63bd762e617a9b3309)
----
- drivers/mtd/nand/ecc.c   | 31 +++++++++++++++++++++++++++++++
- include/linux/mtd/nand.h |  1 +
- 2 files changed, 32 insertions(+)
-
---- a/drivers/mtd/nand/ecc.c
-+++ b/drivers/mtd/nand/ecc.c
-@@ -699,6 +699,37 @@ void nand_ecc_put_on_host_hw_engine(stru
- }
- EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine);
- 
-+/*
-+ * In the case of a pipelined engine, the device registering the ECC
-+ * engine is not necessarily the ECC engine itself but may be a host controller.
-+ * It is then useful to provide a helper to retrieve the right device object
-+ * which actually represents the ECC engine.
-+ */
-+struct device *nand_ecc_get_engine_dev(struct device *host)
-+{
-+	struct platform_device *ecc_pdev;
-+	struct device_node *np;
-+
-+	/*
-+	 * If the device node contains this property, it means we need to follow
-+	 * it in order to get the right ECC engine device we are looking for.
-+	 */
-+	np = of_parse_phandle(host->of_node, "nand-ecc-engine", 0);
-+	if (!np)
-+		return host;
-+
-+	ecc_pdev = of_find_device_by_node(np);
-+	if (!ecc_pdev) {
-+		of_node_put(np);
-+		return NULL;
-+	}
-+
-+	platform_device_put(ecc_pdev);
-+	of_node_put(np);
-+
-+	return &ecc_pdev->dev;
-+}
-+
- MODULE_LICENSE("GPL");
- MODULE_AUTHOR("Miquel Raynal <[email protected]>");
- MODULE_DESCRIPTION("Generic ECC engine");
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -309,6 +309,7 @@ struct nand_ecc_engine *nand_ecc_get_sw_
- struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand);
- struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand);
- void nand_ecc_put_on_host_hw_engine(struct nand_device *nand);
-+struct device *nand_ecc_get_engine_dev(struct device *host);
- 
- #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING)
- struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void);

target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch

@@ -1,71 +0,0 @@
-From 3e45577e70cbf8fdc5c13033114989794a3797d5 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <[email protected]>
-Date: Thu, 27 Jan 2022 10:17:56 +0100
-Subject: [PATCH 04/15] spi: spi-mem: Introduce a capability structure
-
-Create a spi_controller_mem_caps structure and put it within the
-spi_controller structure close to the spi_controller_mem_ops
-strucure. So far the only field in this structure is the support for dtr
-operations, but soon we will add another parameter.
-
-Also create a helper to parse the capabilities and check if the
-requested capability has been set or not.
-
-Signed-off-by: Miquel Raynal <[email protected]>
-Reviewed-by: Pratyush Yadav <[email protected]>
-Reviewed-by: Boris Brezillon <[email protected]>
-Reviewed-by: Tudor Ambarus <[email protected]>
-Reviewed-by: Mark Brown <[email protected]>
-Link: https://lore.kernel.org/linux-mtd/[email protected]
-(cherry picked from commit 4a3cc7fb6e63bcfdedec25364738f1493345bd20)
----
- include/linux/spi/spi-mem.h | 11 +++++++++++
- include/linux/spi/spi.h     |  3 +++
- 2 files changed, 14 insertions(+)
-
---- a/include/linux/spi/spi-mem.h
-+++ b/include/linux/spi/spi-mem.h
-@@ -286,6 +286,17 @@ struct spi_controller_mem_ops {
- };
- 
- /**
-+ * struct spi_controller_mem_caps - SPI memory controller capabilities
-+ * @dtr: Supports DTR operations
-+ */
-+struct spi_controller_mem_caps {
-+	bool dtr;
-+};
-+
-+#define spi_mem_controller_is_capable(ctlr, cap)	\
-+	((ctlr)->mem_caps && (ctlr)->mem_caps->cap)
-+
-+/**
-  * struct spi_mem_driver - SPI memory driver
-  * @spidrv: inherit from a SPI driver
-  * @probe: probe a SPI memory. Usually where detection/initialization takes
---- a/include/linux/spi/spi.h
-+++ b/include/linux/spi/spi.h
-@@ -23,6 +23,7 @@ struct software_node;
- struct spi_controller;
- struct spi_transfer;
- struct spi_controller_mem_ops;
-+struct spi_controller_mem_caps;
- 
- /*
-  * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
-@@ -419,6 +420,7 @@ extern struct spi_device *spi_new_ancill
-  * @mem_ops: optimized/dedicated operations for interactions with SPI memory.
-  *	     This field is optional and should only be implemented if the
-  *	     controller has native support for memory like operations.
-+ * @mem_caps: controller capabilities for the handling of memory operations.
-  * @unprepare_message: undo any work done by prepare_message().
-  * @slave_abort: abort the ongoing transfer request on an SPI slave controller
-  * @cs_gpios: LEGACY: array of GPIO descs to use as chip select lines; one per
-@@ -643,6 +645,7 @@ struct spi_controller {
- 
- 	/* Optimized handlers for SPI memory-like operations. */
- 	const struct spi_controller_mem_ops *mem_ops;
-+	const struct spi_controller_mem_caps *mem_caps;
- 
- 	/* gpio chip select */
- 	int			*cs_gpios;

target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch

@@ -1,51 +0,0 @@
-From c9cae7e1e5c87d0aa76b7bededa5191a0c8cf25a Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <[email protected]>
-Date: Thu, 27 Jan 2022 10:17:57 +0100
-Subject: [PATCH 05/15] spi: spi-mem: Check the controller extra capabilities
-
-Controllers can now provide a spi-mem capabilities structure. Let's make
-use of it in spi_mem_controller_default_supports_op(). As we want to
-check for DTR operations as well as normal operations in a single
-helper, let's pull the necessary checks from spi_mem_dtr_supports_op()
-for now.
-
-However, because no controller provide these extra capabilities, this
-change has no effect so far.
-
-Signed-off-by: Miquel Raynal <[email protected]>
-Reviewed-by: Pratyush Yadav <[email protected]>
-Reviewed-by: Boris Brezillon <[email protected]>
-Reviewed-by: Tudor Ambarus <[email protected]>
-Link: https://lore.kernel.org/linux-mtd/[email protected]
-(cherry picked from commit cb7e96ee81edaa48c67d84c14df2cbe464391c37)
----
- drivers/spi/spi-mem.c | 17 +++++++++++++----
- 1 file changed, 13 insertions(+), 4 deletions(-)
-
---- a/drivers/spi/spi-mem.c
-+++ b/drivers/spi/spi-mem.c
-@@ -173,11 +173,20 @@ EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_o
- bool spi_mem_default_supports_op(struct spi_mem *mem,
- 				 const struct spi_mem_op *op)
- {
--	if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
--		return false;
-+	struct spi_controller *ctlr = mem->spi->controller;
-+	bool op_is_dtr =
-+		op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr;
- 
--	if (op->cmd.nbytes != 1)
--		return false;
-+	if (op_is_dtr) {
-+		if (!spi_mem_controller_is_capable(ctlr, dtr))
-+			return false;
-+
-+		if (op->cmd.nbytes != 2)
-+			return false;
-+	} else {
-+		if (op->cmd.nbytes != 1)
-+			return false;
-+	}
- 
- 	return spi_mem_check_buswidth(mem, op);
- }

target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch

@@ -1,111 +0,0 @@
-From 2e5fba82e4aeb72d71230eef2541881615aaf7cf Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <[email protected]>
-Date: Thu, 27 Jan 2022 10:18:00 +0100
-Subject: [PATCH 06/15] spi: spi-mem: Kill the spi_mem_dtr_supports_op() helper
-
-Now that spi_mem_default_supports_op() has access to the static
-controller capabilities (relating to memory operations), and now that
-these capabilities have been filled by the relevant controllers, there
-is no need for a specific helper checking only DTR operations, so let's
-just kill spi_mem_dtr_supports_op() and simply use
-spi_mem_default_supports_op() instead.
-
-Signed-off-by: Miquel Raynal <[email protected]>
-Reviewed-by: Pratyush Yadav <[email protected]>
-Reviewed-by: Boris Brezillon <[email protected]>
-Reviewed-by: Tudor Ambarus <[email protected]>
-Link: https://lore.kernel.org/linux-mtd/[email protected]
-(cherry picked from commit 9a15efc5d5e6b5beaed0883e5bdcd0b1384c1b20)
----
- drivers/spi/spi-cadence-quadspi.c |  5 +----
- drivers/spi/spi-mem.c             | 10 ----------
- drivers/spi/spi-mxic.c            | 10 +---------
- include/linux/spi/spi-mem.h       | 11 -----------
- 4 files changed, 2 insertions(+), 34 deletions(-)
-
---- a/drivers/spi/spi-cadence-quadspi.c
-+++ b/drivers/spi/spi-cadence-quadspi.c
-@@ -1249,10 +1249,7 @@ static bool cqspi_supports_mem_op(struct
- 		return false;
- 	}
- 
--	if (all_true)
--		return spi_mem_dtr_supports_op(mem, op);
--	else
--		return spi_mem_default_supports_op(mem, op);
-+	return spi_mem_default_supports_op(mem, op);
- }
- 
- static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
---- a/drivers/spi/spi-mem.c
-+++ b/drivers/spi/spi-mem.c
-@@ -160,16 +160,6 @@ static bool spi_mem_check_buswidth(struc
- 	return true;
- }
- 
--bool spi_mem_dtr_supports_op(struct spi_mem *mem,
--			     const struct spi_mem_op *op)
--{
--	if (op->cmd.nbytes != 2)
--		return false;
--
--	return spi_mem_check_buswidth(mem, op);
--}
--EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op);
--
- bool spi_mem_default_supports_op(struct spi_mem *mem,
- 				 const struct spi_mem_op *op)
- {
---- a/drivers/spi/spi-mxic.c
-+++ b/drivers/spi/spi-mxic.c
-@@ -331,8 +331,6 @@ static int mxic_spi_data_xfer(struct mxi
- static bool mxic_spi_mem_supports_op(struct spi_mem *mem,
- 				     const struct spi_mem_op *op)
- {
--	bool all_false;
--
- 	if (op->data.buswidth > 8 || op->addr.buswidth > 8 ||
- 	    op->dummy.buswidth > 8 || op->cmd.buswidth > 8)
- 		return false;
-@@ -344,13 +342,7 @@ static bool mxic_spi_mem_supports_op(str
- 	if (op->addr.nbytes > 7)
- 		return false;
- 
--	all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
--		    !op->data.dtr;
--
--	if (all_false)
--		return spi_mem_default_supports_op(mem, op);
--	else
--		return spi_mem_dtr_supports_op(mem, op);
-+	return spi_mem_default_supports_op(mem, op);
- }
- 
- static int mxic_spi_mem_exec_op(struct spi_mem *mem,
---- a/include/linux/spi/spi-mem.h
-+++ b/include/linux/spi/spi-mem.h
-@@ -330,10 +330,6 @@ void spi_controller_dma_unmap_mem_op_dat
- 
- bool spi_mem_default_supports_op(struct spi_mem *mem,
- 				 const struct spi_mem_op *op);
--
--bool spi_mem_dtr_supports_op(struct spi_mem *mem,
--			     const struct spi_mem_op *op);
--
- #else
- static inline int
- spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
-@@ -356,13 +352,6 @@ bool spi_mem_default_supports_op(struct
- {
- 	return false;
- }
--
--static inline
--bool spi_mem_dtr_supports_op(struct spi_mem *mem,
--			     const struct spi_mem_op *op)
--{
--	return false;
--}
- #endif /* CONFIG_SPI_MEM */
- 
- int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op);

target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch

@@ -1,72 +0,0 @@
-From 9e7eb0ea442ecb1c3fe443289e288694f10c5148 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <[email protected]>
-Date: Thu, 27 Jan 2022 10:18:01 +0100
-Subject: [PATCH 07/15] spi: spi-mem: Add an ecc parameter to the spi_mem_op
- structure
-
-Soon the SPI-NAND core will need a way to request a SPI controller to
-enable ECC support for a given operation. This is because of the
-pipelined integration of certain ECC engines, which are directly managed
-by the SPI controller itself.
-
-Introduce a spi_mem_op additional field for this purpose: ecc.
-
-So far this field is left unset and checked to be false by all
-the SPI controller drivers in their ->supports_op() hook, as they all
-call spi_mem_default_supports_op().
-
-Signed-off-by: Miquel Raynal <[email protected]>
-Acked-by: Pratyush Yadav <[email protected]>
-Reviewed-by: Boris Brezillon <[email protected]>
-Reviewed-by: Tudor Ambarus <[email protected]>
-Link: https://lore.kernel.org/linux-mtd/[email protected]
-(cherry picked from commit a433c2cbd75ab76f277364f44e76f32c7df306e7)
----
- drivers/spi/spi-mem.c       | 5 +++++
- include/linux/spi/spi-mem.h | 4 ++++
- 2 files changed, 9 insertions(+)
-
---- a/drivers/spi/spi-mem.c
-+++ b/drivers/spi/spi-mem.c
-@@ -178,6 +178,11 @@ bool spi_mem_default_supports_op(struct
- 			return false;
- 	}
- 
-+	if (op->data.ecc) {
-+		if (!spi_mem_controller_is_capable(ctlr, ecc))
-+			return false;
-+	}
-+
- 	return spi_mem_check_buswidth(mem, op);
- }
- EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
---- a/include/linux/spi/spi-mem.h
-+++ b/include/linux/spi/spi-mem.h
-@@ -89,6 +89,7 @@ enum spi_mem_data_dir {
-  * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not
-  * @data.buswidth: number of IO lanes used to send/receive the data
-  * @data.dtr: whether the data should be sent in DTR mode or not
-+ * @data.ecc: whether error correction is required or not
-  * @data.dir: direction of the transfer
-  * @data.nbytes: number of data bytes to send/receive. Can be zero if the
-  *		 operation does not involve transferring data
-@@ -119,6 +120,7 @@ struct spi_mem_op {
- 	struct {
- 		u8 buswidth;
- 		u8 dtr : 1;
-+		u8 ecc : 1;
- 		enum spi_mem_data_dir dir;
- 		unsigned int nbytes;
- 		union {
-@@ -288,9 +290,11 @@ struct spi_controller_mem_ops {
- /**
-  * struct spi_controller_mem_caps - SPI memory controller capabilities
-  * @dtr: Supports DTR operations
-+ * @ecc: Supports operations with error correction
-  */
- struct spi_controller_mem_caps {
- 	bool dtr;
-+	bool ecc;
- };
- 
- #define spi_mem_controller_is_capable(ctlr, cap)	\

target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch

@@ -1,50 +0,0 @@
-From 94ef3c35b935a63f6c156957c92f6cf33c9a8dae Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <[email protected]>
-Date: Thu, 27 Jan 2022 10:18:02 +0100
-Subject: [PATCH 08/15] mtd: spinand: Delay a little bit the dirmap creation
-
-As we will soon tweak the dirmap creation to act a little bit
-differently depending on the picked ECC engine, we need to initialize
-dirmaps after ECC engines. This should not have any effect as dirmaps
-are not yet used at this point.
-
-Signed-off-by: Miquel Raynal <[email protected]>
-Reviewed-by: Boris Brezillon <[email protected]>
-Link: https://lore.kernel.org/linux-mtd/[email protected]
-(cherry picked from commit dc4c2cbf0be2d4a8e2a65013ea2815bb2c8ba949)
----
- drivers/mtd/nand/spi/core.c | 16 ++++++++--------
- 1 file changed, 8 insertions(+), 8 deletions(-)
-
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -1221,14 +1221,6 @@ static int spinand_init(struct spinand_d
- 	if (ret)
- 		goto err_free_bufs;
- 
--	ret = spinand_create_dirmaps(spinand);
--	if (ret) {
--		dev_err(dev,
--			"Failed to create direct mappings for read/write operations (err = %d)\n",
--			ret);
--		goto err_manuf_cleanup;
--	}
--
- 	ret = nanddev_init(nand, &spinand_ops, THIS_MODULE);
- 	if (ret)
- 		goto err_manuf_cleanup;
-@@ -1263,6 +1255,14 @@ static int spinand_init(struct spinand_d
- 	mtd->ecc_strength = nanddev_get_ecc_conf(nand)->strength;
- 	mtd->ecc_step_size = nanddev_get_ecc_conf(nand)->step_size;
- 
-+	ret = spinand_create_dirmaps(spinand);
-+	if (ret) {
-+		dev_err(dev,
-+			"Failed to create direct mappings for read/write operations (err = %d)\n",
-+			ret);
-+		goto err_cleanup_ecc_engine;
-+	}
-+
- 	return 0;
- 
- err_cleanup_ecc_engine:

target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch

@@ -1,98 +0,0 @@
-From eb4a2d282c3c5752211d69be6dff2674119e5583 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <[email protected]>
-Date: Thu, 27 Jan 2022 10:18:03 +0100
-Subject: [PATCH 09/15] mtd: spinand: Create direct mapping descriptors for ECC
- operations
-
-In order for pipelined ECC engines to be able to enable/disable the ECC
-engine only when needed and avoid races when future parallel-operations
-will be supported, we need to provide the information about the use of
-the ECC engine in the direct mapping hooks. As direct mapping
-configurations are meant to be static, it is best to create two new
-mappings: one for regular 'raw' accesses and one for accesses involving
-correction. It is up to the driver to use or not the new ECC enable
-boolean contained in the spi-mem operation.
-
-As dirmaps are not free (they consume a few pages of MMIO address space)
-and because these extra entries are only meant to be used by pipelined
-engines, let's limit their use to this specific type of engine and save
-a bit of memory with all the other setups.
-
-Signed-off-by: Miquel Raynal <[email protected]>
-Reviewed-by: Boris Brezillon <[email protected]>
-Link: https://lore.kernel.org/linux-mtd/[email protected]
-(cherry picked from commit f9d7c7265bcff7d9a17425a8cddf702e8fe159c2)
----
- drivers/mtd/nand/spi/core.c | 35 +++++++++++++++++++++++++++++++++--
- include/linux/mtd/spinand.h |  2 ++
- 2 files changed, 35 insertions(+), 2 deletions(-)
-
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -381,7 +381,10 @@ static int spinand_read_from_cache_op(st
- 		}
- 	}
- 
--	rdesc = spinand->dirmaps[req->pos.plane].rdesc;
-+	if (req->mode == MTD_OPS_RAW)
-+		rdesc = spinand->dirmaps[req->pos.plane].rdesc;
-+	else
-+		rdesc = spinand->dirmaps[req->pos.plane].rdesc_ecc;
- 
- 	while (nbytes) {
- 		ret = spi_mem_dirmap_read(rdesc, column, nbytes, buf);
-@@ -452,7 +455,10 @@ static int spinand_write_to_cache_op(str
- 			       req->ooblen);
- 	}
- 
--	wdesc = spinand->dirmaps[req->pos.plane].wdesc;
-+	if (req->mode == MTD_OPS_RAW)
-+		wdesc = spinand->dirmaps[req->pos.plane].wdesc;
-+	else
-+		wdesc = spinand->dirmaps[req->pos.plane].wdesc_ecc;
- 
- 	while (nbytes) {
- 		ret = spi_mem_dirmap_write(wdesc, column, nbytes, buf);
-@@ -875,6 +881,31 @@ static int spinand_create_dirmap(struct
- 
- 	spinand->dirmaps[plane].rdesc = desc;
- 
-+	if (nand->ecc.engine->integration != NAND_ECC_ENGINE_INTEGRATION_PIPELINED) {
-+		spinand->dirmaps[plane].wdesc_ecc = spinand->dirmaps[plane].wdesc;
-+		spinand->dirmaps[plane].rdesc_ecc = spinand->dirmaps[plane].rdesc;
-+
-+		return 0;
-+	}
-+
-+	info.op_tmpl = *spinand->op_templates.update_cache;
-+	info.op_tmpl.data.ecc = true;
-+	desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
-+					  spinand->spimem, &info);
-+	if (IS_ERR(desc))
-+		return PTR_ERR(desc);
-+
-+	spinand->dirmaps[plane].wdesc_ecc = desc;
-+
-+	info.op_tmpl = *spinand->op_templates.read_cache;
-+	info.op_tmpl.data.ecc = true;
-+	desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
-+					  spinand->spimem, &info);
-+	if (IS_ERR(desc))
-+		return PTR_ERR(desc);
-+
-+	spinand->dirmaps[plane].rdesc_ecc = desc;
-+
- 	return 0;
- }
- 
---- a/include/linux/mtd/spinand.h
-+++ b/include/linux/mtd/spinand.h
-@@ -392,6 +392,8 @@ struct spinand_info {
- struct spinand_dirmap {
- 	struct spi_mem_dirmap_desc *wdesc;
- 	struct spi_mem_dirmap_desc *rdesc;
-+	struct spi_mem_dirmap_desc *wdesc_ecc;
-+	struct spi_mem_dirmap_desc *rdesc_ecc;
- };
- 
- /**

target/linux/mediatek/patches-5.15/120-11-v5.19-mtd-nand-make-mtk_ecc.c-a-separated-module.patch

@@ -1,1383 +0,0 @@
-From ebb9653d4a87c64fb679e4c339e867556dada719 Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <[email protected]>
-Date: Tue, 22 Mar 2022 18:44:21 +0800
-Subject: [PATCH 11/15] mtd: nand: make mtk_ecc.c a separated module
-
-this code will be used in mediatek snfi spi-mem controller with
-pipelined ECC engine.
-
-Signed-off-by: Chuanhong Guo <[email protected]>
-(cherry picked from commit 316f47cec4ce5b81aa8006de202d8769c117a52d)
----
- drivers/mtd/nand/Kconfig                                   | 7 +++++++
- drivers/mtd/nand/Makefile                                  | 1 +
- drivers/mtd/nand/{raw/mtk_ecc.c => ecc-mtk.c}              | 3 +--
- drivers/mtd/nand/raw/Kconfig                               | 1 +
- drivers/mtd/nand/raw/Makefile                              | 2 +-
- drivers/mtd/nand/raw/mtk_nand.c                            | 2 +-
- .../nand/raw/mtk_ecc.h => include/linux/mtd/nand-ecc-mtk.h | 0
- 7 files changed, 12 insertions(+), 4 deletions(-)
- rename drivers/mtd/nand/{raw/mtk_ecc.c => ecc-mtk.c} (99%)
- rename drivers/mtd/nand/raw/mtk_ecc.h => include/linux/mtd/nand-ecc-mtk.h (100%)
-
---- a/drivers/mtd/nand/Kconfig
-+++ b/drivers/mtd/nand/Kconfig
-@@ -50,6 +50,13 @@ config MTD_NAND_MTK_BMT
- 	bool "Support MediaTek NAND Bad-block Management Table"
- 	default n
- 
-+config MTD_NAND_ECC_MEDIATEK
-+	tristate "Mediatek hardware ECC engine"
-+	depends on HAS_IOMEM
-+	select MTD_NAND_ECC
-+	help
-+	  This enables support for the hardware ECC engine from Mediatek.
-+
- endmenu
- 
- endmenu
---- a/drivers/mtd/nand/Makefile
-+++ b/drivers/mtd/nand/Makefile
-@@ -3,6 +3,7 @@
- nandcore-objs := core.o bbt.o
- obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o
- obj-$(CONFIG_MTD_NAND_MTK_BMT)	+= mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o
-+obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o
- 
- obj-y	+= onenand/
- obj-y	+= raw/
---- a/drivers/mtd/nand/raw/mtk_ecc.c
-+++ /dev/null
-@@ -1,599 +0,0 @@
--// SPDX-License-Identifier: GPL-2.0 OR MIT
--/*
-- * MTK ECC controller driver.
-- * Copyright (C) 2016  MediaTek Inc.
-- * Authors:	Xiaolei Li		<[email protected]>
-- *		Jorge Ramirez-Ortiz	<[email protected]>
-- */
--
--#include <linux/platform_device.h>
--#include <linux/dma-mapping.h>
--#include <linux/interrupt.h>
--#include <linux/clk.h>
--#include <linux/module.h>
--#include <linux/iopoll.h>
--#include <linux/of.h>
--#include <linux/of_platform.h>
--#include <linux/mutex.h>
--
--#include "mtk_ecc.h"
--
--#define ECC_IDLE_MASK		BIT(0)
--#define ECC_IRQ_EN		BIT(0)
--#define ECC_PG_IRQ_SEL		BIT(1)
--#define ECC_OP_ENABLE		(1)
--#define ECC_OP_DISABLE		(0)
--
--#define ECC_ENCCON		(0x00)
--#define ECC_ENCCNFG		(0x04)
--#define		ECC_MS_SHIFT		(16)
--#define ECC_ENCDIADDR		(0x08)
--#define ECC_ENCIDLE		(0x0C)
--#define ECC_DECCON		(0x100)
--#define ECC_DECCNFG		(0x104)
--#define		DEC_EMPTY_EN		BIT(31)
--#define		DEC_CNFG_CORRECT	(0x3 << 12)
--#define ECC_DECIDLE		(0x10C)
--#define ECC_DECENUM0		(0x114)
--
--#define ECC_TIMEOUT		(500000)
--
--#define ECC_IDLE_REG(op)	((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
--#define ECC_CTL_REG(op)		((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
--
--struct mtk_ecc_caps {
--	u32 err_mask;
--	u32 err_shift;
--	const u8 *ecc_strength;
--	const u32 *ecc_regs;
--	u8 num_ecc_strength;
--	u8 ecc_mode_shift;
--	u32 parity_bits;
--	int pg_irq_sel;
--};
--
--struct mtk_ecc {
--	struct device *dev;
--	const struct mtk_ecc_caps *caps;
--	void __iomem *regs;
--	struct clk *clk;
--
--	struct completion done;
--	struct mutex lock;
--	u32 sectors;
--
--	u8 *eccdata;
--};
--
--/* ecc strength that each IP supports */
--static const u8 ecc_strength_mt2701[] = {
--	4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
--	40, 44, 48, 52, 56, 60
--};
--
--static const u8 ecc_strength_mt2712[] = {
--	4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
--	40, 44, 48, 52, 56, 60, 68, 72, 80
--};
--
--static const u8 ecc_strength_mt7622[] = {
--	4, 6, 8, 10, 12
--};
--
--enum mtk_ecc_regs {
--	ECC_ENCPAR00,
--	ECC_ENCIRQ_EN,
--	ECC_ENCIRQ_STA,
--	ECC_DECDONE,
--	ECC_DECIRQ_EN,
--	ECC_DECIRQ_STA,
--};
--
--static int mt2701_ecc_regs[] = {
--	[ECC_ENCPAR00] =        0x10,
--	[ECC_ENCIRQ_EN] =       0x80,
--	[ECC_ENCIRQ_STA] =      0x84,
--	[ECC_DECDONE] =         0x124,
--	[ECC_DECIRQ_EN] =       0x200,
--	[ECC_DECIRQ_STA] =      0x204,
--};
--
--static int mt2712_ecc_regs[] = {
--	[ECC_ENCPAR00] =        0x300,
--	[ECC_ENCIRQ_EN] =       0x80,
--	[ECC_ENCIRQ_STA] =      0x84,
--	[ECC_DECDONE] =         0x124,
--	[ECC_DECIRQ_EN] =       0x200,
--	[ECC_DECIRQ_STA] =      0x204,
--};
--
--static int mt7622_ecc_regs[] = {
--	[ECC_ENCPAR00] =        0x10,
--	[ECC_ENCIRQ_EN] =       0x30,
--	[ECC_ENCIRQ_STA] =      0x34,
--	[ECC_DECDONE] =         0x11c,
--	[ECC_DECIRQ_EN] =       0x140,
--	[ECC_DECIRQ_STA] =      0x144,
--};
--
--static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
--				     enum mtk_ecc_operation op)
--{
--	struct device *dev = ecc->dev;
--	u32 val;
--	int ret;
--
--	ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,
--					val & ECC_IDLE_MASK,
--					10, ECC_TIMEOUT);
--	if (ret)
--		dev_warn(dev, "%s NOT idle\n",
--			 op == ECC_ENCODE ? "encoder" : "decoder");
--}
--
--static irqreturn_t mtk_ecc_irq(int irq, void *id)
--{
--	struct mtk_ecc *ecc = id;
--	u32 dec, enc;
--
--	dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
--		    & ECC_IRQ_EN;
--	if (dec) {
--		dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
--		if (dec & ecc->sectors) {
--			/*
--			 * Clear decode IRQ status once again to ensure that
--			 * there will be no extra IRQ.
--			 */
--			readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
--			ecc->sectors = 0;
--			complete(&ecc->done);
--		} else {
--			return IRQ_HANDLED;
--		}
--	} else {
--		enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
--		      & ECC_IRQ_EN;
--		if (enc)
--			complete(&ecc->done);
--		else
--			return IRQ_NONE;
--	}
--
--	return IRQ_HANDLED;
--}
--
--static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
--{
--	u32 ecc_bit, dec_sz, enc_sz;
--	u32 reg, i;
--
--	for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
--		if (ecc->caps->ecc_strength[i] == config->strength)
--			break;
--	}
--
--	if (i == ecc->caps->num_ecc_strength) {
--		dev_err(ecc->dev, "invalid ecc strength %d\n",
--			config->strength);
--		return -EINVAL;
--	}
--
--	ecc_bit = i;
--
--	if (config->op == ECC_ENCODE) {
--		/* configure ECC encoder (in bits) */
--		enc_sz = config->len << 3;
--
--		reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
--		reg |= (enc_sz << ECC_MS_SHIFT);
--		writel(reg, ecc->regs + ECC_ENCCNFG);
--
--		if (config->mode != ECC_NFI_MODE)
--			writel(lower_32_bits(config->addr),
--			       ecc->regs + ECC_ENCDIADDR);
--
--	} else {
--		/* configure ECC decoder (in bits) */
--		dec_sz = (config->len << 3) +
--			 config->strength * ecc->caps->parity_bits;
--
--		reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
--		reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
--		reg |= DEC_EMPTY_EN;
--		writel(reg, ecc->regs + ECC_DECCNFG);
--
--		if (config->sectors)
--			ecc->sectors = 1 << (config->sectors - 1);
--	}
--
--	return 0;
--}
--
--void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
--		       int sectors)
--{
--	u32 offset, i, err;
--	u32 bitflips = 0;
--
--	stats->corrected = 0;
--	stats->failed = 0;
--
--	for (i = 0; i < sectors; i++) {
--		offset = (i >> 2) << 2;
--		err = readl(ecc->regs + ECC_DECENUM0 + offset);
--		err = err >> ((i % 4) * ecc->caps->err_shift);
--		err &= ecc->caps->err_mask;
--		if (err == ecc->caps->err_mask) {
--			/* uncorrectable errors */
--			stats->failed++;
--			continue;
--		}
--
--		stats->corrected += err;
--		bitflips = max_t(u32, bitflips, err);
--	}
--
--	stats->bitflips = bitflips;
--}
--EXPORT_SYMBOL(mtk_ecc_get_stats);
--
--void mtk_ecc_release(struct mtk_ecc *ecc)
--{
--	clk_disable_unprepare(ecc->clk);
--	put_device(ecc->dev);
--}
--EXPORT_SYMBOL(mtk_ecc_release);
--
--static void mtk_ecc_hw_init(struct mtk_ecc *ecc)
--{
--	mtk_ecc_wait_idle(ecc, ECC_ENCODE);
--	writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
--
--	mtk_ecc_wait_idle(ecc, ECC_DECODE);
--	writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
--}
--
--static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
--{
--	struct platform_device *pdev;
--	struct mtk_ecc *ecc;
--
--	pdev = of_find_device_by_node(np);
--	if (!pdev)
--		return ERR_PTR(-EPROBE_DEFER);
--
--	ecc = platform_get_drvdata(pdev);
--	if (!ecc) {
--		put_device(&pdev->dev);
--		return ERR_PTR(-EPROBE_DEFER);
--	}
--
--	clk_prepare_enable(ecc->clk);
--	mtk_ecc_hw_init(ecc);
--
--	return ecc;
--}
--
--struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)
--{
--	struct mtk_ecc *ecc = NULL;
--	struct device_node *np;
--
--	np = of_parse_phandle(of_node, "ecc-engine", 0);
--	if (np) {
--		ecc = mtk_ecc_get(np);
--		of_node_put(np);
--	}
--
--	return ecc;
--}
--EXPORT_SYMBOL(of_mtk_ecc_get);
--
--int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
--{
--	enum mtk_ecc_operation op = config->op;
--	u16 reg_val;
--	int ret;
--
--	ret = mutex_lock_interruptible(&ecc->lock);
--	if (ret) {
--		dev_err(ecc->dev, "interrupted when attempting to lock\n");
--		return ret;
--	}
--
--	mtk_ecc_wait_idle(ecc, op);
--
--	ret = mtk_ecc_config(ecc, config);
--	if (ret) {
--		mutex_unlock(&ecc->lock);
--		return ret;
--	}
--
--	if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) {
--		init_completion(&ecc->done);
--		reg_val = ECC_IRQ_EN;
--		/*
--		 * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it
--		 * means this chip can only generate one ecc irq during page
--		 * read / write. If is 0, generate one ecc irq each ecc step.
--		 */
--		if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
--			reg_val |= ECC_PG_IRQ_SEL;
--		if (op == ECC_ENCODE)
--			writew(reg_val, ecc->regs +
--			       ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
--		else
--			writew(reg_val, ecc->regs +
--			       ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
--	}
--
--	writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
--
--	return 0;
--}
--EXPORT_SYMBOL(mtk_ecc_enable);
--
--void mtk_ecc_disable(struct mtk_ecc *ecc)
--{
--	enum mtk_ecc_operation op = ECC_ENCODE;
--
--	/* find out the running operation */
--	if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
--		op = ECC_DECODE;
--
--	/* disable it */
--	mtk_ecc_wait_idle(ecc, op);
--	if (op == ECC_DECODE) {
--		/*
--		 * Clear decode IRQ status in case there is a timeout to wait
--		 * decode IRQ.
--		 */
--		readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
--		writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
--	} else {
--		writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
--	}
--
--	writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
--
--	mutex_unlock(&ecc->lock);
--}
--EXPORT_SYMBOL(mtk_ecc_disable);
--
--int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)
--{
--	int ret;
--
--	ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
--	if (!ret) {
--		dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
--			(op == ECC_ENCODE) ? "encoder" : "decoder");
--		return -ETIMEDOUT;
--	}
--
--	return 0;
--}
--EXPORT_SYMBOL(mtk_ecc_wait_done);
--
--int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
--		   u8 *data, u32 bytes)
--{
--	dma_addr_t addr;
--	u32 len;
--	int ret;
--
--	addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
--	ret = dma_mapping_error(ecc->dev, addr);
--	if (ret) {
--		dev_err(ecc->dev, "dma mapping error\n");
--		return -EINVAL;
--	}
--
--	config->op = ECC_ENCODE;
--	config->addr = addr;
--	ret = mtk_ecc_enable(ecc, config);
--	if (ret) {
--		dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
--		return ret;
--	}
--
--	ret = mtk_ecc_wait_done(ecc, ECC_ENCODE);
--	if (ret)
--		goto timeout;
--
--	mtk_ecc_wait_idle(ecc, ECC_ENCODE);
--
--	/* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
--	len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
--
--	/* write the parity bytes generated by the ECC back to temp buffer */
--	__ioread32_copy(ecc->eccdata,
--			ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
--			round_up(len, 4));
--
--	/* copy into possibly unaligned OOB region with actual length */
--	memcpy(data + bytes, ecc->eccdata, len);
--timeout:
--
--	dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
--	mtk_ecc_disable(ecc);
--
--	return ret;
--}
--EXPORT_SYMBOL(mtk_ecc_encode);
--
--void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
--{
--	const u8 *ecc_strength = ecc->caps->ecc_strength;
--	int i;
--
--	for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
--		if (*p <= ecc_strength[i]) {
--			if (!i)
--				*p = ecc_strength[i];
--			else if (*p != ecc_strength[i])
--				*p = ecc_strength[i - 1];
--			return;
--		}
--	}
--
--	*p = ecc_strength[ecc->caps->num_ecc_strength - 1];
--}
--EXPORT_SYMBOL(mtk_ecc_adjust_strength);
--
--unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
--{
--	return ecc->caps->parity_bits;
--}
--EXPORT_SYMBOL(mtk_ecc_get_parity_bits);
--
--static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
--	.err_mask = 0x3f,
--	.err_shift = 8,
--	.ecc_strength = ecc_strength_mt2701,
--	.ecc_regs = mt2701_ecc_regs,
--	.num_ecc_strength = 20,
--	.ecc_mode_shift = 5,
--	.parity_bits = 14,
--	.pg_irq_sel = 0,
--};
--
--static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
--	.err_mask = 0x7f,
--	.err_shift = 8,
--	.ecc_strength = ecc_strength_mt2712,
--	.ecc_regs = mt2712_ecc_regs,
--	.num_ecc_strength = 23,
--	.ecc_mode_shift = 5,
--	.parity_bits = 14,
--	.pg_irq_sel = 1,
--};
--
--static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
--	.err_mask = 0x1f,
--	.err_shift = 5,
--	.ecc_strength = ecc_strength_mt7622,
--	.ecc_regs = mt7622_ecc_regs,
--	.num_ecc_strength = 5,
--	.ecc_mode_shift = 4,
--	.parity_bits = 13,
--	.pg_irq_sel = 0,
--};
--
--static const struct of_device_id mtk_ecc_dt_match[] = {
--	{
--		.compatible = "mediatek,mt2701-ecc",
--		.data = &mtk_ecc_caps_mt2701,
--	}, {
--		.compatible = "mediatek,mt2712-ecc",
--		.data = &mtk_ecc_caps_mt2712,
--	}, {
--		.compatible = "mediatek,mt7622-ecc",
--		.data = &mtk_ecc_caps_mt7622,
--	},
--	{},
--};
--
--static int mtk_ecc_probe(struct platform_device *pdev)
--{
--	struct device *dev = &pdev->dev;
--	struct mtk_ecc *ecc;
--	struct resource *res;
--	u32 max_eccdata_size;
--	int irq, ret;
--
--	ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
--	if (!ecc)
--		return -ENOMEM;
--
--	ecc->caps = of_device_get_match_data(dev);
--
--	max_eccdata_size = ecc->caps->num_ecc_strength - 1;
--	max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
--	max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
--	max_eccdata_size = round_up(max_eccdata_size, 4);
--	ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
--	if (!ecc->eccdata)
--		return -ENOMEM;
--
--	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--	ecc->regs = devm_ioremap_resource(dev, res);
--	if (IS_ERR(ecc->regs))
--		return PTR_ERR(ecc->regs);
--
--	ecc->clk = devm_clk_get(dev, NULL);
--	if (IS_ERR(ecc->clk)) {
--		dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
--		return PTR_ERR(ecc->clk);
--	}
--
--	irq = platform_get_irq(pdev, 0);
--	if (irq < 0)
--		return irq;
--
--	ret = dma_set_mask(dev, DMA_BIT_MASK(32));
--	if (ret) {
--		dev_err(dev, "failed to set DMA mask\n");
--		return ret;
--	}
--
--	ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
--	if (ret) {
--		dev_err(dev, "failed to request irq\n");
--		return -EINVAL;
--	}
--
--	ecc->dev = dev;
--	mutex_init(&ecc->lock);
--	platform_set_drvdata(pdev, ecc);
--	dev_info(dev, "probed\n");
--
--	return 0;
--}
--
--#ifdef CONFIG_PM_SLEEP
--static int mtk_ecc_suspend(struct device *dev)
--{
--	struct mtk_ecc *ecc = dev_get_drvdata(dev);
--
--	clk_disable_unprepare(ecc->clk);
--
--	return 0;
--}
--
--static int mtk_ecc_resume(struct device *dev)
--{
--	struct mtk_ecc *ecc = dev_get_drvdata(dev);
--	int ret;
--
--	ret = clk_prepare_enable(ecc->clk);
--	if (ret) {
--		dev_err(dev, "failed to enable clk\n");
--		return ret;
--	}
--
--	return 0;
--}
--
--static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);
--#endif
--
--MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);
--
--static struct platform_driver mtk_ecc_driver = {
--	.probe  = mtk_ecc_probe,
--	.driver = {
--		.name  = "mtk-ecc",
--		.of_match_table = of_match_ptr(mtk_ecc_dt_match),
--#ifdef CONFIG_PM_SLEEP
--		.pm = &mtk_ecc_pm_ops,
--#endif
--	},
--};
--
--module_platform_driver(mtk_ecc_driver);
--
--MODULE_AUTHOR("Xiaolei Li <[email protected]>");
--MODULE_DESCRIPTION("MTK Nand ECC Driver");
--MODULE_LICENSE("Dual MIT/GPL");
---- /dev/null
-+++ b/drivers/mtd/nand/ecc-mtk.c
-@@ -0,0 +1,598 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/*
-+ * MTK ECC controller driver.
-+ * Copyright (C) 2016  MediaTek Inc.
-+ * Authors:	Xiaolei Li		<[email protected]>
-+ *		Jorge Ramirez-Ortiz	<[email protected]>
-+ */
-+
-+#include <linux/platform_device.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/interrupt.h>
-+#include <linux/clk.h>
-+#include <linux/module.h>
-+#include <linux/iopoll.h>
-+#include <linux/of.h>
-+#include <linux/of_platform.h>
-+#include <linux/mutex.h>
-+#include <linux/mtd/nand-ecc-mtk.h>
-+
-+#define ECC_IDLE_MASK		BIT(0)
-+#define ECC_IRQ_EN		BIT(0)
-+#define ECC_PG_IRQ_SEL		BIT(1)
-+#define ECC_OP_ENABLE		(1)
-+#define ECC_OP_DISABLE		(0)
-+
-+#define ECC_ENCCON		(0x00)
-+#define ECC_ENCCNFG		(0x04)
-+#define		ECC_MS_SHIFT		(16)
-+#define ECC_ENCDIADDR		(0x08)
-+#define ECC_ENCIDLE		(0x0C)
-+#define ECC_DECCON		(0x100)
-+#define ECC_DECCNFG		(0x104)
-+#define		DEC_EMPTY_EN		BIT(31)
-+#define		DEC_CNFG_CORRECT	(0x3 << 12)
-+#define ECC_DECIDLE		(0x10C)
-+#define ECC_DECENUM0		(0x114)
-+
-+#define ECC_TIMEOUT		(500000)
-+
-+#define ECC_IDLE_REG(op)	((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
-+#define ECC_CTL_REG(op)		((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
-+
-+struct mtk_ecc_caps {
-+	u32 err_mask;
-+	u32 err_shift;
-+	const u8 *ecc_strength;
-+	const u32 *ecc_regs;
-+	u8 num_ecc_strength;
-+	u8 ecc_mode_shift;
-+	u32 parity_bits;
-+	int pg_irq_sel;
-+};
-+
-+struct mtk_ecc {
-+	struct device *dev;
-+	const struct mtk_ecc_caps *caps;
-+	void __iomem *regs;
-+	struct clk *clk;
-+
-+	struct completion done;
-+	struct mutex lock;
-+	u32 sectors;
-+
-+	u8 *eccdata;
-+};
-+
-+/* ecc strength that each IP supports */
-+static const u8 ecc_strength_mt2701[] = {
-+	4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
-+	40, 44, 48, 52, 56, 60
-+};
-+
-+static const u8 ecc_strength_mt2712[] = {
-+	4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
-+	40, 44, 48, 52, 56, 60, 68, 72, 80
-+};
-+
-+static const u8 ecc_strength_mt7622[] = {
-+	4, 6, 8, 10, 12
-+};
-+
-+enum mtk_ecc_regs {
-+	ECC_ENCPAR00,
-+	ECC_ENCIRQ_EN,
-+	ECC_ENCIRQ_STA,
-+	ECC_DECDONE,
-+	ECC_DECIRQ_EN,
-+	ECC_DECIRQ_STA,
-+};
-+
-+static int mt2701_ecc_regs[] = {
-+	[ECC_ENCPAR00] =        0x10,
-+	[ECC_ENCIRQ_EN] =       0x80,
-+	[ECC_ENCIRQ_STA] =      0x84,
-+	[ECC_DECDONE] =         0x124,
-+	[ECC_DECIRQ_EN] =       0x200,
-+	[ECC_DECIRQ_STA] =      0x204,
-+};
-+
-+static int mt2712_ecc_regs[] = {
-+	[ECC_ENCPAR00] =        0x300,
-+	[ECC_ENCIRQ_EN] =       0x80,
-+	[ECC_ENCIRQ_STA] =      0x84,
-+	[ECC_DECDONE] =         0x124,
-+	[ECC_DECIRQ_EN] =       0x200,
-+	[ECC_DECIRQ_STA] =      0x204,
-+};
-+
-+static int mt7622_ecc_regs[] = {
-+	[ECC_ENCPAR00] =        0x10,
-+	[ECC_ENCIRQ_EN] =       0x30,
-+	[ECC_ENCIRQ_STA] =      0x34,
-+	[ECC_DECDONE] =         0x11c,
-+	[ECC_DECIRQ_EN] =       0x140,
-+	[ECC_DECIRQ_STA] =      0x144,
-+};
-+
-+static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
-+				     enum mtk_ecc_operation op)
-+{
-+	struct device *dev = ecc->dev;
-+	u32 val;
-+	int ret;
-+
-+	ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,
-+					val & ECC_IDLE_MASK,
-+					10, ECC_TIMEOUT);
-+	if (ret)
-+		dev_warn(dev, "%s NOT idle\n",
-+			 op == ECC_ENCODE ? "encoder" : "decoder");
-+}
-+
-+static irqreturn_t mtk_ecc_irq(int irq, void *id)
-+{
-+	struct mtk_ecc *ecc = id;
-+	u32 dec, enc;
-+
-+	dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
-+		    & ECC_IRQ_EN;
-+	if (dec) {
-+		dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
-+		if (dec & ecc->sectors) {
-+			/*
-+			 * Clear decode IRQ status once again to ensure that
-+			 * there will be no extra IRQ.
-+			 */
-+			readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
-+			ecc->sectors = 0;
-+			complete(&ecc->done);
-+		} else {
-+			return IRQ_HANDLED;
-+		}
-+	} else {
-+		enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
-+		      & ECC_IRQ_EN;
-+		if (enc)
-+			complete(&ecc->done);
-+		else
-+			return IRQ_NONE;
-+	}
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
-+{
-+	u32 ecc_bit, dec_sz, enc_sz;
-+	u32 reg, i;
-+
-+	for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
-+		if (ecc->caps->ecc_strength[i] == config->strength)
-+			break;
-+	}
-+
-+	if (i == ecc->caps->num_ecc_strength) {
-+		dev_err(ecc->dev, "invalid ecc strength %d\n",
-+			config->strength);
-+		return -EINVAL;
-+	}
-+
-+	ecc_bit = i;
-+
-+	if (config->op == ECC_ENCODE) {
-+		/* configure ECC encoder (in bits) */
-+		enc_sz = config->len << 3;
-+
-+		reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
-+		reg |= (enc_sz << ECC_MS_SHIFT);
-+		writel(reg, ecc->regs + ECC_ENCCNFG);
-+
-+		if (config->mode != ECC_NFI_MODE)
-+			writel(lower_32_bits(config->addr),
-+			       ecc->regs + ECC_ENCDIADDR);
-+
-+	} else {
-+		/* configure ECC decoder (in bits) */
-+		dec_sz = (config->len << 3) +
-+			 config->strength * ecc->caps->parity_bits;
-+
-+		reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
-+		reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
-+		reg |= DEC_EMPTY_EN;
-+		writel(reg, ecc->regs + ECC_DECCNFG);
-+
-+		if (config->sectors)
-+			ecc->sectors = 1 << (config->sectors - 1);
-+	}
-+
-+	return 0;
-+}
-+
-+void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
-+		       int sectors)
-+{
-+	u32 offset, i, err;
-+	u32 bitflips = 0;
-+
-+	stats->corrected = 0;
-+	stats->failed = 0;
-+
-+	for (i = 0; i < sectors; i++) {
-+		offset = (i >> 2) << 2;
-+		err = readl(ecc->regs + ECC_DECENUM0 + offset);
-+		err = err >> ((i % 4) * ecc->caps->err_shift);
-+		err &= ecc->caps->err_mask;
-+		if (err == ecc->caps->err_mask) {
-+			/* uncorrectable errors */
-+			stats->failed++;
-+			continue;
-+		}
-+
-+		stats->corrected += err;
-+		bitflips = max_t(u32, bitflips, err);
-+	}
-+
-+	stats->bitflips = bitflips;
-+}
-+EXPORT_SYMBOL(mtk_ecc_get_stats);
-+
-+void mtk_ecc_release(struct mtk_ecc *ecc)
-+{
-+	clk_disable_unprepare(ecc->clk);
-+	put_device(ecc->dev);
-+}
-+EXPORT_SYMBOL(mtk_ecc_release);
-+
-+static void mtk_ecc_hw_init(struct mtk_ecc *ecc)
-+{
-+	mtk_ecc_wait_idle(ecc, ECC_ENCODE);
-+	writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
-+
-+	mtk_ecc_wait_idle(ecc, ECC_DECODE);
-+	writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
-+}
-+
-+static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
-+{
-+	struct platform_device *pdev;
-+	struct mtk_ecc *ecc;
-+
-+	pdev = of_find_device_by_node(np);
-+	if (!pdev)
-+		return ERR_PTR(-EPROBE_DEFER);
-+
-+	ecc = platform_get_drvdata(pdev);
-+	if (!ecc) {
-+		put_device(&pdev->dev);
-+		return ERR_PTR(-EPROBE_DEFER);
-+	}
-+
-+	clk_prepare_enable(ecc->clk);
-+	mtk_ecc_hw_init(ecc);
-+
-+	return ecc;
-+}
-+
-+struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)
-+{
-+	struct mtk_ecc *ecc = NULL;
-+	struct device_node *np;
-+
-+	np = of_parse_phandle(of_node, "ecc-engine", 0);
-+	if (np) {
-+		ecc = mtk_ecc_get(np);
-+		of_node_put(np);
-+	}
-+
-+	return ecc;
-+}
-+EXPORT_SYMBOL(of_mtk_ecc_get);
-+
-+int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
-+{
-+	enum mtk_ecc_operation op = config->op;
-+	u16 reg_val;
-+	int ret;
-+
-+	ret = mutex_lock_interruptible(&ecc->lock);
-+	if (ret) {
-+		dev_err(ecc->dev, "interrupted when attempting to lock\n");
-+		return ret;
-+	}
-+
-+	mtk_ecc_wait_idle(ecc, op);
-+
-+	ret = mtk_ecc_config(ecc, config);
-+	if (ret) {
-+		mutex_unlock(&ecc->lock);
-+		return ret;
-+	}
-+
-+	if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) {
-+		init_completion(&ecc->done);
-+		reg_val = ECC_IRQ_EN;
-+		/*
-+		 * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it
-+		 * means this chip can only generate one ecc irq during page
-+		 * read / write. If is 0, generate one ecc irq each ecc step.
-+		 */
-+		if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
-+			reg_val |= ECC_PG_IRQ_SEL;
-+		if (op == ECC_ENCODE)
-+			writew(reg_val, ecc->regs +
-+			       ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
-+		else
-+			writew(reg_val, ecc->regs +
-+			       ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
-+	}
-+
-+	writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(mtk_ecc_enable);
-+
-+void mtk_ecc_disable(struct mtk_ecc *ecc)
-+{
-+	enum mtk_ecc_operation op = ECC_ENCODE;
-+
-+	/* find out the running operation */
-+	if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
-+		op = ECC_DECODE;
-+
-+	/* disable it */
-+	mtk_ecc_wait_idle(ecc, op);
-+	if (op == ECC_DECODE) {
-+		/*
-+		 * Clear decode IRQ status in case there is a timeout to wait
-+		 * decode IRQ.
-+		 */
-+		readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
-+		writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
-+	} else {
-+		writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
-+	}
-+
-+	writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
-+
-+	mutex_unlock(&ecc->lock);
-+}
-+EXPORT_SYMBOL(mtk_ecc_disable);
-+
-+int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)
-+{
-+	int ret;
-+
-+	ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
-+	if (!ret) {
-+		dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
-+			(op == ECC_ENCODE) ? "encoder" : "decoder");
-+		return -ETIMEDOUT;
-+	}
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(mtk_ecc_wait_done);
-+
-+int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
-+		   u8 *data, u32 bytes)
-+{
-+	dma_addr_t addr;
-+	u32 len;
-+	int ret;
-+
-+	addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
-+	ret = dma_mapping_error(ecc->dev, addr);
-+	if (ret) {
-+		dev_err(ecc->dev, "dma mapping error\n");
-+		return -EINVAL;
-+	}
-+
-+	config->op = ECC_ENCODE;
-+	config->addr = addr;
-+	ret = mtk_ecc_enable(ecc, config);
-+	if (ret) {
-+		dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
-+		return ret;
-+	}
-+
-+	ret = mtk_ecc_wait_done(ecc, ECC_ENCODE);
-+	if (ret)
-+		goto timeout;
-+
-+	mtk_ecc_wait_idle(ecc, ECC_ENCODE);
-+
-+	/* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
-+	len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
-+
-+	/* write the parity bytes generated by the ECC back to temp buffer */
-+	__ioread32_copy(ecc->eccdata,
-+			ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
-+			round_up(len, 4));
-+
-+	/* copy into possibly unaligned OOB region with actual length */
-+	memcpy(data + bytes, ecc->eccdata, len);
-+timeout:
-+
-+	dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
-+	mtk_ecc_disable(ecc);
-+
-+	return ret;
-+}
-+EXPORT_SYMBOL(mtk_ecc_encode);
-+
-+void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
-+{
-+	const u8 *ecc_strength = ecc->caps->ecc_strength;
-+	int i;
-+
-+	for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
-+		if (*p <= ecc_strength[i]) {
-+			if (!i)
-+				*p = ecc_strength[i];
-+			else if (*p != ecc_strength[i])
-+				*p = ecc_strength[i - 1];
-+			return;
-+		}
-+	}
-+
-+	*p = ecc_strength[ecc->caps->num_ecc_strength - 1];
-+}
-+EXPORT_SYMBOL(mtk_ecc_adjust_strength);
-+
-+unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
-+{
-+	return ecc->caps->parity_bits;
-+}
-+EXPORT_SYMBOL(mtk_ecc_get_parity_bits);
-+
-+static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
-+	.err_mask = 0x3f,
-+	.err_shift = 8,
-+	.ecc_strength = ecc_strength_mt2701,
-+	.ecc_regs = mt2701_ecc_regs,
-+	.num_ecc_strength = 20,
-+	.ecc_mode_shift = 5,
-+	.parity_bits = 14,
-+	.pg_irq_sel = 0,
-+};
-+
-+static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
-+	.err_mask = 0x7f,
-+	.err_shift = 8,
-+	.ecc_strength = ecc_strength_mt2712,
-+	.ecc_regs = mt2712_ecc_regs,
-+	.num_ecc_strength = 23,
-+	.ecc_mode_shift = 5,
-+	.parity_bits = 14,
-+	.pg_irq_sel = 1,
-+};
-+
-+static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
-+	.err_mask = 0x1f,
-+	.err_shift = 5,
-+	.ecc_strength = ecc_strength_mt7622,
-+	.ecc_regs = mt7622_ecc_regs,
-+	.num_ecc_strength = 5,
-+	.ecc_mode_shift = 4,
-+	.parity_bits = 13,
-+	.pg_irq_sel = 0,
-+};
-+
-+static const struct of_device_id mtk_ecc_dt_match[] = {
-+	{
-+		.compatible = "mediatek,mt2701-ecc",
-+		.data = &mtk_ecc_caps_mt2701,
-+	}, {
-+		.compatible = "mediatek,mt2712-ecc",
-+		.data = &mtk_ecc_caps_mt2712,
-+	}, {
-+		.compatible = "mediatek,mt7622-ecc",
-+		.data = &mtk_ecc_caps_mt7622,
-+	},
-+	{},
-+};
-+
-+static int mtk_ecc_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct mtk_ecc *ecc;
-+	struct resource *res;
-+	u32 max_eccdata_size;
-+	int irq, ret;
-+
-+	ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
-+	if (!ecc)
-+		return -ENOMEM;
-+
-+	ecc->caps = of_device_get_match_data(dev);
-+
-+	max_eccdata_size = ecc->caps->num_ecc_strength - 1;
-+	max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
-+	max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
-+	max_eccdata_size = round_up(max_eccdata_size, 4);
-+	ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
-+	if (!ecc->eccdata)
-+		return -ENOMEM;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	ecc->regs = devm_ioremap_resource(dev, res);
-+	if (IS_ERR(ecc->regs))
-+		return PTR_ERR(ecc->regs);
-+
-+	ecc->clk = devm_clk_get(dev, NULL);
-+	if (IS_ERR(ecc->clk)) {
-+		dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
-+		return PTR_ERR(ecc->clk);
-+	}
-+
-+	irq = platform_get_irq(pdev, 0);
-+	if (irq < 0)
-+		return irq;
-+
-+	ret = dma_set_mask(dev, DMA_BIT_MASK(32));
-+	if (ret) {
-+		dev_err(dev, "failed to set DMA mask\n");
-+		return ret;
-+	}
-+
-+	ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
-+	if (ret) {
-+		dev_err(dev, "failed to request irq\n");
-+		return -EINVAL;
-+	}
-+
-+	ecc->dev = dev;
-+	mutex_init(&ecc->lock);
-+	platform_set_drvdata(pdev, ecc);
-+	dev_info(dev, "probed\n");
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_PM_SLEEP
-+static int mtk_ecc_suspend(struct device *dev)
-+{
-+	struct mtk_ecc *ecc = dev_get_drvdata(dev);
-+
-+	clk_disable_unprepare(ecc->clk);
-+
-+	return 0;
-+}
-+
-+static int mtk_ecc_resume(struct device *dev)
-+{
-+	struct mtk_ecc *ecc = dev_get_drvdata(dev);
-+	int ret;
-+
-+	ret = clk_prepare_enable(ecc->clk);
-+	if (ret) {
-+		dev_err(dev, "failed to enable clk\n");
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);
-+#endif
-+
-+MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);
-+
-+static struct platform_driver mtk_ecc_driver = {
-+	.probe  = mtk_ecc_probe,
-+	.driver = {
-+		.name  = "mtk-ecc",
-+		.of_match_table = of_match_ptr(mtk_ecc_dt_match),
-+#ifdef CONFIG_PM_SLEEP
-+		.pm = &mtk_ecc_pm_ops,
-+#endif
-+	},
-+};
-+
-+module_platform_driver(mtk_ecc_driver);
-+
-+MODULE_AUTHOR("Xiaolei Li <[email protected]>");
-+MODULE_DESCRIPTION("MTK Nand ECC Driver");
-+MODULE_LICENSE("Dual MIT/GPL");
---- a/drivers/mtd/nand/raw/Kconfig
-+++ b/drivers/mtd/nand/raw/Kconfig
-@@ -360,6 +360,7 @@ config MTD_NAND_QCOM
- 
- config MTD_NAND_MTK
- 	tristate "MTK NAND controller"
-+	depends on MTD_NAND_ECC_MEDIATEK
- 	depends on ARCH_MEDIATEK || COMPILE_TEST
- 	depends on HAS_IOMEM
- 	help
---- a/drivers/mtd/nand/raw/Makefile
-+++ b/drivers/mtd/nand/raw/Makefile
-@@ -48,7 +48,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI)		+= sunxi_n
- obj-$(CONFIG_MTD_NAND_HISI504)	        += hisi504_nand.o
- obj-$(CONFIG_MTD_NAND_BRCMNAND)		+= brcmnand/
- obj-$(CONFIG_MTD_NAND_QCOM)		+= qcom_nandc.o
--obj-$(CONFIG_MTD_NAND_MTK)		+= mtk_ecc.o mtk_nand.o
-+obj-$(CONFIG_MTD_NAND_MTK)		+= mtk_nand.o
- obj-$(CONFIG_MTD_NAND_MXIC)		+= mxic_nand.o
- obj-$(CONFIG_MTD_NAND_TEGRA)		+= tegra_nand.o
- obj-$(CONFIG_MTD_NAND_STM32_FMC2)	+= stm32_fmc2_nand.o
---- a/drivers/mtd/nand/raw/mtk_nand.c
-+++ b/drivers/mtd/nand/raw/mtk_nand.c
-@@ -17,7 +17,7 @@
- #include <linux/iopoll.h>
- #include <linux/of.h>
- #include <linux/of_device.h>
--#include "mtk_ecc.h"
-+#include <linux/mtd/nand-ecc-mtk.h>
- 
- /* NAND controller register definition */
- #define NFI_CNFG		(0x00)
---- a/drivers/mtd/nand/raw/mtk_ecc.h
-+++ /dev/null
-@@ -1,47 +0,0 @@
--/* SPDX-License-Identifier: GPL-2.0 OR MIT */
--/*
-- * MTK SDG1 ECC controller
-- *
-- * Copyright (c) 2016 Mediatek
-- * Authors:	Xiaolei Li		<[email protected]>
-- *		Jorge Ramirez-Ortiz	<[email protected]>
-- */
--
--#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__
--#define __DRIVERS_MTD_NAND_MTK_ECC_H__
--
--#include <linux/types.h>
--
--enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1};
--enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE};
--
--struct device_node;
--struct mtk_ecc;
--
--struct mtk_ecc_stats {
--	u32 corrected;
--	u32 bitflips;
--	u32 failed;
--};
--
--struct mtk_ecc_config {
--	enum mtk_ecc_operation op;
--	enum mtk_ecc_mode mode;
--	dma_addr_t addr;
--	u32 strength;
--	u32 sectors;
--	u32 len;
--};
--
--int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32);
--void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int);
--int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation);
--int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);
--void mtk_ecc_disable(struct mtk_ecc *);
--void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p);
--unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc);
--
--struct mtk_ecc *of_mtk_ecc_get(struct device_node *);
--void mtk_ecc_release(struct mtk_ecc *);
--
--#endif
---- /dev/null
-+++ b/include/linux/mtd/nand-ecc-mtk.h
-@@ -0,0 +1,47 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/*
-+ * MTK SDG1 ECC controller
-+ *
-+ * Copyright (c) 2016 Mediatek
-+ * Authors:	Xiaolei Li		<[email protected]>
-+ *		Jorge Ramirez-Ortiz	<[email protected]>
-+ */
-+
-+#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__
-+#define __DRIVERS_MTD_NAND_MTK_ECC_H__
-+
-+#include <linux/types.h>
-+
-+enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1};
-+enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE};
-+
-+struct device_node;
-+struct mtk_ecc;
-+
-+struct mtk_ecc_stats {
-+	u32 corrected;
-+	u32 bitflips;
-+	u32 failed;
-+};
-+
-+struct mtk_ecc_config {
-+	enum mtk_ecc_operation op;
-+	enum mtk_ecc_mode mode;
-+	dma_addr_t addr;
-+	u32 strength;
-+	u32 sectors;
-+	u32 len;
-+};
-+
-+int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32);
-+void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int);
-+int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation);
-+int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);
-+void mtk_ecc_disable(struct mtk_ecc *);
-+void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p);
-+unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc);
-+
-+struct mtk_ecc *of_mtk_ecc_get(struct device_node *);
-+void mtk_ecc_release(struct mtk_ecc *);
-+
-+#endif

target/linux/mediatek/patches-5.15/120-12-v5.19-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch

@@ -1,1537 +0,0 @@
-From 8170bafa8936e9fbfdce992932a63bd20eca3bc3 Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <[email protected]>
-Date: Sat, 2 Apr 2022 10:16:11 +0800
-Subject: [PATCH v6 2/5] spi: add driver for MTK SPI NAND Flash Interface
-
-This driver implements support for the SPI-NAND mode of MTK NAND Flash
-Interface as a SPI-MEM controller with pipelined ECC capability.
-
-Signed-off-by: Chuanhong Guo <[email protected]>
-Tested-by: Daniel Golle <[email protected]>
----
-Change since v1:
-  fix CI warnings
-
-Changes since v2:
- use streamed DMA api to avoid an extra memory copy during read
- make ECC engine config a per-nand context
- take user-requested ECC strength into account
-
-Change since v3: none
-Changes since v4:
- fix missing OOB write
- print page format with dev_dbg
- replace uint*_t copied from vendor driver with u*
-
-Changes since v5:
- add missing nfi mode register configuration in probe
- fix an off-by-one bug in mtk_snand_mac_io
-
- drivers/spi/Kconfig        |   10 +
- drivers/spi/Makefile       |    1 +
- drivers/spi/spi-mtk-snfi.c | 1470 ++++++++++++++++++++++++++++++++++++
- 3 files changed, 1481 insertions(+)
- create mode 100644 drivers/spi/spi-mtk-snfi.c
-
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -529,6 +529,16 @@ config SPI_MTK_NOR
- 	  SPI interface as well as several SPI NOR specific instructions
- 	  via SPI MEM interface.
- 
-+config SPI_MTK_SNFI
-+	tristate "MediaTek SPI NAND Flash Interface"
-+	depends on ARCH_MEDIATEK || COMPILE_TEST
-+	depends on MTD_NAND_ECC_MEDIATEK
-+	help
-+	  This enables support for SPI-NAND mode on the MediaTek NAND
-+	  Flash Interface found on MediaTek ARM SoCs. This controller
-+	  is implemented as a SPI-MEM controller with pipelined ECC
-+	  capcability.
-+
- config SPI_NPCM_FIU
- 	tristate "Nuvoton NPCM FLASH Interface Unit"
- 	depends on ARCH_NPCM || COMPILE_TEST
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -71,6 +71,7 @@ obj-$(CONFIG_SPI_MPC52xx)		+= spi-mpc52x
- obj-$(CONFIG_SPI_MT65XX)                += spi-mt65xx.o
- obj-$(CONFIG_SPI_MT7621)		+= spi-mt7621.o
- obj-$(CONFIG_SPI_MTK_NOR)		+= spi-mtk-nor.o
-+obj-$(CONFIG_SPI_MTK_SNFI)		+= spi-mtk-snfi.o
- obj-$(CONFIG_SPI_MXIC)			+= spi-mxic.o
- obj-$(CONFIG_SPI_MXS)			+= spi-mxs.o
- obj-$(CONFIG_SPI_NPCM_FIU)		+= spi-npcm-fiu.o
---- /dev/null
-+++ b/drivers/spi/spi-mtk-snfi.c
-@@ -0,0 +1,1470 @@
-+// SPDX-License-Identifier: GPL-2.0
-+//
-+// Driver for the SPI-NAND mode of Mediatek NAND Flash Interface
-+//
-+// Copyright (c) 2022 Chuanhong Guo <[email protected]>
-+//
-+// This driver is based on the SPI-NAND mtd driver from Mediatek SDK:
-+//
-+// Copyright (C) 2020 MediaTek Inc.
-+// Author: Weijie Gao <[email protected]>
-+//
-+// This controller organize the page data as several interleaved sectors
-+// like the following: (sizeof(FDM + ECC) = snf->nfi_cfg.spare_size)
-+// +---------+------+------+---------+------+------+-----+
-+// | Sector1 | FDM1 | ECC1 | Sector2 | FDM2 | ECC2 | ... |
-+// +---------+------+------+---------+------+------+-----+
-+// With auto-format turned on, DMA only returns this part:
-+// +---------+---------+-----+
-+// | Sector1 | Sector2 | ... |
-+// +---------+---------+-----+
-+// The FDM data will be filled to the registers, and ECC parity data isn't
-+// accessible.
-+// With auto-format off, all ((Sector+FDM+ECC)*nsectors) will be read over DMA
-+// in it's original order shown in the first table. ECC can't be turned on when
-+// auto-format is off.
-+//
-+// However, Linux SPI-NAND driver expects the data returned as:
-+// +------+-----+
-+// | Page | OOB |
-+// +------+-----+
-+// where the page data is continuously stored instead of interleaved.
-+// So we assume all instructions matching the page_op template between ECC
-+// prepare_io_req and finish_io_req are for page cache r/w.
-+// Here's how this spi-mem driver operates when reading:
-+//  1. Always set snf->autofmt = true in prepare_io_req (even when ECC is off).
-+//  2. Perform page ops and let the controller fill the DMA bounce buffer with
-+//     de-interleaved sector data and set FDM registers.
-+//  3. Return the data as:
-+//     +---------+---------+-----+------+------+-----+
-+//     | Sector1 | Sector2 | ... | FDM1 | FDM2 | ... |
-+//     +---------+---------+-----+------+------+-----+
-+//  4. For other matching spi_mem ops outside a prepare/finish_io_req pair,
-+//     read the data with auto-format off into the bounce buffer and copy
-+//     needed data to the buffer specified in the request.
-+//
-+// Write requests operates in a similar manner.
-+// As a limitation of this strategy, we won't be able to access any ECC parity
-+// data at all in Linux.
-+//
-+// Here's the bad block mark situation on MTK chips:
-+// In older chips like mt7622, MTK uses the first FDM byte in the first sector
-+// as the bad block mark. After de-interleaving, this byte appears at [pagesize]
-+// in the returned data, which is the BBM position expected by kernel. However,
-+// the conventional bad block mark is the first byte of the OOB, which is part
-+// of the last sector data in the interleaved layout. Instead of fixing their
-+// hardware, MTK decided to address this inconsistency in software. On these
-+// later chips, the BootROM expects the following:
-+// 1. The [pagesize] byte on a nand page is used as BBM, which will appear at
-+//    (page_size - (nsectors - 1) * spare_size) in the DMA buffer.
-+// 2. The original byte stored at that position in the DMA buffer will be stored
-+//    as the first byte of the FDM section in the last sector.
-+// We can't disagree with the BootROM, so after de-interleaving, we need to
-+// perform the following swaps in read:
-+// 1. Store the BBM at [page_size - (nsectors - 1) * spare_size] to [page_size],
-+//    which is the expected BBM position by kernel.
-+// 2. Store the page data byte at [pagesize + (nsectors-1) * fdm] back to
-+//    [page_size - (nsectors - 1) * spare_size]
-+// Similarly, when writing, we need to perform swaps in the other direction.
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/mutex.h>
-+#include <linux/clk.h>
-+#include <linux/interrupt.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/iopoll.h>
-+#include <linux/of_platform.h>
-+#include <linux/mtd/nand-ecc-mtk.h>
-+#include <linux/spi/spi.h>
-+#include <linux/spi/spi-mem.h>
-+#include <linux/mtd/nand.h>
-+
-+// NFI registers
-+#define NFI_CNFG 0x000
-+#define CNFG_OP_MODE_S 12
-+#define CNFG_OP_MODE_CUST 6
-+#define CNFG_OP_MODE_PROGRAM 3
-+#define CNFG_AUTO_FMT_EN BIT(9)
-+#define CNFG_HW_ECC_EN BIT(8)
-+#define CNFG_DMA_BURST_EN BIT(2)
-+#define CNFG_READ_MODE BIT(1)
-+#define CNFG_DMA_MODE BIT(0)
-+
-+#define NFI_PAGEFMT 0x0004
-+#define NFI_SPARE_SIZE_LS_S 16
-+#define NFI_FDM_ECC_NUM_S 12
-+#define NFI_FDM_NUM_S 8
-+#define NFI_SPARE_SIZE_S 4
-+#define NFI_SEC_SEL_512 BIT(2)
-+#define NFI_PAGE_SIZE_S 0
-+#define NFI_PAGE_SIZE_512_2K 0
-+#define NFI_PAGE_SIZE_2K_4K 1
-+#define NFI_PAGE_SIZE_4K_8K 2
-+#define NFI_PAGE_SIZE_8K_16K 3
-+
-+#define NFI_CON 0x008
-+#define CON_SEC_NUM_S 12
-+#define CON_BWR BIT(9)
-+#define CON_BRD BIT(8)
-+#define CON_NFI_RST BIT(1)
-+#define CON_FIFO_FLUSH BIT(0)
-+
-+#define NFI_INTR_EN 0x010
-+#define NFI_INTR_STA 0x014
-+#define NFI_IRQ_INTR_EN BIT(31)
-+#define NFI_IRQ_CUS_READ BIT(8)
-+#define NFI_IRQ_CUS_PG BIT(7)
-+
-+#define NFI_CMD 0x020
-+#define NFI_CMD_DUMMY_READ 0x00
-+#define NFI_CMD_DUMMY_WRITE 0x80
-+
-+#define NFI_STRDATA 0x040
-+#define STR_DATA BIT(0)
-+
-+#define NFI_STA 0x060
-+#define NFI_NAND_FSM GENMASK(28, 24)
-+#define NFI_FSM GENMASK(19, 16)
-+#define READ_EMPTY BIT(12)
-+
-+#define NFI_FIFOSTA 0x064
-+#define FIFO_WR_REMAIN_S 8
-+#define FIFO_RD_REMAIN_S 0
-+
-+#define NFI_ADDRCNTR 0x070
-+#define SEC_CNTR GENMASK(16, 12)
-+#define SEC_CNTR_S 12
-+#define NFI_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S)
-+
-+#define NFI_STRADDR 0x080
-+
-+#define NFI_BYTELEN 0x084
-+#define BUS_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S)
-+
-+#define NFI_FDM0L 0x0a0
-+#define NFI_FDM0M 0x0a4
-+#define NFI_FDML(n) (NFI_FDM0L + (n)*8)
-+#define NFI_FDMM(n) (NFI_FDM0M + (n)*8)
-+
-+#define NFI_DEBUG_CON1 0x220
-+#define WBUF_EN BIT(2)
-+
-+#define NFI_MASTERSTA 0x224
-+#define MAS_ADDR GENMASK(11, 9)
-+#define MAS_RD GENMASK(8, 6)
-+#define MAS_WR GENMASK(5, 3)
-+#define MAS_RDDLY GENMASK(2, 0)
-+#define NFI_MASTERSTA_MASK_7622 (MAS_ADDR | MAS_RD | MAS_WR | MAS_RDDLY)
-+
-+// SNFI registers
-+#define SNF_MAC_CTL 0x500
-+#define MAC_XIO_SEL BIT(4)
-+#define SF_MAC_EN BIT(3)
-+#define SF_TRIG BIT(2)
-+#define WIP_READY BIT(1)
-+#define WIP BIT(0)
-+
-+#define SNF_MAC_OUTL 0x504
-+#define SNF_MAC_INL 0x508
-+
-+#define SNF_RD_CTL2 0x510
-+#define DATA_READ_DUMMY_S 8
-+#define DATA_READ_MAX_DUMMY 0xf
-+#define DATA_READ_CMD_S 0
-+
-+#define SNF_RD_CTL3 0x514
-+
-+#define SNF_PG_CTL1 0x524
-+#define PG_LOAD_CMD_S 8
-+
-+#define SNF_PG_CTL2 0x528
-+
-+#define SNF_MISC_CTL 0x538
-+#define SW_RST BIT(28)
-+#define FIFO_RD_LTC_S 25
-+#define PG_LOAD_X4_EN BIT(20)
-+#define DATA_READ_MODE_S 16
-+#define DATA_READ_MODE GENMASK(18, 16)
-+#define DATA_READ_MODE_X1 0
-+#define DATA_READ_MODE_X2 1
-+#define DATA_READ_MODE_X4 2
-+#define DATA_READ_MODE_DUAL 5
-+#define DATA_READ_MODE_QUAD 6
-+#define PG_LOAD_CUSTOM_EN BIT(7)
-+#define DATARD_CUSTOM_EN BIT(6)
-+#define CS_DESELECT_CYC_S 0
-+
-+#define SNF_MISC_CTL2 0x53c
-+#define PROGRAM_LOAD_BYTE_NUM_S 16
-+#define READ_DATA_BYTE_NUM_S 11
-+
-+#define SNF_DLY_CTL3 0x548
-+#define SFCK_SAM_DLY_S 0
-+
-+#define SNF_STA_CTL1 0x550
-+#define CUS_PG_DONE BIT(28)
-+#define CUS_READ_DONE BIT(27)
-+#define SPI_STATE_S 0
-+#define SPI_STATE GENMASK(3, 0)
-+
-+#define SNF_CFG 0x55c
-+#define SPI_MODE BIT(0)
-+
-+#define SNF_GPRAM 0x800
-+#define SNF_GPRAM_SIZE 0xa0
-+
-+#define SNFI_POLL_INTERVAL 1000000
-+
-+static const u8 mt7622_spare_sizes[] = { 16, 26, 27, 28 };
-+
-+struct mtk_snand_caps {
-+	u16 sector_size;
-+	u16 max_sectors;
-+	u16 fdm_size;
-+	u16 fdm_ecc_size;
-+	u16 fifo_size;
-+
-+	bool bbm_swap;
-+	bool empty_page_check;
-+	u32 mastersta_mask;
-+
-+	const u8 *spare_sizes;
-+	u32 num_spare_size;
-+};
-+
-+static const struct mtk_snand_caps mt7622_snand_caps = {
-+	.sector_size = 512,
-+	.max_sectors = 8,
-+	.fdm_size = 8,
-+	.fdm_ecc_size = 1,
-+	.fifo_size = 32,
-+	.bbm_swap = false,
-+	.empty_page_check = false,
-+	.mastersta_mask = NFI_MASTERSTA_MASK_7622,
-+	.spare_sizes = mt7622_spare_sizes,
-+	.num_spare_size = ARRAY_SIZE(mt7622_spare_sizes)
-+};
-+
-+static const struct mtk_snand_caps mt7629_snand_caps = {
-+	.sector_size = 512,
-+	.max_sectors = 8,
-+	.fdm_size = 8,
-+	.fdm_ecc_size = 1,
-+	.fifo_size = 32,
-+	.bbm_swap = true,
-+	.empty_page_check = false,
-+	.mastersta_mask = NFI_MASTERSTA_MASK_7622,
-+	.spare_sizes = mt7622_spare_sizes,
-+	.num_spare_size = ARRAY_SIZE(mt7622_spare_sizes)
-+};
-+
-+struct mtk_snand_conf {
-+	size_t page_size;
-+	size_t oob_size;
-+	u8 nsectors;
-+	u8 spare_size;
-+};
-+
-+struct mtk_snand {
-+	struct spi_controller *ctlr;
-+	struct device *dev;
-+	struct clk *nfi_clk;
-+	struct clk *pad_clk;
-+	void __iomem *nfi_base;
-+	int irq;
-+	struct completion op_done;
-+	const struct mtk_snand_caps *caps;
-+	struct mtk_ecc_config *ecc_cfg;
-+	struct mtk_ecc *ecc;
-+	struct mtk_snand_conf nfi_cfg;
-+	struct mtk_ecc_stats ecc_stats;
-+	struct nand_ecc_engine ecc_eng;
-+	bool autofmt;
-+	u8 *buf;
-+	size_t buf_len;
-+};
-+
-+static struct mtk_snand *nand_to_mtk_snand(struct nand_device *nand)
-+{
-+	struct nand_ecc_engine *eng = nand->ecc.engine;
-+
-+	return container_of(eng, struct mtk_snand, ecc_eng);
-+}
-+
-+static inline int snand_prepare_bouncebuf(struct mtk_snand *snf, size_t size)
-+{
-+	if (snf->buf_len >= size)
-+		return 0;
-+	kfree(snf->buf);
-+	snf->buf = kmalloc(size, GFP_KERNEL);
-+	if (!snf->buf)
-+		return -ENOMEM;
-+	snf->buf_len = size;
-+	memset(snf->buf, 0xff, snf->buf_len);
-+	return 0;
-+}
-+
-+static inline u32 nfi_read32(struct mtk_snand *snf, u32 reg)
-+{
-+	return readl(snf->nfi_base + reg);
-+}
-+
-+static inline void nfi_write32(struct mtk_snand *snf, u32 reg, u32 val)
-+{
-+	writel(val, snf->nfi_base + reg);
-+}
-+
-+static inline void nfi_write16(struct mtk_snand *snf, u32 reg, u16 val)
-+{
-+	writew(val, snf->nfi_base + reg);
-+}
-+
-+static inline void nfi_rmw32(struct mtk_snand *snf, u32 reg, u32 clr, u32 set)
-+{
-+	u32 val;
-+
-+	val = readl(snf->nfi_base + reg);
-+	val &= ~clr;
-+	val |= set;
-+	writel(val, snf->nfi_base + reg);
-+}
-+
-+static void nfi_read_data(struct mtk_snand *snf, u32 reg, u8 *data, u32 len)
-+{
-+	u32 i, val = 0, es = sizeof(u32);
-+
-+	for (i = reg; i < reg + len; i++) {
-+		if (i == reg || i % es == 0)
-+			val = nfi_read32(snf, i & ~(es - 1));
-+
-+		*data++ = (u8)(val >> (8 * (i % es)));
-+	}
-+}
-+
-+static int mtk_nfi_reset(struct mtk_snand *snf)
-+{
-+	u32 val, fifo_mask;
-+	int ret;
-+
-+	nfi_write32(snf, NFI_CON, CON_FIFO_FLUSH | CON_NFI_RST);
-+
-+	ret = readw_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val,
-+				 !(val & snf->caps->mastersta_mask), 0,
-+				 SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "NFI master is still busy after reset\n");
-+		return ret;
-+	}
-+
-+	ret = readl_poll_timeout(snf->nfi_base + NFI_STA, val,
-+				 !(val & (NFI_FSM | NFI_NAND_FSM)), 0,
-+				 SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "Failed to reset NFI\n");
-+		return ret;
-+	}
-+
-+	fifo_mask = ((snf->caps->fifo_size - 1) << FIFO_RD_REMAIN_S) |
-+		    ((snf->caps->fifo_size - 1) << FIFO_WR_REMAIN_S);
-+	ret = readw_poll_timeout(snf->nfi_base + NFI_FIFOSTA, val,
-+				 !(val & fifo_mask), 0, SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "NFI FIFOs are not empty\n");
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_snand_mac_reset(struct mtk_snand *snf)
-+{
-+	int ret;
-+	u32 val;
-+
-+	nfi_rmw32(snf, SNF_MISC_CTL, 0, SW_RST);
-+
-+	ret = readl_poll_timeout(snf->nfi_base + SNF_STA_CTL1, val,
-+				 !(val & SPI_STATE), 0, SNFI_POLL_INTERVAL);
-+	if (ret)
-+		dev_err(snf->dev, "Failed to reset SNFI MAC\n");
-+
-+	nfi_write32(snf, SNF_MISC_CTL,
-+		    (2 << FIFO_RD_LTC_S) | (10 << CS_DESELECT_CYC_S));
-+
-+	return ret;
-+}
-+
-+static int mtk_snand_mac_trigger(struct mtk_snand *snf, u32 outlen, u32 inlen)
-+{
-+	int ret;
-+	u32 val;
-+
-+	nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN);
-+	nfi_write32(snf, SNF_MAC_OUTL, outlen);
-+	nfi_write32(snf, SNF_MAC_INL, inlen);
-+
-+	nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN | SF_TRIG);
-+
-+	ret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val,
-+				 val & WIP_READY, 0, SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "Timed out waiting for WIP_READY\n");
-+		goto cleanup;
-+	}
-+
-+	ret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val, !(val & WIP),
-+				 0, SNFI_POLL_INTERVAL);
-+	if (ret)
-+		dev_err(snf->dev, "Timed out waiting for WIP cleared\n");
-+
-+cleanup:
-+	nfi_write32(snf, SNF_MAC_CTL, 0);
-+
-+	return ret;
-+}
-+
-+static int mtk_snand_mac_io(struct mtk_snand *snf, const struct spi_mem_op *op)
-+{
-+	u32 rx_len = 0;
-+	u32 reg_offs = 0;
-+	u32 val = 0;
-+	const u8 *tx_buf = NULL;
-+	u8 *rx_buf = NULL;
-+	int i, ret;
-+	u8 b;
-+
-+	if (op->data.dir == SPI_MEM_DATA_IN) {
-+		rx_len = op->data.nbytes;
-+		rx_buf = op->data.buf.in;
-+	} else {
-+		tx_buf = op->data.buf.out;
-+	}
-+
-+	mtk_snand_mac_reset(snf);
-+
-+	for (i = 0; i < op->cmd.nbytes; i++, reg_offs++) {
-+		b = (op->cmd.opcode >> ((op->cmd.nbytes - i - 1) * 8)) & 0xff;
-+		val |= b << (8 * (reg_offs % 4));
-+		if (reg_offs % 4 == 3) {
-+			nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);
-+			val = 0;
-+		}
-+	}
-+
-+	for (i = 0; i < op->addr.nbytes; i++, reg_offs++) {
-+		b = (op->addr.val >> ((op->addr.nbytes - i - 1) * 8)) & 0xff;
-+		val |= b << (8 * (reg_offs % 4));
-+		if (reg_offs % 4 == 3) {
-+			nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);
-+			val = 0;
-+		}
-+	}
-+
-+	for (i = 0; i < op->dummy.nbytes; i++, reg_offs++) {
-+		if (reg_offs % 4 == 3) {
-+			nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);
-+			val = 0;
-+		}
-+	}
-+
-+	if (op->data.dir == SPI_MEM_DATA_OUT) {
-+		for (i = 0; i < op->data.nbytes; i++, reg_offs++) {
-+			val |= tx_buf[i] << (8 * (reg_offs % 4));
-+			if (reg_offs % 4 == 3) {
-+				nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);
-+				val = 0;
-+			}
-+		}
-+	}
-+
-+	if (reg_offs % 4)
-+		nfi_write32(snf, SNF_GPRAM + (reg_offs & ~3), val);
-+
-+	for (i = 0; i < reg_offs; i += 4)
-+		dev_dbg(snf->dev, "%d: %08X", i,
-+			nfi_read32(snf, SNF_GPRAM + i));
-+
-+	dev_dbg(snf->dev, "SNF TX: %u RX: %u", reg_offs, rx_len);
-+
-+	ret = mtk_snand_mac_trigger(snf, reg_offs, rx_len);
-+	if (ret)
-+		return ret;
-+
-+	if (!rx_len)
-+		return 0;
-+
-+	nfi_read_data(snf, SNF_GPRAM + reg_offs, rx_buf, rx_len);
-+	return 0;
-+}
-+
-+static int mtk_snand_setup_pagefmt(struct mtk_snand *snf, u32 page_size,
-+				   u32 oob_size)
-+{
-+	int spare_idx = -1;
-+	u32 spare_size, spare_size_shift, pagesize_idx;
-+	u32 sector_size_512;
-+	u8 nsectors;
-+	int i;
-+
-+	// skip if it's already configured as required.
-+	if (snf->nfi_cfg.page_size == page_size &&
-+	    snf->nfi_cfg.oob_size == oob_size)
-+		return 0;
-+
-+	nsectors = page_size / snf->caps->sector_size;
-+	if (nsectors > snf->caps->max_sectors) {
-+		dev_err(snf->dev, "too many sectors required.\n");
-+		goto err;
-+	}
-+
-+	if (snf->caps->sector_size == 512) {
-+		sector_size_512 = NFI_SEC_SEL_512;
-+		spare_size_shift = NFI_SPARE_SIZE_S;
-+	} else {
-+		sector_size_512 = 0;
-+		spare_size_shift = NFI_SPARE_SIZE_LS_S;
-+	}
-+
-+	switch (page_size) {
-+	case SZ_512:
-+		pagesize_idx = NFI_PAGE_SIZE_512_2K;
-+		break;
-+	case SZ_2K:
-+		if (snf->caps->sector_size == 512)
-+			pagesize_idx = NFI_PAGE_SIZE_2K_4K;
-+		else
-+			pagesize_idx = NFI_PAGE_SIZE_512_2K;
-+		break;
-+	case SZ_4K:
-+		if (snf->caps->sector_size == 512)
-+			pagesize_idx = NFI_PAGE_SIZE_4K_8K;
-+		else
-+			pagesize_idx = NFI_PAGE_SIZE_2K_4K;
-+		break;
-+	case SZ_8K:
-+		if (snf->caps->sector_size == 512)
-+			pagesize_idx = NFI_PAGE_SIZE_8K_16K;
-+		else
-+			pagesize_idx = NFI_PAGE_SIZE_4K_8K;
-+		break;
-+	case SZ_16K:
-+		pagesize_idx = NFI_PAGE_SIZE_8K_16K;
-+		break;
-+	default:
-+		dev_err(snf->dev, "unsupported page size.\n");
-+		goto err;
-+	}
-+
-+	spare_size = oob_size / nsectors;
-+	// If we're using the 1KB sector size, HW will automatically double the
-+	// spare size. We should only use half of the value in this case.
-+	if (snf->caps->sector_size == 1024)
-+		spare_size /= 2;
-+
-+	for (i = snf->caps->num_spare_size - 1; i >= 0; i--) {
-+		if (snf->caps->spare_sizes[i] <= spare_size) {
-+			spare_size = snf->caps->spare_sizes[i];
-+			if (snf->caps->sector_size == 1024)
-+				spare_size *= 2;
-+			spare_idx = i;
-+			break;
-+		}
-+	}
-+
-+	if (spare_idx < 0) {
-+		dev_err(snf->dev, "unsupported spare size: %u\n", spare_size);
-+		goto err;
-+	}
-+
-+	nfi_write32(snf, NFI_PAGEFMT,
-+		    (snf->caps->fdm_ecc_size << NFI_FDM_ECC_NUM_S) |
-+			    (snf->caps->fdm_size << NFI_FDM_NUM_S) |
-+			    (spare_idx << spare_size_shift) |
-+			    (pagesize_idx << NFI_PAGE_SIZE_S) |
-+			    sector_size_512);
-+
-+	snf->nfi_cfg.page_size = page_size;
-+	snf->nfi_cfg.oob_size = oob_size;
-+	snf->nfi_cfg.nsectors = nsectors;
-+	snf->nfi_cfg.spare_size = spare_size;
-+
-+	dev_dbg(snf->dev, "page format: (%u + %u) * %u\n",
-+		snf->caps->sector_size, spare_size, nsectors);
-+	return snand_prepare_bouncebuf(snf, page_size + oob_size);
-+err:
-+	dev_err(snf->dev, "page size %u + %u is not supported\n", page_size,
-+		oob_size);
-+	return -EOPNOTSUPP;
-+}
-+
-+static int mtk_snand_ooblayout_ecc(struct mtd_info *mtd, int section,
-+				   struct mtd_oob_region *oobecc)
-+{
-+	// ECC area is not accessible
-+	return -ERANGE;
-+}
-+
-+static int mtk_snand_ooblayout_free(struct mtd_info *mtd, int section,
-+				    struct mtd_oob_region *oobfree)
-+{
-+	struct nand_device *nand = mtd_to_nanddev(mtd);
-+	struct mtk_snand *ms = nand_to_mtk_snand(nand);
-+
-+	if (section >= ms->nfi_cfg.nsectors)
-+		return -ERANGE;
-+
-+	oobfree->length = ms->caps->fdm_size - 1;
-+	oobfree->offset = section * ms->caps->fdm_size + 1;
-+	return 0;
-+}
-+
-+static const struct mtd_ooblayout_ops mtk_snand_ooblayout = {
-+	.ecc = mtk_snand_ooblayout_ecc,
-+	.free = mtk_snand_ooblayout_free,
-+};
-+
-+static int mtk_snand_ecc_init_ctx(struct nand_device *nand)
-+{
-+	struct mtk_snand *snf = nand_to_mtk_snand(nand);
-+	struct nand_ecc_props *conf = &nand->ecc.ctx.conf;
-+	struct nand_ecc_props *reqs = &nand->ecc.requirements;
-+	struct nand_ecc_props *user = &nand->ecc.user_conf;
-+	struct mtd_info *mtd = nanddev_to_mtd(nand);
-+	int step_size = 0, strength = 0, desired_correction = 0, steps;
-+	bool ecc_user = false;
-+	int ret;
-+	u32 parity_bits, max_ecc_bytes;
-+	struct mtk_ecc_config *ecc_cfg;
-+
-+	ret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize,
-+				      nand->memorg.oobsize);
-+	if (ret)
-+		return ret;
-+
-+	ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL);
-+	if (!ecc_cfg)
-+		return -ENOMEM;
-+
-+	nand->ecc.ctx.priv = ecc_cfg;
-+
-+	if (user->step_size && user->strength) {
-+		step_size = user->step_size;
-+		strength = user->strength;
-+		ecc_user = true;
-+	} else if (reqs->step_size && reqs->strength) {
-+		step_size = reqs->step_size;
-+		strength = reqs->strength;
-+	}
-+
-+	if (step_size && strength) {
-+		steps = mtd->writesize / step_size;
-+		desired_correction = steps * strength;
-+		strength = desired_correction / snf->nfi_cfg.nsectors;
-+	}
-+
-+	ecc_cfg->mode = ECC_NFI_MODE;
-+	ecc_cfg->sectors = snf->nfi_cfg.nsectors;
-+	ecc_cfg->len = snf->caps->sector_size + snf->caps->fdm_ecc_size;
-+
-+	// calculate the max possible strength under current page format
-+	parity_bits = mtk_ecc_get_parity_bits(snf->ecc);
-+	max_ecc_bytes = snf->nfi_cfg.spare_size - snf->caps->fdm_size;
-+	ecc_cfg->strength = max_ecc_bytes * 8 / parity_bits;
-+	mtk_ecc_adjust_strength(snf->ecc, &ecc_cfg->strength);
-+
-+	// if there's a user requested strength, find the minimum strength that
-+	// meets the requirement. Otherwise use the maximum strength which is
-+	// expected by BootROM.
-+	if (ecc_user && strength) {
-+		u32 s_next = ecc_cfg->strength - 1;
-+
-+		while (1) {
-+			mtk_ecc_adjust_strength(snf->ecc, &s_next);
-+			if (s_next >= ecc_cfg->strength)
-+				break;
-+			if (s_next < strength)
-+				break;
-+			s_next = ecc_cfg->strength - 1;
-+		}
-+	}
-+
-+	mtd_set_ooblayout(mtd, &mtk_snand_ooblayout);
-+
-+	conf->step_size = snf->caps->sector_size;
-+	conf->strength = ecc_cfg->strength;
-+
-+	if (ecc_cfg->strength < strength)
-+		dev_warn(snf->dev, "unable to fulfill ECC of %u bits.\n",
-+			 strength);
-+	dev_info(snf->dev, "ECC strength: %u bits per %u bytes\n",
-+		 ecc_cfg->strength, snf->caps->sector_size);
-+
-+	return 0;
-+}
-+
-+static void mtk_snand_ecc_cleanup_ctx(struct nand_device *nand)
-+{
-+	struct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand);
-+
-+	kfree(ecc_cfg);
-+}
-+
-+static int mtk_snand_ecc_prepare_io_req(struct nand_device *nand,
-+					struct nand_page_io_req *req)
-+{
-+	struct mtk_snand *snf = nand_to_mtk_snand(nand);
-+	struct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand);
-+	int ret;
-+
-+	ret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize,
-+				      nand->memorg.oobsize);
-+	if (ret)
-+		return ret;
-+	snf->autofmt = true;
-+	snf->ecc_cfg = ecc_cfg;
-+	return 0;
-+}
-+
-+static int mtk_snand_ecc_finish_io_req(struct nand_device *nand,
-+				       struct nand_page_io_req *req)
-+{
-+	struct mtk_snand *snf = nand_to_mtk_snand(nand);
-+	struct mtd_info *mtd = nanddev_to_mtd(nand);
-+
-+	snf->ecc_cfg = NULL;
-+	snf->autofmt = false;
-+	if ((req->mode == MTD_OPS_RAW) || (req->type != NAND_PAGE_READ))
-+		return 0;
-+
-+	if (snf->ecc_stats.failed)
-+		mtd->ecc_stats.failed += snf->ecc_stats.failed;
-+	mtd->ecc_stats.corrected += snf->ecc_stats.corrected;
-+	return snf->ecc_stats.failed ? -EBADMSG : snf->ecc_stats.bitflips;
-+}
-+
-+static struct nand_ecc_engine_ops mtk_snfi_ecc_engine_ops = {
-+	.init_ctx = mtk_snand_ecc_init_ctx,
-+	.cleanup_ctx = mtk_snand_ecc_cleanup_ctx,
-+	.prepare_io_req = mtk_snand_ecc_prepare_io_req,
-+	.finish_io_req = mtk_snand_ecc_finish_io_req,
-+};
-+
-+static void mtk_snand_read_fdm(struct mtk_snand *snf, u8 *buf)
-+{
-+	u32 vall, valm;
-+	u8 *oobptr = buf;
-+	int i, j;
-+
-+	for (i = 0; i < snf->nfi_cfg.nsectors; i++) {
-+		vall = nfi_read32(snf, NFI_FDML(i));
-+		valm = nfi_read32(snf, NFI_FDMM(i));
-+
-+		for (j = 0; j < snf->caps->fdm_size; j++)
-+			oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8);
-+
-+		oobptr += snf->caps->fdm_size;
-+	}
-+}
-+
-+static void mtk_snand_write_fdm(struct mtk_snand *snf, const u8 *buf)
-+{
-+	u32 fdm_size = snf->caps->fdm_size;
-+	const u8 *oobptr = buf;
-+	u32 vall, valm;
-+	int i, j;
-+
-+	for (i = 0; i < snf->nfi_cfg.nsectors; i++) {
-+		vall = 0;
-+		valm = 0;
-+
-+		for (j = 0; j < 8; j++) {
-+			if (j < 4)
-+				vall |= (j < fdm_size ? oobptr[j] : 0xff)
-+					<< (j * 8);
-+			else
-+				valm |= (j < fdm_size ? oobptr[j] : 0xff)
-+					<< ((j - 4) * 8);
-+		}
-+
-+		nfi_write32(snf, NFI_FDML(i), vall);
-+		nfi_write32(snf, NFI_FDMM(i), valm);
-+
-+		oobptr += fdm_size;
-+	}
-+}
-+
-+static void mtk_snand_bm_swap(struct mtk_snand *snf, u8 *buf)
-+{
-+	u32 buf_bbm_pos, fdm_bbm_pos;
-+
-+	if (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1)
-+		return;
-+
-+	// swap [pagesize] byte on nand with the first fdm byte
-+	// in the last sector.
-+	buf_bbm_pos = snf->nfi_cfg.page_size -
-+		      (snf->nfi_cfg.nsectors - 1) * snf->nfi_cfg.spare_size;
-+	fdm_bbm_pos = snf->nfi_cfg.page_size +
-+		      (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size;
-+
-+	swap(snf->buf[fdm_bbm_pos], buf[buf_bbm_pos]);
-+}
-+
-+static void mtk_snand_fdm_bm_swap(struct mtk_snand *snf)
-+{
-+	u32 fdm_bbm_pos1, fdm_bbm_pos2;
-+
-+	if (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1)
-+		return;
-+
-+	// swap the first fdm byte in the first and the last sector.
-+	fdm_bbm_pos1 = snf->nfi_cfg.page_size;
-+	fdm_bbm_pos2 = snf->nfi_cfg.page_size +
-+		       (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size;
-+	swap(snf->buf[fdm_bbm_pos1], snf->buf[fdm_bbm_pos2]);
-+}
-+
-+static int mtk_snand_read_page_cache(struct mtk_snand *snf,
-+				     const struct spi_mem_op *op)
-+{
-+	u8 *buf = snf->buf;
-+	u8 *buf_fdm = buf + snf->nfi_cfg.page_size;
-+	// the address part to be sent by the controller
-+	u32 op_addr = op->addr.val;
-+	// where to start copying data from bounce buffer
-+	u32 rd_offset = 0;
-+	u32 dummy_clk = (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth);
-+	u32 op_mode = 0;
-+	u32 dma_len = snf->buf_len;
-+	int ret = 0;
-+	u32 rd_mode, rd_bytes, val;
-+	dma_addr_t buf_dma;
-+
-+	if (snf->autofmt) {
-+		u32 last_bit;
-+		u32 mask;
-+
-+		dma_len = snf->nfi_cfg.page_size;
-+		op_mode = CNFG_AUTO_FMT_EN;
-+		if (op->data.ecc)
-+			op_mode |= CNFG_HW_ECC_EN;
-+		// extract the plane bit:
-+		// Find the highest bit set in (pagesize+oobsize).
-+		// Bits higher than that in op->addr are kept and sent over SPI
-+		// Lower bits are used as an offset for copying data from DMA
-+		// bounce buffer.
-+		last_bit = fls(snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size);
-+		mask = (1 << last_bit) - 1;
-+		rd_offset = op_addr & mask;
-+		op_addr &= ~mask;
-+
-+		// check if we can dma to the caller memory
-+		if (rd_offset == 0 && op->data.nbytes >= snf->nfi_cfg.page_size)
-+			buf = op->data.buf.in;
-+	}
-+	mtk_snand_mac_reset(snf);
-+	mtk_nfi_reset(snf);
-+
-+	// command and dummy cycles
-+	nfi_write32(snf, SNF_RD_CTL2,
-+		    (dummy_clk << DATA_READ_DUMMY_S) |
-+			    (op->cmd.opcode << DATA_READ_CMD_S));
-+
-+	// read address
-+	nfi_write32(snf, SNF_RD_CTL3, op_addr);
-+
-+	// Set read op_mode
-+	if (op->data.buswidth == 4)
-+		rd_mode = op->addr.buswidth == 4 ? DATA_READ_MODE_QUAD :
-+						   DATA_READ_MODE_X4;
-+	else if (op->data.buswidth == 2)
-+		rd_mode = op->addr.buswidth == 2 ? DATA_READ_MODE_DUAL :
-+						   DATA_READ_MODE_X2;
-+	else
-+		rd_mode = DATA_READ_MODE_X1;
-+	rd_mode <<= DATA_READ_MODE_S;
-+	nfi_rmw32(snf, SNF_MISC_CTL, DATA_READ_MODE,
-+		  rd_mode | DATARD_CUSTOM_EN);
-+
-+	// Set bytes to read
-+	rd_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) *
-+		   snf->nfi_cfg.nsectors;
-+	nfi_write32(snf, SNF_MISC_CTL2,
-+		    (rd_bytes << PROGRAM_LOAD_BYTE_NUM_S) | rd_bytes);
-+
-+	// NFI read prepare
-+	nfi_write16(snf, NFI_CNFG,
-+		    (CNFG_OP_MODE_CUST << CNFG_OP_MODE_S) | CNFG_DMA_BURST_EN |
-+			    CNFG_READ_MODE | CNFG_DMA_MODE | op_mode);
-+
-+	nfi_write32(snf, NFI_CON, (snf->nfi_cfg.nsectors << CON_SEC_NUM_S));
-+
-+	buf_dma = dma_map_single(snf->dev, buf, dma_len, DMA_FROM_DEVICE);
-+	if (dma_mapping_error(snf->dev, buf_dma)) {
-+		dev_err(snf->dev, "DMA mapping failed.\n");
-+		goto cleanup;
-+	}
-+	nfi_write32(snf, NFI_STRADDR, buf_dma);
-+	if (op->data.ecc) {
-+		snf->ecc_cfg->op = ECC_DECODE;
-+		ret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg);
-+		if (ret)
-+			goto cleanup_dma;
-+	}
-+	// Prepare for custom read interrupt
-+	nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_READ);
-+	reinit_completion(&snf->op_done);
-+
-+	// Trigger NFI into custom mode
-+	nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_READ);
-+
-+	// Start DMA read
-+	nfi_rmw32(snf, NFI_CON, 0, CON_BRD);
-+	nfi_write16(snf, NFI_STRDATA, STR_DATA);
-+
-+	if (!wait_for_completion_timeout(
-+		    &snf->op_done, usecs_to_jiffies(SNFI_POLL_INTERVAL))) {
-+		dev_err(snf->dev, "DMA timed out for reading from cache.\n");
-+		ret = -ETIMEDOUT;
-+		goto cleanup;
-+	}
-+
-+	// Wait for BUS_SEC_CNTR returning expected value
-+	ret = readl_poll_timeout(snf->nfi_base + NFI_BYTELEN, val,
-+				 BUS_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0,
-+				 SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "Timed out waiting for BUS_SEC_CNTR\n");
-+		goto cleanup2;
-+	}
-+
-+	// Wait for bus becoming idle
-+	ret = readl_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val,
-+				 !(val & snf->caps->mastersta_mask), 0,
-+				 SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "Timed out waiting for bus becoming idle\n");
-+		goto cleanup2;
-+	}
-+
-+	if (op->data.ecc) {
-+		ret = mtk_ecc_wait_done(snf->ecc, ECC_DECODE);
-+		if (ret) {
-+			dev_err(snf->dev, "wait ecc done timeout\n");
-+			goto cleanup2;
-+		}
-+		// save status before disabling ecc
-+		mtk_ecc_get_stats(snf->ecc, &snf->ecc_stats,
-+				  snf->nfi_cfg.nsectors);
-+	}
-+
-+	dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE);
-+
-+	if (snf->autofmt) {
-+		mtk_snand_read_fdm(snf, buf_fdm);
-+		if (snf->caps->bbm_swap) {
-+			mtk_snand_bm_swap(snf, buf);
-+			mtk_snand_fdm_bm_swap(snf);
-+		}
-+	}
-+
-+	// copy data back
-+	if (nfi_read32(snf, NFI_STA) & READ_EMPTY) {
-+		memset(op->data.buf.in, 0xff, op->data.nbytes);
-+		snf->ecc_stats.bitflips = 0;
-+		snf->ecc_stats.failed = 0;
-+		snf->ecc_stats.corrected = 0;
-+	} else {
-+		if (buf == op->data.buf.in) {
-+			u32 cap_len = snf->buf_len - snf->nfi_cfg.page_size;
-+			u32 req_left = op->data.nbytes - snf->nfi_cfg.page_size;
-+
-+			if (req_left)
-+				memcpy(op->data.buf.in + snf->nfi_cfg.page_size,
-+				       buf_fdm,
-+				       cap_len < req_left ? cap_len : req_left);
-+		} else if (rd_offset < snf->buf_len) {
-+			u32 cap_len = snf->buf_len - rd_offset;
-+
-+			if (op->data.nbytes < cap_len)
-+				cap_len = op->data.nbytes;
-+			memcpy(op->data.buf.in, snf->buf + rd_offset, cap_len);
-+		}
-+	}
-+cleanup2:
-+	if (op->data.ecc)
-+		mtk_ecc_disable(snf->ecc);
-+cleanup_dma:
-+	// unmap dma only if any error happens. (otherwise it's done before
-+	// data copying)
-+	if (ret)
-+		dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE);
-+cleanup:
-+	// Stop read
-+	nfi_write32(snf, NFI_CON, 0);
-+	nfi_write16(snf, NFI_CNFG, 0);
-+
-+	// Clear SNF done flag
-+	nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_READ_DONE);
-+	nfi_write32(snf, SNF_STA_CTL1, 0);
-+
-+	// Disable interrupt
-+	nfi_read32(snf, NFI_INTR_STA);
-+	nfi_write32(snf, NFI_INTR_EN, 0);
-+
-+	nfi_rmw32(snf, SNF_MISC_CTL, DATARD_CUSTOM_EN, 0);
-+	return ret;
-+}
-+
-+static int mtk_snand_write_page_cache(struct mtk_snand *snf,
-+				      const struct spi_mem_op *op)
-+{
-+	// the address part to be sent by the controller
-+	u32 op_addr = op->addr.val;
-+	// where to start copying data from bounce buffer
-+	u32 wr_offset = 0;
-+	u32 op_mode = 0;
-+	int ret = 0;
-+	u32 wr_mode = 0;
-+	u32 dma_len = snf->buf_len;
-+	u32 wr_bytes, val;
-+	size_t cap_len;
-+	dma_addr_t buf_dma;
-+
-+	if (snf->autofmt) {
-+		u32 last_bit;
-+		u32 mask;
-+
-+		dma_len = snf->nfi_cfg.page_size;
-+		op_mode = CNFG_AUTO_FMT_EN;
-+		if (op->data.ecc)
-+			op_mode |= CNFG_HW_ECC_EN;
-+
-+		last_bit = fls(snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size);
-+		mask = (1 << last_bit) - 1;
-+		wr_offset = op_addr & mask;
-+		op_addr &= ~mask;
-+	}
-+	mtk_snand_mac_reset(snf);
-+	mtk_nfi_reset(snf);
-+
-+	if (wr_offset)
-+		memset(snf->buf, 0xff, wr_offset);
-+
-+	cap_len = snf->buf_len - wr_offset;
-+	if (op->data.nbytes < cap_len)
-+		cap_len = op->data.nbytes;
-+	memcpy(snf->buf + wr_offset, op->data.buf.out, cap_len);
-+	if (snf->autofmt) {
-+		if (snf->caps->bbm_swap) {
-+			mtk_snand_fdm_bm_swap(snf);
-+			mtk_snand_bm_swap(snf, snf->buf);
-+		}
-+		mtk_snand_write_fdm(snf, snf->buf + snf->nfi_cfg.page_size);
-+	}
-+
-+	// Command
-+	nfi_write32(snf, SNF_PG_CTL1, (op->cmd.opcode << PG_LOAD_CMD_S));
-+
-+	// write address
-+	nfi_write32(snf, SNF_PG_CTL2, op_addr);
-+
-+	// Set read op_mode
-+	if (op->data.buswidth == 4)
-+		wr_mode = PG_LOAD_X4_EN;
-+
-+	nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_X4_EN,
-+		  wr_mode | PG_LOAD_CUSTOM_EN);
-+
-+	// Set bytes to write
-+	wr_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) *
-+		   snf->nfi_cfg.nsectors;
-+	nfi_write32(snf, SNF_MISC_CTL2,
-+		    (wr_bytes << PROGRAM_LOAD_BYTE_NUM_S) | wr_bytes);
-+
-+	// NFI write prepare
-+	nfi_write16(snf, NFI_CNFG,
-+		    (CNFG_OP_MODE_PROGRAM << CNFG_OP_MODE_S) |
-+			    CNFG_DMA_BURST_EN | CNFG_DMA_MODE | op_mode);
-+
-+	nfi_write32(snf, NFI_CON, (snf->nfi_cfg.nsectors << CON_SEC_NUM_S));
-+	buf_dma = dma_map_single(snf->dev, snf->buf, dma_len, DMA_TO_DEVICE);
-+	if (dma_mapping_error(snf->dev, buf_dma)) {
-+		dev_err(snf->dev, "DMA mapping failed.\n");
-+		goto cleanup;
-+	}
-+	nfi_write32(snf, NFI_STRADDR, buf_dma);
-+	if (op->data.ecc) {
-+		snf->ecc_cfg->op = ECC_ENCODE;
-+		ret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg);
-+		if (ret)
-+			goto cleanup_dma;
-+	}
-+	// Prepare for custom write interrupt
-+	nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_PG);
-+	reinit_completion(&snf->op_done);
-+	;
-+
-+	// Trigger NFI into custom mode
-+	nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_WRITE);
-+
-+	// Start DMA write
-+	nfi_rmw32(snf, NFI_CON, 0, CON_BWR);
-+	nfi_write16(snf, NFI_STRDATA, STR_DATA);
-+
-+	if (!wait_for_completion_timeout(
-+		    &snf->op_done, usecs_to_jiffies(SNFI_POLL_INTERVAL))) {
-+		dev_err(snf->dev, "DMA timed out for program load.\n");
-+		ret = -ETIMEDOUT;
-+		goto cleanup_ecc;
-+	}
-+
-+	// Wait for NFI_SEC_CNTR returning expected value
-+	ret = readl_poll_timeout(snf->nfi_base + NFI_ADDRCNTR, val,
-+				 NFI_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0,
-+				 SNFI_POLL_INTERVAL);
-+	if (ret)
-+		dev_err(snf->dev, "Timed out waiting for NFI_SEC_CNTR\n");
-+
-+cleanup_ecc:
-+	if (op->data.ecc)
-+		mtk_ecc_disable(snf->ecc);
-+cleanup_dma:
-+	dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_TO_DEVICE);
-+cleanup:
-+	// Stop write
-+	nfi_write32(snf, NFI_CON, 0);
-+	nfi_write16(snf, NFI_CNFG, 0);
-+
-+	// Clear SNF done flag
-+	nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_PG_DONE);
-+	nfi_write32(snf, SNF_STA_CTL1, 0);
-+
-+	// Disable interrupt
-+	nfi_read32(snf, NFI_INTR_STA);
-+	nfi_write32(snf, NFI_INTR_EN, 0);
-+
-+	nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_CUSTOM_EN, 0);
-+
-+	return ret;
-+}
-+
-+/**
-+ * mtk_snand_is_page_ops() - check if the op is a controller supported page op.
-+ * @op spi-mem op to check
-+ *
-+ * Check whether op can be executed with read_from_cache or program_load
-+ * mode in the controller.
-+ * This controller can execute typical Read From Cache and Program Load
-+ * instructions found on SPI-NAND with 2-byte address.
-+ * DTR and cmd buswidth & nbytes should be checked before calling this.
-+ *
-+ * Return: true if the op matches the instruction template
-+ */
-+static bool mtk_snand_is_page_ops(const struct spi_mem_op *op)
-+{
-+	if (op->addr.nbytes != 2)
-+		return false;
-+
-+	if (op->addr.buswidth != 1 && op->addr.buswidth != 2 &&
-+	    op->addr.buswidth != 4)
-+		return false;
-+
-+	// match read from page instructions
-+	if (op->data.dir == SPI_MEM_DATA_IN) {
-+		// check dummy cycle first
-+		if (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth >
-+		    DATA_READ_MAX_DUMMY)
-+			return false;
-+		// quad io / quad out
-+		if ((op->addr.buswidth == 4 || op->addr.buswidth == 1) &&
-+		    op->data.buswidth == 4)
-+			return true;
-+
-+		// dual io / dual out
-+		if ((op->addr.buswidth == 2 || op->addr.buswidth == 1) &&
-+		    op->data.buswidth == 2)
-+			return true;
-+
-+		// standard spi
-+		if (op->addr.buswidth == 1 && op->data.buswidth == 1)
-+			return true;
-+	} else if (op->data.dir == SPI_MEM_DATA_OUT) {
-+		// check dummy cycle first
-+		if (op->dummy.nbytes)
-+			return false;
-+		// program load quad out
-+		if (op->addr.buswidth == 1 && op->data.buswidth == 4)
-+			return true;
-+		// standard spi
-+		if (op->addr.buswidth == 1 && op->data.buswidth == 1)
-+			return true;
-+	}
-+	return false;
-+}
-+
-+static bool mtk_snand_supports_op(struct spi_mem *mem,
-+				  const struct spi_mem_op *op)
-+{
-+	if (!spi_mem_default_supports_op(mem, op))
-+		return false;
-+	if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1)
-+		return false;
-+	if (mtk_snand_is_page_ops(op))
-+		return true;
-+	return ((op->addr.nbytes == 0 || op->addr.buswidth == 1) &&
-+		(op->dummy.nbytes == 0 || op->dummy.buswidth == 1) &&
-+		(op->data.nbytes == 0 || op->data.buswidth == 1));
-+}
-+
-+static int mtk_snand_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
-+{
-+	struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master);
-+	// page ops transfer size must be exactly ((sector_size + spare_size) *
-+	// nsectors). Limit the op size if the caller requests more than that.
-+	// exec_op will read more than needed and discard the leftover if the
-+	// caller requests less data.
-+	if (mtk_snand_is_page_ops(op)) {
-+		size_t l;
-+		// skip adjust_op_size for page ops
-+		if (ms->autofmt)
-+			return 0;
-+		l = ms->caps->sector_size + ms->nfi_cfg.spare_size;
-+		l *= ms->nfi_cfg.nsectors;
-+		if (op->data.nbytes > l)
-+			op->data.nbytes = l;
-+	} else {
-+		size_t hl = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
-+
-+		if (hl >= SNF_GPRAM_SIZE)
-+			return -EOPNOTSUPP;
-+		if (op->data.nbytes > SNF_GPRAM_SIZE - hl)
-+			op->data.nbytes = SNF_GPRAM_SIZE - hl;
-+	}
-+	return 0;
-+}
-+
-+static int mtk_snand_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
-+{
-+	struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master);
-+
-+	dev_dbg(ms->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode,
-+		op->addr.val, op->addr.buswidth, op->addr.nbytes,
-+		op->data.buswidth, op->data.nbytes);
-+	if (mtk_snand_is_page_ops(op)) {
-+		if (op->data.dir == SPI_MEM_DATA_IN)
-+			return mtk_snand_read_page_cache(ms, op);
-+		else
-+			return mtk_snand_write_page_cache(ms, op);
-+	} else {
-+		return mtk_snand_mac_io(ms, op);
-+	}
-+}
-+
-+static const struct spi_controller_mem_ops mtk_snand_mem_ops = {
-+	.adjust_op_size = mtk_snand_adjust_op_size,
-+	.supports_op = mtk_snand_supports_op,
-+	.exec_op = mtk_snand_exec_op,
-+};
-+
-+static const struct spi_controller_mem_caps mtk_snand_mem_caps = {
-+	.ecc = true,
-+};
-+
-+static irqreturn_t mtk_snand_irq(int irq, void *id)
-+{
-+	struct mtk_snand *snf = id;
-+	u32 sta, ien;
-+
-+	sta = nfi_read32(snf, NFI_INTR_STA);
-+	ien = nfi_read32(snf, NFI_INTR_EN);
-+
-+	if (!(sta & ien))
-+		return IRQ_NONE;
-+
-+	nfi_write32(snf, NFI_INTR_EN, 0);
-+	complete(&snf->op_done);
-+	return IRQ_HANDLED;
-+}
-+
-+static const struct of_device_id mtk_snand_ids[] = {
-+	{ .compatible = "mediatek,mt7622-snand", .data = &mt7622_snand_caps },
-+	{ .compatible = "mediatek,mt7629-snand", .data = &mt7629_snand_caps },
-+	{},
-+};
-+
-+MODULE_DEVICE_TABLE(of, mtk_snand_ids);
-+
-+static int mtk_snand_enable_clk(struct mtk_snand *ms)
-+{
-+	int ret;
-+
-+	ret = clk_prepare_enable(ms->nfi_clk);
-+	if (ret) {
-+		dev_err(ms->dev, "unable to enable nfi clk\n");
-+		return ret;
-+	}
-+	ret = clk_prepare_enable(ms->pad_clk);
-+	if (ret) {
-+		dev_err(ms->dev, "unable to enable pad clk\n");
-+		goto err1;
-+	}
-+	return 0;
-+err1:
-+	clk_disable_unprepare(ms->nfi_clk);
-+	return ret;
-+}
-+
-+static void mtk_snand_disable_clk(struct mtk_snand *ms)
-+{
-+	clk_disable_unprepare(ms->pad_clk);
-+	clk_disable_unprepare(ms->nfi_clk);
-+}
-+
-+static int mtk_snand_probe(struct platform_device *pdev)
-+{
-+	struct device_node *np = pdev->dev.of_node;
-+	const struct of_device_id *dev_id;
-+	struct spi_controller *ctlr;
-+	struct mtk_snand *ms;
-+	int ret;
-+
-+	dev_id = of_match_node(mtk_snand_ids, np);
-+	if (!dev_id)
-+		return -EINVAL;
-+
-+	ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*ms));
-+	if (!ctlr)
-+		return -ENOMEM;
-+	platform_set_drvdata(pdev, ctlr);
-+
-+	ms = spi_controller_get_devdata(ctlr);
-+
-+	ms->ctlr = ctlr;
-+	ms->caps = dev_id->data;
-+
-+	ms->ecc = of_mtk_ecc_get(np);
-+	if (IS_ERR(ms->ecc))
-+		return PTR_ERR(ms->ecc);
-+	else if (!ms->ecc)
-+		return -ENODEV;
-+
-+	ms->nfi_base = devm_platform_ioremap_resource(pdev, 0);
-+	if (IS_ERR(ms->nfi_base)) {
-+		ret = PTR_ERR(ms->nfi_base);
-+		goto release_ecc;
-+	}
-+
-+	ms->dev = &pdev->dev;
-+
-+	ms->nfi_clk = devm_clk_get(&pdev->dev, "nfi_clk");
-+	if (IS_ERR(ms->nfi_clk)) {
-+		ret = PTR_ERR(ms->nfi_clk);
-+		dev_err(&pdev->dev, "unable to get nfi_clk, err = %d\n", ret);
-+		goto release_ecc;
-+	}
-+
-+	ms->pad_clk = devm_clk_get(&pdev->dev, "pad_clk");
-+	if (IS_ERR(ms->pad_clk)) {
-+		ret = PTR_ERR(ms->pad_clk);
-+		dev_err(&pdev->dev, "unable to get pad_clk, err = %d\n", ret);
-+		goto release_ecc;
-+	}
-+
-+	ret = mtk_snand_enable_clk(ms);
-+	if (ret)
-+		goto release_ecc;
-+
-+	init_completion(&ms->op_done);
-+
-+	ms->irq = platform_get_irq(pdev, 0);
-+	if (ms->irq < 0) {
-+		ret = ms->irq;
-+		goto disable_clk;
-+	}
-+	ret = devm_request_irq(ms->dev, ms->irq, mtk_snand_irq, 0x0,
-+			       "mtk-snand", ms);
-+	if (ret) {
-+		dev_err(ms->dev, "failed to request snfi irq\n");
-+		goto disable_clk;
-+	}
-+
-+	ret = dma_set_mask(ms->dev, DMA_BIT_MASK(32));
-+	if (ret) {
-+		dev_err(ms->dev, "failed to set dma mask\n");
-+		goto disable_clk;
-+	}
-+
-+	// switch to SNFI mode
-+	nfi_write32(ms, SNF_CFG, SPI_MODE);
-+
-+	// setup an initial page format for ops matching page_cache_op template
-+	// before ECC is called.
-+	ret = mtk_snand_setup_pagefmt(ms, ms->caps->sector_size,
-+				      ms->caps->spare_sizes[0]);
-+	if (ret) {
-+		dev_err(ms->dev, "failed to set initial page format\n");
-+		goto disable_clk;
-+	}
-+
-+	// setup ECC engine
-+	ms->ecc_eng.dev = &pdev->dev;
-+	ms->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED;
-+	ms->ecc_eng.ops = &mtk_snfi_ecc_engine_ops;
-+	ms->ecc_eng.priv = ms;
-+
-+	ret = nand_ecc_register_on_host_hw_engine(&ms->ecc_eng);
-+	if (ret) {
-+		dev_err(&pdev->dev, "failed to register ecc engine.\n");
-+		goto disable_clk;
-+	}
-+
-+	ctlr->num_chipselect = 1;
-+	ctlr->mem_ops = &mtk_snand_mem_ops;
-+	ctlr->mem_caps = &mtk_snand_mem_caps;
-+	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
-+	ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
-+	ctlr->dev.of_node = pdev->dev.of_node;
-+	ret = spi_register_controller(ctlr);
-+	if (ret) {
-+		dev_err(&pdev->dev, "spi_register_controller failed.\n");
-+		goto disable_clk;
-+	}
-+
-+	return 0;
-+disable_clk:
-+	mtk_snand_disable_clk(ms);
-+release_ecc:
-+	mtk_ecc_release(ms->ecc);
-+	return ret;
-+}
-+
-+static int mtk_snand_remove(struct platform_device *pdev)
-+{
-+	struct spi_controller *ctlr = platform_get_drvdata(pdev);
-+	struct mtk_snand *ms = spi_controller_get_devdata(ctlr);
-+
-+	spi_unregister_controller(ctlr);
-+	mtk_snand_disable_clk(ms);
-+	mtk_ecc_release(ms->ecc);
-+	kfree(ms->buf);
-+	return 0;
-+}
-+
-+static struct platform_driver mtk_snand_driver = {
-+	.probe = mtk_snand_probe,
-+	.remove = mtk_snand_remove,
-+	.driver = {
-+		.name = "mtk-snand",
-+		.of_match_table = mtk_snand_ids,
-+	},
-+};
-+
-+module_platform_driver(mtk_snand_driver);
-+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Chuanhong Guo <[email protected]>");
-+MODULE_DESCRIPTION("MeidaTek SPI-NAND Flash Controller Driver");

target/linux/mediatek/patches-5.15/120-13-v5.19-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch

@@ -1,30 +0,0 @@
-From 433b76fa0f3ca2865841abc21538dd8077ca3edd Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <[email protected]>
-Date: Mon, 4 Apr 2022 00:05:38 +0800
-Subject: [PATCH 13/15] mtd: nand: mtk-ecc: also parse nand-ecc-engine if
- available
-
-The recently added ECC engine support introduced a generic property
-named nand-ecc-engine for ecc engine phandle. This patch adds support
-for this new property.
-
-Signed-off-by: Chuanhong Guo <[email protected]>
-(cherry picked from commit a41f25feb6e47c1c4d8d3279ae990ccbd8dfab54)
----
- drivers/mtd/nand/ecc-mtk.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/ecc-mtk.c
-+++ b/drivers/mtd/nand/ecc-mtk.c
-@@ -279,7 +279,10 @@ struct mtk_ecc *of_mtk_ecc_get(struct de
- 	struct mtk_ecc *ecc = NULL;
- 	struct device_node *np;
- 
--	np = of_parse_phandle(of_node, "ecc-engine", 0);
-+	np = of_parse_phandle(of_node, "nand-ecc-engine", 0);
-+	/* for backward compatibility */
-+	if (!np)
-+		np = of_parse_phandle(of_node, "ecc-engine", 0);
- 	if (np) {
- 		ecc = mtk_ecc_get(np);
- 		of_node_put(np);

target/linux/mediatek/patches-5.15/120-14-v5.19-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch

@@ -1,35 +0,0 @@
-From 9ba7c246063ae43baf2e53ccc8c8b5f8d025aaaa Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <[email protected]>
-Date: Sun, 3 Apr 2022 10:19:29 +0800
-Subject: [PATCH 15/15] arm64: dts: mediatek: add mtk-snfi for mt7622
-
-This patch adds a device-tree node for the MTK SPI-NAND Flash Interface
-for MT7622 device tree.
-
-Signed-off-by: Chuanhong Guo <[email protected]>
-(cherry picked from commit 2e022641709011ef0843d0416b0f264b5fc217af)
----
- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -553,6 +553,18 @@
- 		status = "disabled";
- 	};
- 
-+	snfi: spi@1100d000 {
-+		compatible = "mediatek,mt7622-snand";
-+		reg = <0 0x1100d000 0 0x1000>;
-+		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
-+		clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
-+		clock-names = "nfi_clk", "pad_clk";
-+		nand-ecc-engine = <&bch>;
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		status = "disabled";
-+	};
-+
- 	bch: ecc@1100e000 {
- 		compatible = "mediatek,mt7622-ecc";
- 		reg = <0 0x1100e000 0 0x1000>;

target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch

@@ -1,20 +0,0 @@
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -724,7 +724,7 @@ static int spinand_mtd_write(struct mtd_
- static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
- {
- 	struct spinand_device *spinand = nand_to_spinand(nand);
--	u8 marker[2] = { };
-+	u8 marker[1] = { };
- 	struct nand_page_io_req req = {
- 		.pos = *pos,
- 		.ooblen = sizeof(marker),
-@@ -735,7 +735,7 @@ static bool spinand_isbad(struct nand_de
- 
- 	spinand_select_target(spinand, pos->target);
- 	spinand_read_page(spinand, &req);
--	if (marker[0] != 0xff || marker[1] != 0xff)
-+	if (marker[0] != 0xff)
- 		return true;
- 
- 	return false;

target/linux/mediatek/patches-5.15/130-dts-mt7629-add-snand-support.patch

@@ -1,94 +0,0 @@
-From c813fbe806257c574240770ef716fbee19f7dbfa Mon Sep 17 00:00:00 2001
-From: Xiangsheng Hou <[email protected]>
-Date: Thu, 6 Jun 2019 16:29:04 +0800
-Subject: [PATCH] spi: spi-mem: Mediatek: Add SPI Nand support for MT7629
-
-Signed-off-by: Xiangsheng Hou <[email protected]>
----
- arch/arm/boot/dts/mt7629-rfb.dts | 45 ++++++++++++++++++++++++++++++++
- arch/arm/boot/dts/mt7629.dtsi    | 22 ++++++++++++++++
- 3 files changed, 79 insertions(+)
-
---- a/arch/arm/boot/dts/mt7629.dtsi
-+++ b/arch/arm/boot/dts/mt7629.dtsi
-@@ -272,6 +272,27 @@
- 			status = "disabled";
- 		};
- 
-+		snfi: spi@1100d000 {
-+			compatible = "mediatek,mt7629-snand";
-+			reg = <0x1100d000 0x1000>;
-+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
-+			clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
-+			clock-names = "nfi_clk", "pad_clk";
-+			nand-ecc-engine = <&bch>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "disabled";
-+		};
-+
-+		bch: ecc@1100e000 {
-+			compatible = "mediatek,mt7622-ecc";
-+			reg = <0x1100e000 0x1000>;
-+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
-+			clocks = <&pericfg CLK_PERI_NFIECC_PD>;
-+			clock-names = "nfiecc_clk";
-+			status = "disabled";
-+		};
-+
- 		spi: spi@1100a000 {
- 			compatible = "mediatek,mt7629-spi",
- 				     "mediatek,mt7622-spi";
---- a/arch/arm/boot/dts/mt7629-rfb.dts
-+++ b/arch/arm/boot/dts/mt7629-rfb.dts
-@@ -254,6 +254,50 @@
- 	};
- };
- 
-+&bch {
-+	status = "okay";
-+};
-+
-+&snfi {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&serial_nand_pins>;
-+	status = "okay";
-+	flash@0 {
-+		compatible = "spi-nand";
-+		reg = <0>;
-+		spi-tx-bus-width = <4>;
-+		spi-rx-bus-width = <4>;
-+		nand-ecc-engine = <&snfi>;
-+
-+		partitions {
-+			compatible = "fixed-partitions";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			partition@0 {
-+				label = "Bootloader";
-+				reg = <0x00000 0x0100000>;
-+				read-only;
-+			};
-+
-+			partition@100000 {
-+				label = "Config";
-+				reg = <0x100000 0x0040000>;
-+			};
-+
-+			partition@140000 {
-+				label = "factory";
-+				reg = <0x140000 0x0080000>;
-+			};
-+
-+			partition@1c0000 {
-+				label = "firmware";
-+				reg = <0x1c0000 0x1000000>;
-+			};
-+		};
-+	};
-+};
-+
- &spi {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&spi_pins>;

target/linux/mediatek/patches-5.15/131-dts-mt7622-add-snand-support.patch

@@ -1,68 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -539,6 +539,65 @@
- 	status = "disabled";
- };
- 
-+&bch {
-+	status = "okay";
-+};
-+
-+&snfi {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&serial_nand_pins>;
-+	status = "okay";
-+	flash@0 {
-+		compatible = "spi-nand";
-+		reg = <0>;
-+		spi-tx-bus-width = <4>;
-+		spi-rx-bus-width = <4>;
-+		nand-ecc-engine = <&snfi>;
-+
-+		partitions {
-+			compatible = "fixed-partitions";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			partition@0 {
-+				label = "Preloader";
-+				reg = <0x00000 0x0080000>;
-+				read-only;
-+			};
-+
-+			partition@80000 {
-+				label = "ATF";
-+				reg = <0x80000 0x0040000>;
-+			};
-+
-+			partition@c0000 {
-+				label = "Bootloader";
-+				reg = <0xc0000 0x0080000>;
-+			};
-+
-+			partition@140000 {
-+				label = "Config";
-+				reg = <0x140000 0x0080000>;
-+			};
-+
-+			partition@1c0000 {
-+				label = "Factory";
-+				reg = <0x1c0000 0x0100000>;
-+			};
-+
-+			partition@200000 {
-+				label = "firmware";
-+				reg = <0x2c0000 0x2000000>;
-+			};
-+
-+			partition@2200000 {
-+				label = "User_data";
-+				reg = <0x22c0000 0x4000000>;
-+			};
-+		};
-+	};
-+};
-+
- &spi0 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&spic0_pins>;

target/linux/mediatek/patches-5.15/140-dts-fix-wmac-support-for-mt7622-rfb1.patch

@@ -1,18 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -580,7 +580,7 @@
- 				reg = <0x140000 0x0080000>;
- 			};
- 
--			partition@1c0000 {
-+			factory: partition@1c0000 {
- 				label = "Factory";
- 				reg = <0x1c0000 0x0100000>;
- 			};
-@@ -641,5 +641,6 @@
- &wmac {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&wmac_pins>;
-+	mediatek,mtd-eeprom = <&factory 0x0000>;
- 	status = "okay";
- };

target/linux/mediatek/patches-5.15/150-dts-mt7623-eip97-inside-secure-support.patch

@@ -1,24 +0,0 @@
---- a/arch/arm/boot/dts/mt7623.dtsi
-+++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -951,17 +951,15 @@
- 	};
- 
- 	crypto: crypto@1b240000 {
--		compatible = "mediatek,eip97-crypto";
-+		compatible = "inside-secure,safexcel-eip97";
- 		reg = <0 0x1b240000 0 0x20000>;
- 		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
- 			     <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
- 			     <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
--			     <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
--			     <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
-+			     <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
-+		interrupt-names = "ring0", "ring1", "ring2", "ring3";
- 		clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
--		clock-names = "cryp";
--		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
--		status = "disabled";
-+		status = "okay";
- 	};
- 
- 	bdpsys: syscon@1c000000 {

target/linux/mediatek/patches-5.15/160-dts-mt7623-bpi-r2-earlycon.patch

@@ -1,11 +0,0 @@
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -19,7 +19,7 @@
- 
- 	chosen {
- 		stdout-path = "serial2:115200n8";
--		bootargs = "console=ttyS2,115200n8 console=tty1";
-+		bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
- 	};
- 
- 	connector {

target/linux/mediatek/patches-5.15/161-dts-mt7623-bpi-r2-mmc-device-order.patch

@@ -1,11 +0,0 @@
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -15,6 +15,8 @@
- 
- 	aliases {
- 		serial2 = &uart2;
-+		mmc0 = &mmc0;
-+		mmc1 = &mmc1;
- 	};
- 
- 	chosen {

target/linux/mediatek/patches-5.15/162-dts-mt7623-bpi-r2-led-aliases.patch

@@ -1,29 +0,0 @@
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -17,6 +17,10 @@
- 		serial2 = &uart2;
- 		mmc0 = &mmc0;
- 		mmc1 = &mmc1;
-+		led-boot = &led_system_green;
-+		led-failsafe = &led_system_blue;
-+		led-running = &led_system_green;
-+		led-upgrade = &led_system_blue;
- 	};
- 
- 	chosen {
-@@ -112,13 +116,13 @@
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&led_pins_a>;
- 
--		blue {
-+		led_system_blue: blue {
- 			label = "bpi-r2:pio:blue";
- 			gpios = <&pio 240 GPIO_ACTIVE_LOW>;
- 			default-state = "off";
- 		};
- 
--		green {
-+		led_system_green: green {
- 			label = "bpi-r2:pio:green";
- 			gpios = <&pio 241 GPIO_ACTIVE_LOW>;
- 			default-state = "off";

target/linux/mediatek/patches-5.15/163-dts-mt7623-bpi-r2-ethernet-alias.patch

@@ -1,10 +0,0 @@
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -15,6 +15,7 @@
- 
- 	aliases {
- 		serial2 = &uart2;
-+		ethernet0 = &gmac0;
- 		mmc0 = &mmc0;
- 		mmc1 = &mmc1;
- 		led-boot = &led_system_green;

target/linux/mediatek/patches-5.15/173-arm-dts-mt7623-add-musb-device-nodes.patch

@@ -1,69 +0,0 @@
-From 21d106f15262f5a2ef7531636e0703ee61c33c61 Mon Sep 17 00:00:00 2001
-From: Sungbo Eo <[email protected]>
-Date: Sun, 8 Aug 2021 21:38:40 +0900
-Subject: [PATCH 2/2] arm: dts: mt7623: add musb device nodes
-
-MT7623 has an musb controller that is compatible with the one from MT2701.
-
-Signed-off-by: Sungbo Eo <[email protected]>
----
- arch/arm/boot/dts/mt7623.dtsi  | 34 ++++++++++++++++++++++++++++++++++
- arch/arm/boot/dts/mt7623a.dtsi |  4 ++++
- 2 files changed, 38 insertions(+)
-
---- a/arch/arm/boot/dts/mt7623.dtsi
-+++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -585,6 +585,40 @@
- 		status = "disabled";
- 	};
- 
-+	usb0: usb@11200000 {
-+		compatible = "mediatek,mt7623-musb",
-+			     "mediatek,mtk-musb";
-+		reg = <0 0x11200000 0 0x1000>;
-+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
-+		interrupt-names = "mc";
-+		phys = <&u2port2 PHY_TYPE_USB2>;
-+		dr_mode = "otg";
-+		clocks = <&pericfg CLK_PERI_USB0>,
-+			 <&pericfg CLK_PERI_USB0_MCU>,
-+			 <&pericfg CLK_PERI_USB_SLV>;
-+		clock-names = "main","mcu","univpll";
-+		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
-+		status = "disabled";
-+	};
-+
-+	u2phy1: t-phy@11210000 {
-+		compatible = "mediatek,mt7623-tphy",
-+			     "mediatek,generic-tphy-v1";
-+		reg = <0 0x11210000 0 0x0800>;
-+		#address-cells = <2>;
-+		#size-cells = <2>;
-+		ranges;
-+		status = "disabled";
-+
-+		u2port2: usb-phy@11210800 {
-+			reg = <0 0x11210800 0 0x0100>;
-+			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
-+			clock-names = "ref";
-+			#phy-cells = <1>;
-+			status = "okay";
-+		};
-+	};
-+
- 	audsys: clock-controller@11220000 {
- 		compatible = "mediatek,mt7623-audsys",
- 			     "mediatek,mt2701-audsys",
---- a/arch/arm/boot/dts/mt7623a.dtsi
-+++ b/arch/arm/boot/dts/mt7623a.dtsi
-@@ -35,6 +35,10 @@
- 	clock-names = "ethif";
- };
- 
-+&usb0 {
-+	power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>;
-+};
-+
- &usb1 {
- 	power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>;
- };

target/linux/mediatek/patches-5.15/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch

@@ -1,13 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -160,6 +160,10 @@
- 		switch@0 {
- 			compatible = "mediatek,mt7531";
- 			reg = <0>;
-+			interrupt-controller;
-+			#interrupt-cells = <1>;
-+			interrupt-parent = <&pio>;
-+			interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
- 			reset-gpios = <&pio 54 0>;
- 
- 			ports {

target/linux/mediatek/patches-5.15/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch

@@ -1,106 +0,0 @@
-From patchwork Tue Apr 26 19:51:36 2022
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-Date: Tue, 26 Apr 2022 20:51:36 +0100
-From: Daniel Golle <[email protected]>
-To: [email protected], [email protected],
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-Cc: Rob Herring <[email protected]>,
- Krzysztof Kozlowski <[email protected]>,
- Matthias Brugger <[email protected]>
-Subject: [PATCH] arm64: dts: mediatek: mt7622: fix GICv2 range
-Message-ID: <YmhNSLgp/[email protected]>
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-X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 
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- linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org
-
-With the current range specified for the CPU interface there is an
-error message at boot:
-
-GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set
-
-Setting irqchip.gicv2_force_probe=1 in bootargs results in:
-
-GIC: Aliased GICv2 at 0x0000000010320000, trying to find the canonical range over 128kB
-GIC: Adjusting CPU interface base to 0x000000001032f000
-GIC: Using split EOI/Deactivate mode
-
-Using the adjusted CPU interface base and 8K size results in only the
-final line remaining and fully working system as well as /proc/interrupts
-showing additional IPI3,4,5,6:
-
-IPI3:         0          0       CPU stop (for crash dump) interrupts
-IPI4:         0          0       Timer broadcast interrupts
-IPI5:         0          0       IRQ work interrupts
-IPI6:         0          0       CPU wake-up interrupts
-
-Signed-off-by: Daniel Golle <[email protected]>
----
- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -339,7 +339,7 @@
- 		#interrupt-cells = <3>;
- 		interrupt-parent = <&gic>;
- 		reg = <0 0x10310000 0 0x1000>,
--		      <0 0x10320000 0 0x1000>,
-+		      <0 0x1032f000 0 0x2000>,
- 		      <0 0x10340000 0 0x2000>,
- 		      <0 0x10360000 0 0x2000>;
- 	};

target/linux/mediatek/patches-5.15/191-v5.19-arm64-dts-mt7622-specify-the-L2-cache-topology.patch

@@ -1,132 +0,0 @@
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-On an MT7622 system, the kernel complains of not being able to detect the cache
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-order to fix this.
-
-Signed-off-by: Rui Salvaterra <[email protected]>
----
- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -80,6 +80,7 @@
- 			enable-method = "psci";
- 			clock-frequency = <1300000000>;
- 			cci-control-port = <&cci_control2>;
-+			next-level-cache = <&L2>;
- 		};
- 
- 		cpu1: cpu@1 {
-@@ -94,6 +95,12 @@
- 			enable-method = "psci";
- 			clock-frequency = <1300000000>;
- 			cci-control-port = <&cci_control2>;
-+			next-level-cache = <&L2>;
-+		};
-+
-+		L2: l2-cache {
-+			compatible = "cache";
-+			cache-level = <2>;
- 		};
- 	};
- 

target/linux/mediatek/patches-5.15/192-v5.19-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch

@@ -1,122 +0,0 @@
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-Cc: [email protected], [email protected], [email protected],
- Rui Salvaterra <[email protected]>
-Subject: [PATCH] arm64: dts: mt7622: specify the number of DMA requests
-Date: Fri, 29 Apr 2022 09:42:25 +0100
-Message-Id: <[email protected]>
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- <http://lists.infradead.org/mailman/options/linux-arm-kernel>,
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- linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org
-
-The MT7622 device tree never bothered to specify the number of virtual DMA
-channels for the HSDMA controller, always falling back to the default value of
-3. Make this value explicit, in order to avoid the following dmesg notification:
-
-mtk_hsdma 1b007000.dma-controller: Using 3 as missing dma-requests property
-
-Signed-off-by: Rui Salvaterra <[email protected]>
----
- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -942,6 +942,7 @@
- 		clock-names = "hsdma";
- 		power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
- 		#dma-cells = <1>;
-+		dma-requests = <3>;
- 	};
- 
- 	pcie_mirror: pcie-mirror@10000400 {

target/linux/mediatek/patches-5.15/193-dts-mt7623-thermal_zone_fix.patch

@@ -1,48 +0,0 @@
-From 824d56e753a588fcfd650db1822e34a02a48bb77 Mon Sep 17 00:00:00 2001
-From: Bruno Umuarama <[email protected]>
-Date: Thu, 13 Oct 2022 21:18:21 +0000
-Subject: [PATCH] mediatek: mt7623: fix thermal zone
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Raising the temperatures for passive and active trips. @VA1DER
-proposed at issue 9396 to remove passive trip. This commit relates to
-his suggestion.
-
-Without this patch. the CPU will be throttled all the way down to 98MHz
-if the temperature rises even a degree above the trip point, and it was
-further discovered that if the internal temperature of the device is
-above the first trip point temperature when it boots then it will start
-in a throttled state and even
-$ echo disabled > /sys/class/thermal/thermal_zone0/mode
-will have no effect.
-
-The patch increases the passive trip point and active cooling map. The
-throttling temperature will then be at 77°C and 82°C, which is still a
-low enough temperature for ARM devices to not be in the real danger
-zone, and gives some operational headroom.
-
-Signed-off-by: Bruno Umuarama <[email protected]>
----
- arch/arm/boot/dts/mt7623.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm/boot/dts/mt7623.dtsi
-+++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -160,13 +160,13 @@
- 
- 				trips {
- 					cpu_passive: cpu-passive {
--						temperature = <57000>;
-+						temperature = <77000>;
- 						hysteresis = <2000>;
- 						type = "passive";
- 					};
- 
- 					cpu_active: cpu-active {
--						temperature = <67000>;
-+						temperature = <82000>;
- 						hysteresis = <2000>;
- 						type = "active";
- 					};

target/linux/mediatek/patches-5.15/194-dts-mt7968a-add-ramoops.patch

@@ -1,17 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -68,6 +68,14 @@
- 		#address-cells = <2>;
- 		#size-cells = <2>;
- 		ranges;
-+
-+		/* 64 KiB reserved for ramoops/pstore */
-+		ramoops@42ff0000 {
-+			compatible = "ramoops";
-+			reg = <0 0x42ff0000 0 0x10000>;
-+			record-size = <0x1000>;
-+		};
-+
- 		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
- 		secmon_reserved: secmon@43000000 {
- 			reg = <0 0x43000000 0 0x30000>;

target/linux/mediatek/patches-5.15/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch

@@ -1,196 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-@@ -23,6 +23,10 @@
- 		serial0 = &uart0;
- 		ethernet0 = &gmac0;
- 		ethernet1 = &gmac1;
-+		led-boot = &green_led;
-+		led-failsafe = &green_led;
-+		led-running = &green_led;
-+		led-upgrade = &blue_led;
- 	};
- 
- 	chosen {
-@@ -419,27 +423,27 @@
- 
- 		port@1 {
- 			reg = <1>;
--			label = "lan0";
-+			label = "lan1";
- 		};
- 
- 		port@2 {
- 			reg = <2>;
--			label = "lan1";
-+			label = "lan2";
- 		};
- 
- 		port@3 {
- 			reg = <3>;
--			label = "lan2";
-+			label = "lan3";
- 		};
- 
- 		port@4 {
- 			reg = <4>;
--			label = "lan3";
-+			label = "lan4";
- 		};
- 
- 		port5: port@5 {
- 			reg = <5>;
--			label = "lan4";
-+			label = "sfp2";
- 			phy-mode = "2500base-x";
- 			sfp = <&sfp2>;
- 			managed = "in-band-status";
-@@ -490,9 +494,137 @@
- 
- &wifi {
- 	status = "okay";
--	pinctrl-names = "default", "dbdc";
-+	pinctrl-names = "default";
- 	pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
--	pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
-+
-+	mediatek,eeprom-data = <0x86790900 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x01000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000800 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x24649090 0x00280000 0x05100000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
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-+				0xc1c2c1c2 0x41c341c3 0x3fc13fc1 0x40c13fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c13fc2
-+				0x3fc140c0 0x41c040c0 0x3fc33fc3 0x40c23fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c23fc2
-+				0x3fc140c1 0x41c040c0 0x00000000 0x00000000 0x41c741c7 0xc1c7c1c7 0x00000000 0x00000000
-+				0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
-+				0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
-+				0x00a0ce00 0x00000000 0xb6840000 0x00000000 0x00000000 0x00000000 0x18181818 0x18181818
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x004b5763 0x0000004b 0x57630000 0x004b5763 0x0000004b 0x57630000 0x88888888 0x08474759
-+				0x69780849 0x49596d7a 0x0849495a 0x6d790848 0x48596c78 0x08484858 0x6a780848 0x48586a78
-+				0x08484858 0x6c78084a 0x4a5b6d79 0x08474759 0x697a0848 0x48596b79 0x08484859 0x6c7a0848
-+				0x48586c79 0x08484857 0x68770848 0x48576877 0x08484857 0x6a77084a 0x4a5a6a77 0x08464659
-+				0x69790848 0x48586b79 0x08484858 0x6c7a0848 0x48596c79 0x08484857 0x68770848 0x48576877
-+				0x08494958 0x6d7a084b 0x4b5c6c77 0x0847475a 0x6a7b0849 0x495a6e7c 0x0849495a 0x6e7c0849
-+				0x495b6e7c 0x08494959 0x6a7a0849 0x49596a7a 0x084a4a5a 0x6f7d084b 0x4b5c6e7b 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x85848484
-+				0xc3c4c4c5 0xc4c3c33f 0xc3c3c2c2 0xc2c2c03f 0xc3c3c3c4 0xc4c4c33f 0xc2c2c2c2 0xc1c3c1c1
-+				0xc0c08282 0x83848686 0x88880000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00001111 0x00000000
-+				0x8080f703 0x10808080 0x80050d13 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x000000a4 0xce000000 0x0000b684 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
- 
- 	led {
- 		led-active-low;
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
-@@ -55,6 +55,7 @@
- 					partition@c00000 {
- 						label = "fit";
- 						reg = <0xc00000 0x1400000>;
-+						compatible = "denx,fit";
- 					};
- 				};
- 			};

target/linux/mediatek/patches-5.15/200-phy-phy-mtk-tphy-Add-hifsys-support.patch

@@ -1,66 +0,0 @@
-From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001
-From: Kristian Evensen <[email protected]>
-Date: Mon, 30 Apr 2018 14:38:01 +0200
-Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support
-
----
- drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++
- 1 file changed, 20 insertions(+)
-
---- a/drivers/phy/mediatek/phy-mtk-tphy.c
-+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
-@@ -18,6 +18,8 @@
- #include <linux/phy/phy.h>
- #include <linux/platform_device.h>
- #include <linux/regmap.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/regmap.h>
- 
- /* version V1 sub-banks offset base address */
- /* banks shared by multiple phys */
-@@ -311,6 +313,9 @@
- 
- #define TPHY_CLKS_CNT	2
- 
-+#define HIF_SYSCFG1			0x14
-+#define HIF_SYSCFG1_PHY2_MASK		(0x3 << 20)
-+
- enum mtk_phy_version {
- 	MTK_PHY_V1 = 1,
- 	MTK_PHY_V2,
-@@ -377,6 +382,7 @@ struct mtk_tphy {
- 	void __iomem *sif_base;	/* only shared sif */
- 	const struct mtk_phy_pdata *pdata;
- 	struct mtk_phy_instance **phys;
-+	struct regmap *hif;
- 	int nphys;
- 	int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
- 	int src_coef; /* coefficient for slew rate calibrate */
-@@ -730,6 +736,10 @@ static void pcie_phy_instance_init(struc
- 	if (tphy->pdata->version != MTK_PHY_V1)
- 		return;
- 
-+	if (tphy->hif)
-+		regmap_update_bits(tphy->hif, HIF_SYSCFG1,
-+				   HIF_SYSCFG1_PHY2_MASK, 0);
-+
- 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
- 	tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H);
- 	tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2);
-@@ -1437,6 +1447,16 @@ static int mtk_tphy_probe(struct platfor
- 					 &tphy->src_coef);
- 	}
- 
-+	if (of_find_property(np, "mediatek,phy-switch", NULL)) {
-+		tphy->hif = syscon_regmap_lookup_by_phandle(np,
-+							    "mediatek,phy-switch");
-+		if (IS_ERR(tphy->hif)) {
-+			dev_err(&pdev->dev,
-+				"missing \"mediatek,phy-switch\" phandle\n");
-+			return PTR_ERR(tphy->hif);
-+		}
-+	}
-+
- 	port = 0;
- 	for_each_child_of_node(np, child_np) {
- 		struct mtk_phy_instance *instance;

target/linux/mediatek/patches-5.15/210-v6.1-pinctrl-mediatek-add-support-for-MT7986-SoC.patch

@@ -1,26 +0,0 @@
---- a/drivers/pinctrl/mediatek/Kconfig
-+++ b/drivers/pinctrl/mediatek/Kconfig
-@@ -120,6 +120,13 @@ config PINCTRL_MT7622
- 	default ARM64 && ARCH_MEDIATEK
- 	select PINCTRL_MTK_MOORE
- 
-+config PINCTRL_MT7986
-+	bool "Mediatek MT7986 pin control"
-+	depends on OF
-+	depends on ARM64 || COMPILE_TEST
-+	default ARM64 && ARCH_MEDIATEK
-+	select PINCTRL_MTK_MOORE
-+
- config PINCTRL_MT8167
- 	bool "Mediatek MT8167 pin control"
- 	depends on OF
---- a/drivers/pinctrl/mediatek/Makefile
-+++ b/drivers/pinctrl/mediatek/Makefile
-@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MT6797)	+= pinctrl-
- obj-$(CONFIG_PINCTRL_MT7622)	+= pinctrl-mt7622.o
- obj-$(CONFIG_PINCTRL_MT7623)	+= pinctrl-mt7623.o
- obj-$(CONFIG_PINCTRL_MT7629)	+= pinctrl-mt7629.o
-+obj-$(CONFIG_PINCTRL_MT7986)	+= pinctrl-mt7986.o
- obj-$(CONFIG_PINCTRL_MT8167)	+= pinctrl-mt8167.o
- obj-$(CONFIG_PINCTRL_MT8173)	+= pinctrl-mt8173.o
- obj-$(CONFIG_PINCTRL_MT8183)	+= pinctrl-mt8183.o

target/linux/mediatek/patches-5.15/211-v5.16-clk-mediatek-Add-API-for-clock-resource-recycle.patch

@@ -1,28 +0,0 @@
---- a/drivers/clk/mediatek/clk-mtk.c
-+++ b/drivers/clk/mediatek/clk-mtk.c
-@@ -43,6 +43,15 @@ err_out:
- 	return NULL;
- }
- 
-+void mtk_free_clk_data(struct clk_onecell_data *clk_data)
-+{
-+	if (!clk_data)
-+		return;
-+
-+	kfree(clk_data->clks);
-+	kfree(clk_data);
-+}
-+
- void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
- 		int num, struct clk_onecell_data *clk_data)
- {
---- a/drivers/clk/mediatek/clk-mtk.h
-+++ b/drivers/clk/mediatek/clk-mtk.h
-@@ -202,6 +202,7 @@ void mtk_clk_register_dividers(const str
- 				struct clk_onecell_data *clk_data);
- 
- struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
-+void mtk_free_clk_data(struct clk_onecell_data *clk_data);
- 
- #define HAVE_RST_BAR	BIT(0)
- #define PLL_AO		BIT(1)