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@@ -0,0 +1,135 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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+/dts-v1/;
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+
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+#include "FRITZ736X.dtsi"
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+
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+#include <dt-bindings/input/input.h>
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+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
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+
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+/ {
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+ compatible = "avm,fritz7362sl", "avm,fritz736x", "lantiq,xway", "lantiq,vr9";
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+ model = "AVM FRITZ!Box 7362 SL";
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+};
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+
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+&power_green {
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+ label = "fritz7362sl:green:power";
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+};
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+
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+&power_red {
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+ label = "fritz7362sl:red:power";
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+};
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+
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+&info_green {
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+ label = "fritz7362sl:green:info";
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+};
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+
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+&wifi {
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+ label = "fritz7362sl:green:wlan";
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+};
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+
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+&info_red {
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+ label = "fritz7362sl:red:info";
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+};
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+
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+&dect {
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+ label = "fritz7362sl:green:dect";
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+};
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+
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+&gpio {
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+ pins_spi_default: pins_spi_default {
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+ spi_in {
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+ lantiq,groups = "spi_di";
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+ lantiq,function = "spi";
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+ };
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+
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+ spi_out {
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+ lantiq,groups = "spi_do", "spi_clk",
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+ "spi_cs4";
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+ lantiq,function = "spi";
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+ lantiq,output = <1>;
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+ };
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+ };
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+};
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+
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+&state_default {
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+ nand {
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+ lantiq,groups = "nand ale", "nand cle",
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+ "nand cs1", "nand rd", "nand rdy";
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+ lantiq,function = "ebu";
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+ };
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+
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+ pcie-rst {
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+ lantiq,pins = "io21";
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+ lantiq,open-drain = <1>;
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+ lantiq,output = <1>;
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+ };
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+};
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+
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+&spi {
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+ status = "okay";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pins_spi_default>;
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+
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+ flash@4 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "jedec,spi-nor";
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+ reg = <4 0>;
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+ spi-max-frequency = <1000000>;
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+
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+ urlader: partition@0 {
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+ reg = <0x0 0x40000>;
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+ label = "urlader";
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+ read-only;
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+ };
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+
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+ partition@40000 {
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+ reg = <0x40000 0x60000>;
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+ label = "tffs (1)";
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+ read-only;
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+ };
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+
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+ partition@A0000 {
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+ reg = <0xA0000 0x60000>;
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+ label = "tffs (2)";
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+ read-only;
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+ };
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+ };
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+};
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+
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+&localbus {
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+ nand@1 {
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+ compatible = "lantiq,nand-xway";
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+ lantiq,cs1 = <1>;
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+ bank-width = <1>;
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+ reg = <1 0x0 0x2000000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ nand-ecc-mode = "on-die";
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+
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+ partitions {
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+ compatible = "fixed-partitions";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ partition@0 {
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+ label = "kernel";
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+ reg = <0x0 0x400000>;
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+ };
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+
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+ partition@400000 {
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+ label = "ubi";
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+ reg = <0x400000 0x7c00000>;
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+ };
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+ };
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+ };
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+};
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+
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+&pcie0 {
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+ gpio-reset = <&gpio 21 GPIO_ACTIVE_LOW>;
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+
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+ pcie@0 {
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+ #size-cells = <1>;
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+ #address-cells = <2>;
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+ };
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+};
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