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@@ -0,0 +1,190 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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+
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+#include "rtl838x.dtsi"
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+#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi"
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+
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+#include <dt-bindings/interrupt-controller/irq.h>
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+
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+/ {
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+ compatible = "panasonic,m24eg-pn28240k", "realtek,rtl8382-soc";
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+ model = "Panasonic Switch-M24eG PN28240K";
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+
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+ aliases {
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+ led-boot = &led_status_eco_green;
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+ led-failsafe = &led_status_eco_amber;
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+ led-running = &led_status_eco_green;
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+ led-upgrade = &led_status_eco_green;
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+ };
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+
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+ /*
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+ * sfp0/1 are "combo" port with each TP port (23/24), and they are
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+ * connected to the RTL8218FB. Currently, there is no support for
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+ * the chip and only TP ports work by the RTL8218D support.
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+ */
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+ sfp0: sfp-p23 {
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+ compatible = "sff,sfp";
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+ i2c-bus = <&i2c0>;
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+ tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
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+ tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
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+ mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
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+ los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ sfp1: sfp-p24 {
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+ compatible = "sff,sfp";
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+ i2c-bus = <&i2c1>;
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+ tx-fault-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
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+ tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
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+ mod-def0-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
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+ los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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+ };
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+};
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+
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+&leds {
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+ led_status_eco_amber: led-5 {
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+ label = "amber:status_eco";
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+ gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
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+ color = <LED_COLOR_ID_AMBER>;
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+ function = LED_FUNCTION_STATUS;
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+ function-enumerator = <1>;
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+ };
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+
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+ led_status_eco_green: led-6 {
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+ label = "green:status_eco";
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+ gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
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+ color = <LED_COLOR_ID_GREEN>;
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+ function = LED_FUNCTION_STATUS;
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+ function-enumerator = <2>;
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+ };
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+};
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+
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+&i2c_gpio_0 {
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+ scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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+ sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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+};
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+
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+&i2c_gpio_1 {
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+ scl-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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+ sda-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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+};
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+
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+&gpio2 {
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ interrupt-parent = <&gpio0>;
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+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
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+
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+ /*
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+ * GPIO12 (IO1_4): RTL8218B + RTL8218FB
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+ *
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+ * This GPIO pin should be specified as "reset-gpio" in mdio node,
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+ * but the current configuration of RTL8218B phy in the phy driver
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+ * seems to be incomplete and RTL8218FB phy won't be configured on
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+ * RTL8218D support. So, ethernet ports on these phys will be broken
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+ * after hard-resetting.
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+ * (RTL8218FB phy will be detected as RTL8218D by the phy driver)
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+ * At the moment, configure this GPIO pin as gpio-hog to avoid breaking
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+ * by resetting.
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+ */
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+ ext_switch_reset {
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+ gpio-hog;
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+ gpios = <12 GPIO_ACTIVE_HIGH>;
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+ output-high;
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+ line-name = "ext-switch-reset";
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+ };
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+};
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+
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+&i2c_switch {
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+ i2c0: i2c@0 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0>;
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+ };
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+
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+ i2c1: i2c@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <1>;
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+ };
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+};
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+
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+ðernet0 {
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+ mdio-bus {
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+ compatible = "realtek,rtl838x-mdio";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ EXTERNAL_PHY(0)
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+ EXTERNAL_PHY(1)
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+ EXTERNAL_PHY(2)
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+ EXTERNAL_PHY(3)
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+ EXTERNAL_PHY(4)
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+ EXTERNAL_PHY(5)
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+ EXTERNAL_PHY(6)
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+ EXTERNAL_PHY(7)
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+
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+ INTERNAL_PHY(8)
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+ INTERNAL_PHY(9)
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+ INTERNAL_PHY(10)
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+ INTERNAL_PHY(11)
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+ INTERNAL_PHY(12)
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+ INTERNAL_PHY(13)
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+ INTERNAL_PHY(14)
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+ INTERNAL_PHY(15)
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+
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+ /* RTL8218FB */
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+ EXTERNAL_PHY(16)
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+ EXTERNAL_PHY(17)
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+ EXTERNAL_PHY(18)
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+ EXTERNAL_PHY(19)
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+ EXTERNAL_PHY(20)
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+ EXTERNAL_PHY(21)
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+ EXTERNAL_PHY(22)
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+ EXTERNAL_PHY(23)
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+ };
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+};
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+
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+&switch0 {
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ SWITCH_PORT(0, 1, qsgmii)
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+ SWITCH_PORT(1, 2, qsgmii)
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+ SWITCH_PORT(2, 3, qsgmii)
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+ SWITCH_PORT(3, 4, qsgmii)
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+ SWITCH_PORT(4, 5, qsgmii)
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+ SWITCH_PORT(5, 6, qsgmii)
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+ SWITCH_PORT(6, 7, qsgmii)
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+ SWITCH_PORT(7, 8, qsgmii)
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+
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+ SWITCH_PORT(8, 9, internal)
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+ SWITCH_PORT(9, 10, internal)
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+ SWITCH_PORT(10, 11, internal)
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+ SWITCH_PORT(11, 12, internal)
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+ SWITCH_PORT(12, 13, internal)
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+ SWITCH_PORT(13, 14, internal)
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+ SWITCH_PORT(14, 15, internal)
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+ SWITCH_PORT(15, 16, internal)
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+
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+ SWITCH_PORT(16, 17, qsgmii)
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+ SWITCH_PORT(17, 18, qsgmii)
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+ SWITCH_PORT(18, 19, qsgmii)
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+ SWITCH_PORT(19, 20, qsgmii)
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+ SWITCH_PORT(20, 21, qsgmii)
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+ SWITCH_PORT(21, 22, qsgmii)
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+ SWITCH_PORT(22, 23, qsgmii)
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+ SWITCH_PORT(23, 24, qsgmii)
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+
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+ port@28 {
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+ ethernet = <ðernet0>;
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+ reg = <28>;
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+ phy-mode = "internal";
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+
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+ };
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+ };
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+};
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INAGAKI Hiroshi