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986-rt2x00-add-TX-LOFT-calibration.patch

986-rt2x00-add-TX-LOFT-calibration.patch 33 KB
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  1. --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
    2. 

  2. +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
    3. 

  3. @@ -9000,6 +9000,954 @@ restore_value:
    4. 

  4.  }
    5. 

  5.  EXPORT_SYMBOL_GPL(rt2800_rxiq_calibration);
    6. 

  6.  
    7. 

  7. +static void rt2800_rf_configstore(struct rt2x00_dev *rt2x00dev, rf_reg_pair rf_reg_record[][13], u8 chain)
    8. 

  8. +{
    9. 

  9. +	u8 rfvalue = 0;
    10. 

  10. +
    11. 

  11. +	if (chain == CHAIN_0) {
    12. 

  12. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
    13. 

  13. +		rf_reg_record[CHAIN_0][0].bank = 0;
    14. 

  14. +		rf_reg_record[CHAIN_0][0].reg = 1;
    15. 

  15. +		rf_reg_record[CHAIN_0][0].value = rfvalue;
    16. 

  16. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
    17. 

  17. +		rf_reg_record[CHAIN_0][1].bank = 0;
    18. 

  18. +		rf_reg_record[CHAIN_0][1].reg = 2;
    19. 

  19. +		rf_reg_record[CHAIN_0][1].value = rfvalue;
    20. 

  20. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
    21. 

  21. +		rf_reg_record[CHAIN_0][2].bank = 0;
    22. 

  22. +		rf_reg_record[CHAIN_0][2].reg = 35;
    23. 

  23. +		rf_reg_record[CHAIN_0][2].value = rfvalue;
    24. 

  24. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
    25. 

  25. +		rf_reg_record[CHAIN_0][3].bank = 0;
    26. 

  26. +		rf_reg_record[CHAIN_0][3].reg = 42;
    27. 

  27. +		rf_reg_record[CHAIN_0][3].value = rfvalue;
    28. 

  28. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);
    29. 

  29. +		rf_reg_record[CHAIN_0][4].bank = 4;
    30. 

  30. +		rf_reg_record[CHAIN_0][4].reg = 0;
    31. 

  31. +		rf_reg_record[CHAIN_0][4].value = rfvalue;
    32. 

  32. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 2);
    33. 

  33. +		rf_reg_record[CHAIN_0][5].bank = 4;
    34. 

  34. +		rf_reg_record[CHAIN_0][5].reg = 2;
    35. 

  35. +		rf_reg_record[CHAIN_0][5].value = rfvalue;
    36. 

  36. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 34);
    37. 

  37. +		rf_reg_record[CHAIN_0][6].bank = 4;
    38. 

  38. +		rf_reg_record[CHAIN_0][6].reg = 34;
    39. 

  39. +		rf_reg_record[CHAIN_0][6].value = rfvalue;
    40. 

  40. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
    41. 

  41. +		rf_reg_record[CHAIN_0][7].bank = 5;
    42. 

  42. +		rf_reg_record[CHAIN_0][7].reg = 3;
    43. 

  43. +		rf_reg_record[CHAIN_0][7].value = rfvalue;
    44. 

  44. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
    45. 

  45. +		rf_reg_record[CHAIN_0][8].bank = 5;
    46. 

  46. +		rf_reg_record[CHAIN_0][8].reg = 4;
    47. 

  47. +		rf_reg_record[CHAIN_0][8].value = rfvalue;
    48. 

  48. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
    49. 

  49. +		rf_reg_record[CHAIN_0][9].bank = 5;
    50. 

  50. +		rf_reg_record[CHAIN_0][9].reg = 17;
    51. 

  51. +		rf_reg_record[CHAIN_0][9].value = rfvalue;
    52. 

  52. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
    53. 

  53. +		rf_reg_record[CHAIN_0][10].bank = 5;
    54. 

  54. +		rf_reg_record[CHAIN_0][10].reg = 18;
    55. 

  55. +		rf_reg_record[CHAIN_0][10].value = rfvalue;
    56. 

  56. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
    57. 

  57. +		rf_reg_record[CHAIN_0][11].bank = 5;
    58. 

  58. +		rf_reg_record[CHAIN_0][11].reg = 19;
    59. 

  59. +		rf_reg_record[CHAIN_0][11].value = rfvalue;
    60. 

  60. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
    61. 

  61. +		rf_reg_record[CHAIN_0][12].bank = 5;
    62. 

  62. +		rf_reg_record[CHAIN_0][12].reg = 20;
    63. 

  63. +		rf_reg_record[CHAIN_0][12].value = rfvalue;
    64. 

  64. +	} else if (chain == CHAIN_1) {
    65. 

  65. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
    66. 

  66. +		rf_reg_record[CHAIN_1][0].bank = 0;
    67. 

  67. +		rf_reg_record[CHAIN_1][0].reg = 1;
    68. 

  68. +		rf_reg_record[CHAIN_1][0].value = rfvalue;
    69. 

  69. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
    70. 

  70. +		rf_reg_record[CHAIN_1][1].bank = 0;
    71. 

  71. +		rf_reg_record[CHAIN_1][1].reg = 2;
    72. 

  72. +		rf_reg_record[CHAIN_1][1].value = rfvalue;
    73. 

  73. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
    74. 

  74. +		rf_reg_record[CHAIN_1][2].bank = 0;
    75. 

  75. +		rf_reg_record[CHAIN_1][2].reg = 35;
    76. 

  76. +		rf_reg_record[CHAIN_1][2].value = rfvalue;
    77. 

  77. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
    78. 

  78. +		rf_reg_record[CHAIN_1][3].bank = 0;
    79. 

  79. +		rf_reg_record[CHAIN_1][3].reg = 42;
    80. 

  80. +		rf_reg_record[CHAIN_1][3].value = rfvalue;
    81. 

  81. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);
    82. 

  82. +		rf_reg_record[CHAIN_1][4].bank = 6;
    83. 

  83. +		rf_reg_record[CHAIN_1][4].reg = 0;
    84. 

  84. +		rf_reg_record[CHAIN_1][4].value = rfvalue;
    85. 

  85. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 2);
    86. 

  86. +		rf_reg_record[CHAIN_1][5].bank = 6;
    87. 

  87. +		rf_reg_record[CHAIN_1][5].reg = 2;
    88. 

  88. +		rf_reg_record[CHAIN_1][5].value = rfvalue;
    89. 

  89. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 34);
    90. 

  90. +		rf_reg_record[CHAIN_1][6].bank = 6;
    91. 

  91. +		rf_reg_record[CHAIN_1][6].reg = 34;
    92. 

  92. +		rf_reg_record[CHAIN_1][6].value = rfvalue;
    93. 

  93. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);
    94. 

  94. +		rf_reg_record[CHAIN_1][7].bank = 7;
    95. 

  95. +		rf_reg_record[CHAIN_1][7].reg = 3;
    96. 

  96. +		rf_reg_record[CHAIN_1][7].value = rfvalue;
    97. 

  97. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
    98. 

  98. +		rf_reg_record[CHAIN_1][8].bank = 7;
    99. 

  99. +		rf_reg_record[CHAIN_1][8].reg = 4;
    100. 

  100. +		rf_reg_record[CHAIN_1][8].value = rfvalue;
    101. 

  101. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);
    102. 

  102. +		rf_reg_record[CHAIN_1][9].bank = 7;
    103. 

  103. +		rf_reg_record[CHAIN_1][9].reg = 17;
    104. 

  104. +		rf_reg_record[CHAIN_1][9].value = rfvalue;
    105. 

  105. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);
    106. 

  106. +		rf_reg_record[CHAIN_1][10].bank = 7;
    107. 

  107. +		rf_reg_record[CHAIN_1][10].reg = 18;
    108. 

  108. +		rf_reg_record[CHAIN_1][10].value = rfvalue;
    109. 

  109. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);
    110. 

  110. +		rf_reg_record[CHAIN_1][11].bank = 7;
    111. 

  111. +		rf_reg_record[CHAIN_1][11].reg = 19;
    112. 

  112. +		rf_reg_record[CHAIN_1][11].value = rfvalue;
    113. 

  113. +		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);
    114. 

  114. +		rf_reg_record[CHAIN_1][12].bank = 7;
    115. 

  115. +		rf_reg_record[CHAIN_1][12].reg = 20;
    116. 

  116. +		rf_reg_record[CHAIN_1][12].value = rfvalue;
    117. 

  117. +	} else {
    118. 

  118. +		rt2x00_warn(rt2x00dev, "Unknown chain = %u\n", chain);
    119. 

  119. +		return;
    120. 

  120. +	}
    121. 

  121. +
    122. 

  122. +	return;
    123. 

  123. +}
    124. 

  124. +EXPORT_SYMBOL_GPL(rt2800_rf_configstore);
    125. 

  125. +
    126. 

  126. +static void rt2800_rf_configrecover(struct rt2x00_dev *rt2x00dev, rf_reg_pair rf_record[][13])
    127. 

  127. +{
    128. 

  128. +	u8 chain_index = 0, record_index = 0;
    129. 

  129. +	u8 bank = 0, rf_register = 0, value = 0;
    130. 

  130. +
    131. 

  131. +	for (chain_index = 0; chain_index < 2; chain_index++) {
    132. 

  132. +		for (record_index = 0; record_index < 13; record_index++) {
    133. 

  133. +			bank = rf_record[chain_index][record_index].bank;
    134. 

  134. +			rf_register = rf_record[chain_index][record_index].reg;
    135. 

  135. +			value = rf_record[chain_index][record_index].value;
    136. 

  136. +			rt2800_rfcsr_write_bank(rt2x00dev, bank, rf_register, value);
    137. 

  137. +			rt2x00_dbg(rt2x00dev, "bank: %d, rf_register: %d, value: %x\n", bank, rf_register, value);
    138. 

  138. +		}
    139. 

  139. +	}
    140. 

  140. +
    141. 

  141. +	return;
    142. 

  142. +}
    143. 

  143. +EXPORT_SYMBOL_GPL(rt2800_rf_configrecover);
    144. 

  144. +
    145. 

  145. +static void rt2800_setbbptonegenerator(struct rt2x00_dev *rt2x00dev)
    146. 

  146. +{
    147. 

  147. +	rt2800_bbp_write(rt2x00dev, 158, 0xAA);
    148. 

  148. +	rt2800_bbp_write(rt2x00dev, 159, 0x00);
    149. 

  149. +
    150. 

  150. +	rt2800_bbp_write(rt2x00dev, 158, 0xAB);
    151. 

  151. +	rt2800_bbp_write(rt2x00dev, 159, 0x0A);
    152. 

  152. +
    153. 

  153. +	rt2800_bbp_write(rt2x00dev, 158, 0xAC);
    154. 

  154. +	rt2800_bbp_write(rt2x00dev, 159, 0x3F);
    155. 

  155. +
    156. 

  156. +	rt2800_bbp_write(rt2x00dev, 158, 0xAD);
    157. 

  157. +	rt2800_bbp_write(rt2x00dev, 159, 0x3F);
    158. 

  158. +
    159. 

  159. +	rt2800_bbp_write(rt2x00dev, 244, 0x40);
    160. 

  160. +
    161. 

  161. +	return;
    162. 

  162. +}
    163. 

  163. +EXPORT_SYMBOL_GPL(rt2800_setbbptonegenerator);
    164. 

  164. +
    165. 

  165. +u32 rt2800_do_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx, u8 read_neg)
    166. 

  166. +{
    167. 

  167. +	u32 macvalue = 0;
    168. 

  168. +	int fftout_i = 0, fftout_q = 0;
    169. 

  169. +	u32 ptmp=0, pint = 0;
    170. 

  170. +	u8 bbp = 0;
    171. 

  171. +	u8 tidxi;
    172. 

  172. +
    173. 

  173. +	rt2800_bbp_write(rt2x00dev, 158, 0x00);
    174. 

  174. +	rt2800_bbp_write(rt2x00dev, 159, 0x9b);
    175. 

  175. +
    176. 

  176. +	bbp = 0x9b;
    177. 

  177. +
    178. 

  178. +	while (bbp == 0x9b) {
    179. 

  179. +		udelay(10);
    180. 

  180. +		bbp = rt2800_bbp_read(rt2x00dev, 159);
    181. 

  181. +		bbp = bbp & 0xff;
    182. 

  182. +	}
    183. 

  183. +
    184. 

  184. +	rt2800_bbp_write(rt2x00dev, 158, 0xba);
    185. 

  185. +	rt2800_bbp_write(rt2x00dev, 159, tidx);
    186. 

  186. +	rt2800_bbp_write(rt2x00dev, 159, tidx);
    187. 

  187. +	rt2800_bbp_write(rt2x00dev, 159, tidx);
    188. 

  188. +
    189. 

  189. +	macvalue = rt2800_register_read(rt2x00dev, 0x057C);
    190. 

  190. +
    191. 

  191. +	fftout_i = (macvalue >> 16);
    192. 

  192. +	fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
    193. 

  193. +	fftout_q = (macvalue & 0xffff);
    194. 

  194. +	fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
    195. 

  195. +	ptmp = (fftout_i * fftout_i);
    196. 

  196. +	ptmp = ptmp + (fftout_q * fftout_q);
    197. 

  197. +	pint = ptmp;
    198. 

  198. +	rt2x00_dbg(rt2x00dev, "I = %d,  Q = %d, power = %x\n", fftout_i, fftout_q, pint);
    199. 

  199. +	if (read_neg) {
    200. 

  200. +		pint = pint >> 1;
    201. 

  201. +		tidxi = 0x40 - tidx;
    202. 

  202. +		tidxi = tidxi & 0x3f;
    203. 

  203. +
    204. 

  204. +		rt2800_bbp_write(rt2x00dev, 158, 0xba);
    205. 

  205. +		rt2800_bbp_write(rt2x00dev, 159, tidxi);
    206. 

  206. +		rt2800_bbp_write(rt2x00dev, 159, tidxi);
    207. 

  207. +		rt2800_bbp_write(rt2x00dev, 159, tidxi);
    208. 

  208. +
    209. 

  209. +		macvalue = rt2800_register_read(rt2x00dev, 0x057C);
    210. 

  210. +
    211. 

  211. +		fftout_i = (macvalue >> 16);
    212. 

  212. +		fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
    213. 

  213. +		fftout_q = (macvalue & 0xffff);
    214. 

  214. +		fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
    215. 

  215. +		ptmp = (fftout_i * fftout_i);
    216. 

  216. +		ptmp = ptmp + (fftout_q * fftout_q);
    217. 

  217. +		ptmp = ptmp >> 1;
    218. 

  218. +		pint = pint + ptmp;
    219. 

  219. +	}
    220. 

  220. +
    221. 

  221. +	return pint;
    222. 

  222. +}
    223. 

  223. +EXPORT_SYMBOL_GPL(rt2800_do_fft_accumulation);
    224. 

  224. +
    225. 

  225. +u32 rt2800_read_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx) {
    226. 

  226. +	u32 macvalue = 0;
    227. 

  227. +	int fftout_i = 0, fftout_q = 0;
    228. 

  228. +	u32 ptmp=0, pint = 0;
    229. 

  229. +
    230. 

  230. +	rt2800_bbp_write(rt2x00dev, 158, 0xBA);
    231. 

  231. +	rt2800_bbp_write(rt2x00dev, 159, tidx);
    232. 

  232. +	rt2800_bbp_write(rt2x00dev, 159, tidx);
    233. 

  233. +	rt2800_bbp_write(rt2x00dev, 159, tidx);
    234. 

  234. +
    235. 

  235. +	macvalue = rt2800_register_read(rt2x00dev, 0x057C);
    236. 

  236. +
    237. 

  237. +	fftout_i = (macvalue >> 16);
    238. 

  238. +	fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
    239. 

  239. +	fftout_q = (macvalue & 0xffff);
    240. 

  240. +	fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
    241. 

  241. +	ptmp = (fftout_i * fftout_i);
    242. 

  242. +	ptmp = ptmp + (fftout_q * fftout_q);
    243. 

  243. +	pint = ptmp;
    244. 

  244. +	rt2x00_info(rt2x00dev, "I = %d,  Q = %d, power = %x\n", fftout_i, fftout_q, pint);
    245. 

  245. +
    246. 

  246. +	return pint;
    247. 

  247. +}
    248. 

  248. +EXPORT_SYMBOL_GPL(rt2800_read_fft_accumulation);
    249. 

  249. +
    250. 

  250. +static void rt2800_write_dc(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc, u8 iorq, u8 dc)
    251. 

  251. +{
    252. 

  252. +	u8 bbp = 0;
    253. 

  253. +
    254. 

  254. +	rt2800_bbp_write(rt2x00dev, 158, 0xb0);
    255. 

  255. +	bbp = alc | 0x80;
    256. 

  256. +	rt2800_bbp_write(rt2x00dev, 159, bbp);
    257. 

  257. +
    258. 

  258. +	if (ch_idx == 0)
    259. 

  259. +		bbp = (iorq == 0) ? 0xb1: 0xb2;
    260. 

  260. +	else
    261. 

  261. +		bbp = (iorq == 0) ? 0xb8: 0xb9;
    262. 

  262. +
    263. 

  263. +	rt2800_bbp_write(rt2x00dev, 158, bbp);
    264. 

  264. +	bbp = dc;
    265. 

  265. +	rt2800_bbp_write(rt2x00dev, 159, bbp);
    266. 

  266. +
    267. 

  267. +	return;
    268. 

  268. +}
    269. 

  269. +EXPORT_SYMBOL_GPL(rt2800_write_dc);
    270. 

  270. +
    271. 

  271. +static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc_idx, u8 dc_result[][RF_ALC_NUM][2])
    272. 

  272. +{
    273. 

  273. +	u32 p0 = 0, p1 = 0, pf = 0;
    274. 

  274. +	char idx0 = 0, idx1 = 0;
    275. 

  275. +	u8 idxf[] = {0x00, 0x00};
    276. 

  276. +	u8 ibit = 0x20;
    277. 

  277. +	u8 iorq;
    278. 

  278. +	char bidx;
    279. 

  279. +
    280. 

  280. +	rt2800_bbp_write(rt2x00dev, 158, 0xb0);
    281. 

  281. +	rt2800_bbp_write(rt2x00dev, 159, 0x80);
    282. 

  282. +
    283. 

  283. +	for (bidx = 5; bidx >= 0; bidx--) {
    284. 

  284. +		for (iorq = 0; iorq <= 1; iorq++) {
    285. 

  285. +			rt2x00_dbg(rt2x00dev, "\n========================================================\n");
    286. 

  286. +
    287. 

  287. +			if (idxf[iorq] == 0x20) {
    288. 

  288. +				idx0 = 0x20;
    289. 

  289. +				p0 = pf;
    290. 

  290. +			} else {
    291. 

  291. +				idx0 = idxf[iorq] - ibit;
    292. 

  292. +				idx0 = idx0 & 0x3F;
    293. 

  293. +				rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx0);
    294. 

  294. +				p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
    295. 

  295. +			}
    296. 

  296. +
    297. 

  297. +			idx1 = idxf[iorq] + ((bidx == 5) ? 0 : ibit);
    298. 

  298. +			idx1 = idx1 & 0x3F;
    299. 

  299. +			rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx1);
    300. 

  300. +			p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
    301. 

  301. +
    302. 

  302. +			rt2x00_dbg(rt2x00dev, "alc=%u, IorQ=%u, idx_final=%2x\n", alc_idx, iorq, idxf[iorq]);
    303. 

  303. +			rt2x00_dbg(rt2x00dev, "p0=%x, p1=%x, pf=%x, idx_0=%x, idx_1=%x, ibit=%x !\n", p0, p1, pf, idx0, idx1, ibit);
    304. 

  304. +
    305. 

  305. +			if ((bidx != 5) && (pf <= p0) && (pf < p1)) {
    306. 

  306. +				pf = pf;
    307. 

  307. +				idxf[iorq] = idxf[iorq];
    308. 

  308. +			} else if (p0 < p1) {
    309. 

  309. +				pf = p0;
    310. 

  310. +				idxf[iorq] = idx0 & 0x3F;
    311. 

  311. +			} else {
    312. 

  312. +				pf = p1;
    313. 

  313. +				idxf[iorq] = idx1 & 0x3F;
    314. 

  314. +			}
    315. 

  315. +			rt2x00_dbg(rt2x00dev, "IorQ=%u, idx_final[%u]:%x, pf:%8x\n", iorq, iorq, idxf[iorq], pf);
    316. 

  316. +
    317. 

  317. +			rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idxf[iorq]);
    318. 

  318. +
    319. 

  319. +		}
    320. 

  320. +		ibit = ibit >> 1;
    321. 

  321. +	}
    322. 

  322. +	dc_result[ch_idx][alc_idx][0] = idxf[0];
    323. 

  323. +	dc_result[ch_idx][alc_idx][1] = idxf[1];
    324. 

  324. +
    325. 

  325. +	return;
    326. 

  326. +}
    327. 

  327. +EXPORT_SYMBOL_GPL(rt2800_loft_search);
    328. 

  328. +
    329. 

  329. +static void rt2800_iq_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 *ges, u8 *pes)
    330. 

  330. +{
    331. 

  331. +	u32 p0 = 0, p1 = 0, pf = 0;
    332. 

  332. +	char perr = 0, gerr = 0, iq_err = 0;
    333. 

  333. +	char pef = 0, gef = 0;
    334. 

  334. +	char psta, pend;
    335. 

  335. +	char gsta, gend;
    336. 

  336. +
    337. 

  337. +	u8 ibit = 0x20;
    338. 

  338. +	u8 first_search = 0x00, touch_neg_max = 0x00;
    339. 

  339. +	char idx0 = 0, idx1 = 0;
    340. 

  340. +	u8 gop;
    341. 

  341. +	u8 bbp = 0;
    342. 

  342. +	char bidx;
    343. 

  343. +
    344. 

  344. +	rt2x00_info(rt2x00dev, "IQCalibration Start!\n");
    345. 

  345. +	for (bidx = 5; bidx >= 1; bidx--) {
    346. 

  346. +		for (gop = 0; gop < 2; gop++) {
    347. 

  347. +			rt2x00_dbg(rt2x00dev, "\n========================================================\n");
    348. 

  348. +
    349. 

  349. +			if ((gop == 1) || (bidx < 4)) {
    350. 

  350. +				if (gop == 0)
    351. 

  351. +					iq_err = gerr;
    352. 

  352. +				else
    353. 

  353. +					iq_err = perr;
    354. 

  354. +
    355. 

  355. +				first_search = (gop == 0) ? (bidx == 3) : (bidx == 5);
    356. 

  356. +				touch_neg_max = (gop) ? ((iq_err & 0x0F) == 0x08) : ((iq_err & 0x3F) == 0x20);
    357. 

  357. +
    358. 

  358. +				if (touch_neg_max) {
    359. 

  359. +					p0 = pf;
    360. 

  360. +					idx0 = iq_err;
    361. 

  361. +				} else {
    362. 

  362. +					idx0 = iq_err - ibit;
    363. 

  363. +					bbp = (ch_idx == 0) ? ((gop == 0) ? 0x28 : 0x29): ((gop == 0) ? 0x46 : 0x47);
    364. 

  364. +
    365. 

  365. +					rt2800_bbp_write(rt2x00dev, 158, bbp);
    366. 

  366. +					rt2800_bbp_write(rt2x00dev, 159, idx0);
    367. 

  367. +
    368. 

  368. +					p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
    369. 

  369. +				}
    370. 

  370. +
    371. 

  371. +				idx1 = iq_err + (first_search ? 0 : ibit);
    372. 

  372. +				idx1 = (gop == 0) ? (idx1 & 0x0F) : (idx1 & 0x3F);
    373. 

  373. +
    374. 

  374. +				bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 : (gop == 0) ? 0x46 : 0x47;
    375. 

  375. +
    376. 

  376. +				rt2800_bbp_write(rt2x00dev, 158, bbp);
    377. 

  377. +				rt2800_bbp_write(rt2x00dev, 159, idx1);
    378. 

  378. +
    379. 

  379. +				p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
    380. 

  380. +
    381. 

  381. +				rt2x00_dbg(rt2x00dev, "p0=%x, p1=%x, pwer_final=%x, idx0=%x, idx1=%x, iq_err=%x, gop=%d, ibit=%x !\n", p0, p1, pf, idx0, idx1, iq_err, gop, ibit);
    382. 

  382. +
    383. 

  383. +				if ((!first_search) && (pf <= p0) && (pf < p1)) {
    384. 

  384. +					pf = pf;
    385. 

  385. +				} else if (p0 < p1) {
    386. 

  386. +					pf = p0;
    387. 

  387. +					iq_err = idx0;
    388. 

  388. +				} else {
    389. 

  389. +					pf = p1;
    390. 

  390. +					iq_err = idx1;
    391. 

  391. +				}
    392. 

  392. +
    393. 

  393. +				bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 : (gop == 0) ? 0x46 : 0x47;
    394. 

  394. +
    395. 

  395. +				rt2800_bbp_write(rt2x00dev, 158, bbp);
    396. 

  396. +				rt2800_bbp_write(rt2x00dev, 159, iq_err);
    397. 

  397. +
    398. 

  398. +				if (gop == 0)
    399. 

  399. +					gerr = iq_err;
    400. 

  400. +				else
    401. 

  401. +					perr = iq_err;
    402. 

  402. +
    403. 

  403. +				rt2x00_dbg(rt2x00dev, "IQCalibration pf=%8x (%2x, %2x) !\n", pf, gerr & 0x0F, perr & 0x3F);
    404. 

  404. +
    405. 

  405. +			}
    406. 

  406. +		}
    407. 

  407. +
    408. 

  408. +		if (bidx > 0)
    409. 

  409. +			ibit = (ibit >> 1);
    410. 

  410. +	}
    411. 

  411. +	gerr = (gerr & 0x08) ? (gerr & 0x0F) - 0x10 : (gerr & 0x0F);
    412. 

  412. +	perr = (perr & 0x20) ? (perr & 0x3F) - 0x40 : (perr & 0x3F);
    413. 

  413. +
    414. 

  414. +	gerr = (gerr < -0x07) ? -0x07 : (gerr > 0x05) ? 0x05 : gerr;
    415. 

  415. +	gsta = gerr - 1;
    416. 

  416. +	gend = gerr + 2;
    417. 

  417. +
    418. 

  418. +	perr = (perr < -0x1f) ? -0x1f : (perr > 0x1d) ? 0x1d : perr;
    419. 

  419. +	psta = perr - 1;
    420. 

  420. +	pend = perr + 2;
    421. 

  421. +
    422. 

  422. +	for (gef = gsta; gef <= gend; gef = gef + 1)
    423. 

  423. +		for (pef = psta; pef <= pend; pef = pef + 1) {
    424. 

  424. +			bbp = (ch_idx == 0) ? 0x28 : 0x46;
    425. 

  425. +			rt2800_bbp_write(rt2x00dev, 158, bbp);
    426. 

  426. +			rt2800_bbp_write(rt2x00dev, 159, gef & 0x0F);
    427. 

  427. +
    428. 

  428. +			bbp = (ch_idx == 0) ? 0x29 : 0x47;
    429. 

  429. +			rt2800_bbp_write(rt2x00dev, 158, bbp);
    430. 

  430. +			rt2800_bbp_write(rt2x00dev, 159, pef & 0x3F);
    431. 

  431. +
    432. 

  432. +			p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
    433. 

  433. +			if ((gef == gsta) && (pef == psta)) {
    434. 

  434. +				pf = p1;
    435. 

  435. +				gerr = gef;
    436. 

  436. +				perr = pef;
    437. 

  437. +			}
    438. 

  438. +			else if (pf > p1){
    439. 

  439. +				pf = p1;
    440. 

  440. +				gerr = gef;
    441. 

  441. +				perr = pef;
    442. 

  442. +			}
    443. 

  443. +			rt2x00_dbg(rt2x00dev, "Fine IQCalibration p1=%8x pf=%8x (%2x, %2x) !\n", p1, pf, gef & 0x0F, pef & 0x3F);
    444. 

  444. +		}
    445. 

  445. +
    446. 

  446. +	ges[ch_idx] = gerr & 0x0F;
    447. 

  447. +	pes[ch_idx] = perr & 0x3F;
    448. 

  448. +
    449. 

  449. +	rt2x00_info(rt2x00dev, "IQCalibration Done! CH = %u, (gain=%2x, phase=%2x)\n", ch_idx, gerr & 0x0F, perr & 0x3F);
    450. 

  450. +
    451. 

  451. +	return;
    452. 

  452. +}
    453. 

  453. +EXPORT_SYMBOL_GPL(rt2800_iq_search);
    454. 

  454. +
    455. 

  455. +static void rt2800_rf_aux_tx0_loopback(struct rt2x00_dev *rt2x00dev)
    456. 

  456. +{
    457. 

  457. +	rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x21);
    458. 

  458. +	rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x10);
    459. 

  459. +	rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
    460. 

  460. +	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x1b);
    461. 

  461. +	rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, 0x81);
    462. 

  462. +	rt2800_rfcsr_write_bank(rt2x00dev, 4, 2, 0x81);
    463. 

  463. +	rt2800_rfcsr_write_bank(rt2x00dev, 4, 34, 0xee);
    464. 

  464. +	rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, 0x2d);
    465. 

  465. +	rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x2d);
    466. 

  466. +	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80);
    467. 

  467. +	rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xd7);
    468. 

  468. +	rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0xa2);
    469. 

  469. +	rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20);
    470. 

  470. +}
    471. 

  471. +EXPORT_SYMBOL_GPL(rt2800_rf_aux_tx0_loopback);
    472. 

  472. +
    473. 

  473. +static void rt2800_rf_aux_tx1_loopback(struct rt2x00_dev *rt2x00dev)
    474. 

  474. +{
    475. 

  475. +	rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x22);
    476. 

  476. +	rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x20);
    477. 

  477. +	rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
    478. 

  478. +	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x4b);
    479. 

  479. +	rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, 0x81);
    480. 

  480. +	rt2800_rfcsr_write_bank(rt2x00dev, 6, 2, 0x81);
    481. 

  481. +	rt2800_rfcsr_write_bank(rt2x00dev, 6, 34, 0xee);
    482. 

  482. +	rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, 0x2d);
    483. 

  483. +	rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, 0x2d);
    484. 

  484. +	rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, 0x80);
    485. 

  485. +	rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, 0xd7);
    486. 

  486. +	rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, 0xa2);
    487. 

  487. +	rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, 0x20);
    488. 

  488. +}
    489. 

  489. +EXPORT_SYMBOL_GPL(rt2800_rf_aux_tx1_loopback);
    490. 

  490. +
    491. 

  491. +void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev)
    492. 

  492. +{
    493. 

  493. +	rf_reg_pair rf_store[CHAIN_NUM][13];
    494. 

  494. +	u32 macorg1 = 0;
    495. 

  495. +	u32 macorg2 = 0;
    496. 

  496. +	u32 macorg3 = 0;
    497. 

  497. +	u32 macorg4 = 0;
    498. 

  498. +	u32 macorg5 = 0;
    499. 

  499. +	u32 orig528 = 0;
    500. 

  500. +	u32 orig52c = 0;
    501. 

  501. +
    502. 

  502. +	u32 savemacsysctrl = 0, mtxcycle = 0;
    503. 

  503. +	u32 macvalue = 0;
    504. 

  504. +	u32 mac13b8 = 0;
    505. 

  505. +	u32 p0 = 0, p1 = 0;
    506. 

  506. +	u32 p0_idx10 = 0, p1_idx10 = 0;
    507. 

  507. +
    508. 

  508. +	u8 rfvalue;
    509. 

  509. +	u8 loft_dc_search_result[CHAIN_NUM][RF_ALC_NUM][2];
    510. 

  510. +	u8 ger[CHAIN_NUM], per[CHAIN_NUM];
    511. 

  511. +	u8 rf_gain[] = {0x00, 0x01, 0x02, 0x04, 0x08, 0x0c};
    512. 

  512. +	u8 rfvga_gain_table[] = {0x24, 0x25, 0x26, 0x27, 0x28, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3F};
    513. 

  513. +
    514. 

  514. +	u8 vga_gain[] = {14, 14};
    515. 

  515. +	u8 bbp_2324gain[] = {0x16, 0x14, 0x12, 0x10, 0x0c, 0x08};
    516. 

  516. +	u8 bbp = 0, ch_idx = 0, rf_alc_idx = 0, idx = 0;
    517. 

  517. +	u8 bbpr30, rfb0r39, rfb0r42;
    518. 

  518. +	u8 bbpr1;
    519. 

  519. +	u8 bbpr4;
    520. 

  520. +	u8 bbpr241, bbpr242;
    521. 

  521. +	u8 count_step;
    522. 

  522. +
    523. 

  523. +	savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
    524. 

  524. +	macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
    525. 

  525. +	macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
    526. 

  526. +	macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
    527. 

  527. +	macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
    528. 

  528. +	macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
    529. 

  529. +	mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
    530. 

  530. +	orig528 = rt2800_register_read(rt2x00dev, RF_CONTROL2);
    531. 

  531. +	orig52c = rt2800_register_read(rt2x00dev, RF_BYPASS2);
    532. 

  532. +
    533. 

  533. +	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
    534. 

  534. +	macvalue &= (~0x04);
    535. 

  535. +	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
    536. 

  536. +
    537. 

  537. +	for (mtxcycle = 0; mtxcycle < 10000; mtxcycle++) {
    538. 

  538. +		macvalue = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
    539. 

  539. +		if (macvalue & 0x01)
    540. 

  540. +			udelay(50);
    541. 

  541. +		else
    542. 

  542. +			break;
    543. 

  543. +	}
    544. 

  544. +
    545. 

  545. +	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
    546. 

  546. +	macvalue &= (~0x08);
    547. 

  547. +	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
    548. 

  548. +
    549. 

  549. +	for (mtxcycle = 0; mtxcycle < 10000; mtxcycle++) {
    550. 

  550. +		macvalue = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
    551. 

  551. +		if (macvalue & 0x02)
    552. 

  552. +			udelay(50);
    553. 

  553. +		else
    554. 

  554. +			break;
    555. 

  555. +	}
    556. 

  556. +
    557. 

  557. +	for (ch_idx = 0; ch_idx < 2; ch_idx++) {
    558. 

  558. +		rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
    559. 

  559. +	}
    560. 

  560. +
    561. 

  561. +	bbpr30 = rt2800_bbp_read(rt2x00dev, 30);
    562. 

  562. +	rfb0r39 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 39);
    563. 

  563. +	rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
    564. 

  564. +
    565. 

  565. +	rt2800_bbp_write(rt2x00dev, 30, 0x1F);
    566. 

  566. +	rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, 0x80);
    567. 

  567. +	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x5B);
    568. 

  568. +
    569. 

  569. +	rt2800_bbp_write(rt2x00dev, 23, 0x00);
    570. 

  570. +	rt2800_bbp_write(rt2x00dev, 24, 0x00);
    571. 

  571. +
    572. 

  572. +	rt2800_setbbptonegenerator(rt2x00dev);
    573. 

  573. +
    574. 

  574. +	for (ch_idx = 0; ch_idx < 2; ch_idx ++) {
    575. 

  575. +		rt2800_bbp_write(rt2x00dev, 23, 0x00);
    576. 

  576. +		rt2800_bbp_write(rt2x00dev, 24, 0x00);
    577. 

  577. +		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00);
    578. 

  578. +		rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
    579. 

  579. +		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
    580. 

  580. +		rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
    581. 

  581. +		rt2800_register_write(rt2x00dev, 0x13b8, 0x10);
    582. 

  582. +		udelay(1);
    583. 

  583. +
    584. 

  584. +		if (ch_idx == 0) {
    585. 

  585. +			rt2800_rf_aux_tx0_loopback(rt2x00dev);
    586. 

  586. +		} else {
    587. 

  587. +			rt2800_rf_aux_tx1_loopback(rt2x00dev);
    588. 

  588. +		}
    589. 

  589. +		udelay(1);
    590. 

  590. +
    591. 

  591. +		if (ch_idx == 0) {
    592. 

  592. +			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
    593. 

  593. +		} else {
    594. 

  594. +			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
    595. 

  595. +		}
    596. 

  596. +
    597. 

  597. +		rt2800_bbp_write(rt2x00dev, 158, 0x05);
    598. 

  598. +		rt2800_bbp_write(rt2x00dev, 159, 0x00);
    599. 

  599. +
    600. 

  600. +		rt2800_bbp_write(rt2x00dev, 158, 0x01);
    601. 

  601. +		if (ch_idx == 0)
    602. 

  602. +			rt2800_bbp_write(rt2x00dev, 159, 0x00);
    603. 

  603. +		else
    604. 

  604. +			rt2800_bbp_write(rt2x00dev, 159, 0x01);
    605. 

  605. +
    606. 

  606. +		vga_gain[ch_idx] = 18;
    607. 

  607. +		for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
    608. 

  608. +			rt2800_bbp_write(rt2x00dev, 23, bbp_2324gain[rf_alc_idx]);
    609. 

  609. +			rt2800_bbp_write(rt2x00dev, 24, bbp_2324gain[rf_alc_idx]);
    610. 

  610. +
    611. 

  611. +			macvalue = rt2800_register_read(rt2x00dev, RF_CONTROL3);
    612. 

  612. +			macvalue &= (~0x0000F1F1);
    613. 

  613. +			macvalue |= (rf_gain[rf_alc_idx] << 4);
    614. 

  614. +			macvalue |= (rf_gain[rf_alc_idx] << 12);
    615. 

  615. +			rt2800_register_write(rt2x00dev, RF_CONTROL3, macvalue);
    616. 

  616. +			macvalue = (0x0000F1F1);
    617. 

  617. +			rt2800_register_write(rt2x00dev, RF_BYPASS3, macvalue);
    618. 

  618. +
    619. 

  619. +			if (rf_alc_idx == 0) {
    620. 

  620. +				rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x21);
    621. 

  621. +				for (;vga_gain[ch_idx] > 0;vga_gain[ch_idx] = vga_gain[ch_idx] - 2) {
    622. 

  622. +					rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
    623. 

  623. +					rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
    624. 

  624. +					rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
    625. 

  625. +					rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
    626. 

  626. +					rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
    627. 

  627. +					p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
    628. 

  628. +					rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x21);
    629. 

  629. +					p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
    630. 

  630. +					rt2x00_dbg(rt2x00dev, "LOFT AGC %d %d\n", p0, p1);
    631. 

  631. +					if ((p0 < 7000*7000) && (p1 < (7000*7000))) {
    632. 

  632. +						break;
    633. 

  633. +					}
    634. 

  634. +				}
    635. 

  635. +
    636. 

  636. +				rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
    637. 

  637. +				rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
    638. 

  638. +
    639. 

  639. +				rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n",vga_gain[ch_idx], rfvga_gain_table[vga_gain[ch_idx]]);
    640. 

  640. +
    641. 

  641. +				if (vga_gain[ch_idx] < 0)
    642. 

  642. +					vga_gain[ch_idx] = 0;
    643. 

  643. +		 	}
    644. 

  644. +
    645. 

  645. +			rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
    646. 

  646. +
    647. 

  647. +			rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
    648. 

  648. +			rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
    649. 

  649. +
    650. 

  650. +			rt2800_loft_search(rt2x00dev, ch_idx, rf_alc_idx, loft_dc_search_result);
    651. 

  651. +		}
    652. 

  652. +	}
    653. 

  653. +
    654. 

  654. +	for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
    655. 

  655. +		for (idx = 0; idx < 4; idx++) {
    656. 

  656. +			rt2800_bbp_write(rt2x00dev, 158, 0xB0);
    657. 

  657. +			bbp = (idx<<2) + rf_alc_idx;
    658. 

  658. +			rt2800_bbp_write(rt2x00dev, 159, bbp);
    659. 

  659. +			rt2x00_dbg(rt2x00dev, " ALC %2x,", bbp);
    660. 

  660. +
    661. 

  661. +			rt2800_bbp_write(rt2x00dev, 158, 0xb1);
    662. 

  662. +			bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x00];
    663. 

  663. +			bbp = bbp & 0x3F;
    664. 

  664. +			rt2800_bbp_write(rt2x00dev, 159, bbp);
    665. 

  665. +			rt2x00_dbg(rt2x00dev, " I0 %2x,", bbp);
    666. 

  666. +
    667. 

  667. +			rt2800_bbp_write(rt2x00dev, 158, 0xb2);
    668. 

  668. +			bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x01];
    669. 

  669. +			bbp = bbp & 0x3F;
    670. 

  670. +			rt2800_bbp_write(rt2x00dev, 159, bbp);
    671. 

  671. +			rt2x00_dbg(rt2x00dev, " Q0 %2x,", bbp);
    672. 

  672. +
    673. 

  673. +			rt2800_bbp_write(rt2x00dev, 158, 0xb8);
    674. 

  674. +			bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x00];
    675. 

  675. +			bbp = bbp & 0x3F;
    676. 

  676. +			rt2800_bbp_write(rt2x00dev, 159, bbp);
    677. 

  677. +			rt2x00_dbg(rt2x00dev, " I1 %2x,", bbp);
    678. 

  678. +
    679. 

  679. +			rt2800_bbp_write(rt2x00dev, 158, 0xb9);
    680. 

  680. +			bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x01];
    681. 

  681. +			bbp = bbp & 0x3F;
    682. 

  682. +			rt2800_bbp_write(rt2x00dev, 159, bbp);
    683. 

  683. +			rt2x00_dbg(rt2x00dev, " Q1 %2x\n", bbp);
    684. 

  684. +		}
    685. 

  685. +	}
    686. 

  686. +
    687. 

  687. +	rt2800_bbp_write(rt2x00dev, 23, 0x00);
    688. 

  688. +	rt2800_bbp_write(rt2x00dev, 24, 0x00);
    689. 

  689. +
    690. 

  690. +	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
    691. 

  691. +
    692. 

  692. +	rt2800_bbp_write(rt2x00dev, 158, 0x00);
    693. 

  693. +	rt2800_bbp_write(rt2x00dev, 159, 0x00);
    694. 

  694. +
    695. 

  695. +	bbp = 0x00;
    696. 

  696. +	rt2800_bbp_write(rt2x00dev, 244, 0x00);
    697. 

  697. +
    698. 

  698. +	rt2800_bbp_write(rt2x00dev, 21, 0x01);
    699. 

  699. +	udelay(1);
    700. 

  700. +	rt2800_bbp_write(rt2x00dev, 21, 0x00);
    701. 

  701. +
    702. 

  702. +	rt2800_rf_configrecover(rt2x00dev, rf_store);
    703. 

  703. +
    704. 

  704. +	rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
    705. 

  705. +	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
    706. 

  706. +	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
    707. 

  707. +	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
    708. 

  708. +	rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
    709. 

  709. +	udelay(1);
    710. 

  710. +	rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
    711. 

  711. +	rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
    712. 

  712. +	rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
    713. 

  713. +	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
    714. 

  714. +	rt2800_register_write(rt2x00dev, RF_CONTROL2, orig528);
    715. 

  715. +	rt2800_register_write(rt2x00dev, RF_BYPASS2, orig52c);
    716. 

  716. +	rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
    717. 

  717. +
    718. 

  718. +	rt2x00_info(rt2x00dev, "LOFT Calibration Done!\n");
    719. 

  719. +
    720. 

  720. +	savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
    721. 

  721. +	macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
    722. 

  722. +	macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
    723. 

  723. +	macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
    724. 

  724. +	macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
    725. 

  725. +	macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
    726. 

  726. +
    727. 

  727. +	bbpr1 = rt2800_bbp_read(rt2x00dev, 1);
    728. 

  728. +	bbpr4 = rt2800_bbp_read(rt2x00dev, 4);
    729. 

  729. +	bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
    730. 

  730. +	bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
    731. 

  731. +	mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
    732. 

  732. +
    733. 

  733. +	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
    734. 

  734. +	macvalue &= (~0x04);
    735. 

  735. +	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
    736. 

  736. +	for (mtxcycle = 0; mtxcycle < 10000; mtxcycle++) {
    737. 

  737. +		macvalue = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
    738. 

  738. +		if (macvalue & 0x01)
    739. 

  739. +			udelay(50);
    740. 

  740. +		else
    741. 

  741. +			break;
    742. 

  742. +	}
    743. 

  743. +
    744. 

  744. +	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
    745. 

  745. +	macvalue &= (~0x08);
    746. 

  746. +	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
    747. 

  747. +	for (mtxcycle = 0; mtxcycle < 10000; mtxcycle++) {
    748. 

  748. +		macvalue = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
    749. 

  749. +		if (macvalue & 0x02)
    750. 

  750. +			udelay(50);
    751. 

  751. +		else
    752. 

  752. +			break;
    753. 

  753. +	}
    754. 

  754. +
    755. 

  755. +	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
    756. 

  756. +		rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000101);
    757. 

  757. +		rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
    758. 

  758. +	}
    759. 

  759. +
    760. 

  760. +	rt2800_bbp_write(rt2x00dev, 23, 0x00);
    761. 

  761. +	rt2800_bbp_write(rt2x00dev, 24, 0x00);
    762. 

  762. +
    763. 

  763. +	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
    764. 

  764. +		rt2800_bbp_write(rt2x00dev, 4, bbpr4 & (~0x18));
    765. 

  765. +		rt2800_bbp_write(rt2x00dev, 21, 0x01);
    766. 

  766. +		udelay(1);
    767. 

  767. +		rt2800_bbp_write(rt2x00dev, 21, 0x00);
    768. 

  768. +
    769. 

  769. +		rt2800_bbp_write(rt2x00dev, 241, 0x14);
    770. 

  770. +		rt2800_bbp_write(rt2x00dev, 242, 0x80);
    771. 

  771. +		rt2800_bbp_write(rt2x00dev, 244, 0x31);
    772. 

  772. +	} else {
    773. 

  773. +		rt2800_setbbptonegenerator(rt2x00dev);
    774. 

  774. +	}
    775. 

  775. +
    776. 

  776. +	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
    777. 

  777. +	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
    778. 

  778. +	udelay(1);
    779. 

  779. +
    780. 

  780. +	rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
    781. 

  781. +
    782. 

  782. +	if (!test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
    783. 

  783. +		rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000000);
    784. 

  784. +		rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
    785. 

  785. +	}
    786. 

  786. +
    787. 

  787. +	rt2800_register_write(rt2x00dev, 0x13b8, 0x00000010);
    788. 

  788. +
    789. 

  789. +	for (ch_idx = 0; ch_idx < 2; ch_idx++) {
    790. 

  790. +		rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
    791. 

  791. +	}
    792. 

  792. +
    793. 

  793. +	rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x3B);
    794. 

  794. +	rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x3B);
    795. 

  795. +
    796. 

  796. +	rt2800_bbp_write(rt2x00dev, 158, 0x03);
    797. 

  797. +	rt2800_bbp_write(rt2x00dev, 159, 0x60);
    798. 

  798. +	rt2800_bbp_write(rt2x00dev, 158, 0xB0);
    799. 

  799. +	rt2800_bbp_write(rt2x00dev, 159, 0x80);
    800. 

  800. +
    801. 

  801. +	for (ch_idx = 0; ch_idx < 2; ch_idx ++) {
    802. 

  802. +		rt2800_bbp_write(rt2x00dev, 23, 0x00);
    803. 

  803. +		rt2800_bbp_write(rt2x00dev, 24, 0x00);
    804. 

  804. +
    805. 

  805. +		if (ch_idx == 0) {
    806. 

  806. +			rt2800_bbp_write(rt2x00dev, 158, 0x01);
    807. 

  807. +			rt2800_bbp_write(rt2x00dev, 159, 0x00);
    808. 

  808. +			if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
    809. 

  809. +				bbp = bbpr1 & (~0x18);
    810. 

  810. +				bbp = bbp | 0x00;
    811. 

  811. +				rt2800_bbp_write(rt2x00dev, 1, bbp);
    812. 

  812. +			}
    813. 

  813. +			rt2800_rf_aux_tx0_loopback(rt2x00dev);
    814. 

  814. +			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
    815. 

  815. +		} else {
    816. 

  816. +			rt2800_bbp_write(rt2x00dev, 158, 0x01);
    817. 

  817. +			rt2800_bbp_write(rt2x00dev, 159, 0x01);
    818. 

  818. +			if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) {
    819. 

  819. +				bbp = bbpr1 & (~0x18);
    820. 

  820. +				bbp = bbp | 0x08;
    821. 

  821. +				rt2800_bbp_write(rt2x00dev, 1, bbp);
    822. 

  822. +			}
    823. 

  823. +			rt2800_rf_aux_tx1_loopback(rt2x00dev);
    824. 

  824. +			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
    825. 

  825. +		}
    826. 

  826. +
    827. 

  827. +		rt2800_bbp_write(rt2x00dev, 158, 0x05);
    828. 

  828. +		rt2800_bbp_write(rt2x00dev, 159, 0x04);
    829. 

  829. +
    830. 

  830. +		bbp = (ch_idx == 0) ? 0x28 : 0x46;
    831. 

  831. +		rt2800_bbp_write(rt2x00dev, 158, bbp);
    832. 

  832. +		rt2800_bbp_write(rt2x00dev, 159, 0x00);
    833. 

  833. +
    834. 

  834. +		if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
    835. 

  835. +			rt2800_bbp_write(rt2x00dev, 23, 0x06);
    836. 

  836. +			rt2800_bbp_write(rt2x00dev, 24, 0x06);
    837. 

  837. +			count_step = 1;
    838. 

  838. +		} else {
    839. 

  839. +			rt2800_bbp_write(rt2x00dev, 23, 0x1F);
    840. 

  840. +			rt2800_bbp_write(rt2x00dev, 24, 0x1F);
    841. 

  841. +			count_step = 2;
    842. 

  842. +		}
    843. 

  843. +
    844. 

  844. +		for (;vga_gain[ch_idx] < 19; vga_gain[ch_idx]=(vga_gain[ch_idx] + count_step)) {
    845. 

  845. +			rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
    846. 

  846. +			rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
    847. 

  847. +			rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
    848. 

  848. +
    849. 

  849. +			bbp = (ch_idx == 0) ? 0x29 : 0x47;
    850. 

  850. +			rt2800_bbp_write(rt2x00dev, 158, bbp);
    851. 

  851. +			rt2800_bbp_write(rt2x00dev, 159, 0x00);
    852. 

  852. +			p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
    853. 

  853. +			if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
    854. 

  854. +				p0_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
    855. 

  855. +			}
    856. 

  856. +
    857. 

  857. +			bbp = (ch_idx == 0) ? 0x29 : 0x47;
    858. 

  858. +			rt2800_bbp_write(rt2x00dev, 158, bbp);
    859. 

  859. +			rt2800_bbp_write(rt2x00dev, 159, 0x21);
    860. 

  860. +			p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
    861. 

  861. +			if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) {
    862. 

  862. +				p1_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
    863. 

  863. +			}
    864. 

  864. +
    865. 

  865. +			rt2x00_dbg(rt2x00dev, "IQ AGC %d %d\n", p0, p1);
    866. 

  866. +
    867. 

  867. +			if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
    868. 

  868. +				rt2x00_dbg(rt2x00dev, "IQ AGC IDX 10 %d %d\n", p0_idx10, p1_idx10);
    869. 

  869. +				if ((p0_idx10 > 7000*7000) || (p1_idx10 > 7000*7000)) {
    870. 

  870. +					if (vga_gain[ch_idx]!=0)
    871. 

  871. +						vga_gain[ch_idx] = vga_gain[ch_idx]-1;
    872. 

  872. +					break;
    873. 

  873. +				}
    874. 

  874. +			}
    875. 

  875. +
    876. 

  876. +			if ((p0 > 2500*2500) || (p1 > 2500*2500)) {
    877. 

  877. +				break;
    878. 

  878. +			}
    879. 

  879. +		}
    880. 

  880. +
    881. 

  881. +		if (vga_gain[ch_idx] > 18)
    882. 

  882. +			vga_gain[ch_idx] = 18;
    883. 

  883. +		rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n",vga_gain[ch_idx], rfvga_gain_table[vga_gain[ch_idx]]);
    884. 

  884. +
    885. 

  885. +		bbp = (ch_idx == 0) ? 0x29 : 0x47;
    886. 

  886. +		rt2800_bbp_write(rt2x00dev, 158, bbp);
    887. 

  887. +		rt2800_bbp_write(rt2x00dev, 159, 0x00);
    888. 

  888. +
    889. 

  889. +		rt2800_iq_search(rt2x00dev, ch_idx, ger, per);
    890. 

  890. +	}
    891. 

  891. +
    892. 

  892. +	rt2800_bbp_write(rt2x00dev, 23, 0x00);
    893. 

  893. +	rt2800_bbp_write(rt2x00dev, 24, 0x00);
    894. 

  894. +	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
    895. 

  895. +
    896. 

  896. +	rt2800_bbp_write(rt2x00dev, 158, 0x28);
    897. 

  897. +	bbp = ger[CHAIN_0] & 0x0F;
    898. 

  898. +	rt2800_bbp_write(rt2x00dev, 159, bbp);
    899. 

  899. +
    900. 

  900. +	rt2800_bbp_write(rt2x00dev, 158, 0x29);
    901. 

  901. +	bbp = per[CHAIN_0] & 0x3F;
    902. 

  902. +	rt2800_bbp_write(rt2x00dev, 159, bbp);
    903. 

  903. +
    904. 

  904. +	rt2800_bbp_write(rt2x00dev, 158, 0x46);
    905. 

  905. +	bbp = ger[CHAIN_1] & 0x0F;
    906. 

  906. +	rt2800_bbp_write(rt2x00dev, 159, bbp);
    907. 

  907. +
    908. 

  908. +	rt2800_bbp_write(rt2x00dev, 158, 0x47);
    909. 

  909. +	bbp = per[CHAIN_1] & 0x3F;
    910. 

  910. +	rt2800_bbp_write(rt2x00dev, 159, bbp);
    911. 

  911. +
    912. 

  912. +	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
    913. 

  913. +		rt2800_bbp_write(rt2x00dev, 1, bbpr1);
    914. 

  914. +		rt2800_bbp_write(rt2x00dev, 241, bbpr241);
    915. 

  915. +		rt2800_bbp_write(rt2x00dev, 242, bbpr242);
    916. 

  916. +	}
    917. 

  917. +	rt2800_bbp_write(rt2x00dev, 244, 0x00);
    918. 

  918. +
    919. 

  919. +	rt2800_bbp_write(rt2x00dev, 158, 0x00);
    920. 

  920. +	rt2800_bbp_write(rt2x00dev, 159, 0x00);
    921. 

  921. +	rt2800_bbp_write(rt2x00dev, 158, 0xB0);
    922. 

  922. +	rt2800_bbp_write(rt2x00dev, 159, 0x00);
    923. 

  923. +
    924. 

  924. +	rt2800_bbp_write(rt2x00dev, 30, bbpr30);
    925. 

  925. +	rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, rfb0r39);
    926. 

  926. +	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
    927. 

  927. +
    928. 

  928. +	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
    929. 

  929. +		rt2800_bbp_write(rt2x00dev, 4, bbpr4);
    930. 

  930. +	}
    931. 

  931. +
    932. 

  932. +	rt2800_bbp_write(rt2x00dev, 21, 0x01);
    933. 

  933. +	udelay(1);
    934. 

  934. +	rt2800_bbp_write(rt2x00dev, 21, 0x00);
    935. 

  935. +
    936. 

  936. +	rt2800_rf_configrecover(rt2x00dev, rf_store);
    937. 

  937. +
    938. 

  938. +	rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
    939. 

  939. +	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
    940. 

  940. +	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
    941. 

  941. +	rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
    942. 

  942. +	udelay(1);
    943. 

  943. +	rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
    944. 

  944. +	rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
    945. 

  945. +	rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
    946. 

  946. +	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
    947. 

  947. +	rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
    948. 

  948. +
    949. 

  949. +	rt2x00_info(rt2x00dev, "TX IQ Calibration Done!\n");
    950. 

  950. +
    951. 

  951. +	return;
    952. 

  952. +}
    953. 

  953. +EXPORT_SYMBOL_GPL(rt2800_loft_iq_calibration);
    954. 

  954. +
    955. 

  955.  static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
    956. 

  956.  				       bool set_bw, bool is_ht40)
    957. 

  957.  {
    958. 

  958. @@ -9612,6 +10560,7 @@ static void rt2800_init_rfcsr_6352(struc
    959. 

  959.  	rt2800_rxdcoc_calibration(rt2x00dev);
    960. 

  960.  	rt2800_bw_filter_calibration(rt2x00dev, true);
    961. 

  961.  	rt2800_bw_filter_calibration(rt2x00dev, false);
    962. 

  962. +	rt2800_loft_iq_calibration(rt2x00dev);
    963. 

  963.  	rt2800_rxiq_calibration(rt2x00dev);
    964. 

  964.  }
    965. 

  965.  
    966. 

  966. --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
    967. 

  967. +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
    968. 

  968. @@ -28,6 +28,16 @@
    969. 

  969.  #define WCID_START	33
    970. 

  970.  #define WCID_END	222
    971. 

  971.  #define STA_IDS_SIZE	(WCID_END - WCID_START + 2)
    972. 

  972. +#define CHAIN_0		0x0
    973. 

  973. +#define CHAIN_1		0x1
    974. 

  974. +#define RF_ALC_NUM	6
    975. 

  975. +#define CHAIN_NUM	2
    976. 

  976. +
    977. 

  977. +typedef struct rf_reg_pair {
    978. 

  978. +	u8 bank;
    979. 

  979. +	u8 reg;
    980. 

  980. +	u8 value;
    981. 

  981. +} rf_reg_pair;
    982. 

  982.  
    983. 

  983.  /* RT2800 driver data structure */
    984. 

  984.  struct rt2800_drv_data {
    985. 

  985. @@ -248,6 +258,7 @@ int rt2800_calcrcalibrationcode(struct r
    986. 

  986.  void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev);
    987. 

  987.  void rt2800_rxdcoc_calibration(struct rt2x00_dev *rt2x00dev);
    988. 

  988.  void rt2800_rxiq_calibration(struct rt2x00_dev *rt2x00dev);
    989. 

  989. +void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev);
    990. 

  990.  
    991. 

  991.  int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev);
    992. 

  992.  void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev);
    993. 

  993. --- a/drivers/net/wireless/ralink/rt2x00/rt2x00.h
    994. 

  994. +++ b/drivers/net/wireless/ralink/rt2x00/rt2x00.h
    995. 

  995. @@ -577,6 +577,7 @@ struct rt2x00lib_ops {
    996. 

  996.  	void (*r_calibration) (struct rt2x00_dev *rt2x00dev);
    997. 

  997.  	void (*rxdcoc_calibration) (struct rt2x00_dev *rt2x00dev);
    998. 

  998.  	void (*rxiq_calibration) (struct rt2x00_dev *rt2x00dev);
    999. 

  999. +	void (*loft_iq_calibration) (struct rt2x00_dev *rt2x00dev);
    1000. 

  1000.  
    1001. 

  1001.  	/*
    1002. 

  1002.  	 * Data queue handlers.
    1003.