0002-02-v5.5-ARM-dts-qcom-ipq4019-Add-SDHCI-controller-node.patch 1.2 KB

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  1. From 04b3b72b5b8fdb883bfdc619cb29b03641b1cc6a Mon Sep 17 00:00:00 2001
  2. From: Robert Marko <[email protected]>
  3. Date: Thu, 15 Aug 2019 19:28:23 +0200
  4. Subject: [PATCH] ARM: dts: qcom: ipq4019: Add SDHCI controller node
  5. IPQ4019 has a built in SD/eMMC controller which is supported by the
  6. SDHCI MSM driver, by the "qcom,sdhci-msm-v4" binding.
  7. So lets add the appropriate node for it.
  8. Signed-off-by: Robert Marko <[email protected]>
  9. Signed-off-by: Bjorn Andersson <[email protected]>
  10. ---
  11. arch/arm/boot/dts/qcom-ipq4019.dtsi | 12 ++++++++++++
  12. 1 file changed, 12 insertions(+)
  13. --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
  14. +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
  15. @@ -206,6 +206,18 @@
  16. interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
  17. };
  18. + sdhci: sdhci@7824900 {
  19. + compatible = "qcom,sdhci-msm-v4";
  20. + reg = <0x7824900 0x11c>, <0x7824000 0x800>;
  21. + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
  22. + interrupt-names = "hc_irq", "pwr_irq";
  23. + bus-width = <8>;
  24. + clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>,
  25. + <&gcc GCC_DCD_XO_CLK>;
  26. + clock-names = "core", "iface", "xo";
  27. + status = "disabled";
  28. + };
  29. +
  30. blsp_dma: dma@7884000 {
  31. compatible = "qcom,bam-v1.7.0";
  32. reg = <0x07884000 0x23000>;