uboot-lantiq: update to v2013.10

Patches created from tree:
[email protected]:danielschwierzeck/u-boot-lantiq.git
v2013.10..u-boot-lantiq-v2013.10-openwrt4

Signed-off-by: Daniel Schwierzeck <[email protected]>

SVN-Revision: 40482

package/boot/uboot-lantiq/Makefile

@@ -8,7 +8,7 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=u-boot
-PKG_VERSION:=2013.01
+PKG_VERSION:=2013.10
 PKG_RELEASE:=1
 
 PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
@@ -16,7 +16,7 @@ PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
 PKG_SOURCE_URL:= \
 	http://mirror2.openwrt.org/sources \
 	ftp://ftp.denx.de/pub/u-boot
-PKG_MD5SUM:=e58a8a7f78972248190d83de0dc362ce
+PKG_MD5SUM:=a076a044b64371edc52f7e562b13f6b2
 PKG_TARGETS:=bin
 
 PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)

package/boot/uboot-lantiq/README

@@ -0,0 +1,6 @@
+# How to refresh patches
+
+$ git clone [email protected]:danielschwierzeck/u-boot-lantiq.git
+$ mkdir -p $OPENWRT_ROOT/packages/boot/uboot-lantiq/patches
+$ cd u-boot-lantiq.git
+$ git format-patch -p -k --no-renames --no-binary -o $OPENWRT_ROOT/package/boot/uboot-lantiq/patches v2013.10..u-boot-lantiq-v2013.10-openwrtN

package/boot/uboot-lantiq/patches/0001-sf-fix-out-of-order-calls-for-spi_claim_bus-and-spi_.patch

@@ -0,0 +1,175 @@
+From 909840ef844013379e5ec399c1e76c65d1a6eb1d Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <[email protected]>
+Date: Sat, 12 Oct 2013 21:09:47 +0200
+Subject: sf: fix out-of-order calls for spi_claim_bus and spi_release_bus
+
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
+index 108665f..d34747b 100644
+--- a/drivers/mtd/spi/sf_ops.c
++++ b/drivers/mtd/spi/sf_ops.c
+@@ -132,12 +132,6 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
+ 	if (buf == NULL)
+ 		timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
+ 
+-	ret = spi_claim_bus(flash->spi);
+-	if (ret) {
+-		debug("SF: unable to claim SPI bus\n");
+-		return ret;
+-	}
+-
+ 	ret = spi_flash_cmd_write_enable(flash);
+ 	if (ret < 0) {
+ 		debug("SF: enabling write failed\n");
+@@ -158,8 +152,6 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
+ 		return ret;
+ 	}
+ 
+-	spi_release_bus(spi);
+-
+ 	return ret;
+ }
+ 
+@@ -175,12 +167,18 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+ 		return -1;
+ 	}
+ 
++	ret = spi_claim_bus(flash->spi);
++	if (ret) {
++		debug("SF: unable to claim SPI bus\n");
++		return ret;
++	}
++
+ 	cmd[0] = flash->erase_cmd;
+ 	while (len) {
+ #ifdef CONFIG_SPI_FLASH_BAR
+ 		ret = spi_flash_bank(flash, offset);
+ 		if (ret < 0)
+-			return ret;
++			goto done;
+ #endif
+ 		spi_flash_addr(offset, cmd);
+ 
+@@ -190,13 +188,16 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+ 		ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
+ 		if (ret < 0) {
+ 			debug("SF: erase failed\n");
+-			break;
++			goto done;
+ 		}
+ 
+ 		offset += erase_size;
+ 		len -= erase_size;
+ 	}
+ 
++done:
++	spi_release_bus(flash->spi);
++
+ 	return ret;
+ }
+ 
+@@ -208,6 +209,12 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+ 	u8 cmd[4];
+ 	int ret = -1;
+ 
++	ret = spi_claim_bus(flash->spi);
++	if (ret) {
++		debug("SF: unable to claim SPI bus\n");
++		return ret;
++	}
++
+ 	page_size = flash->page_size;
+ 
+ 	cmd[0] = CMD_PAGE_PROGRAM;
+@@ -215,7 +222,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+ #ifdef CONFIG_SPI_FLASH_BAR
+ 		ret = spi_flash_bank(flash, offset);
+ 		if (ret < 0)
+-			return ret;
++			goto done;
+ #endif
+ 		byte_addr = offset % page_size;
+ 		chunk_len = min(len - actual, page_size - byte_addr);
+@@ -232,12 +239,15 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+ 					buf + actual, chunk_len);
+ 		if (ret < 0) {
+ 			debug("SF: write failed\n");
+-			break;
++			goto done;
+ 		}
+ 
+ 		offset += chunk_len;
+ 	}
+ 
++done:
++	spi_release_bus(flash->spi);
++
+ 	return ret;
+ }
+ 
+@@ -247,20 +257,12 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
+ 	struct spi_slave *spi = flash->spi;
+ 	int ret;
+ 
+-	ret = spi_claim_bus(flash->spi);
+-	if (ret) {
+-		debug("SF: unable to claim SPI bus\n");
+-		return ret;
+-	}
+-
+ 	ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
+ 	if (ret < 0) {
+ 		debug("SF: read cmd failed\n");
+ 		return ret;
+ 	}
+ 
+-	spi_release_bus(spi);
+-
+ 	return ret;
+ }
+ 
+@@ -271,6 +273,12 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+ 	u32 remain_len, read_len;
+ 	int ret = -1;
+ 
++	ret = spi_claim_bus(flash->spi);
++	if (ret) {
++		debug("SF: unable to claim SPI bus\n");
++		return ret;
++	}
++
+ 	/* Handle memory-mapped SPI */
+ 	if (flash->memory_map) {
+ 		spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP);
+@@ -289,7 +297,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+ 		ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
+ 		if (ret) {
+ 			debug("SF: fail to set bank%d\n", bank_sel);
+-			return ret;
++			goto done;
+ 		}
+ #endif
+ 		remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset;
+@@ -304,7 +312,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+ 							data, read_len);
+ 		if (ret < 0) {
+ 			debug("SF: read failed\n");
+-			break;
++			goto done;
+ 		}
+ 
+ 		offset += read_len;
+@@ -312,6 +320,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+ 		data += read_len;
+ 	}
+ 
++done:
++	spi_release_bus(flash->spi);
++
+ 	return ret;
+ }
+ 
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0002-sf-consistently-use-debug-for-warning-error-messages.patch

@@ -0,0 +1,54 @@
+From bb7df8c6ff30be3786483767d3afb0e77a69a640 Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <[email protected]>
+Date: Sat, 12 Oct 2013 21:21:18 +0200
+Subject: sf: consistently use debug() for warning/error messages
+
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
+index 5eb8ffe..04356f1 100644
+--- a/drivers/mtd/spi/sf_probe.c
++++ b/drivers/mtd/spi/sf_probe.c
+@@ -176,8 +176,8 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
+ 	}
+ 
+ 	if (i == ARRAY_SIZE(spi_flash_params_table)) {
+-		printf("SF: Unsupported flash IDs: ");
+-		printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
++		debug("SF: Unsupported flash IDs: ");
++		debug("manuf %02x, jedec %04x, ext_jedec %04x\n",
+ 		       idcode[0], jedec, ext_jedec);
+ 		return NULL;
+ 	}
+@@ -296,7 +296,7 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+ 	/* Setup spi_slave */
+ 	spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
+ 	if (!spi) {
+-		printf("SF: Failed to set up slave\n");
++		debug("SF: Failed to set up slave\n");
+ 		return NULL;
+ 	}
+ 
+@@ -310,7 +310,7 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+ 	/* Read the ID codes */
+ 	ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
+ 	if (ret) {
+-		printf("SF: Failed to get idcodes\n");
++		debug("SF: Failed to get idcodes\n");
+ 		goto err_read_id;
+ 	}
+ 
+@@ -341,8 +341,8 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+ #endif
+ #ifndef CONFIG_SPI_FLASH_BAR
+ 	if (flash->size > SPI_FLASH_16MB_BOUN) {
+-		puts("SF: Warning - Only lower 16MiB accessible,");
+-		puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
++		debug("SF: Warning - Only lower 16MiB accessible,");
++		debug(" Full access #define CONFIG_SPI_FLASH_BAR\n");
+ 	}
+ #endif
+ 
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0002-sf-handle-CONFIG_MANUAL_RELOC.patch

@@ -1,46 +0,0 @@
-From 60e8a35f0efa5a7e5d797a3f239971c84061ef11 Mon Sep 17 00:00:00 2001
-From: Daniel Schwierzeck <[email protected]>
-Date: Tue, 6 Nov 2012 21:39:47 +0100
-Subject: sf: handle CONFIG_MANUAL_RELOC
-
-Signed-off-by: Daniel Schwierzeck <[email protected]>
-
---- a/drivers/mtd/spi/spi_flash.c
-+++ b/drivers/mtd/spi/spi_flash.c
-@@ -293,7 +293,7 @@ int spi_flash_cmd_write_status(struct sp
-  */
- #define IDCODE_CONT_LEN 0
- #define IDCODE_PART_LEN 5
--static const struct {
-+static struct {
- 	const u8 shift;
- 	const u8 idcode;
- 	struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode);
-@@ -335,6 +335,10 @@ static const struct {
- };
- #define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN)
- 
-+#ifdef CONFIG_NEEDS_MANUAL_RELOC
-+DECLARE_GLOBAL_DATA_PTR;
-+#endif
-+
- struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
- 		unsigned int max_hz, unsigned int spi_mode)
- {
-@@ -342,6 +346,16 @@ struct spi_flash *spi_flash_probe(unsign
- 	struct spi_flash *flash = NULL;
- 	int ret, i, shift;
- 	u8 idcode[IDCODE_LEN], *idp;
-+#ifdef CONFIG_NEEDS_MANUAL_RELOC
-+	static int relocated;
-+
-+	if (!relocated) {
-+		for (i = 0; i < ARRAY_SIZE(flashes); i++)
-+			flashes[i].probe += gd->reloc_off;
-+
-+		relocated = 1;
-+	}
-+#endif
- 
- 	spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
- 	if (!spi) {

package/boot/uboot-lantiq/patches/0003-sf-factor-out-malloc-from-SPI-flash-drivers.patch

@@ -1,719 +0,0 @@
-From 73d127565b5a4b19bcaacabc505689ee039f16fd Mon Sep 17 00:00:00 2001
-From: Daniel Schwierzeck <[email protected]>
-Date: Sun, 11 Nov 2012 03:11:38 +0100
-Subject: sf: factor out malloc from SPI flash drivers
-
-Signed-off-by: Daniel Schwierzeck <[email protected]>
-
---- a/drivers/mtd/spi/atmel.c
-+++ b/drivers/mtd/spi/atmel.c
-@@ -40,18 +40,6 @@ struct atmel_spi_flash_params {
- 	const char	*name;
- };
- 
--/* spi_flash needs to be first so upper layers can free() it */
--struct atmel_spi_flash {
--	struct spi_flash flash;
--	const struct atmel_spi_flash_params *params;
--};
--
--static inline struct atmel_spi_flash *
--to_atmel_spi_flash(struct spi_flash *flash)
--{
--	return container_of(flash, struct atmel_spi_flash, flash);
--}
--
- static const struct atmel_spi_flash_params atmel_spi_flash_table[] = {
- 	{
- 		.idcode1		= 0x22,
-@@ -156,7 +144,8 @@ static int at45_wait_ready(struct spi_fl
-  * Assemble the address part of a command for AT45 devices in
-  * non-power-of-two page size mode.
-  */
--static void at45_build_address(struct atmel_spi_flash *asf, u8 *cmd, u32 offset)
-+static void at45_build_address(const struct atmel_spi_flash_params *params,
-+				u8 *cmd, u32 offset)
- {
- 	unsigned long page_addr;
- 	unsigned long byte_addr;
-@@ -167,7 +156,7 @@ static void at45_build_address(struct at
- 	 * The "extra" space per page is the power-of-two page size
- 	 * divided by 32.
- 	 */
--	page_shift = asf->params->l2_page_size;
-+	page_shift = params->l2_page_size;
- 	page_size = (1 << page_shift) + (1 << (page_shift - 5));
- 	page_shift++;
- 	page_addr = offset / page_size;
-@@ -181,11 +170,11 @@ static void at45_build_address(struct at
- static int dataflash_read_fast_at45(struct spi_flash *flash,
- 		u32 offset, size_t len, void *buf)
- {
--	struct atmel_spi_flash *asf = to_atmel_spi_flash(flash);
-+	const struct atmel_spi_flash_params *params = flash->priv;
- 	u8 cmd[5];
- 
- 	cmd[0] = CMD_READ_ARRAY_FAST;
--	at45_build_address(asf, cmd + 1, offset);
-+	at45_build_address(params, cmd + 1, offset);
- 	cmd[4] = 0x00;
- 
- 	return spi_flash_read_common(flash, cmd, sizeof(cmd), buf, len);
-@@ -197,7 +186,7 @@ static int dataflash_read_fast_at45(stru
- static int dataflash_write_p2(struct spi_flash *flash,
- 		u32 offset, size_t len, const void *buf)
- {
--	struct atmel_spi_flash *asf = to_atmel_spi_flash(flash);
-+	const struct atmel_spi_flash_params *params = flash->priv;
- 	unsigned long page_size;
- 	u32 addr = offset;
- 	size_t chunk_len;
-@@ -211,7 +200,7 @@ static int dataflash_write_p2(struct spi
- 	 * the other is being programmed into main memory.
- 	 */
- 
--	page_size = (1 << asf->params->l2_page_size);
-+	page_size = (1 << params->l2_page_size);
- 
- 	ret = spi_claim_bus(flash->spi);
- 	if (ret) {
-@@ -263,7 +252,7 @@ out:
- static int dataflash_write_at45(struct spi_flash *flash,
- 		u32 offset, size_t len, const void *buf)
- {
--	struct atmel_spi_flash *asf = to_atmel_spi_flash(flash);
-+	const struct atmel_spi_flash_params *params = flash->priv;
- 	unsigned long page_addr;
- 	unsigned long byte_addr;
- 	unsigned long page_size;
-@@ -279,7 +268,7 @@ static int dataflash_write_at45(struct s
- 	 * the other is being programmed into main memory.
- 	 */
- 
--	page_shift = asf->params->l2_page_size;
-+	page_shift = params->l2_page_size;
- 	page_size = (1 << page_shift) + (1 << (page_shift - 5));
- 	page_shift++;
- 	page_addr = offset / page_size;
-@@ -338,7 +327,7 @@ out:
-  */
- static int dataflash_erase_p2(struct spi_flash *flash, u32 offset, size_t len)
- {
--	struct atmel_spi_flash *asf = to_atmel_spi_flash(flash);
-+	const struct atmel_spi_flash_params *params = flash->priv;
- 	unsigned long page_size;
- 
- 	size_t actual;
-@@ -351,7 +340,7 @@ static int dataflash_erase_p2(struct spi
- 	 * when possible.
- 	 */
- 
--	page_size = (1 << asf->params->l2_page_size);
-+	page_size = (1 << params->l2_page_size);
- 
- 	if (offset % page_size || len % page_size) {
- 		debug("SF: Erase offset/length not multiple of page size\n");
-@@ -397,7 +386,7 @@ out:
- 
- static int dataflash_erase_at45(struct spi_flash *flash, u32 offset, size_t len)
- {
--	struct atmel_spi_flash *asf = to_atmel_spi_flash(flash);
-+	const struct atmel_spi_flash_params *params = flash->priv;
- 	unsigned long page_addr;
- 	unsigned long page_size;
- 	unsigned int page_shift;
-@@ -411,7 +400,7 @@ static int dataflash_erase_at45(struct s
- 	 * when possible.
- 	 */
- 
--	page_shift = asf->params->l2_page_size;
-+	page_shift = params->l2_page_size;
- 	page_size = (1 << page_shift) + (1 << (page_shift - 5));
- 	page_shift++;
- 	page_addr = offset / page_size;
-@@ -458,12 +447,12 @@ out:
- 	return ret;
- }
- 
--struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode)
-+int spi_flash_probe_atmel(struct spi_flash *flash, u8 *idcode)
- {
- 	const struct atmel_spi_flash_params *params;
-+	struct spi_slave *spi = flash->spi;
- 	unsigned page_size;
- 	unsigned int family;
--	struct atmel_spi_flash *asf;
- 	unsigned int i;
- 	int ret;
- 	u8 status;
-@@ -477,18 +466,11 @@ struct spi_flash *spi_flash_probe_atmel(
- 	if (i == ARRAY_SIZE(atmel_spi_flash_table)) {
- 		debug("SF: Unsupported DataFlash ID %02x\n",
- 				idcode[1]);
--		return NULL;
--	}
--
--	asf = malloc(sizeof(struct atmel_spi_flash));
--	if (!asf) {
--		debug("SF: Failed to allocate memory\n");
--		return NULL;
-+		return 0;
- 	}
- 
--	asf->params = params;
--	asf->flash.spi = spi;
--	asf->flash.name = params->name;
-+	flash->priv = (void *)params;
-+	flash->name = params->name;
- 
- 	/* Assuming power-of-two page size initially. */
- 	page_size = 1 << params->l2_page_size;
-@@ -503,48 +485,44 @@ struct spi_flash *spi_flash_probe_atmel(
- 		 */
- 		ret = spi_flash_cmd(spi, CMD_AT45_READ_STATUS, &status, 1);
- 		if (ret)
--			goto err;
-+			return -1;
- 
- 		debug("SF: AT45 status register: %02x\n", status);
- 
- 		if (!(status & AT45_STATUS_P2_PAGE_SIZE)) {
--			asf->flash.read = dataflash_read_fast_at45;
--			asf->flash.write = dataflash_write_at45;
--			asf->flash.erase = dataflash_erase_at45;
-+			flash->read = dataflash_read_fast_at45;
-+			flash->write = dataflash_write_at45;
-+			flash->erase = dataflash_erase_at45;
- 			page_size += 1 << (params->l2_page_size - 5);
- 		} else {
--			asf->flash.read = spi_flash_cmd_read_fast;
--			asf->flash.write = dataflash_write_p2;
--			asf->flash.erase = dataflash_erase_p2;
-+			flash->read = spi_flash_cmd_read_fast;
-+			flash->write = dataflash_write_p2;
-+			flash->erase = dataflash_erase_p2;
- 		}
- 
--		asf->flash.page_size = page_size;
--		asf->flash.sector_size = page_size;
-+		flash->page_size = page_size;
-+		flash->sector_size = page_size;
- 		break;
- 
- 	case DF_FAMILY_AT26F:
- 	case DF_FAMILY_AT26DF:
--		asf->flash.read = spi_flash_cmd_read_fast;
--		asf->flash.write = spi_flash_cmd_write_multi;
--		asf->flash.erase = spi_flash_cmd_erase;
--		asf->flash.page_size = page_size;
--		asf->flash.sector_size = 4096;
-+		flash->read = spi_flash_cmd_read_fast;
-+		flash->write = spi_flash_cmd_write_multi;
-+		flash->erase = spi_flash_cmd_erase;
-+		flash->page_size = page_size;
-+		flash->sector_size = 4096;
- 		/* clear SPRL# bit for locked flash */
--		spi_flash_cmd_write_status(&asf->flash, 0);
-+		spi_flash_cmd_write_status(flash, 0);
- 		break;
- 
- 	default:
- 		debug("SF: Unsupported DataFlash family %u\n", family);
--		goto err;
-+		return -1;
- 	}
- 
--	asf->flash.size = page_size * params->pages_per_block
-+	flash->size = page_size * params->pages_per_block
- 				* params->blocks_per_sector
- 				* params->nr_sectors;
- 
--	return &asf->flash;
--
--err:
--	free(asf);
--	return NULL;
-+	return 1;
- }
---- a/drivers/mtd/spi/eon.c
-+++ b/drivers/mtd/spi/eon.c
-@@ -29,10 +29,9 @@ static const struct eon_spi_flash_params
- 	},
- };
- 
--struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode)
-+int spi_flash_probe_eon(struct spi_flash *flash, u8 *idcode)
- {
- 	const struct eon_spi_flash_params *params;
--	struct spi_flash *flash;
- 	unsigned int i;
- 
- 	for (i = 0; i < ARRAY_SIZE(eon_spi_flash_table); ++i) {
-@@ -43,16 +42,10 @@ struct spi_flash *spi_flash_probe_eon(st
- 
- 	if (i == ARRAY_SIZE(eon_spi_flash_table)) {
- 		debug("SF: Unsupported EON ID %02x\n", idcode[1]);
--		return NULL;
-+		return 0;
- 	}
- 
--	flash = malloc(sizeof(*flash));
--	if (!flash) {
--		debug("SF: Failed to allocate memory\n");
--		return NULL;
--	}
--
--	flash->spi = spi;
-+	flash->priv = (void *)params;
- 	flash->name = params->name;
- 
- 	flash->write = spi_flash_cmd_write_multi;
-@@ -63,5 +56,5 @@ struct spi_flash *spi_flash_probe_eon(st
- 	flash->size = 256 * 16
- 	    * params->nr_sectors;
- 
--	return flash;
-+	return 1;
- }
---- a/drivers/mtd/spi/macronix.c
-+++ b/drivers/mtd/spi/macronix.c
-@@ -79,10 +79,9 @@ static const struct macronix_spi_flash_p
- 	},
- };
- 
--struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode)
-+int spi_flash_probe_macronix(struct spi_flash *flash, u8 *idcode)
- {
- 	const struct macronix_spi_flash_params *params;
--	struct spi_flash *flash;
- 	unsigned int i;
- 	u16 id = idcode[2] | idcode[1] << 8;
- 
-@@ -94,16 +93,10 @@ struct spi_flash *spi_flash_probe_macron
- 
- 	if (i == ARRAY_SIZE(macronix_spi_flash_table)) {
- 		debug("SF: Unsupported Macronix ID %04x\n", id);
--		return NULL;
-+		return 0;
- 	}
- 
--	flash = malloc(sizeof(*flash));
--	if (!flash) {
--		debug("SF: Failed to allocate memory\n");
--		return NULL;
--	}
--
--	flash->spi = spi;
-+	flash->priv = (void *)params;
- 	flash->name = params->name;
- 
- 	flash->write = spi_flash_cmd_write_multi;
-@@ -116,5 +109,5 @@ struct spi_flash *spi_flash_probe_macron
- 	/* Clear BP# bits for read-only flash */
- 	spi_flash_cmd_write_status(flash, 0);
- 
--	return flash;
-+	return 1;
- }
---- a/drivers/mtd/spi/ramtron.c
-+++ b/drivers/mtd/spi/ramtron.c
-@@ -69,17 +69,6 @@ struct ramtron_spi_fram_params {
- 	const char *name;	/* name for display and/or matching */
- };
- 
--struct ramtron_spi_fram {
--	struct spi_flash flash;
--	const struct ramtron_spi_fram_params *params;
--};
--
--static inline struct ramtron_spi_fram *to_ramtron_spi_fram(struct spi_flash
--							     *flash)
--{
--	return container_of(flash, struct ramtron_spi_fram, flash);
--}
--
- /*
-  * table describing supported FRAM chips:
-  * chips without RDID command must have the values 0xff for id1 and id2
-@@ -155,18 +144,18 @@ static const struct ramtron_spi_fram_par
- static int ramtron_common(struct spi_flash *flash,
- 		u32 offset, size_t len, void *buf, u8 command)
- {
--	struct ramtron_spi_fram *sn = to_ramtron_spi_fram(flash);
-+	const struct ramtron_spi_fram_params *params = flash->priv;
- 	u8 cmd[4];
- 	int cmd_len;
- 	int ret;
- 
--	if (sn->params->addr_len == 3 && sn->params->merge_cmd == 0) {
-+	if (params->addr_len == 3 && params->merge_cmd == 0) {
- 		cmd[0] = command;
- 		cmd[1] = offset >> 16;
- 		cmd[2] = offset >> 8;
- 		cmd[3] = offset;
- 		cmd_len = 4;
--	} else if (sn->params->addr_len == 2 && sn->params->merge_cmd == 0) {
-+	} else if (params->addr_len == 2 && params->merge_cmd == 0) {
- 		cmd[0] = command;
- 		cmd[1] = offset >> 8;
- 		cmd[2] = offset;
-@@ -230,10 +219,9 @@ static int ramtron_erase(struct spi_flas
-  * nore: we are called here with idcode pointing to the first non-0x7f byte
-  * already!
-  */
--struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode)
-+int spi_fram_probe_ramtron(struct spi_flash *flash, u8 *idcode)
- {
- 	const struct ramtron_spi_fram_params *params;
--	struct ramtron_spi_fram *sn;
- 	unsigned int i;
- #ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
- 	int ret;
-@@ -259,11 +247,11 @@ struct spi_flash *spi_fram_probe_ramtron
- 		 */
- 		ret = spi_flash_cmd(spi, CMD_READ_STATUS, &sr, 1);
- 		if (ret)
--			return NULL;
-+			return 0;
- 
- 		/* Bits 5,4,0 are fixed 0 for all devices */
- 		if ((sr & 0x31) != 0x00)
--			return NULL;
-+			return 0;
- 		/* now find the device */
- 		for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) {
- 			params = &ramtron_spi_fram_table[i];
-@@ -281,23 +269,16 @@ struct spi_flash *spi_fram_probe_ramtron
- 	/* arriving here means no method has found a device we can handle */
- 	debug("SF/ramtron: unsupported device id0=%02x id1=%02x id2=%02x\n",
- 		idcode[0], idcode[1], idcode[2]);
--	return NULL;
-+	return 0;
- 
- found:
--	sn = malloc(sizeof(*sn));
--	if (!sn) {
--		debug("SF: Failed to allocate memory\n");
--		return NULL;
--	}
-+	flash->priv = (void *)params;
-+	flash->name = params->name;
- 
--	sn->params = params;
--	sn->flash.spi = spi;
--	sn->flash.name = params->name;
--
--	sn->flash.write = ramtron_write;
--	sn->flash.read = ramtron_read;
--	sn->flash.erase = ramtron_erase;
--	sn->flash.size = params->size;
-+	flash->write = ramtron_write;
-+	flash->read = ramtron_read;
-+	flash->erase = ramtron_erase;
-+	flash->size = params->size;
- 
--	return &sn->flash;
-+	return 1;
- }
---- a/drivers/mtd/spi/spansion.c
-+++ b/drivers/mtd/spi/spansion.c
-@@ -105,10 +105,9 @@ static const struct spansion_spi_flash_p
- 	},
- };
- 
--struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode)
-+int spi_flash_probe_spansion(struct spi_flash *flash, u8 *idcode)
- {
- 	const struct spansion_spi_flash_params *params;
--	struct spi_flash *flash;
- 	unsigned int i;
- 	unsigned short jedec, ext_jedec;
- 
-@@ -125,16 +124,10 @@ struct spi_flash *spi_flash_probe_spansi
- 
- 	if (i == ARRAY_SIZE(spansion_spi_flash_table)) {
- 		debug("SF: Unsupported SPANSION ID %04x %04x\n", jedec, ext_jedec);
--		return NULL;
-+		return 0;
- 	}
- 
--	flash = malloc(sizeof(*flash));
--	if (!flash) {
--		debug("SF: Failed to allocate memory\n");
--		return NULL;
--	}
--
--	flash->spi = spi;
-+	flash->priv = (void *)params;
- 	flash->name = params->name;
- 
- 	flash->write = spi_flash_cmd_write_multi;
-@@ -144,5 +137,5 @@ struct spi_flash *spi_flash_probe_spansi
- 	flash->sector_size = 256 * params->pages_per_sector;
- 	flash->size = flash->sector_size * params->nr_sectors;
- 
--	return flash;
-+	return 1;
- }
---- a/drivers/mtd/spi/spi_flash.c
-+++ b/drivers/mtd/spi/spi_flash.c
-@@ -296,7 +296,7 @@ int spi_flash_cmd_write_status(struct sp
- static struct {
- 	const u8 shift;
- 	const u8 idcode;
--	struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode);
-+	int (*probe) (struct spi_flash *flash, u8 *idcode);
- } flashes[] = {
- 	/* Keep it sorted by define name */
- #ifdef CONFIG_SPI_FLASH_ATMEL
-@@ -343,7 +343,7 @@ struct spi_flash *spi_flash_probe(unsign
- 		unsigned int max_hz, unsigned int spi_mode)
- {
- 	struct spi_slave *spi;
--	struct spi_flash *flash = NULL;
-+	struct spi_flash *flash;
- 	int ret, i, shift;
- 	u8 idcode[IDCODE_LEN], *idp;
- #ifdef CONFIG_NEEDS_MANUAL_RELOC
-@@ -379,6 +379,15 @@ struct spi_flash *spi_flash_probe(unsign
- 	print_buffer(0, idcode, 1, sizeof(idcode), 0);
- #endif
- 
-+	flash = malloc(sizeof(*flash));
-+	if (!flash) {
-+		debug("SF: failed to alloc memory\n");
-+		goto err_malloc;
-+	}
-+
-+	memset(flash, 0, sizeof(*flash));
-+	flash->spi = spi;
-+
- 	/* count the number of continuation bytes */
- 	for (shift = 0, idp = idcode;
- 	     shift < IDCODE_CONT_LEN && *idp == 0x7f;
-@@ -389,12 +398,12 @@ struct spi_flash *spi_flash_probe(unsign
- 	for (i = 0; i < ARRAY_SIZE(flashes); ++i)
- 		if (flashes[i].shift == shift && flashes[i].idcode == *idp) {
- 			/* we have a match, call probe */
--			flash = flashes[i].probe(spi, idp);
--			if (flash)
-+			ret = flashes[i].probe(flash, idp);
-+			if (ret)
- 				break;
- 		}
- 
--	if (!flash) {
-+	if (ret <= 0) {
- 		printf("SF: Unsupported manufacturer %02x\n", *idp);
- 		goto err_manufacturer_probe;
- 	}
-@@ -408,6 +417,8 @@ struct spi_flash *spi_flash_probe(unsign
- 	return flash;
- 
- err_manufacturer_probe:
-+	free(flash);
-+err_malloc:
- err_read_id:
- 	spi_release_bus(spi);
- err_claim_bus:
---- a/drivers/mtd/spi/spi_flash_internal.h
-+++ b/drivers/mtd/spi/spi_flash_internal.h
-@@ -98,11 +98,11 @@ int spi_flash_cmd_wait_ready(struct spi_
- int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len);
- 
- /* Manufacturer-specific probe functions */
--struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode);
--struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode);
--struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode);
--struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode);
--struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode);
--struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode);
--struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode);
--struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode);
-+int spi_flash_probe_spansion(struct spi_flash *flash, u8 *idcode);
-+int spi_flash_probe_atmel(struct spi_flash *flash, u8 *idcode);
-+int spi_flash_probe_eon(struct spi_flash *flash, u8 *idcode);
-+int spi_flash_probe_macronix(struct spi_flash *flash, u8 *idcode);
-+int spi_flash_probe_sst(struct spi_flash *flash, u8 *idcode);
-+int spi_flash_probe_stmicro(struct spi_flash *flash, u8 *idcode);
-+int spi_flash_probe_winbond(struct spi_flash *flash, u8 *idcode);
-+int spi_fram_probe_ramtron(struct spi_flash *flash, u8 *idcode);
---- a/drivers/mtd/spi/sst.c
-+++ b/drivers/mtd/spi/sst.c
-@@ -39,11 +39,6 @@ struct sst_spi_flash_params {
- 	const char *name;
- };
- 
--struct sst_spi_flash {
--	struct spi_flash flash;
--	const struct sst_spi_flash_params *params;
--};
--
- static const struct sst_spi_flash_params sst_spi_flash_table[] = {
- 	{
- 		.idcode1 = 0x8d,
-@@ -185,11 +180,9 @@ sst_write_wp(struct spi_flash *flash, u3
- 	return ret;
- }
- 
--struct spi_flash *
--spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode)
-+int spi_flash_probe_sst(struct spi_flash *flash, u8 *idcode)
- {
- 	const struct sst_spi_flash_params *params;
--	struct sst_spi_flash *stm;
- 	size_t i;
- 
- 	for (i = 0; i < ARRAY_SIZE(sst_spi_flash_table); ++i) {
-@@ -200,31 +193,24 @@ spi_flash_probe_sst(struct spi_slave *sp
- 
- 	if (i == ARRAY_SIZE(sst_spi_flash_table)) {
- 		debug("SF: Unsupported SST ID %02x\n", idcode[1]);
--		return NULL;
--	}
--
--	stm = malloc(sizeof(*stm));
--	if (!stm) {
--		debug("SF: Failed to allocate memory\n");
--		return NULL;
-+		return 0;
- 	}
- 
--	stm->params = params;
--	stm->flash.spi = spi;
--	stm->flash.name = params->name;
-+	flash->priv = (void *)params;
-+	flash->name = params->name;
- 
--	if (stm->params->flags & SST_FEAT_WP)
--		stm->flash.write = sst_write_wp;
-+	if (params->flags & SST_FEAT_WP)
-+		flash->write = sst_write_wp;
- 	else
--		stm->flash.write = spi_flash_cmd_write_multi;
--	stm->flash.erase = spi_flash_cmd_erase;
--	stm->flash.read = spi_flash_cmd_read_fast;
--	stm->flash.page_size = 256;
--	stm->flash.sector_size = 4096;
--	stm->flash.size = stm->flash.sector_size * params->nr_sectors;
-+		flash->write = spi_flash_cmd_write_multi;
-+	flash->erase = spi_flash_cmd_erase;
-+	flash->read = spi_flash_cmd_read_fast;
-+	flash->page_size = 256;
-+	flash->sector_size = 4096;
-+	flash->size = flash->sector_size * params->nr_sectors;
- 
- 	/* Flash powers up read-only, so clear BP# bits */
--	spi_flash_cmd_write_status(&stm->flash, 0);
-+	spi_flash_cmd_write_status(flash, 0);
- 
--	return &stm->flash;
-+	return 1;
- }
---- a/drivers/mtd/spi/stmicro.c
-+++ b/drivers/mtd/spi/stmicro.c
-@@ -112,10 +112,10 @@ static const struct stmicro_spi_flash_pa
- 	},
- };
- 
--struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode)
-+int spi_flash_probe_stmicro(struct spi_flash *flash, u8 * idcode)
- {
- 	const struct stmicro_spi_flash_params *params;
--	struct spi_flash *flash;
-+	struct spi_slave *spi = flash->spi;
- 	unsigned int i;
- 	u16 id;
- 
-@@ -123,13 +123,13 @@ struct spi_flash *spi_flash_probe_stmicr
- 		i = spi_flash_cmd(spi, CMD_M25PXX_RES,
- 				  idcode, 4);
- 		if (i)
--			return NULL;
-+			return 0;
- 		if ((idcode[3] & 0xf0) == 0x10) {
- 			idcode[0] = 0x20;
- 			idcode[1] = 0x20;
- 			idcode[2] = idcode[3] + 1;
- 		} else
--			return NULL;
-+			return 0;
- 	}
- 
- 	id = ((idcode[1] << 8) | idcode[2]);
-@@ -143,16 +143,10 @@ struct spi_flash *spi_flash_probe_stmicr
- 
- 	if (i == ARRAY_SIZE(stmicro_spi_flash_table)) {
- 		debug("SF: Unsupported STMicro ID %04x\n", id);
--		return NULL;
-+		return 0;
- 	}
- 
--	flash = malloc(sizeof(*flash));
--	if (!flash) {
--		debug("SF: Failed to allocate memory\n");
--		return NULL;
--	}
--
--	flash->spi = spi;
-+	flash->priv = (void *)params;
- 	flash->name = params->name;
- 
- 	flash->write = spi_flash_cmd_write_multi;
-@@ -162,5 +156,5 @@ struct spi_flash *spi_flash_probe_stmicr
- 	flash->sector_size = 256 * params->pages_per_sector;
- 	flash->size = flash->sector_size * params->nr_sectors;
- 
--	return flash;
-+	return 1;
- }
---- a/drivers/mtd/spi/winbond.c
-+++ b/drivers/mtd/spi/winbond.c
-@@ -69,10 +69,9 @@ static const struct winbond_spi_flash_pa
- 	},
- };
- 
--struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode)
-+int spi_flash_probe_winbond(struct spi_flash *flash, u8 *idcode)
- {
- 	const struct winbond_spi_flash_params *params;
--	struct spi_flash *flash;
- 	unsigned int i;
- 
- 	for (i = 0; i < ARRAY_SIZE(winbond_spi_flash_table); i++) {
-@@ -84,16 +83,10 @@ struct spi_flash *spi_flash_probe_winbon
- 	if (i == ARRAY_SIZE(winbond_spi_flash_table)) {
- 		debug("SF: Unsupported Winbond ID %02x%02x\n",
- 				idcode[1], idcode[2]);
--		return NULL;
-+		return 0;
- 	}
- 
--	flash = malloc(sizeof(*flash));
--	if (!flash) {
--		debug("SF: Failed to allocate memory\n");
--		return NULL;
--	}
--
--	flash->spi = spi;
-+	flash->priv = (void *)params;
- 	flash->name = params->name;
- 
- 	flash->write = spi_flash_cmd_write_multi;
-@@ -103,5 +96,5 @@ struct spi_flash *spi_flash_probe_winbon
- 	flash->sector_size = 4096;
- 	flash->size = 4096 * 16 * params->nr_blocks;
- 
--	return flash;
-+	return 1;
- }
---- a/include/spi_flash.h
-+++ b/include/spi_flash.h
-@@ -31,6 +31,7 @@ struct spi_flash {
- 	struct spi_slave *spi;
- 
- 	const char	*name;
-+	void		*priv;
- 
- 	/* Total flash size */
- 	u32		size;

package/boot/uboot-lantiq/patches/0003-sf-move-malloc-of-spi_flash-to-spi_flash_probe.patch

@@ -0,0 +1,115 @@
+From 36b7400465fe2339f1c78274b3fd258ade3a4c00 Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <[email protected]>
+Date: Sat, 12 Oct 2013 21:30:07 +0200
+Subject: sf: move malloc of spi_flash to spi_flash_probe()
+
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
+index 04356f1..2bba10c 100644
+--- a/drivers/mtd/spi/sf_probe.c
++++ b/drivers/mtd/spi/sf_probe.c
+@@ -153,11 +153,10 @@ static const struct spi_flash_params spi_flash_params_table[] = {
+ 	 */
+ };
+ 
+-static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
++static int spi_flash_validate_params(struct spi_flash *flash,
+ 		u8 *idcode)
+ {
+ 	const struct spi_flash_params *params;
+-	struct spi_flash *flash;
+ 	int i;
+ 	u16 jedec = idcode[1] << 8 | idcode[2];
+ 	u16 ext_jedec = idcode[3] << 8 | idcode[4];
+@@ -179,20 +178,12 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
+ 		debug("SF: Unsupported flash IDs: ");
+ 		debug("manuf %02x, jedec %04x, ext_jedec %04x\n",
+ 		       idcode[0], jedec, ext_jedec);
+-		return NULL;
+-	}
+-
+-	flash = malloc(sizeof(*flash));
+-	if (!flash) {
+-		debug("SF: Failed to allocate spi_flash\n");
+-		return NULL;
++		return -1;
+ 	}
+-	memset(flash, '\0', sizeof(*flash));
+ 
+ 	/* Assign spi data */
+-	flash->spi = spi;
+ 	flash->name = params->name;
+-	flash->memory_map = spi->memory_map;
++	flash->memory_map = flash->spi->memory_map;
+ 
+ 	/* Assign spi_flash ops */
+ 	flash->write = spi_flash_cmd_write_ops;
+@@ -239,7 +230,7 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
+ 		if (spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
+ 					  &curr_bank, 1)) {
+ 			debug("SF: fail to read bank addr register\n");
+-			return NULL;
++			return -1;
+ 		}
+ 		flash->bank_curr = curr_bank;
+ 	} else {
+@@ -254,7 +245,7 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
+ 		spi_flash_cmd_write_status(flash, 0);
+ #endif
+ 
+-	return flash;
++	return 0;
+ }
+ 
+ #ifdef CONFIG_OF_CONTROL
+@@ -289,15 +280,22 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+ 		unsigned int max_hz, unsigned int spi_mode)
+ {
+ 	struct spi_slave *spi;
+-	struct spi_flash *flash = NULL;
++	struct spi_flash *flash;
+ 	u8 idcode[5];
+ 	int ret;
+ 
++	flash = malloc(sizeof(*flash));
++	if (!flash) {
++		debug("SF: Failed to allocate spi_flash\n");
++		return NULL;
++	}
++	memset(flash, 0, sizeof(*flash));
++
+ 	/* Setup spi_slave */
+ 	spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
+ 	if (!spi) {
+ 		debug("SF: Failed to set up slave\n");
+-		return NULL;
++		goto err_setup;
+ 	}
+ 
+ 	/* Claim spi bus */
+@@ -320,8 +318,9 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+ #endif
+ 
+ 	/* Validate params from spi_flash_params table */
+-	flash = spi_flash_validate_params(spi, idcode);
+-	if (!flash)
++	flash->spi = spi;
++	ret = spi_flash_validate_params(flash, idcode);
++	if (ret)
+ 		goto err_read_id;
+ 
+ #ifdef CONFIG_OF_CONTROL
+@@ -355,6 +354,9 @@ err_read_id:
+ 	spi_release_bus(spi);
+ err_claim_bus:
+ 	spi_free_slave(spi);
++err_setup:
++	free(flash);
++
+ 	return NULL;
+ }
+ 
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0004-sf-add-malloc-free-probe-functions-dedicated-for-SPL.patch

@@ -1,131 +0,0 @@
-From f9ab44c271fbd82a5702b6ba067fa90e33a30089 Mon Sep 17 00:00:00 2001
-From: Daniel Schwierzeck <[email protected]>
-Date: Wed, 7 Nov 2012 15:29:27 +0100
-Subject: sf: add malloc-free probe functions dedicated for SPL
-
-Signed-off-by: Daniel Schwierzeck <[email protected]>
-
---- a/drivers/mtd/spi/spi_flash.c
-+++ b/drivers/mtd/spi/spi_flash.c
-@@ -339,11 +339,11 @@ static struct {
- DECLARE_GLOBAL_DATA_PTR;
- #endif
- 
--struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
--		unsigned int max_hz, unsigned int spi_mode)
-+int spi_flash_probe_spl(struct spi_flash *flash, unsigned int bus,
-+			unsigned int cs, unsigned int max_hz,
-+			unsigned int spi_mode)
- {
- 	struct spi_slave *spi;
--	struct spi_flash *flash;
- 	int ret, i, shift;
- 	u8 idcode[IDCODE_LEN], *idp;
- #ifdef CONFIG_NEEDS_MANUAL_RELOC
-@@ -359,8 +359,8 @@ struct spi_flash *spi_flash_probe(unsign
- 
- 	spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
- 	if (!spi) {
--		printf("SF: Failed to set up slave\n");
--		return NULL;
-+		debug("SF: Failed to set up slave\n");
-+		return -1;
- 	}
- 
- 	ret = spi_claim_bus(spi);
-@@ -379,13 +379,6 @@ struct spi_flash *spi_flash_probe(unsign
- 	print_buffer(0, idcode, 1, sizeof(idcode), 0);
- #endif
- 
--	flash = malloc(sizeof(*flash));
--	if (!flash) {
--		debug("SF: failed to alloc memory\n");
--		goto err_malloc;
--	}
--
--	memset(flash, 0, sizeof(*flash));
- 	flash->spi = spi;
- 
- 	/* count the number of continuation bytes */
-@@ -404,30 +397,58 @@ struct spi_flash *spi_flash_probe(unsign
- 		}
- 
- 	if (ret <= 0) {
--		printf("SF: Unsupported manufacturer %02x\n", *idp);
-+		debug("SF: Unsupported manufacturer %02x\n", *idp);
- 		goto err_manufacturer_probe;
- 	}
- 
--	printf("SF: Detected %s with page size ", flash->name);
--	print_size(flash->sector_size, ", total ");
--	print_size(flash->size, "\n");
--
- 	spi_release_bus(spi);
- 
--	return flash;
-+	return 0;
- 
- err_manufacturer_probe:
--	free(flash);
--err_malloc:
- err_read_id:
- 	spi_release_bus(spi);
- err_claim_bus:
- 	spi_free_slave(spi);
-+
-+	return ret;
-+}
-+
-+struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
-+		unsigned int max_hz, unsigned int spi_mode)
-+{
-+	struct spi_flash *flash;
-+	int ret;
-+
-+	flash = malloc(sizeof(*flash));
-+	if (!flash) {
-+		debug("SF: Failed to malloc spi_flash\n");
-+		return NULL;
-+	}
-+	memset(flash, 0, sizeof(*flash));
-+
-+	ret = spi_flash_probe_spl(flash, bus, cs, max_hz, spi_mode);
-+	if (ret)
-+		goto err_probe;
-+
-+	printf("SF:    %s, page size ", flash->name);
-+	print_size(flash->sector_size, ", total ");
-+	print_size(flash->size, "\n");
-+
-+	return flash;
-+
-+err_probe:
-+	free(flash);
- 	return NULL;
- }
- 
--void spi_flash_free(struct spi_flash *flash)
-+void spi_flash_free_spl(struct spi_flash *flash)
- {
- 	spi_free_slave(flash->spi);
-+}
-+
-+void spi_flash_free(struct spi_flash *flash)
-+{
-+	spi_flash_free_spl(flash);
- 	free(flash);
- }
---- a/include/spi_flash.h
-+++ b/include/spi_flash.h
-@@ -52,6 +52,11 @@ struct spi_flash *spi_flash_probe(unsign
- 		unsigned int max_hz, unsigned int spi_mode);
- void spi_flash_free(struct spi_flash *flash);
- 
-+int spi_flash_probe_spl(struct spi_flash *flash, unsigned int bus,
-+			unsigned int cs, unsigned int max_hz,
-+			unsigned int spi_mode);
-+void spi_flash_free_spl(struct spi_flash *flash);
-+
- static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
- 		size_t len, void *buf)
- {

package/boot/uboot-lantiq/patches/0004-sf-add-slim-probe-funtions-for-SPL.patch

@@ -0,0 +1,87 @@
+From da11da943487e2f724f25d409bcaa1f099637c0b Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <[email protected]>
+Date: Sun, 13 Oct 2013 14:56:45 +0200
+Subject: sf: add slim probe funtions for SPL
+
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
+index 2bba10c..380aa09 100644
+--- a/drivers/mtd/spi/sf_probe.c
++++ b/drivers/mtd/spi/sf_probe.c
+@@ -365,3 +365,58 @@ void spi_flash_free(struct spi_flash *flash)
+ 	spi_free_slave(flash->spi);
+ 	free(flash);
+ }
++
++#ifdef CONFIG_SPI_SPL_SIMPLE
++int spl_spi_flash_probe(struct spi_flash *flash)
++{
++	struct spi_slave *spi;
++	u8 idcode[5];
++	int ret;
++
++	/* Setup spi_slave */
++	spi = spi_setup_slave(CONFIG_SPL_SPI_BUS, CONFIG_SPL_SPI_CS,
++		CONFIG_SPL_SPI_MAX_HZ, CONFIG_SPL_SPI_MODE);
++	if (!spi) {
++		debug("SF: Failed to set up slave\n");
++		return -1;
++	}
++
++	/* Claim spi bus */
++	ret = spi_claim_bus(spi);
++	if (ret) {
++		debug("SF: Failed to claim SPI bus: %d\n", ret);
++		goto err_claim_bus;
++	}
++
++	/* Read the ID codes */
++	ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
++	if (ret) {
++		debug("SF: Failed to get idcodes\n");
++		goto err_read_id;
++	}
++
++	/* Validate params from spi_flash_params table */
++	flash->spi = spi;
++	ret = spi_flash_validate_params(flash, idcode);
++	if (ret)
++		goto err_read_id;
++
++	/* Release spi bus */
++	spi_release_bus(spi);
++
++	return 0;
++
++err_read_id:
++	spi_release_bus(spi);
++err_claim_bus:
++	spi_free_slave(spi);
++	flash->spi = NULL;
++
++	return ret;
++}
++
++void spl_spi_flash_free(struct spi_flash *flash)
++{
++	spi_free_slave(flash->spi);
++}
++#endif
+diff --git a/include/spi_flash.h b/include/spi_flash.h
+index 25ca8f1..411dd1b 100644
+--- a/include/spi_flash.h
++++ b/include/spi_flash.h
+@@ -69,6 +69,9 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+ 		unsigned int max_hz, unsigned int spi_mode);
+ void spi_flash_free(struct spi_flash *flash);
+ 
++int spl_spi_flash_probe(struct spi_flash *flash);
++void spl_spi_flash_free(struct spi_flash *flash);
++
+ static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
+ 		size_t len, void *buf)
+ {
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0005-sf-factor-out-the-flash-address-calculation.patch

@@ -1,107 +0,0 @@
-From acb2721e1cd2e7488a7b08a4ed590177369a1689 Mon Sep 17 00:00:00 2001
-From: Daniel Schwierzeck <[email protected]>
-Date: Tue, 6 Nov 2012 19:10:40 +0100
-Subject: sf: factor out the flash address calculation
-
-Signed-off-by: Daniel Schwierzeck <[email protected]>
-
---- a/drivers/mtd/spi/spi_flash.c
-+++ b/drivers/mtd/spi/spi_flash.c
-@@ -15,12 +15,22 @@
- 
- #include "spi_flash_internal.h"
- 
--static void spi_flash_addr(u32 addr, u8 *cmd)
-+static void spi_flash_addr(struct spi_flash *flash, u32 addr, u8 *cmd, u8 *cmd_len)
- {
- 	/* cmd[0] is actual command */
- 	cmd[1] = addr >> 16;
- 	cmd[2] = addr >> 8;
- 	cmd[3] = addr >> 0;
-+	*cmd_len = 4;
-+}
-+
-+static void spi_flash_page_addr(struct spi_flash *flash, u32 page_addr, u32 byte_addr, u8 *cmd, u8 *cmd_len)
-+{
-+	/* cmd[0] is actual command */
-+	cmd[1] = page_addr >> 8;
-+	cmd[2] = page_addr >> 0;
-+	cmd[3] = byte_addr;
-+	*cmd_len = 4;
- }
- 
- static int spi_flash_read_write(struct spi_slave *spi,
-@@ -71,7 +81,7 @@ int spi_flash_cmd_write_multi(struct spi
- 	unsigned long page_addr, byte_addr, page_size;
- 	size_t chunk_len, actual;
- 	int ret;
--	u8 cmd[4];
-+	u8 cmd[4], cmd_len;
- 
- 	page_size = flash->page_size;
- 	page_addr = offset / page_size;
-@@ -87,9 +97,7 @@ int spi_flash_cmd_write_multi(struct spi
- 	for (actual = 0; actual < len; actual += chunk_len) {
- 		chunk_len = min(len - actual, page_size - byte_addr);
- 
--		cmd[1] = page_addr >> 8;
--		cmd[2] = page_addr;
--		cmd[3] = byte_addr;
-+		spi_flash_page_addr(flash, page_addr, byte_addr, cmd, &cmd_len);
- 
- 		debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
- 		      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
-@@ -100,7 +108,7 @@ int spi_flash_cmd_write_multi(struct spi
- 			break;
- 		}
- 
--		ret = spi_flash_cmd_write(flash->spi, cmd, 4,
-+		ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
- 					  buf + actual, chunk_len);
- 		if (ret < 0) {
- 			debug("SF: write failed\n");
-@@ -138,13 +146,13 @@ int spi_flash_read_common(struct spi_fla
- int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
- 		size_t len, void *data)
- {
--	u8 cmd[5];
-+	u8 cmd[5], cmd_len;
- 
- 	cmd[0] = CMD_READ_ARRAY_FAST;
--	spi_flash_addr(offset, cmd);
--	cmd[4] = 0x00;
-+	spi_flash_addr(flash, offset, cmd, &cmd_len);
-+	cmd[cmd_len] = 0x00;
- 
--	return spi_flash_read_common(flash, cmd, sizeof(cmd), data, len);
-+	return spi_flash_read_common(flash, cmd, cmd_len + 1, data, len);
- }
- 
- int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
-@@ -194,7 +202,7 @@ int spi_flash_cmd_erase(struct spi_flash
- {
- 	u32 start, end, erase_size;
- 	int ret;
--	u8 cmd[4];
-+	u8 cmd[4], cmd_len;
- 
- 	erase_size = flash->sector_size;
- 	if (offset % erase_size || len % erase_size) {
-@@ -216,7 +224,7 @@ int spi_flash_cmd_erase(struct spi_flash
- 	end = start + len;
- 
- 	while (offset < end) {
--		spi_flash_addr(offset, cmd);
-+		spi_flash_addr(flash, offset, cmd, &cmd_len);
- 		offset += erase_size;
- 
- 		debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
-@@ -226,7 +234,7 @@ int spi_flash_cmd_erase(struct spi_flash
- 		if (ret)
- 			goto out;
- 
--		ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), NULL, 0);
-+		ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, NULL, 0);
- 		if (ret)
- 			goto out;
- 

package/boot/uboot-lantiq/patches/0005-sf-make-calculatiom-of-address-bytes-completely-conf.patch

@@ -0,0 +1,143 @@
+From 6fb5f86b094756d94de8abe7425e3d290ff22dd2 Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <[email protected]>
+Date: Sun, 13 Oct 2013 15:09:28 +0200
+Subject: sf: make calculatiom of address bytes completely configurable
+
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
+index d34747b..207adf5 100644
+--- a/drivers/mtd/spi/sf_ops.c
++++ b/drivers/mtd/spi/sf_ops.c
+@@ -15,12 +15,17 @@
+ 
+ #include "sf_internal.h"
+ 
+-static void spi_flash_addr(u32 addr, u8 *cmd)
++static void spi_flash_addr(const struct spi_flash *flash, u32 addr, u8 *cmd)
+ {
+ 	/* cmd[0] is actual command */
+-	cmd[1] = addr >> 16;
+-	cmd[2] = addr >> 8;
+-	cmd[3] = addr >> 0;
++	cmd[1] = addr >> (flash->addr_width * 8 - 8);
++	cmd[2] = addr >> (flash->addr_width * 8 - 16);
++	cmd[3] = addr >> (flash->addr_width * 8 - 24);
++}
++
++static int spi_flash_cmdsz(const struct spi_flash *flash)
++{
++	return 1 + flash->addr_width;
+ }
+ 
+ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
+@@ -158,7 +163,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
+ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+ {
+ 	u32 erase_size;
+-	u8 cmd[4];
++	u8 cmd[4], cmd_len;
+ 	int ret = -1;
+ 
+ 	erase_size = flash->erase_size;
+@@ -180,12 +185,13 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+ 		if (ret < 0)
+ 			goto done;
+ #endif
+-		spi_flash_addr(offset, cmd);
++		spi_flash_addr(flash, offset, cmd);
++		cmd_len = spi_flash_cmdsz(flash);
+ 
+ 		debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
+ 		      cmd[2], cmd[3], offset);
+ 
+-		ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
++		ret = spi_flash_write_common(flash, cmd, cmd_len, NULL, 0);
+ 		if (ret < 0) {
+ 			debug("SF: erase failed\n");
+ 			goto done;
+@@ -206,7 +212,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+ {
+ 	unsigned long byte_addr, page_size;
+ 	size_t chunk_len, actual;
+-	u8 cmd[4];
++	u8 cmd[4], cmd_len;
+ 	int ret = -1;
+ 
+ 	ret = spi_claim_bus(flash->spi);
+@@ -230,12 +236,13 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+ 		if (flash->spi->max_write_size)
+ 			chunk_len = min(chunk_len, flash->spi->max_write_size);
+ 
+-		spi_flash_addr(offset, cmd);
++		spi_flash_addr(flash, offset, cmd);
++		cmd_len = spi_flash_cmdsz(flash);
+ 
+ 		debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
+ 		      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+ 
+-		ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
++		ret = spi_flash_write_common(flash, cmd, cmd_len,
+ 					buf + actual, chunk_len);
+ 		if (ret < 0) {
+ 			debug("SF: write failed\n");
+@@ -269,7 +276,7 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
+ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+ 		size_t len, void *data)
+ {
+-	u8 cmd[5], bank_sel = 0;
++	u8 cmd[5], cmd_len, bank_sel = 0;
+ 	u32 remain_len, read_len;
+ 	int ret = -1;
+ 
+@@ -288,7 +295,6 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+ 	}
+ 
+ 	cmd[0] = CMD_READ_ARRAY_FAST;
+-	cmd[4] = 0x00;
+ 
+ 	while (len) {
+ #ifdef CONFIG_SPI_FLASH_BAR
+@@ -306,9 +312,11 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+ 		else
+ 			read_len = remain_len;
+ 
+-		spi_flash_addr(offset, cmd);
++		spi_flash_addr(flash, offset, cmd);
++		cmd_len = spi_flash_cmdsz(flash);
++		cmd[cmd_len] = 0x00;
+ 
+-		ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
++		ret = spi_flash_read_common(flash, cmd, cmd_len + 1,
+ 							data, read_len);
+ 		if (ret < 0) {
+ 			debug("SF: read failed\n");
+diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
+index 380aa09..84289db 100644
+--- a/drivers/mtd/spi/sf_probe.c
++++ b/drivers/mtd/spi/sf_probe.c
+@@ -218,6 +218,9 @@ static int spi_flash_validate_params(struct spi_flash *flash,
+ 		flash->poll_cmd = CMD_FLAG_STATUS;
+ #endif
+ 
++	/* Configure default 3-byte addressing */
++	flash->addr_width = 3;
++
+ 	/* Configure the BAR - discover bank cmds and read current bank */
+ #ifdef CONFIG_SPI_FLASH_BAR
+ 	u8 curr_bank = 0;
+diff --git a/include/spi_flash.h b/include/spi_flash.h
+index 411dd1b..cc9398b 100644
+--- a/include/spi_flash.h
++++ b/include/spi_flash.h
+@@ -57,6 +57,7 @@ struct spi_flash {
+ #endif
+ 	u8 poll_cmd;
+ 	u8 erase_cmd;
++	u8 addr_width;
+ 
+ 	void *memory_map;
+ 	int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf);
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0006-sf-add-generic-support-for-4-byte-address-mode.patch

@@ -1,161 +0,0 @@
-From fb9ed0ef6f0ba6b6535c64dcfcf45c161723e56f Mon Sep 17 00:00:00 2001
-From: Daniel Schwierzeck <[email protected]>
-Date: Tue, 6 Nov 2012 19:31:38 +0100
-Subject: sf: add generic support for 4-byte address mode
-
-Signed-off-by: Daniel Schwierzeck <[email protected]>
-
---- a/drivers/mtd/spi/spi_flash.c
-+++ b/drivers/mtd/spi/spi_flash.c
-@@ -18,19 +18,35 @@
- static void spi_flash_addr(struct spi_flash *flash, u32 addr, u8 *cmd, u8 *cmd_len)
- {
- 	/* cmd[0] is actual command */
--	cmd[1] = addr >> 16;
--	cmd[2] = addr >> 8;
--	cmd[3] = addr >> 0;
--	*cmd_len = 4;
-+	if (spi_flash_use_4byte_mode(flash)) {
-+		cmd[1] = addr >> 24;
-+		cmd[2] = addr >> 16;
-+		cmd[3] = addr >> 8;
-+		cmd[4] = addr >> 0;
-+		*cmd_len = 5;
-+	} else {
-+		cmd[1] = addr >> 16;
-+		cmd[2] = addr >> 8;
-+		cmd[3] = addr >> 0;
-+		*cmd_len = 4;
-+	}
- }
- 
- static void spi_flash_page_addr(struct spi_flash *flash, u32 page_addr, u32 byte_addr, u8 *cmd, u8 *cmd_len)
- {
- 	/* cmd[0] is actual command */
--	cmd[1] = page_addr >> 8;
--	cmd[2] = page_addr >> 0;
--	cmd[3] = byte_addr;
--	*cmd_len = 4;
-+	if (spi_flash_use_4byte_mode(flash)) {
-+		cmd[1] = page_addr >> 16;
-+		cmd[2] = page_addr >> 8;
-+		cmd[3] = page_addr >> 0;
-+		cmd[4] = byte_addr;
-+		*cmd_len = 5;
-+	} else {
-+		cmd[1] = page_addr >> 8;
-+		cmd[2] = page_addr >> 0;
-+		cmd[3] = byte_addr;
-+		*cmd_len = 4;
-+	}
- }
- 
- static int spi_flash_read_write(struct spi_slave *spi,
-@@ -81,7 +97,7 @@ int spi_flash_cmd_write_multi(struct spi
- 	unsigned long page_addr, byte_addr, page_size;
- 	size_t chunk_len, actual;
- 	int ret;
--	u8 cmd[4], cmd_len;
-+	u8 cmd[5], cmd_len;
- 
- 	page_size = flash->page_size;
- 	page_addr = offset / page_size;
-@@ -99,8 +115,8 @@ int spi_flash_cmd_write_multi(struct spi
- 
- 		spi_flash_page_addr(flash, page_addr, byte_addr, cmd, &cmd_len);
- 
--		debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
--		      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
-+		debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x%02x } chunk_len = %zu\n",
-+		      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], cmd[4], chunk_len);
- 
- 		ret = spi_flash_cmd_write_enable(flash);
- 		if (ret < 0) {
-@@ -146,7 +162,7 @@ int spi_flash_read_common(struct spi_fla
- int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
- 		size_t len, void *data)
- {
--	u8 cmd[5], cmd_len;
-+	u8 cmd[6], cmd_len;
- 
- 	cmd[0] = CMD_READ_ARRAY_FAST;
- 	spi_flash_addr(flash, offset, cmd, &cmd_len);
-@@ -202,7 +218,7 @@ int spi_flash_cmd_erase(struct spi_flash
- {
- 	u32 start, end, erase_size;
- 	int ret;
--	u8 cmd[4], cmd_len;
-+	u8 cmd[5], cmd_len;
- 
- 	erase_size = flash->sector_size;
- 	if (offset % erase_size || len % erase_size) {
-@@ -227,8 +243,8 @@ int spi_flash_cmd_erase(struct spi_flash
- 		spi_flash_addr(flash, offset, cmd, &cmd_len);
- 		offset += erase_size;
- 
--		debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
--		      cmd[2], cmd[3], offset);
-+		debug("SF: erase %2x %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
-+		      cmd[2], cmd[3], cmd[4], offset);
- 
- 		ret = spi_flash_cmd_write_enable(flash);
- 		if (ret)
-@@ -409,6 +425,12 @@ int spi_flash_probe_spl(struct spi_flash
- 		goto err_manufacturer_probe;
- 	}
- 
-+	ret = spi_flash_set_4byte_mode(flash);
-+	if (ret) {
-+		debug("SF: Failed to enable 4 byte mode: %d\n", ret);
-+		goto err_manufacturer_probe;
-+	}
-+
- 	spi_release_bus(spi);
- 
- 	return 0;
---- a/drivers/mtd/spi/spi_flash_internal.h
-+++ b/drivers/mtd/spi/spi_flash_internal.h
-@@ -97,6 +97,31 @@ int spi_flash_cmd_wait_ready(struct spi_
- /* Erase sectors. */
- int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len);
- 
-+#ifdef CONFIG_SPI_FLASH_4BYTE_MODE
-+static inline int spi_flash_use_4byte_mode(struct spi_flash *flash)
-+{
-+	return NULL != flash->set_4byte_mode;
-+}
-+
-+static inline int spi_flash_set_4byte_mode(struct spi_flash *flash)
-+{
-+	if (spi_flash_use_4byte_mode(flash))
-+		return flash->set_4byte_mode(flash);
-+
-+	return 0;
-+}
-+#else
-+static inline int spi_flash_use_4byte_mode(struct spi_flash *flash)
-+{
-+	return 0;
-+}
-+
-+static inline int spi_flash_set_4byte_mode(struct spi_flash *flash)
-+{
-+	return 0;
-+}
-+#endif
-+
- /* Manufacturer-specific probe functions */
- int spi_flash_probe_spansion(struct spi_flash *flash, u8 *idcode);
- int spi_flash_probe_atmel(struct spi_flash *flash, u8 *idcode);
---- a/include/spi_flash.h
-+++ b/include/spi_flash.h
-@@ -46,6 +46,9 @@ struct spi_flash {
- 				size_t len, const void *buf);
- 	int		(*erase)(struct spi_flash *flash, u32 offset,
- 				size_t len);
-+#ifdef CONFIG_SPI_FLASH_4BYTE_MODE
-+	int		(*set_4byte_mode)(struct spi_flash *flash);
-+#endif
- };
- 
- struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,

package/boot/uboot-lantiq/patches/0006-sf-add-support-for-4-byte-addressing.patch

@@ -0,0 +1,169 @@
+From 3af3addee645bd81537be1ddee49969f8dfc64ee Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <[email protected]>
+Date: Sun, 13 Oct 2013 15:24:56 +0200
+Subject: sf: add support for 4-byte addressing
+
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
+index 732ddf8..c5e8eb1 100644
+--- a/drivers/mtd/spi/sf_internal.h
++++ b/drivers/mtd/spi/sf_internal.h
+@@ -38,12 +38,14 @@
+ #define CMD_READ_ID			0x9f
+ 
+ /* Bank addr access commands */
+-#ifdef CONFIG_SPI_FLASH_BAR
+-# define CMD_BANKADDR_BRWR		0x17
+-# define CMD_BANKADDR_BRRD		0x16
+-# define CMD_EXTNADDR_WREAR		0xC5
+-# define CMD_EXTNADDR_RDEAR		0xC8
+-#endif
++#define CMD_BANKADDR_BRWR		0x17
++#define CMD_BANKADDR_BRRD		0x16
++#define CMD_EXTNADDR_WREAR		0xC5
++#define CMD_EXTNADDR_RDEAR		0xC8
++
++/* Macronix style 4-byte addressing */
++#define CMD_EN4B			0xb7
++#define CMD_EX4B			0xe9
+ 
+ /* Common status */
+ #define STATUS_WIP			0x01
+diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
+index 207adf5..1d072f8 100644
+--- a/drivers/mtd/spi/sf_ops.c
++++ b/drivers/mtd/spi/sf_ops.c
+@@ -21,6 +21,7 @@ static void spi_flash_addr(const struct spi_flash *flash, u32 addr, u8 *cmd)
+ 	cmd[1] = addr >> (flash->addr_width * 8 - 8);
+ 	cmd[2] = addr >> (flash->addr_width * 8 - 16);
+ 	cmd[3] = addr >> (flash->addr_width * 8 - 24);
++	cmd[4] = addr >> (flash->addr_width * 8 - 32);
+ }
+ 
+ static int spi_flash_cmdsz(const struct spi_flash *flash)
+@@ -163,7 +164,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
+ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+ {
+ 	u32 erase_size;
+-	u8 cmd[4], cmd_len;
++	u8 cmd[5], cmd_len;
+ 	int ret = -1;
+ 
+ 	erase_size = flash->erase_size;
+@@ -188,8 +189,8 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+ 		spi_flash_addr(flash, offset, cmd);
+ 		cmd_len = spi_flash_cmdsz(flash);
+ 
+-		debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
+-		      cmd[2], cmd[3], offset);
++		debug("SF: erase %2x %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
++		      cmd[2], cmd[3], cmd[4], offset);
+ 
+ 		ret = spi_flash_write_common(flash, cmd, cmd_len, NULL, 0);
+ 		if (ret < 0) {
+@@ -212,7 +213,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+ {
+ 	unsigned long byte_addr, page_size;
+ 	size_t chunk_len, actual;
+-	u8 cmd[4], cmd_len;
++	u8 cmd[5], cmd_len;
+ 	int ret = -1;
+ 
+ 	ret = spi_claim_bus(flash->spi);
+@@ -239,8 +240,8 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+ 		spi_flash_addr(flash, offset, cmd);
+ 		cmd_len = spi_flash_cmdsz(flash);
+ 
+-		debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
+-		      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
++		debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x%02x } chunk_len = %zu\n",
++		      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], cmd[4], chunk_len);
+ 
+ 		ret = spi_flash_write_common(flash, cmd, cmd_len,
+ 					buf + actual, chunk_len);
+@@ -276,9 +277,13 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
+ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+ 		size_t len, void *data)
+ {
+-	u8 cmd[5], cmd_len, bank_sel = 0;
+-	u32 remain_len, read_len;
++	u8 cmd[6], cmd_len;
++	u32 read_len;
+ 	int ret = -1;
++#ifdef CONFIG_SPI_FLASH_BAR
++	u8 bank_sel = 0;
++	u32 remain_len;
++#endif
+ 
+ 	ret = spi_claim_bus(flash->spi);
+ 	if (ret) {
+@@ -305,12 +310,15 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+ 			debug("SF: fail to set bank%d\n", bank_sel);
+ 			goto done;
+ 		}
+-#endif
++
+ 		remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset;
+ 		if (len < remain_len)
+ 			read_len = len;
+ 		else
+ 			read_len = remain_len;
++#else
++		read_len = len;
++#endif
+ 
+ 		spi_flash_addr(flash, offset, cmd);
+ 		cmd_len = spi_flash_cmdsz(flash);
+diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
+index 84289db..ac44287 100644
+--- a/drivers/mtd/spi/sf_probe.c
++++ b/drivers/mtd/spi/sf_probe.c
+@@ -153,6 +153,25 @@ static const struct spi_flash_params spi_flash_params_table[] = {
+ 	 */
+ };
+ 
++int spi_flash_4byte_set(struct spi_flash *flash, u8 idcode0, int enable)
++{
++	u8 cmd, bankaddr;
++
++	switch (idcode0) {
++	case 0xc2:
++	case 0xef:
++	case 0x1c:
++		/* Macronix style */
++		cmd = enable ? CMD_EN4B : CMD_EX4B;
++		return spi_flash_cmd(flash->spi, cmd, NULL, 0);
++	default:
++		/* Spansion style */
++		cmd = CMD_BANKADDR_BRWR;
++		bankaddr = enable << 7;
++		return spi_flash_cmd_write(flash->spi, &cmd, 1, &bankaddr, 1);
++	}
++}
++
+ static int spi_flash_validate_params(struct spi_flash *flash,
+ 		u8 *idcode)
+ {
+@@ -218,8 +237,18 @@ static int spi_flash_validate_params(struct spi_flash *flash,
+ 		flash->poll_cmd = CMD_FLAG_STATUS;
+ #endif
+ 
++#ifndef CONFIG_SPI_FLASH_BAR
++	/* enable 4-byte addressing if the device exceeds 16MiB */
++	if (flash->size > SPI_FLASH_16MB_BOUN) {
++		flash->addr_width = 4;
++		spi_flash_4byte_set(flash, idcode[0], 1);
++	} else {
++		flash->addr_width = 3;
++	}
++#else
+ 	/* Configure default 3-byte addressing */
+ 	flash->addr_width = 3;
++#endif
+ 
+ 	/* Configure the BAR - discover bank cmds and read current bank */
+ #ifdef CONFIG_SPI_FLASH_BAR
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0007-sf-add-support-for-EN25QH256.patch

@@ -0,0 +1,22 @@
+From d5aa0d4117a439803a3d074d2745372036d2a1eb Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <[email protected]>
+Date: Sun, 13 Oct 2013 15:35:34 +0200
+Subject: sf: add support for EN25QH256
+
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
+index ac44287..7e87021 100644
+--- a/drivers/mtd/spi/sf_probe.c
++++ b/drivers/mtd/spi/sf_probe.c
+@@ -53,6 +53,7 @@ static const struct spi_flash_params spi_flash_params_table[] = {
+ 	{"EN25Q64",	   0x1c3017, 0x0,	64 * 1024,   128,	       SECT_4K},
+ 	{"EN25Q128B",	   0x1c3018, 0x0,       64 * 1024,   256,	             0},
+ 	{"EN25S64",	   0x1c3817, 0x0,	64 * 1024,   128,		     0},
++	{"EN25QH256",	   0x1c7019, 0x0,	64 * 1024,   512,		     0},
+ #endif
+ #ifdef CONFIG_SPI_FLASH_GIGADEVICE	/* GIGADEVICE */
+ 	{"GD25Q64B",	   0xc84017, 0x0,	64 * 1024,   128,	       SECT_4K},
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0007-sf-eon-use-16-bit-ID-for-comparison.patch

@@ -1,45 +0,0 @@
-From d32f45357f0475a2f810752eeb9412fe692e1c0a Mon Sep 17 00:00:00 2001
-From: Daniel Schwierzeck <[email protected]>
-Date: Wed, 7 Nov 2012 14:09:21 +0100
-Subject: sf: eon: use 16 bit ID for comparison
-
-Signed-off-by: Daniel Schwierzeck <[email protected]>
-
---- a/drivers/mtd/spi/eon.c
-+++ b/drivers/mtd/spi/eon.c
-@@ -11,19 +11,19 @@
- #include "spi_flash_internal.h"
- 
- struct eon_spi_flash_params {
--	u8 idcode1;
-+	u16 idcode;
- 	u16 nr_sectors;
- 	const char *name;
- };
- 
- static const struct eon_spi_flash_params eon_spi_flash_table[] = {
- 	{
--		.idcode1 = 0x16,
-+		.idcode = 0x3016,
- 		.nr_sectors = 1024,
- 		.name = "EN25Q32B",
- 	},
- 	{
--		.idcode1 = 0x18,
-+		.idcode = 0x3018,
- 		.nr_sectors = 4096,
- 		.name = "EN25Q128",
- 	},
-@@ -33,10 +33,11 @@ int spi_flash_probe_eon(struct spi_flash
- {
- 	const struct eon_spi_flash_params *params;
- 	unsigned int i;
-+	u16 id = idcode[2] | idcode[1] << 8;
- 
- 	for (i = 0; i < ARRAY_SIZE(eon_spi_flash_table); ++i) {
- 		params = &eon_spi_flash_table[i];
--		if (params->idcode1 == idcode[2])
-+		if (params->idcode == id)
- 			break;
- 	}
- 

package/boot/uboot-lantiq/patches/0008-sf-eon-add-support-for-4-byte-address-mode.patch

@@ -1,43 +0,0 @@
-From 37254e3284f61ea495f73a78b7c8efae983781e2 Mon Sep 17 00:00:00 2001
-From: Daniel Schwierzeck <[email protected]>
-Date: Wed, 7 Nov 2012 14:10:07 +0100
-Subject: sf: eon: add support for 4-byte address mode
-
-Signed-off-by: Daniel Schwierzeck <[email protected]>
-
---- a/drivers/mtd/spi/eon.c
-+++ b/drivers/mtd/spi/eon.c
-@@ -10,6 +10,8 @@
- 
- #include "spi_flash_internal.h"
- 
-+#define EN25XX_EN4B		0xb7	/* Enter 4-byte mode */
-+
- struct eon_spi_flash_params {
- 	u16 idcode;
- 	u16 nr_sectors;
-@@ -29,6 +31,13 @@ static const struct eon_spi_flash_params
- 	},
- };
- 
-+static __maybe_unused int eon_set_4byte_mode(struct spi_flash *flash)
-+{
-+	struct spi_slave *spi = flash->spi;
-+
-+	return spi_flash_cmd(spi, EN25XX_EN4B, NULL, 0);
-+}
-+
- int spi_flash_probe_eon(struct spi_flash *flash, u8 *idcode)
- {
- 	const struct eon_spi_flash_params *params;
-@@ -57,5 +66,10 @@ int spi_flash_probe_eon(struct spi_flash
- 	flash->size = 256 * 16
- 	    * params->nr_sectors;
- 
-+#ifdef CONFIG_SPI_FLASH_4BYTE_MODE
-+	if (flash->size > (1 << 24))
-+		flash->set_4byte_mode = eon_set_4byte_mode;
-+#endif
-+
- 	return 1;
- }

package/boot/uboot-lantiq/patches/0008-sf-fix-sector-layout-of-S25FL256S_256K-and-S25FL512S.patch

@@ -0,0 +1,26 @@
+From 5a6d8045190c887c7f65e65fb1bfc8854774c458 Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <[email protected]>
+Date: Sun, 13 Oct 2013 15:40:07 +0200
+Subject: sf: fix sector layout of S25FL256S_256K and S25FL512S_256K
+
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
+index 7e87021..1fc224e 100644
+--- a/drivers/mtd/spi/sf_probe.c
++++ b/drivers/mtd/spi/sf_probe.c
+@@ -80,9 +80,9 @@ static const struct spi_flash_params spi_flash_params_table[] = {
+ 	{"S25FL032P",	   0x010215, 0x4d00,    64 * 1024,    64,	             0},
+ 	{"S25FL064P",	   0x010216, 0x4d00,    64 * 1024,   128,	             0},
+ 	{"S25FL128S_64K",  0x012018, 0x4d01,    64 * 1024,   256,		     0},
+-	{"S25FL256S_256K", 0x010219, 0x4d00,    64 * 1024,   512,	             0},
++	{"S25FL256S_256K", 0x010219, 0x4d00,   256 * 1024,   128,	             0},
+ 	{"S25FL256S_64K",  0x010219, 0x4d01,    64 * 1024,   512,	             0},
+-	{"S25FL512S_256K", 0x010220, 0x4d00,    64 * 1024,  1024,	             0},
++	{"S25FL512S_256K", 0x010220, 0x4d00,   256 * 1024,   256,	             0},
+ 	{"S25FL512S_64K",  0x010220, 0x4d01,    64 * 1024,  1024,	             0},
+ #endif
+ #ifdef CONFIG_SPI_FLASH_STMICRO		/* STMICRO */
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0019-net-switchlib-add-framework-for-ethernet-switch-driv.patch → package/boot/uboot-lantiq/patches/0009-net-switchlib-add-framework-for-ethernet-switch-driv.patch

@@ -1,4 +1,4 @@
-From d8b1597130d228bc7e2bafd0c8d097529018c833 Mon Sep 17 00:00:00 2001
+From 0dff8c753c8929a478357abb38db0d1c1a60ec94 Mon Sep 17 00:00:00 2001
 From: Daniel Schwierzeck <[email protected]>
 Date: Wed, 29 Aug 2012 22:08:15 +0200
 Subject: net: switchlib: add framework for ethernet switch drivers
@@ -10,9 +10,11 @@ setup code for switch devices across different boards.
 Signed-off-by: Daniel Schwierzeck <[email protected]>
 Cc: Joe Hershberger <[email protected]>
 
+diff --git a/Makefile b/Makefile
+index dc04179..6ee9a3c 100644
 --- a/Makefile
 +++ b/Makefile
-@@ -291,6 +291,7 @@ LIBS-y += drivers/mtd/ubi/libubi.o
+@@ -280,6 +280,7 @@ LIBS-y += drivers/mtd/ubi/libubi.o
  LIBS-y += drivers/mtd/spi/libspi_flash.o
  LIBS-y += drivers/net/libnet.o
  LIBS-y += drivers/net/phy/libphy.o
@@ -20,15 +22,17 @@ Cc: Joe Hershberger <[email protected]>
  LIBS-y += drivers/pci/libpci.o
  LIBS-y += drivers/pcmcia/libpcmcia.o
  LIBS-y += drivers/power/libpower.o \
+diff --git a/drivers/net/switch/Makefile b/drivers/net/switch/Makefile
+new file mode 100644
+index 0000000..31719d8
 --- /dev/null
 +++ b/drivers/net/switch/Makefile
-@@ -0,0 +1,31 @@
-+#
-+# This file is released under the terms of GPL v2 and any later version.
-+# See the file COPYING in the root directory of the source tree for details.
+@@ -0,0 +1,30 @@
 +#
 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, [email protected]
-+# Copyright (C) 2011-2012 Daniel Schwierzeck, [email protected]
++# Copyright (C) 2011-2013 Daniel Schwierzeck, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
 +#
 +
 +include $(TOPDIR)/config.mk
@@ -54,14 +58,16 @@ Cc: Joe Hershberger <[email protected]>
 +sinclude $(obj).depend
 +
 +#########################################################################
+diff --git a/drivers/net/switch/switch.c b/drivers/net/switch/switch.c
+new file mode 100644
+index 0000000..0e1d6b7
 --- /dev/null
 +++ b/drivers/net/switch/switch.c
-@@ -0,0 +1,63 @@
+@@ -0,0 +1,62 @@
 +/*
-+ * Copyright (C) 2011-2012 Daniel Schwierzeck, [email protected]
++ * Copyright (C) 2011-2013 Daniel Schwierzeck, [email protected]
 + *
-+ * This file is released under the terms of GPL v2 and any later version.
-+ * See the file COPYING in the root directory of the source tree for details.
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <common.h>
@@ -120,14 +126,17 @@ Cc: Joe Hershberger <[email protected]>
 +
 +	return NULL;
 +}
+diff --git a/include/switch.h b/include/switch.h
+new file mode 100644
+index 0000000..4a7ae63
 --- /dev/null
 +++ b/include/switch.h
-@@ -0,0 +1,95 @@
+@@ -0,0 +1,102 @@
 +/*
 + * This file is released under the terms of GPL v2 and any later version.
 + * See the file COPYING in the root directory of the source tree for details.
 + *
-+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
++ * Copyright (C) 2011-2013 Daniel Schwierzeck, [email protected]
 + */
 +
 +#ifndef __SWITCH_H
@@ -203,7 +212,14 @@ Cc: Joe Hershberger <[email protected]>
 + * Probe the available switch chips and connect the found one
 + * with the given MII bus
 + */
++#ifdef CONFIG_SWITCH_MULTI
 +extern struct switch_device *switch_connect(struct mii_dev *bus);
++#else
++static inline struct switch_device *switch_connect(struct mii_dev *bus)
++{
++	return NULL;
++}
++#endif
 +
 +/*
 + * Setup the given switch device
@@ -218,9 +234,11 @@ Cc: Joe Hershberger <[email protected]>
 +
 +#endif /* __SWITCH_H */
 +
+diff --git a/net/eth.c b/net/eth.c
+index c96e767..03ecc1c 100644
 --- a/net/eth.c
 +++ b/net/eth.c
-@@ -26,6 +26,7 @@
+@@ -10,6 +10,7 @@
  #include <net.h>
  #include <miiphy.h>
  #include <phy.h>
@@ -228,7 +246,7 @@ Cc: Joe Hershberger <[email protected]>
  
  void eth_parse_enetaddr(const char *addr, uchar *enetaddr)
  {
-@@ -303,6 +304,8 @@ int eth_initialize(bd_t *bis)
+@@ -287,6 +288,8 @@ int eth_initialize(bd_t *bis)
  	phy_init();
  #endif
  
@@ -237,3 +255,6 @@ Cc: Joe Hershberger <[email protected]>
  	eth_env_init(bis);
  
  	/*
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0009-sf-eon-add-support-for-EN25QH256.patch

@@ -1,21 +0,0 @@
-From e510be1145796cd44cf5800e187a94ad7c19e764 Mon Sep 17 00:00:00 2001
-From: Daniel Schwierzeck <[email protected]>
-Date: Wed, 7 Nov 2012 14:10:34 +0100
-Subject: sf: eon: add support for EN25QH256
-
-Signed-off-by: Daniel Schwierzeck <[email protected]>
-
---- a/drivers/mtd/spi/eon.c
-+++ b/drivers/mtd/spi/eon.c
-@@ -29,6 +29,11 @@ static const struct eon_spi_flash_params
- 		.nr_sectors = 4096,
- 		.name = "EN25Q128",
- 	},
-+	{
-+		.idcode = 0x7019,
-+		.nr_sectors = 8192,
-+		.name = "EN25QH256",
-+	},
- };
- 
- static __maybe_unused int eon_set_4byte_mode(struct spi_flash *flash)

package/boot/uboot-lantiq/patches/0020-net-switchlib-add-driver-for-Lantiq-PSB697X-switch-f.patch → package/boot/uboot-lantiq/patches/0010-net-switchlib-add-driver-for-Lantiq-PSB697X-switch-f.patch

@@ -1,13 +1,15 @@
-From b8c666eda693906488637c414db9db35b6760e4a Mon Sep 17 00:00:00 2001
+From e2c59cedebf72e4a002134a2932f722b508a5448 Mon Sep 17 00:00:00 2001
 From: Daniel Schwierzeck <[email protected]>
 Date: Wed, 29 Aug 2012 22:08:15 +0200
 Subject: net: switchlib: add driver for Lantiq PSB697X switch family
 
 Signed-off-by: Daniel Schwierzeck <[email protected]>
 
+diff --git a/drivers/net/switch/Makefile b/drivers/net/switch/Makefile
+index 31719d8..a426774 100644
 --- a/drivers/net/switch/Makefile
 +++ b/drivers/net/switch/Makefile
-@@ -11,6 +11,7 @@ include $(TOPDIR)/config.mk
+@@ -10,6 +10,7 @@ include $(TOPDIR)/config.mk
  LIB	:= $(obj)libswitch.o
  
  COBJS-$(CONFIG_SWITCH_MULTI) += switch.o
@@ -15,14 +17,16 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
  
  COBJS	:= $(COBJS-y)
  SRCS	:= $(COBJS:.o=.c)
+diff --git a/drivers/net/switch/psb697x.c b/drivers/net/switch/psb697x.c
+new file mode 100644
+index 0000000..cb6c391
 --- /dev/null
 +++ b/drivers/net/switch/psb697x.c
-@@ -0,0 +1,119 @@
+@@ -0,0 +1,118 @@
 +/*
-+ * Copyright (C) 2011-2012 Daniel Schwierzeck, [email protected]
++ * Copyright (C) 2011-2013 Daniel Schwierzeck, [email protected]
 + *
-+ * This file is released under the terms of GPL v2 and any later version.
-+ * See the file COPYING in the root directory of the source tree for details.
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <common.h>
@@ -137,9 +141,11 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +
 +	switch_driver_register(&psb697x_drv);
 +}
+diff --git a/drivers/net/switch/switch.c b/drivers/net/switch/switch.c
+index 0e1d6b7..3d02610 100644
 --- a/drivers/net/switch/switch.c
 +++ b/drivers/net/switch/switch.c
-@@ -18,6 +18,10 @@ void switch_init(void)
+@@ -17,6 +17,10 @@ void switch_init(void)
  	INIT_LIST_HEAD(&switch_drivers);
  	INIT_LIST_HEAD(&switch_devices);
  
@@ -150,9 +156,11 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
  	board_switch_init();
  }
  
+diff --git a/include/switch.h b/include/switch.h
+index 4a7ae63..fd3cdbd 100644
 --- a/include/switch.h
 +++ b/include/switch.h
-@@ -90,6 +90,7 @@ static inline void switch_setup(struct s
+@@ -97,6 +97,7 @@ static inline void switch_setup(struct switch_device *dev)
  }
  
  /* Init functions for supported Switch drivers */
@@ -160,3 +168,6 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
  
  #endif /* __SWITCH_H */
  
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0010-sf-spansion-fix-device-IDs-and-sector-architecture-f.patch

@@ -1,30 +0,0 @@
-From 81a8e9e192d53ce8b5cafd47190d6c6826519d09 Mon Sep 17 00:00:00 2001
-From: Daniel Schwierzeck <[email protected]>
-Date: Wed, 7 Nov 2012 14:58:59 +0100
-Subject: sf: spansion: fix device IDs and sector architecture for S25FL256S
-
-Signed-off-by: Daniel Schwierzeck <[email protected]>
-
---- a/drivers/mtd/spi/spansion.c
-+++ b/drivers/mtd/spi/spansion.c
-@@ -97,11 +97,18 @@ static const struct spansion_spi_flash_p
- 		.name = "S25FL129P_64K",
- 	},
- 	{
--		.idcode1 = 0x2019,
-+		.idcode1 = 0x0219,
- 		.idcode2 = 0x4d01,
- 		.pages_per_sector = 256,
- 		.nr_sectors = 512,
--		.name = "S25FL256S",
-+		.name = "S25FL256S_64K",
-+	},
-+	{
-+		.idcode1 = 0x0219,
-+		.idcode2 = 0x4d00,
-+		.pages_per_sector = 1024,
-+		.nr_sectors = 128,
-+		.name = "S25FL256S_256K",
- 	},
- };
- 

package/boot/uboot-lantiq/patches/0021-net-switchlib-add-driver-for-Lantiq-ADM6996I-switch-.patch → package/boot/uboot-lantiq/patches/0011-net-switchlib-add-driver-for-Lantiq-ADM6996I-switch-.patch

@@ -1,13 +1,15 @@
-From fcbbb1beb2ae862f5c703c5719ed0e155cbbf82f Mon Sep 17 00:00:00 2001
+From c291443dc97dadcf0c6afd04688a7d9f79a221b5 Mon Sep 17 00:00:00 2001
 From: Daniel Schwierzeck <[email protected]>
 Date: Wed, 29 Aug 2012 22:08:16 +0200
 Subject: net: switchlib: add driver for Lantiq ADM6996I switch family
 
 Signed-off-by: Daniel Schwierzeck <[email protected]>
 
+diff --git a/drivers/net/switch/Makefile b/drivers/net/switch/Makefile
+index a426774..6b7eeb9 100644
 --- a/drivers/net/switch/Makefile
 +++ b/drivers/net/switch/Makefile
-@@ -12,6 +12,7 @@ LIB	:= $(obj)libswitch.o
+@@ -11,6 +11,7 @@ LIB	:= $(obj)libswitch.o
  
  COBJS-$(CONFIG_SWITCH_MULTI) += switch.o
  COBJS-$(CONFIG_SWITCH_PSB697X) += psb697x.o
@@ -15,14 +17,16 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
  
  COBJS	:= $(COBJS-y)
  SRCS	:= $(COBJS:.o=.c)
+diff --git a/drivers/net/switch/adm6996i.c b/drivers/net/switch/adm6996i.c
+new file mode 100644
+index 0000000..46fcdc9
 --- /dev/null
 +++ b/drivers/net/switch/adm6996i.c
-@@ -0,0 +1,116 @@
+@@ -0,0 +1,115 @@
 +/*
-+ * Copyright (C) 2011-2012 Daniel Schwierzeck, [email protected]
++ * Copyright (C) 2011-2013 Daniel Schwierzeck, [email protected]
 + *
-+ * This file is released under the terms of GPL v2 and any later version.
-+ * See the file COPYING in the root directory of the source tree for details.
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <common.h>
@@ -134,9 +138,11 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +
 +	switch_driver_register(&adm6996i_drv);
 +}
+diff --git a/drivers/net/switch/switch.c b/drivers/net/switch/switch.c
+index 3d02610..ea3fe9c 100644
 --- a/drivers/net/switch/switch.c
 +++ b/drivers/net/switch/switch.c
-@@ -21,6 +21,9 @@ void switch_init(void)
+@@ -20,6 +20,9 @@ void switch_init(void)
  #if defined(CONFIG_SWITCH_PSB697X)
  	switch_psb697x_init();
  #endif
@@ -146,9 +152,11 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
  
  	board_switch_init();
  }
+diff --git a/include/switch.h b/include/switch.h
+index fd3cdbd..4b46df0 100644
 --- a/include/switch.h
 +++ b/include/switch.h
-@@ -91,6 +91,7 @@ static inline void switch_setup(struct s
+@@ -98,6 +98,7 @@ static inline void switch_setup(struct switch_device *dev)
  
  /* Init functions for supported Switch drivers */
  extern void switch_psb697x_init(void);
@@ -156,3 +164,6 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
  
  #endif /* __SWITCH_H */
  
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0011-sf-spansion-add-support-for-4-byte-address-mode.patch

@@ -1,55 +0,0 @@
-From 0add8e5c60961d2b99174610df8d3d9d6d192b74 Mon Sep 17 00:00:00 2001
-From: Daniel Schwierzeck <[email protected]>
-Date: Wed, 7 Nov 2012 14:16:11 +0100
-Subject: sf: spansion: add support for 4-byte address mode
-
-Signed-off-by: Daniel Schwierzeck <[email protected]>
-
---- a/drivers/mtd/spi/spansion.c
-+++ b/drivers/mtd/spi/spansion.c
-@@ -31,6 +31,10 @@
- 
- #include "spi_flash_internal.h"
- 
-+#define S25FLXX_BRRD		0x16		/* Read Bank Register */
-+#define S25FLXX_BRWR		0x17		/* Write Bank Register */
-+#define S25FLXX_BAR_EXTADD	(1 << 7)	/* Extended address enable */
-+
- struct spansion_spi_flash_params {
- 	u16 idcode1;
- 	u16 idcode2;
-@@ -112,6 +116,23 @@ static const struct spansion_spi_flash_p
- 	},
- };
- 
-+static __maybe_unused int spansion_set_4byte_mode(struct spi_flash *flash)
-+{
-+	struct spi_slave *spi = flash->spi;
-+	u8 bar, cmd;
-+	int err;
-+
-+	cmd = S25FLXX_BRRD;
-+	err = spi_flash_cmd(spi, cmd, &bar, 1);
-+	if (err)
-+		return err;
-+
-+	bar |= S25FLXX_BAR_EXTADD;
-+	cmd = S25FLXX_BRWR;
-+
-+	return spi_flash_cmd_write(spi, &cmd, 1, &bar, 1);
-+}
-+
- int spi_flash_probe_spansion(struct spi_flash *flash, u8 *idcode)
- {
- 	const struct spansion_spi_flash_params *params;
-@@ -144,5 +165,10 @@ int spi_flash_probe_spansion(struct spi_
- 	flash->sector_size = 256 * params->pages_per_sector;
- 	flash->size = flash->sector_size * params->nr_sectors;
- 
-+#ifdef CONFIG_SPI_FLASH_4BYTE_MODE
-+	if (flash->size > (1 << 24))
-+		flash->set_4byte_mode = spansion_set_4byte_mode;
-+#endif
-+
- 	return 1;
- }

package/boot/uboot-lantiq/patches/0022-net-switchlib-add-driver-for-Atheros-AR8216.patch → package/boot/uboot-lantiq/patches/0012-net-switchlib-add-driver-for-Atheros-AR8216.patch

@@ -1,14 +1,16 @@
-From 16b8c52f80f20e07866e397ff52ff9658766437b Mon Sep 17 00:00:00 2001
-From: Luka Perkov <[email protected]>
+From 1a1d61a2faf0390033a3766559ce0e758e15894e Mon Sep 17 00:00:00 2001
+From: Luka Perkov <[email protected]>
 Date: Wed, 29 Aug 2012 22:08:16 +0200
 Subject: net: switchlib: add driver for Atheros AR8216
 
-Signed-off-by: Luka Perkov <[email protected]>
+Signed-off-by: Luka Perkov <[email protected]>
 Signed-off-by: Daniel Schwierzeck <[email protected]>
 
+diff --git a/drivers/net/switch/Makefile b/drivers/net/switch/Makefile
+index 6b7eeb9..7400897 100644
 --- a/drivers/net/switch/Makefile
 +++ b/drivers/net/switch/Makefile
-@@ -13,6 +13,7 @@ LIB	:= $(obj)libswitch.o
+@@ -12,6 +12,7 @@ LIB	:= $(obj)libswitch.o
  COBJS-$(CONFIG_SWITCH_MULTI) += switch.o
  COBJS-$(CONFIG_SWITCH_PSB697X) += psb697x.o
  COBJS-$(CONFIG_SWITCH_ADM6996I) += adm6996i.o
@@ -16,14 +18,16 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
  
  COBJS	:= $(COBJS-y)
  SRCS	:= $(COBJS:.o=.c)
+diff --git a/drivers/net/switch/ar8216.c b/drivers/net/switch/ar8216.c
+new file mode 100644
+index 0000000..f1348f0
 --- /dev/null
 +++ b/drivers/net/switch/ar8216.c
-@@ -0,0 +1,115 @@
+@@ -0,0 +1,114 @@
 +/*
 + * Copyright (C) 2012 Luka Perkov <[email protected]>
 + *
-+ * This file is released under the terms of GPL v2 and any later version.
-+ * See the file COPYING in the root directory of the source tree for details.
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <common.h>
@@ -134,9 +138,11 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +
 +	switch_driver_register(&ar8216_drv);
 +}
+diff --git a/drivers/net/switch/switch.c b/drivers/net/switch/switch.c
+index ea3fe9c..3e34a7f 100644
 --- a/drivers/net/switch/switch.c
 +++ b/drivers/net/switch/switch.c
-@@ -24,6 +24,9 @@ void switch_init(void)
+@@ -23,6 +23,9 @@ void switch_init(void)
  #if defined(CONFIG_SWITCH_ADM6996I)
  	switch_adm6996i_init();
  #endif
@@ -146,9 +152,11 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
  
  	board_switch_init();
  }
+diff --git a/include/switch.h b/include/switch.h
+index 4b46df0..ae7b123 100644
 --- a/include/switch.h
 +++ b/include/switch.h
-@@ -92,6 +92,7 @@ static inline void switch_setup(struct s
+@@ -99,6 +99,7 @@ static inline void switch_setup(struct switch_device *dev)
  /* Init functions for supported Switch drivers */
  extern void switch_psb697x_init(void);
  extern void switch_adm6996i_init(void);
@@ -156,3 +164,6 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
  
  #endif /* __SWITCH_H */
  
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0012-sf-spansion-add-support-for-S25FL512S.patch

@@ -1,23 +0,0 @@
-From bff335ac524843bc90163c3b231091a5016f8670 Mon Sep 17 00:00:00 2001
-From: Daniel Schwierzeck <[email protected]>
-Date: Wed, 7 Nov 2012 15:07:54 +0100
-Subject: sf: spansion: add support for S25FL512S
-
-Signed-off-by: Daniel Schwierzeck <[email protected]>
-
---- a/drivers/mtd/spi/spansion.c
-+++ b/drivers/mtd/spi/spansion.c
-@@ -114,6 +114,13 @@ static const struct spansion_spi_flash_p
- 		.nr_sectors = 128,
- 		.name = "S25FL256S_256K",
- 	},
-+	{
-+		.idcode1 = 0x0220,
-+		.idcode2 = 0x4d00,
-+		.pages_per_sector = 1024,
-+		.nr_sectors = 256,
-+		.name = "S25FL512S_256K",
-+	},
- };
- 
- static __maybe_unused int spansion_set_4byte_mode(struct spi_flash *flash)

package/boot/uboot-lantiq/patches/0013-net-switchlib-add-driver-for-REALTEK-RTL8306.patch

@@ -0,0 +1,387 @@
+From 42cb399df978a33539b95d668b3f973d927cb902 Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <[email protected]>
+Date: Mon, 17 Dec 2012 23:37:57 +0100
+Subject: net: switchlib: add driver for REALTEK RTL8306
+
+Signed-off-by: Oliver Muth <[email protected]>
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/drivers/net/switch/Makefile b/drivers/net/switch/Makefile
+index 7400897..08c6972 100644
+--- a/drivers/net/switch/Makefile
++++ b/drivers/net/switch/Makefile
+@@ -13,6 +13,7 @@ COBJS-$(CONFIG_SWITCH_MULTI) += switch.o
+ COBJS-$(CONFIG_SWITCH_PSB697X) += psb697x.o
+ COBJS-$(CONFIG_SWITCH_ADM6996I) += adm6996i.o
+ COBJS-$(CONFIG_SWITCH_AR8216) += ar8216.o
++COBJS-$(CONFIG_SWITCH_RTL8306) += rtl8306.o
+ 
+ COBJS	:= $(COBJS-y)
+ SRCS	:= $(COBJS:.o=.c)
+diff --git a/drivers/net/switch/rtl8306.c b/drivers/net/switch/rtl8306.c
+new file mode 100644
+index 0000000..7a6a917
+--- /dev/null
++++ b/drivers/net/switch/rtl8306.c
+@@ -0,0 +1,332 @@
++/*
++ * Based on OpenWRT linux driver
++ *
++ * Copyright (C) 2011-2012 Daniel Schwierzeck, [email protected]
++ * Copyright (C) 2009 Felix Fietkau <[email protected]>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++#define DEBUG
++#include <common.h>
++#include <malloc.h>
++#include <switch.h>
++#include <miiphy.h>
++
++#define RTL8306_REG_PAGE		16
++#define RTL8306_REG_PAGE_LO		(1 << 15)
++#define RTL8306_REG_PAGE_HI		(1 << 1) /* inverted */
++#define RTL8306_CHIPID			0x5988
++
++#define RTL8306_NUM_VLANS		16
++#define RTL8306_NUM_PORTS		6
++#define RTL8306_PORT_CPU		5
++#define RTL8306_NUM_PAGES		4
++#define RTL8306_NUM_REGS		32
++
++enum {
++	RTL_TYPE_S,
++	RTL_TYPE_SD,
++	RTL_TYPE_SDM,
++};
++
++struct rtl_reg {
++	int page;
++	int phy;
++	int reg;
++	int bits;
++	int shift;
++	int inverted;
++};
++
++enum rtl_regidx {
++	RTL_REG_CHIPID,
++	RTL_REG_CHIPVER,
++	RTL_REG_CHIPTYPE,
++	RTL_REG_CPUPORT,
++
++	RTL_REG_EN_CPUPORT,
++	RTL_REG_EN_TAG_OUT,
++	RTL_REG_EN_TAG_CLR,
++	RTL_REG_EN_TAG_IN,
++	RTL_REG_TRAP_CPU,
++	RTL_REG_TRUNK_PORTSEL,
++	RTL_REG_EN_TRUNK,
++	RTL_REG_RESET,
++	RTL_REG_PHY_RESET,
++	RTL_REG_CPU_LINKUP,
++
++	RTL_REG_VLAN_ENABLE,
++	RTL_REG_VLAN_FILTER,
++	RTL_REG_VLAN_TAG_ONLY,
++	RTL_REG_VLAN_TAG_AWARE,
++#define RTL_VLAN_ENUM(id) \
++	RTL_REG_VLAN##id##_VID, \
++	RTL_REG_VLAN##id##_PORTMASK
++	RTL_VLAN_ENUM(0),
++	RTL_VLAN_ENUM(1),
++	RTL_VLAN_ENUM(2),
++	RTL_VLAN_ENUM(3),
++	RTL_VLAN_ENUM(4),
++	RTL_VLAN_ENUM(5),
++	RTL_VLAN_ENUM(6),
++	RTL_VLAN_ENUM(7),
++	RTL_VLAN_ENUM(8),
++	RTL_VLAN_ENUM(9),
++	RTL_VLAN_ENUM(10),
++	RTL_VLAN_ENUM(11),
++	RTL_VLAN_ENUM(12),
++	RTL_VLAN_ENUM(13),
++	RTL_VLAN_ENUM(14),
++	RTL_VLAN_ENUM(15),
++#define RTL_PORT_ENUM(id) \
++	RTL_REG_PORT##id##_PVID, \
++	RTL_REG_PORT##id##_NULL_VID_REPLACE, \
++	RTL_REG_PORT##id##_NON_PVID_DISCARD, \
++	RTL_REG_PORT##id##_VID_INSERT, \
++	RTL_REG_PORT##id##_TAG_INSERT, \
++	RTL_REG_PORT##id##_LINK, \
++	RTL_REG_PORT##id##_SPEED, \
++	RTL_REG_PORT##id##_NWAY, \
++	RTL_REG_PORT##id##_NRESTART, \
++	RTL_REG_PORT##id##_DUPLEX, \
++	RTL_REG_PORT##id##_RXEN, \
++	RTL_REG_PORT##id##_TXEN, \
++	RTL_REG_PORT##id##_LRNEN
++	RTL_PORT_ENUM(0),
++	RTL_PORT_ENUM(1),
++	RTL_PORT_ENUM(2),
++	RTL_PORT_ENUM(3),
++	RTL_PORT_ENUM(4),
++	RTL_PORT_ENUM(5),
++};
++
++static const struct rtl_reg rtl_regs[] = {
++	[RTL_REG_CHIPID]         = { 0, 4, 30, 16,  0, 0 },
++	[RTL_REG_CHIPVER]        = { 0, 4, 31,  8,  0, 0 },
++	[RTL_REG_CHIPTYPE]       = { 0, 4, 31,  2,  8, 0 },
++
++	/* CPU port number */
++	[RTL_REG_CPUPORT]        = { 2, 4, 21,  3,  0, 0 },
++	/* Enable CPU port function */
++	[RTL_REG_EN_CPUPORT]     = { 3, 2, 21,  1, 15, 1 },
++	/* Enable CPU port tag insertion */
++	[RTL_REG_EN_TAG_OUT]     = { 3, 2, 21,  1, 12, 0 },
++	/* Enable CPU port tag removal */
++	[RTL_REG_EN_TAG_CLR]     = { 3, 2, 21,  1, 11, 0 },
++	/* Enable CPU port tag checking */
++	[RTL_REG_EN_TAG_IN]      = { 0, 4, 21,  1,  7, 0 },
++	[RTL_REG_EN_TRUNK]       = { 0, 0, 19,  1, 11, 1 },
++	[RTL_REG_TRUNK_PORTSEL]  = { 0, 0, 16,  1,  6, 1 },
++	[RTL_REG_RESET]          = { 0, 0, 16,  1, 12, 0 },
++	[RTL_REG_PHY_RESET]	 = { 0, 0,  0,  1, 15, 0 },
++	[RTL_REG_CPU_LINKUP]	 = { 0, 6, 22,  1, 15, 0 },
++	[RTL_REG_TRAP_CPU]       = { 3, 2, 22,  1,  6, 0 },
++
++	[RTL_REG_VLAN_TAG_ONLY]  = { 0, 0, 16,  1,  8, 1 },
++	[RTL_REG_VLAN_FILTER]    = { 0, 0, 16,  1,  9, 1 },
++	[RTL_REG_VLAN_TAG_AWARE] = { 0, 0, 16,  1, 10, 1 },
++	[RTL_REG_VLAN_ENABLE]    = { 0, 0, 18,  1,  8, 1 },
++
++#define RTL_VLAN_REGS(id, phy, page, regofs) \
++	[RTL_REG_VLAN##id##_VID] = { page, phy, 25 + regofs, 12, 0, 0 }, \
++	[RTL_REG_VLAN##id##_PORTMASK] = { page, phy, 24 + regofs, 6, 0, 0 }
++	RTL_VLAN_REGS( 0, 0, 0, 0),
++	RTL_VLAN_REGS( 1, 1, 0, 0),
++	RTL_VLAN_REGS( 2, 2, 0, 0),
++	RTL_VLAN_REGS( 3, 3, 0, 0),
++	RTL_VLAN_REGS( 4, 4, 0, 0),
++	RTL_VLAN_REGS( 5, 0, 1, 2),
++	RTL_VLAN_REGS( 6, 1, 1, 2),
++	RTL_VLAN_REGS( 7, 2, 1, 2),
++	RTL_VLAN_REGS( 8, 3, 1, 2),
++	RTL_VLAN_REGS( 9, 4, 1, 2),
++	RTL_VLAN_REGS(10, 0, 1, 4),
++	RTL_VLAN_REGS(11, 1, 1, 4),
++	RTL_VLAN_REGS(12, 2, 1, 4),
++	RTL_VLAN_REGS(13, 3, 1, 4),
++	RTL_VLAN_REGS(14, 4, 1, 4),
++	RTL_VLAN_REGS(15, 0, 1, 6),
++
++#define REG_PORT_SETTING(port, phy) \
++	[RTL_REG_PORT##port##_SPEED] = { 0, phy, 0, 1, 13, 0 }, \
++	[RTL_REG_PORT##port##_NWAY] = { 0, phy, 0, 1, 12, 0 }, \
++	[RTL_REG_PORT##port##_NRESTART] = { 0, phy, 0, 1, 9, 0 }, \
++	[RTL_REG_PORT##port##_DUPLEX] = { 0, phy, 0, 1, 8, 0 }, \
++	[RTL_REG_PORT##port##_TXEN] = { 0, phy, 24, 1, 11, 0 }, \
++	[RTL_REG_PORT##port##_RXEN] = { 0, phy, 24, 1, 10, 0 }, \
++	[RTL_REG_PORT##port##_LRNEN] = { 0, phy, 24, 1, 9, 0 }, \
++	[RTL_REG_PORT##port##_LINK] = { 0, phy, 1, 1, 2, 0 }, \
++	[RTL_REG_PORT##port##_NULL_VID_REPLACE] = { 0, phy, 22, 1, 12, 0 }, \
++	[RTL_REG_PORT##port##_NON_PVID_DISCARD] = { 0, phy, 22, 1, 11, 0 }, \
++	[RTL_REG_PORT##port##_VID_INSERT] = { 0, phy, 22, 2, 9, 0 }, \
++	[RTL_REG_PORT##port##_TAG_INSERT] = { 0, phy, 22, 2, 0, 0 }
++
++	REG_PORT_SETTING(0, 0),
++	REG_PORT_SETTING(1, 1),
++	REG_PORT_SETTING(2, 2),
++	REG_PORT_SETTING(3, 3),
++	REG_PORT_SETTING(4, 4),
++	REG_PORT_SETTING(5, 6),
++
++#define REG_PORT_PVID(phy, page, regofs) \
++	{ page, phy, 24 + regofs, 4, 12, 0 }
++	[RTL_REG_PORT0_PVID] = REG_PORT_PVID(0, 0, 0),
++	[RTL_REG_PORT1_PVID] = REG_PORT_PVID(1, 0, 0),
++	[RTL_REG_PORT2_PVID] = REG_PORT_PVID(2, 0, 0),
++	[RTL_REG_PORT3_PVID] = REG_PORT_PVID(3, 0, 0),
++	[RTL_REG_PORT4_PVID] = REG_PORT_PVID(4, 0, 0),
++	[RTL_REG_PORT5_PVID] = REG_PORT_PVID(0, 1, 2),
++};
++
++static void rtl_set_page(struct mii_dev *bus, unsigned int page)
++{
++	u16 pgsel;
++
++	BUG_ON(page > RTL8306_NUM_PAGES);
++
++	pgsel = bus->read(bus, 0, MDIO_DEVAD_NONE, RTL8306_REG_PAGE);
++	pgsel &= ~(RTL8306_REG_PAGE_LO | RTL8306_REG_PAGE_HI);
++
++	if (page & (1 << 0))
++		pgsel |= RTL8306_REG_PAGE_LO;
++
++	if (!(page & (1 << 1))) /* bit is inverted */
++		pgsel |= RTL8306_REG_PAGE_HI;
++
++	bus->write(bus, 0, MDIO_DEVAD_NONE, RTL8306_REG_PAGE, pgsel);
++
++}
++
++static __maybe_unused int rtl_w16(struct mii_dev *bus, unsigned int page, unsigned int phy,
++			unsigned int reg, u16 val)
++{
++	rtl_set_page(bus, page);
++
++	bus->write(bus, phy, MDIO_DEVAD_NONE, reg, val);
++	bus->read(bus, phy, MDIO_DEVAD_NONE, reg); /* flush */
++
++	return 0;
++}
++
++static int rtl_r16(struct mii_dev *bus, unsigned int page, unsigned int phy,
++			unsigned int reg)
++{
++	rtl_set_page(bus, page);
++
++	return bus->read(bus, phy, MDIO_DEVAD_NONE, reg);
++}
++
++static u16 rtl_rmw(struct mii_dev *bus, unsigned int page, unsigned int phy,
++			unsigned int reg, u16 mask, u16 val)
++{
++	u16 r;
++
++	rtl_set_page(bus, page);
++
++	r = bus->read(bus, phy, MDIO_DEVAD_NONE, reg);
++	r &= ~mask;
++	r |= val;
++	bus->write(bus, phy, MDIO_DEVAD_NONE, reg, r);
++
++	return bus->read(bus, phy, MDIO_DEVAD_NONE, reg); /* flush */
++}
++
++static int rtl_get(struct mii_dev *bus, enum rtl_regidx s)
++{
++	const struct rtl_reg *r = &rtl_regs[s];
++	u16 val;
++
++	BUG_ON(s >= ARRAY_SIZE(rtl_regs));
++
++	if (r->bits == 0) /* unimplemented */
++		return 0;
++
++	val = rtl_r16(bus, r->page, r->phy, r->reg);
++
++	if (r->shift > 0)
++		val >>= r->shift;
++
++	if (r->inverted)
++		val = ~val;
++
++	val &= (1 << r->bits) - 1;
++
++	return val;
++}
++
++static __maybe_unused int rtl_set(struct mii_dev *bus, enum rtl_regidx s, unsigned int val)
++{
++	const struct rtl_reg *r = &rtl_regs[s];
++	u16 mask = 0xffff;
++
++	BUG_ON(s >= ARRAY_SIZE(rtl_regs));
++
++	if (r->bits == 0) /* unimplemented */
++		return 0;
++
++	if (r->shift > 0)
++		val <<= r->shift;
++
++	if (r->inverted)
++		val = ~val;
++
++	if (r->bits != 16) {
++		mask = (1 << r->bits) - 1;
++		mask <<= r->shift;
++	}
++
++	val &= mask;
++
++	return rtl_rmw(bus, r->page, r->phy, r->reg, mask, val);
++}
++
++static int rtl8306_probe(struct switch_device *dev)
++{
++	struct mii_dev *bus = dev->bus;
++	unsigned int chipid, chipver, chiptype;
++
++	chipid = rtl_get(bus, RTL_REG_CHIPID);
++	chipver = rtl_get(bus, RTL_REG_CHIPVER);
++	chiptype = rtl_get(bus, RTL_REG_CHIPTYPE);
++
++	debug("%s: chipid %x, chipver %x, chiptype %x\n",
++		__func__, chipid, chipver, chiptype);
++
++	if (chipid == RTL8306_CHIPID)
++		return 0;
++
++	return 1;
++}
++
++static void rtl8306_setup(struct switch_device *dev)
++{
++	struct mii_dev *bus = dev->bus;
++
++	/* initialize cpu port settings */
++	rtl_set(bus, RTL_REG_CPUPORT, dev->cpu_port);
++	rtl_set(bus, RTL_REG_EN_CPUPORT, 1);
++
++	/* enable phy 5 link status */
++	rtl_set(bus, RTL_REG_CPU_LINKUP, 1);
++//	rtl_set(bus, RTL_REG_PORT5_TXEN, 1);
++//	rtl_set(bus, RTL_REG_PORT5_RXEN, 1);
++//	rtl_set(bus, RTL_REG_PORT5_LRNEN, 1);
++#ifdef DEBUG
++ debug("%s: CPU link up: %i\n",
++		__func__, rtl_get(bus, RTL_REG_PORT5_LINK));
++#endif
++
++}
++
++static struct switch_driver rtl8306_drv = {
++	.name = "rtl8306",
++};
++
++void switch_rtl8306_init(void)
++{
++	/* For archs with manual relocation */
++	rtl8306_drv.probe = rtl8306_probe;
++	rtl8306_drv.setup = rtl8306_setup;
++
++	switch_driver_register(&rtl8306_drv);
++}
+diff --git a/drivers/net/switch/switch.c b/drivers/net/switch/switch.c
+index 3e34a7f..2e1c668 100644
+--- a/drivers/net/switch/switch.c
++++ b/drivers/net/switch/switch.c
+@@ -26,6 +26,9 @@ void switch_init(void)
+ #if defined(CONFIG_SWITCH_AR8216)
+ 	switch_ar8216_init();
+ #endif
++#if defined(CONFIG_SWITCH_RTL8306)
++	switch_rtl8306_init();
++#endif
+ 
+ 	board_switch_init();
+ }
+diff --git a/include/switch.h b/include/switch.h
+index ae7b123..927b1d2 100644
+--- a/include/switch.h
++++ b/include/switch.h
+@@ -100,6 +100,7 @@ static inline void switch_setup(struct switch_device *dev)
+ extern void switch_psb697x_init(void);
+ extern void switch_adm6996i_init(void);
+ extern void switch_ar8216_init(void);
++extern void switch_rtl8306_init(void);
+ 
+ #endif /* __SWITCH_H */
+ 
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0013-sf-macronix-add-support-for-4-byte-address-mode.patch

@@ -1,44 +0,0 @@
-From 207662a9270cc542709fbab0d25fbc361b39748c Mon Sep 17 00:00:00 2001
-From: Daniel Schwierzeck <[email protected]>
-Date: Wed, 7 Nov 2012 15:13:49 +0100
-Subject: sf: macronix: add support for 4-byte address mode
-
-Signed-off-by: Daniel Schwierzeck <[email protected]>
-
---- a/drivers/mtd/spi/macronix.c
-+++ b/drivers/mtd/spi/macronix.c
-@@ -35,6 +35,8 @@
- 
- #include "spi_flash_internal.h"
- 
-+#define MX25XX_EN4B		0xb7	/* Enter 4-byte mode */
-+
- struct macronix_spi_flash_params {
- 	u16 idcode;
- 	u16 nr_blocks;
-@@ -79,6 +81,13 @@ static const struct macronix_spi_flash_p
- 	},
- };
- 
-+static __maybe_unused int macronix_set_4byte_mode(struct spi_flash *flash)
-+{
-+	struct spi_slave *spi = flash->spi;
-+
-+	return spi_flash_cmd(spi, MX25XX_EN4B, NULL, 0);
-+}
-+
- int spi_flash_probe_macronix(struct spi_flash *flash, u8 *idcode)
- {
- 	const struct macronix_spi_flash_params *params;
-@@ -106,6 +115,11 @@ int spi_flash_probe_macronix(struct spi_
- 	flash->sector_size = 256 * 16 * 16;
- 	flash->size = flash->sector_size * params->nr_blocks;
- 
-+#ifdef CONFIG_SPI_FLASH_4BYTE_MODE
-+	if (flash->size > (1 << 24))
-+		flash->set_4byte_mode = macronix_set_4byte_mode;
-+#endif
-+
- 	/* Clear BP# bits for read-only flash */
- 	spi_flash_cmd_write_status(flash, 0);
- 

package/boot/uboot-lantiq/patches/0014-sf-macronix-add-support-for-MX25L25635E.patch

@@ -1,21 +0,0 @@
-From 0f31fef3d6a5110684ea31c5064c45fc448013d6 Mon Sep 17 00:00:00 2001
-From: Daniel Schwierzeck <[email protected]>
-Date: Wed, 7 Nov 2012 15:14:24 +0100
-Subject: sf: macronix: add support for MX25L25635E
-
-Signed-off-by: Daniel Schwierzeck <[email protected]>
-
---- a/drivers/mtd/spi/macronix.c
-+++ b/drivers/mtd/spi/macronix.c
-@@ -79,6 +79,11 @@ static const struct macronix_spi_flash_p
- 		.nr_blocks = 256,
- 		.name = "MX25L12855E",
- 	},
-+	{
-+		.idcode = 0x2019,
-+		.nr_blocks = 512,
-+		.name = "MX25L25635E",
-+	},
- };
- 
- static __maybe_unused int macronix_set_4byte_mode(struct spi_flash *flash)

package/boot/uboot-lantiq/patches/0015-MIPS-lantiq-add-support-for-Lantiq-XWAY-ARX100-SoC-f.patch

@@ -0,0 +1,1283 @@
+From 4953294aa8f8b9023e6b5f7f39059706c72d916c Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <[email protected]>
+Date: Sun, 9 Dec 2012 17:54:56 +0100
+Subject: MIPS: lantiq: add support for Lantiq XWAY ARX100 SoC family
+
+Signed-off-by: Luka Perkov <[email protected]>
+Signed-off-by: John Crispin <[email protected]>
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/arch/mips/cpu/mips32/arx100/Makefile b/arch/mips/cpu/mips32/arx100/Makefile
+new file mode 100644
+index 0000000..98f5f73
+--- /dev/null
++++ b/arch/mips/cpu/mips32/arx100/Makefile
+@@ -0,0 +1,31 @@
++#
++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++include $(TOPDIR)/config.mk
++
++LIB	= $(obj)lib$(SOC).o
++
++COBJS-y	+= cgu.o chipid.o ebu.o mem.o pmu.o rcu.o
++SOBJS-y	+= cgu_init.o mem_init.o
++
++COBJS	:= $(COBJS-y)
++SOBJS	:= $(SOBJS-y)
++SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
++
++all:	$(LIB)
++
++$(LIB):	$(obj).depend $(OBJS)
++	$(call cmd_link_o_target, $(OBJS))
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/arch/mips/cpu/mips32/arx100/cgu.c b/arch/mips/cpu/mips32/arx100/cgu.c
+new file mode 100644
+index 0000000..6e71ee7
+--- /dev/null
++++ b/arch/mips/cpu/mips32/arx100/cgu.c
+@@ -0,0 +1,109 @@
++/*
++ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
++ * Copyright (C) 2012 Daniel Schwierzeck, [email protected]
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/arch/soc.h>
++#include <asm/lantiq/clk.h>
++#include <asm/lantiq/io.h>
++
++#define CGU_SYS_DDR_SEL		(1 << 0)
++#define CGU_SYS_CPU_SEL		(1 << 2)
++#define CGU_SYS_SYS_SHIFT	3
++#define CGU_SYS_SYS_MASK	(0x3 << CGU_SYS_SYS_SHIFT)
++#define CGU_SYS_FPI_SEL		(1 << 6)
++#define CGU_SYS_PPE_SEL		(1 << 7)
++
++struct ltq_cgu_regs {
++	u32	rsvd0;
++	__be32	pll0_cfg;	/* PLL0 config */
++	__be32	pll1_cfg;	/* PLL1 config */
++	u32	rsvd2;
++	__be32	sys;		/* System clock */
++	__be32	update;		/* CGU update control */
++	__be32	if_clk;		/* Interface clock */
++	u32	rsvd3;
++	__be32	smd;		/* SDRAM Memory Control */
++	u32	rsvd4;
++	__be32	ct1_sr;		/* CT status 1 */
++	__be32	ct_kval;	/* CT K value */
++	__be32	pcm_cr;		/* PCM control */
++};
++
++static struct ltq_cgu_regs *ltq_cgu_regs =
++	(struct ltq_cgu_regs *) CKSEG1ADDR(LTQ_CGU_BASE);
++
++static inline u32 ltq_cgu_sys_readl(u32 mask, u32 shift)
++{
++	return (ltq_readl(&ltq_cgu_regs->sys) & mask) >> shift;
++}
++
++static unsigned long ltq_get_system_clock(void)
++{
++	u32 sys_sel;
++	unsigned long clk;
++
++	sys_sel = ltq_cgu_sys_readl(CGU_SYS_SYS_MASK, CGU_SYS_SYS_SHIFT);
++
++	switch (sys_sel) {
++	case 0:
++		clk = CLOCK_333_MHZ;
++		break;
++	case 2:
++		clk = CLOCK_393_MHZ;
++		break;
++	default:
++		clk = 0;
++		break;
++	}
++
++	return clk;
++}
++
++unsigned long ltq_get_io_region_clock(void)
++{
++	u32 ddr_sel;
++	unsigned long clk;
++
++	ddr_sel = ltq_cgu_sys_readl(1, CGU_SYS_DDR_SEL);
++
++	if (ddr_sel)
++		clk = ltq_get_system_clock() / 3;
++	else
++		clk = ltq_get_system_clock() / 2;
++
++	return clk;
++}
++
++unsigned long ltq_get_cpu_clock(void)
++{
++	u32 cpu_sel;
++	unsigned long clk;
++
++	cpu_sel = ltq_cgu_sys_readl(1, CGU_SYS_CPU_SEL);
++
++	if (cpu_sel)
++		clk = ltq_get_io_region_clock();
++	else
++		clk = ltq_get_system_clock();
++
++	return clk;
++}
++
++unsigned long ltq_get_bus_clock(void)
++{
++	u32 fpi_sel;
++	unsigned long clk;
++
++	fpi_sel = ltq_cgu_sys_readl(1, CGU_SYS_FPI_SEL);
++
++	if (fpi_sel)
++		clk = ltq_get_io_region_clock() / 2;
++	else
++		clk = ltq_get_io_region_clock();
++
++	return clk;
++}
+diff --git a/arch/mips/cpu/mips32/arx100/cgu_init.S b/arch/mips/cpu/mips32/arx100/cgu_init.S
+new file mode 100644
+index 0000000..ed70cb2
+--- /dev/null
++++ b/arch/mips/cpu/mips32/arx100/cgu_init.S
+@@ -0,0 +1,105 @@
++/*
++ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
++ * Copyright (C) 2012-2013 Daniel Schwierzeck, [email protected]
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <config.h>
++#include <asm/asm.h>
++#include <asm/regdef.h>
++#include <asm/addrspace.h>
++#include <asm/arch/soc.h>
++
++/* CGU module register */
++#define CGU_PLL0_CFG			0x0004	/* PLL0 config */
++#define CGU_PLL1_CFG			0x0008	/* PLL1 config */
++#define CGU_SYS				0x0010	/* System clock */
++#define CGU_UPDATE			0x0014	/* Clock update control */
++
++/* Valid SYS.PPE_SEL values */
++#define CGU_SYS_PPESEL_SHIFT		7
++#define CGU_SYS_PPESEL_250_MHZ		(0x1 << CGU_SYS_PPESEL_SHIFT)
++
++/* Valid SYS.SYS_SEL values */
++#define CGU_SYS_SYSSEL_SHIFT		3
++#define CGU_SYS_SYSSEL_PLL0_333_MHZ	(0x0 << CGU_SYS_SYSSEL_SHIFT)
++#define CGU_SYS_SYSSEL_PLL1_393_MHZ	(0x2 << CGU_SYS_SYSSEL_SHIFT)
++
++/* Valid SYS.CPU_SEL values */
++#define CGU_SYS_CPUSEL_SHIFT		2
++#define CGU_SYS_CPUSEL_EQUAL_SYSCLK	(0x0 << CGU_SYS_CPUSEL_SHIFT)
++#define CGU_SYS_CPUSEL_EQUAL_DDRCLK	(0x1 << CGU_SYS_CPUSEL_SHIFT)
++
++/* Valid SYS.DDR_SEL values */
++#define CGU_SYS_DDRSEL_HALF_SYSCLK	0x0
++#define CGU_SYS_DDRSEL_THIRD_SYSCLK	0x1
++
++#define CGU_UPDATE_UPD			0x1
++
++#if (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_393_DDR_197)
++#define CGU_SYS_PPESEL_CONFIG		CGU_SYS_PPESEL_250_MHZ
++#define CGU_SYS_SYSSEL_CONFIG		CGU_SYS_SYSSEL_PLL1_393_MHZ
++#define CGU_SYS_CPUSEL_CONFIG		CGU_SYS_CPUSEL_EQUAL_SYSCLK
++#define CGU_SYS_DDRSEL_CONFIG		CGU_SYS_DDRSEL_HALF_SYSCLK
++#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_197_DDR_197)
++#define CGU_SYS_PPESEL_CONFIG		CGU_SYS_PPESEL_250_MHZ
++#define CGU_SYS_SYSSEL_CONFIG		CGU_SYS_SYSSEL_PLL1_393_MHZ
++#define CGU_SYS_CPUSEL_CONFIG		CGU_SYS_CPUSEL_EQUAL_DDRCLK
++#define CGU_SYS_DDRSEL_CONFIG		CGU_SYS_DDRSEL_HALF_SYSCLK
++#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_333_DDR_167)
++#define CGU_SYS_PPESEL_CONFIG		CGU_SYS_PPESEL_250_MHZ
++#define CGU_SYS_SYSSEL_CONFIG		CGU_SYS_SYSSEL_PLL0_333_MHZ
++#define CGU_SYS_CPUSEL_CONFIG		CGU_SYS_CPUSEL_EQUAL_SYSCLK
++#define CGU_SYS_DDRSEL_CONFIG		CGU_SYS_DDRSEL_HALF_SYSCLK
++#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_167_DDR_167)
++#define CGU_SYS_PPESEL_CONFIG		CGU_SYS_PPESEL_250_MHZ
++#define CGU_SYS_SYSSEL_CONFIG		CGU_SYS_SYSSEL_PLL0_333_MHZ
++#define CGU_SYS_CPUSEL_CONFIG		CGU_SYS_CPUSEL_EQUAL_DDRCLK
++#define CGU_SYS_DDRSEL_CONFIG		CGU_SYS_DDRSEL_HALF_SYSCLK
++#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_131_DDR_131)
++#define CGU_SYS_PPESEL_CONFIG		CGU_SYS_PPESEL_250_MHZ
++#define CGU_SYS_SYSSEL_CONFIG		CGU_SYS_SYSSEL_PLL1_393_MHZ
++#define CGU_SYS_CPUSEL_CONFIG		CGU_SYS_CPUSEL_EQUAL_DDRCLK
++#define CGU_SYS_DDRSEL_CONFIG		CGU_SYS_DDRSEL_THIRD_SYSCLK
++#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_111_DDR_111)
++#define CGU_SYS_PPESEL_CONFIG		CGU_SYS_PPESEL_250_MHZ
++#define CGU_SYS_SYSSEL_CONFIG		CGU_SYS_SYSSEL_PLL0_333_MHZ
++#define CGU_SYS_CPUSEL_CONFIG		CGU_SYS_CPUSEL_EQUAL_DDRCLK
++#define CGU_SYS_DDRSEL_CONFIG		CGU_SYS_DDRSEL_THIRD_SYSCLK
++#else
++#error "Invalid system clock configuration!"
++#endif
++
++/* Build register values */
++#define CGU_SYS_VALUE		(CGU_SYS_PPESEL_CONFIG | \
++				CGU_SYS_SYSSEL_CONFIG | \
++				CGU_SYS_CPUSEL_CONFIG | \
++				CGU_SYS_DDRSEL_CONFIG)
++
++	.set noreorder
++
++LEAF(ltq_cgu_init)
++	/* Load current CGU register value */
++	li	t0, (LTQ_CGU_BASE | KSEG1)
++	lw	t1, CGU_SYS(t0)
++
++	/* Load target CGU register values */
++	li	t2, CGU_SYS_VALUE
++
++	/* Only update registers if values differ */
++	beq	t1, t2, finished
++	 nop
++
++	/* Store target register values */
++	sw	t2, CGU_SYS(t0)
++
++	/* Trigger CGU update */
++	li	t1, CGU_UPDATE_UPD
++	sw	t1, CGU_UPDATE(t0)
++
++finished:
++	jr	ra
++	 nop
++
++	END(ltq_cgu_init)
+diff --git a/arch/mips/cpu/mips32/arx100/chipid.c b/arch/mips/cpu/mips32/arx100/chipid.c
+new file mode 100644
+index 0000000..e97d7ef
+--- /dev/null
++++ b/arch/mips/cpu/mips32/arx100/chipid.c
+@@ -0,0 +1,60 @@
++/*
++ * Copyright (C) 2012 Daniel Schwierzeck, [email protected]
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/lantiq/io.h>
++#include <asm/lantiq/chipid.h>
++#include <asm/arch/soc.h>
++
++#define LTQ_CHIPID_VERSION_SHIFT	28
++#define LTQ_CHIPID_VERSION_MASK		(0xF << LTQ_CHIPID_VERSION_SHIFT)
++#define LTQ_CHIPID_PNUM_SHIFT		12
++#define LTQ_CHIPID_PNUM_MASK		(0xFFFF << LTQ_CHIPID_PNUM_SHIFT)
++
++struct ltq_chipid_regs {
++	u32	manid;		/* Manufacturer identification */
++	u32	chipid;		/* Chip identification */
++};
++
++static struct ltq_chipid_regs *ltq_chipid_regs =
++	(struct ltq_chipid_regs *) CKSEG1ADDR(LTQ_CHIPID_BASE);
++
++unsigned int ltq_chip_version_get(void)
++{
++	u32 chipid;
++
++	chipid = ltq_readl(&ltq_chipid_regs->chipid);
++
++	return (chipid & LTQ_CHIPID_VERSION_MASK) >> LTQ_CHIPID_VERSION_SHIFT;
++}
++
++unsigned int ltq_chip_partnum_get(void)
++{
++	u32 chipid;
++
++	chipid = ltq_readl(&ltq_chipid_regs->chipid);
++
++	return (chipid & LTQ_CHIPID_PNUM_MASK) >> LTQ_CHIPID_PNUM_SHIFT;
++}
++
++const char *ltq_chip_partnum_str(void)
++{
++	enum ltq_chip_partnum partnum = ltq_chip_partnum_get();
++
++	switch (partnum) {
++	case LTQ_SOC_ARX188:
++		return "ARX188";
++	case LTQ_SOC_ARX186:
++	case LTQ_SOC_ARX186_2:
++		return "ARX186";
++	case LTQ_SOC_ARX182:
++		return "ARX182";
++	default:
++		printf("Unknown partnum: %x\n", partnum);
++	}
++
++	return "";
++}
+diff --git a/arch/mips/cpu/mips32/arx100/config.mk b/arch/mips/cpu/mips32/arx100/config.mk
+new file mode 100644
+index 0000000..442156a
+--- /dev/null
++++ b/arch/mips/cpu/mips32/arx100/config.mk
+@@ -0,0 +1,30 @@
++#
++# Copyright (C) 2011-2013 Daniel Schwierzeck, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++PF_CPPFLAGS_XRX := $(call cc-option,-mtune=34kc,)
++PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_XRX)
++
++ifdef CONFIG_SPL_BUILD
++PF_ABICALLS		:= -mno-abicalls
++PF_PIC			:= -fno-pic
++PF_PIE			:=
++USE_PRIVATE_LIBGCC	:= yes
++endif
++
++LIBS-y += $(CPUDIR)/lantiq-common/liblantiq-common.o
++
++ifndef CONFIG_SPL_BUILD
++ifdef CONFIG_SYS_BOOT_SFSPL
++ALL-y += $(obj)u-boot.ltq.sfspl
++ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.sfspl
++ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.sfspl
++endif
++ifdef CONFIG_SYS_BOOT_NORSPL
++ALL-y += $(obj)u-boot.ltq.norspl
++ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.norspl
++ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.norspl
++endif
++endif
+diff --git a/arch/mips/cpu/mips32/arx100/ebu.c b/arch/mips/cpu/mips32/arx100/ebu.c
+new file mode 100644
+index 0000000..4ab3cf1
+--- /dev/null
++++ b/arch/mips/cpu/mips32/arx100/ebu.c
+@@ -0,0 +1,111 @@
++/*
++ * Copyright (C) 2011-2013 Daniel Schwierzeck, [email protected]
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/arch/soc.h>
++#include <asm/lantiq/io.h>
++
++#define EBU_ADDRSEL_MASK(mask)		((mask & 0xf) << 4)
++#define EBU_ADDRSEL_REGEN		(1 << 0)
++
++#define EBU_CON_WRDIS			(1 << 31)
++#define EBU_CON_AGEN_DEMUX		(0x0 << 24)
++#define EBU_CON_AGEN_MUX		(0x2 << 24)
++#define EBU_CON_SETUP			(1 << 22)
++#define EBU_CON_WAIT_DIS		(0x0 << 20)
++#define EBU_CON_WAIT_ASYNC		(0x1 << 20)
++#define EBU_CON_WAIT_SYNC		(0x2 << 20)
++#define EBU_CON_WINV			(1 << 19)
++#define EBU_CON_PW_8BIT			(0x0 << 16)
++#define EBU_CON_PW_16BIT		(0x1 << 16)
++#define EBU_CON_ALEC(cycles)		((cycles & 0x3) << 14)
++#define EBU_CON_BCGEN_CS		(0x0 << 12)
++#define EBU_CON_BCGEN_INTEL		(0x1 << 12)
++#define EBU_CON_BCGEN_MOTOROLA		(0x2 << 12)
++#define EBU_CON_WAITWRC(cycles)		((cycles & 0x7) << 8)
++#define EBU_CON_WAITRDC(cycles)		((cycles & 0x3) << 6)
++#define EBU_CON_HOLDC(cycles)		((cycles & 0x3) << 4)
++#define EBU_CON_RECOVC(cycles)		((cycles & 0x3) << 2)
++#define EBU_CON_CMULT_1			0x0
++#define EBU_CON_CMULT_4			0x1
++#define EBU_CON_CMULT_8			0x2
++#define EBU_CON_CMULT_16		0x3
++
++#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH)
++#define ebu_region0_enable		1
++#else
++#define ebu_region0_enable		0
++#endif
++
++#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH)
++#define ebu_region1_enable		1
++#else
++#define ebu_region1_enable		0
++#endif
++
++struct ltq_ebu_regs {
++	u32	clc;
++	u32	rsvd0;
++	u32	id;
++	u32	rsvd1;
++	u32	con;
++	u32	rsvd2[3];
++	u32	addr_sel_0;
++	u32	addr_sel_1;
++	u32	addr_sel_2;
++	u32	addr_sel_3;
++	u32	rsvd3[12];
++	u32	con_0;
++	u32	con_1;
++	u32	con_2;
++	u32	con_3;
++};
++
++static struct ltq_ebu_regs *ltq_ebu_regs =
++	(struct ltq_ebu_regs *) CKSEG1ADDR(LTQ_EBU_BASE);
++
++void ltq_ebu_init(void)
++{
++	if (ebu_region0_enable) {
++		/*
++		 * Map EBU region 0 to range 0x10000000-0x13ffffff and enable
++		 * region control. This supports up to 32 MiB NOR flash in
++		 * bank 0.
++		 */
++		ltq_writel(&ltq_ebu_regs->addr_sel_0, LTQ_EBU_REGION0_BASE |
++			EBU_ADDRSEL_MASK(1) | EBU_ADDRSEL_REGEN);
++
++		ltq_writel(&ltq_ebu_regs->con_0, EBU_CON_AGEN_DEMUX |
++			EBU_CON_WAIT_DIS | EBU_CON_PW_16BIT |
++			EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |
++			EBU_CON_WAITWRC(7) | EBU_CON_WAITRDC(3) |
++			EBU_CON_HOLDC(3) | EBU_CON_RECOVC(3) |
++			EBU_CON_CMULT_16);
++	} else
++		ltq_clrbits(&ltq_ebu_regs->addr_sel_0, EBU_ADDRSEL_REGEN);
++
++	if (ebu_region1_enable) {
++		/*
++		 * Map EBU region 1 to range 0x14000000-0x13ffffff and enable
++		 * region control. This supports NAND flash in bank 1.
++		 */
++		ltq_writel(&ltq_ebu_regs->addr_sel_1, LTQ_EBU_REGION1_BASE |
++			EBU_ADDRSEL_MASK(3) | EBU_ADDRSEL_REGEN);
++
++		ltq_writel(&ltq_ebu_regs->con_1, EBU_CON_AGEN_DEMUX |
++			EBU_CON_SETUP | EBU_CON_WAIT_DIS | EBU_CON_PW_8BIT |
++			EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |
++			EBU_CON_WAITWRC(2) | EBU_CON_WAITRDC(2) |
++			EBU_CON_HOLDC(1) | EBU_CON_RECOVC(1) |
++			EBU_CON_CMULT_4);
++	} else
++		ltq_clrbits(&ltq_ebu_regs->addr_sel_1, EBU_ADDRSEL_REGEN);
++}
++
++void *flash_swap_addr(unsigned long addr)
++{
++	return (void *)(addr ^ 2);
++}
+diff --git a/arch/mips/cpu/mips32/arx100/mem.c b/arch/mips/cpu/mips32/arx100/mem.c
+new file mode 100644
+index 0000000..1fba7cd
+--- /dev/null
++++ b/arch/mips/cpu/mips32/arx100/mem.c
+@@ -0,0 +1,30 @@
++/*
++ * Copyright (C) 2012 Daniel Schwierzeck, [email protected]
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/arch/soc.h>
++#include <asm/lantiq/io.h>
++
++static void *ltq_mc_ddr_base = (void *) CKSEG1ADDR(LTQ_MC_DDR_BASE);
++
++static inline u32 ltq_mc_dc_read(u32 index)
++{
++	return ltq_readl(ltq_mc_ddr_base + LTQ_MC_DDR_DC_OFFSET(index));
++}
++
++phys_size_t initdram(int board_type)
++{
++	u32 col, row, dc04, dc19, dc20;
++
++	dc04 = ltq_mc_dc_read(4);
++	dc19 = ltq_mc_dc_read(19);
++	dc20 = ltq_mc_dc_read(20);
++
++	row = (dc04 & 0xF) - ((dc19 & 0x700) >> 8);
++	col = ((dc04 & 0xF00) >> 8) - (dc20 & 0x7);
++
++	return (1 << (row + col)) * 4 * 2;
++}
+diff --git a/arch/mips/cpu/mips32/arx100/mem_init.S b/arch/mips/cpu/mips32/arx100/mem_init.S
+new file mode 100644
+index 0000000..5d70842
+--- /dev/null
++++ b/arch/mips/cpu/mips32/arx100/mem_init.S
+@@ -0,0 +1,114 @@
++/*
++ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
++ * Copyright (C) 2012 Daniel Schwierzeck, [email protected]
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <config.h>
++#include <asm/asm.h>
++#include <asm/regdef.h>
++#include <asm/addrspace.h>
++#include <asm/arch/soc.h>
++
++/* Must be configured in BOARDDIR */
++#include <ddr_settings.h>
++
++#define LTQ_MC_GEN_ERRCAUSE		0x0010
++#define LTQ_MC_GEN_ERRADDR		0x0020
++#define LTQ_MC_GEN_CON			0x0060
++#define LTQ_MC_GEN_STAT			0x0070
++#define LTQ_MC_GEN_CON_SRAM_DDR_ENABLE	0xD
++#define LTQ_MC_GEN_STAT_DLCK_PWRON	0xC
++
++#define LTQ_MC_DDR_DC03_MC_START	0x100
++
++	/* Store given value in MC DDR CCRx register */
++	.macro dc_sw num, val
++	li	t2, \val
++	sw	t2, LTQ_MC_DDR_DC_OFFSET(\num)(t1)
++	.endm
++
++LEAF(ltq_mem_init)
++	/* Load MC General and MC DDR module base */
++	li	t0, (LTQ_MC_GEN_BASE | KSEG1)
++	li	t1, (LTQ_MC_DDR_BASE | KSEG1)
++
++	/* Clear access error log registers */
++	sw	zero, LTQ_MC_GEN_ERRCAUSE(t0)
++	sw	zero, LTQ_MC_GEN_ERRADDR(t0)
++
++	/* Enable DDR and SRAM module in memory controller */
++	li	t2, LTQ_MC_GEN_CON_SRAM_DDR_ENABLE
++	sw	t2, LTQ_MC_GEN_CON(t0)
++
++	/* Clear start bit of DDR memory controller */
++	sw	zero, LTQ_MC_DDR_DC_OFFSET(3)(t1)
++
++	/* Init memory controller registers with values ddr_settings.h */
++	dc_sw	0, MC_DC00_VALUE
++	dc_sw	1, MC_DC01_VALUE
++	dc_sw	2, MC_DC02_VALUE
++	dc_sw	4, MC_DC04_VALUE
++	dc_sw	5, MC_DC05_VALUE
++	dc_sw	6, MC_DC06_VALUE
++	dc_sw	7, MC_DC07_VALUE
++	dc_sw	8, MC_DC08_VALUE
++	dc_sw	9, MC_DC09_VALUE
++
++	dc_sw	10, MC_DC10_VALUE
++	dc_sw	11, MC_DC11_VALUE
++	dc_sw	12, MC_DC12_VALUE
++	dc_sw	13, MC_DC13_VALUE
++	dc_sw	14, MC_DC14_VALUE
++	dc_sw	15, MC_DC15_VALUE
++	dc_sw	16, MC_DC16_VALUE
++	dc_sw	17, MC_DC17_VALUE
++	dc_sw	18, MC_DC18_VALUE
++	dc_sw	19, MC_DC19_VALUE
++
++	dc_sw	20, MC_DC20_VALUE
++	dc_sw	21, MC_DC21_VALUE
++	dc_sw	22, MC_DC22_VALUE
++	dc_sw	23, MC_DC23_VALUE
++	dc_sw	24, MC_DC24_VALUE
++	dc_sw	25, MC_DC25_VALUE
++	dc_sw	26, MC_DC26_VALUE
++	dc_sw	27, MC_DC27_VALUE
++	dc_sw	28, MC_DC28_VALUE
++	dc_sw	29, MC_DC29_VALUE
++
++	dc_sw	30, MC_DC30_VALUE
++	dc_sw	31, MC_DC31_VALUE
++	dc_sw	32, MC_DC32_VALUE
++	dc_sw	33, MC_DC33_VALUE
++	dc_sw	34, MC_DC34_VALUE
++	dc_sw	35, MC_DC35_VALUE
++	dc_sw	36, MC_DC36_VALUE
++	dc_sw	37, MC_DC37_VALUE
++	dc_sw	38, MC_DC38_VALUE
++	dc_sw	39, MC_DC39_VALUE
++
++	dc_sw	40, MC_DC40_VALUE
++	dc_sw	41, MC_DC41_VALUE
++	dc_sw	42, MC_DC42_VALUE
++	dc_sw	43, MC_DC43_VALUE
++	dc_sw	44, MC_DC44_VALUE
++	dc_sw	45, MC_DC45_VALUE
++	dc_sw	46, MC_DC46_VALUE
++
++	/* Set start bit of DDR memory controller */
++	li	t2, LTQ_MC_DDR_DC03_MC_START
++	sw	t2, LTQ_MC_DDR_DC_OFFSET(3)(t1)
++
++	/* Wait until DLL has locked and core is ready for data transfers */
++wait_ready:
++	lw	t2, LTQ_MC_GEN_STAT(t0)
++	li	t3, LTQ_MC_GEN_STAT_DLCK_PWRON
++	and	t2, t3
++	bne	t2, t3, wait_ready
++
++finished:
++	jr	ra
++
++	END(ltq_mem_init)
+diff --git a/arch/mips/cpu/mips32/arx100/pmu.c b/arch/mips/cpu/mips32/arx100/pmu.c
+new file mode 100644
+index 0000000..d2afe96
+--- /dev/null
++++ b/arch/mips/cpu/mips32/arx100/pmu.c
+@@ -0,0 +1,120 @@
++/*
++ * Copyright (C) 2012 Daniel Schwierzeck, [email protected]
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/lantiq/io.h>
++#include <asm/lantiq/pm.h>
++#include <asm/arch/soc.h>
++
++#define LTQ_PMU_PWDCR_RESERVED		0xE00C200C
++
++#define LTQ_PMU_PWDCR_SWITCH		(1 << 28)
++#define LTQ_PMU_PWDCR_USB1		(1 << 27)
++#define LTQ_PMU_PWDCR_USB1_PHY		(1 << 26)
++#define LTQ_PMU_PWDCR_TDM		(1 << 25)
++#define LTQ_PMU_PWDCR_DDR_MEM		(1 << 24)
++#define LTQ_PMU_PWDCR_PPE_DP		(1 << 23)
++#define LTQ_PMU_PWDCR_PPE_EMA		(1 << 22)
++#define LTQ_PMU_PWDCR_PPE_TC		(1 << 21)
++#define LTQ_PMU_PWDCR_DEU		(1 << 20)
++#define LTQ_PMU_PWDCR_UART1		(1 << 17)
++#define LTQ_PMU_PWDCR_SDIO		(1 << 16)
++#define LTQ_PMU_PWDCR_AHB		(1 << 15)
++#define LTQ_PMU_PWDCR_FPI0		(1 << 14)
++#define LTQ_PMU_PWDCR_GPTC		(1 << 12)
++#define LTQ_PMU_PWDCR_LEDC		(1 << 11)
++#define LTQ_PMU_PWDCR_EBU		(1 << 10)
++#define LTQ_PMU_PWDCR_DSL		(1 << 9)
++#define LTQ_PMU_PWDCR_SPI		(1 << 8)
++#define LTQ_PMU_PWDCR_UART0		(1 << 7)
++#define LTQ_PMU_PWDCR_USB		(1 << 6)
++#define LTQ_PMU_PWDCR_DMA		(1 << 5)
++#define LTQ_PMU_PWDCR_PCI		(1 << 4)
++#define LTQ_PMU_PWDCR_FPI1		(1 << 1)
++#define LTQ_PMU_PWDCR_USB0_PHY		(1 << 0)
++
++struct ltq_pmu_regs {
++	u32	rsvd0[7];
++	__be32	pwdcr;
++	__be32	sr;
++};
++
++static struct ltq_pmu_regs *ltq_pmu_regs =
++	(struct ltq_pmu_regs *) CKSEG1ADDR(LTQ_PMU_BASE);
++
++u32 ltq_pm_map(enum ltq_pm_modules module)
++{
++	u32 val;
++
++	switch (module) {
++	case LTQ_PM_CORE:
++		val = LTQ_PMU_PWDCR_DDR_MEM | LTQ_PMU_PWDCR_UART1 |
++			LTQ_PMU_PWDCR_FPI0 | LTQ_PMU_PWDCR_LEDC |
++			LTQ_PMU_PWDCR_EBU;
++		break;
++	case LTQ_PM_DMA:
++		val = LTQ_PMU_PWDCR_DMA;
++		break;
++	case LTQ_PM_ETH:
++		val = LTQ_PMU_PWDCR_SWITCH | LTQ_PMU_PWDCR_PPE_DP |
++			LTQ_PMU_PWDCR_PPE_EMA | LTQ_PMU_PWDCR_PPE_TC;
++		break;
++	case LTQ_PM_SPI:
++		val = LTQ_PMU_PWDCR_SPI;
++		break;
++	default:
++		val = 0;
++		break;
++	}
++
++	return val;
++}
++
++int ltq_pm_enable(enum ltq_pm_modules module)
++{
++	const unsigned long timeout = 1000;
++	unsigned long timebase;
++	u32 sr, val;
++
++	val = ltq_pm_map(module);
++	if (unlikely(!val))
++		return 1;
++
++	ltq_clrbits(&ltq_pmu_regs->pwdcr, val);
++
++	timebase = get_timer(0);
++
++	do {
++		sr = ltq_readl(&ltq_pmu_regs->sr);
++		if (~sr & val)
++			return 0;
++	} while (get_timer(timebase) < timeout);
++
++	return 1;
++}
++
++int ltq_pm_disable(enum ltq_pm_modules module)
++{
++	u32 val;
++
++	val = ltq_pm_map(module);
++	if (unlikely(!val))
++		return 1;
++
++	ltq_setbits(&ltq_pmu_regs->pwdcr, val);
++
++	return 0;
++}
++
++void ltq_pmu_init(void)
++{
++	u32 set, clr;
++
++	clr = ltq_pm_map(LTQ_PM_CORE);
++	set = ~(LTQ_PMU_PWDCR_RESERVED | clr);
++
++	ltq_clrsetbits(&ltq_pmu_regs->pwdcr, clr, set);
++}
+diff --git a/arch/mips/cpu/mips32/arx100/rcu.c b/arch/mips/cpu/mips32/arx100/rcu.c
+new file mode 100644
+index 0000000..4ff6935
+--- /dev/null
++++ b/arch/mips/cpu/mips32/arx100/rcu.c
+@@ -0,0 +1,130 @@
++/*
++ * Copyright (C) 2012 Daniel Schwierzeck, [email protected]
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/lantiq/io.h>
++#include <asm/lantiq/reset.h>
++#include <asm/lantiq/cpu.h>
++#include <asm/arch/soc.h>
++
++#define LTQ_RCU_RD_SRST		(1 << 30)	/* Global SW Reset */
++#define LTQ_RCU_RD_USB1		(1 << 28)	/* USB1 MAC and PHY */
++#define LTQ_RCU_RD_REG25_PD	(1 << 26)	/* Power down 2.5V regulator */
++#define LTQ_RCU_RD_PPE_ATM_TC	(1 << 22)	/* PPE ATM TC */
++#define LTQ_RCU_RD_ETHSW	(1 << 21)	/* Ethernet switch */
++#define LTQ_RCU_RD_DSP_DEN	(1 << 20)	/* Enable DSP JTAG */
++#define LTQ_RCU_RD_TDM		(1 << 19)	/* TDM module interface */
++#define LTQ_RCU_RD_MC		(1 << 14)	/* Memory Controller */
++#define LTQ_RCU_RD_PCI		(1 << 13)	/* PCI core */
++#define LTQ_RCU_RD_SDIO		(1 << 10)	/* SDIO core */
++#define LTQ_RCU_RD_DMA		(1 << 9)	/* DMA core */
++#define LTQ_RCU_RD_PPE		(1 << 8)	/* PPE core */
++#define LTQ_RCU_RD_ARC_DFE	(1 << 7)	/* ARC/DFE core */
++#define LTQ_RCU_RD_AHB		(1 << 6)	/* AHB bus */
++#define LTQ_RCU_RD_USB		(1 << 4)	/* USB and Phy core */
++#define LTQ_RCU_RD_FPI		(1 << 2)	/* FPI bus */
++#define LTQ_RCU_RD_CPU0		(1 << 1)	/* CPU0 subsystem */
++#define LTQ_RCU_RD_HRST		(1 << 0)	/* HW reset via HRST pin */
++
++#define LTQ_RCU_STAT_BOOT_SHIFT		17
++#define LTQ_RCU_STAT_BOOT_MASK		(0xf << LTQ_RCU_STAT_BOOT_SHIFT)
++
++struct ltq_rcu_regs {
++	u32	rsvd0[4];
++	__be32	req;		/* Reset request */
++	__be32	stat;		/* Reset status */
++	__be32	usb0_cfg;	/* USB0 config */
++	u32	rsvd1[2];
++	__be32	pci_rdy;	/* PCI boot ready */
++	__be32	ppe_conf;	/* PPE config */
++	u32	rsvd2;
++	__be32	usb1_cfg;	/* USB1 config */
++};
++
++static struct ltq_rcu_regs *ltq_rcu_regs =
++	(struct ltq_rcu_regs *) CKSEG1ADDR(LTQ_RCU_BASE);
++
++u32 ltq_reset_map(enum ltq_reset_modules module)
++{
++	u32 val;
++
++	switch (module) {
++	case LTQ_RESET_CORE:
++	case LTQ_RESET_SOFT:
++		val = LTQ_RCU_RD_SRST | LTQ_RCU_RD_CPU0;
++		break;
++	case LTQ_RESET_DMA:
++		val = LTQ_RCU_RD_DMA;
++		break;
++	case LTQ_RESET_ETH:
++		val = LTQ_RCU_RD_PPE | LTQ_RCU_RD_ETHSW;
++		break;
++	case LTQ_RESET_HARD:
++		val = LTQ_RCU_RD_HRST;
++		break;
++	default:
++		val = 0;
++		break;
++	}
++
++	return val;
++}
++
++int ltq_reset_activate(enum ltq_reset_modules module)
++{
++	u32 val;
++
++	val = ltq_reset_map(module);
++	if (unlikely(!val))
++		return 1;
++
++	ltq_setbits(&ltq_rcu_regs->req, val);
++
++	return 0;
++}
++
++int ltq_reset_deactivate(enum ltq_reset_modules module)
++{
++	u32 val;
++
++	val = ltq_reset_map(module);
++	if (unlikely(!val))
++		return 1;
++
++	ltq_clrbits(&ltq_rcu_regs->req, val);
++
++	return 0;
++}
++
++enum ltq_boot_select ltq_boot_select(void)
++{
++	u32 stat;
++	unsigned int bootstrap;
++
++	stat = ltq_readl(&ltq_rcu_regs->stat);
++	bootstrap = (stat & LTQ_RCU_STAT_BOOT_MASK) >> LTQ_RCU_STAT_BOOT_SHIFT;
++
++	switch (bootstrap) {
++	case 0:
++		return BOOT_NOR_NO_BOOTROM;
++	case 1:
++		return BOOT_RGMII0;
++	case 2:
++		return BOOT_NOR;
++	case 3:
++		return BOOT_MII0;
++	case 5:
++		return BOOT_RMII0;
++	case 6:
++		return BOOT_PCI;
++	case 8:
++		return BOOT_UART;
++	case 10:
++		return BOOT_SPI;
++	default:
++		return BOOT_UNKNOWN;
++	}
++}
+diff --git a/arch/mips/cpu/mips32/lantiq-common/cpu.c b/arch/mips/cpu/mips32/lantiq-common/cpu.c
+index 4a7acdf..aa37b35 100644
+--- a/arch/mips/cpu/mips32/lantiq-common/cpu.c
++++ b/arch/mips/cpu/mips32/lantiq-common/cpu.c
+@@ -20,6 +20,7 @@ static const char ltq_bootsel_strings[][16] = {
+ 	"PCI",
+ 	"MII0",
+ 	"RMII0",
++	"RGMII0",
+ 	"RGMII1",
+ 	"unknown",
+ };
+diff --git a/arch/mips/cpu/mips32/lantiq-common/start.S b/arch/mips/cpu/mips32/lantiq-common/start.S
+index 481d739..fc8276e 100644
+--- a/arch/mips/cpu/mips32/lantiq-common/start.S
++++ b/arch/mips/cpu/mips32/lantiq-common/start.S
+@@ -64,6 +64,11 @@
+ #define STATUS_LANTIQ		(STATUS_MIPS24K | STATUS_MIPS32_64)
+ #endif
+ 
++#ifdef CONFIG_SOC_XWAY_ARX100
++#define CONFIG0_LANTIQ		(CONFIG0_MIPS34K | CONFIG0_MIPS32_64)
++#define STATUS_LANTIQ		(STATUS_MIPS34K | STATUS_MIPS32_64)
++#endif
++
+ #ifdef CONFIG_SOC_XWAY_VRX200
+ #define CONFIG0_LANTIQ		(CONFIG0_MIPS34K | CONFIG0_MIPS32_64)
+ #define STATUS_LANTIQ		(STATUS_MIPS34K | STATUS_MIPS32_64)
+diff --git a/arch/mips/include/asm/arch-arx100/config.h b/arch/mips/include/asm/arch-arx100/config.h
+new file mode 100644
+index 0000000..1a6c9bc
+--- /dev/null
++++ b/arch/mips/include/asm/arch-arx100/config.h
+@@ -0,0 +1,175 @@
++/*
++ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
++ * Copyright (C) 2011-2013 Daniel Schwierzeck, [email protected]
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ *
++ * Common board configuration for Lantiq XWAY ARX100 family
++ *
++ * Use following defines in your board config to enable specific features
++ * and drivers for this SoC:
++ *
++ * CONFIG_LTQ_SUPPORT_UART
++ * - support the Danube ASC/UART interface and console
++ *
++ * CONFIG_LTQ_SUPPORT_NOR_FLASH
++ * - support a parallel NOR flash via the CFI interface in flash bank 0
++ *
++ * CONFIG_LTQ_SUPPORT_ETHERNET
++ * - support the Danube ETOP and MAC interface
++ *
++ * CONFIG_LTQ_SUPPORT_SPI_FLASH
++ * - support the Danube SPI interface and serial flash drivers
++ * - specific SPI flash drivers must be configured separately
++ */
++
++#ifndef __ARX100_CONFIG_H__
++#define __ARX100_CONFIG_H__
++
++/* CPU and SoC type */
++#define CONFIG_SOC_LANTIQ
++#define CONFIG_SOC_XWAY_ARX100
++
++/* Cache configuration */
++#define CONFIG_SYS_MIPS_CACHE_MODE	CONF_CM_CACHABLE_NONCOHERENT
++#define CONFIG_SYS_DCACHE_SIZE		(16 * 1024)
++#define CONFIG_SYS_ICACHE_SIZE		(32 * 1024)
++#define CONFIG_SYS_CACHELINE_SIZE	32
++#define CONFIG_SYS_MIPS_CACHE_EXT_INIT
++
++/*
++ * Supported clock modes
++ * PLL0: rational PLL running at 500 MHz
++ * PLL1: fractional PLL running at 393.219 MHz
++ */
++#define LTQ_CLK_CPU_393_DDR_197		0
++#define LTQ_CLK_CPU_197_DDR_197		1
++#define LTQ_CLK_CPU_333_DDR_167		2
++#define LTQ_CLK_CPU_167_DDR_167		3
++#define LTQ_CLK_CPU_131_DDR_131		4
++#define LTQ_CLK_CPU_111_DDR_111		5
++
++/* CPU speed */
++#define CONFIG_SYS_CLOCK_MODE		LTQ_CLK_CPU_333_DDR_167
++#define CONFIG_SYS_MIPS_TIMER_FREQ	166666667
++#define CONFIG_SYS_HZ			1000
++
++/* RAM */
++#define CONFIG_NR_DRAM_BANKS		1
++#define CONFIG_SYS_SDRAM_BASE		0x80000000
++#define CONFIG_SYS_SDRAM_BASE_UC	0xa0000000
++#define CONFIG_SYS_MEMTEST_START	0x81000000
++#define CONFIG_SYS_MEMTEST_END		0x82000000
++#define CONFIG_SYS_LOAD_ADDR		0x81000000
++#define CONFIG_SYS_INIT_SP_OFFSET	(32 * 1024)
++
++/* SRAM */
++#define CONFIG_SYS_SRAM_BASE		0xBE1A0000
++#define CONFIG_SYS_SRAM_SIZE		0x10000
++
++/* ASC/UART driver and console */
++#define CONFIG_LANTIQ_SERIAL
++#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
++
++/* GPIO */
++#define CONFIG_LANTIQ_GPIO
++#define CONFIG_LTQ_GPIO_MAX_BANKS	3
++#define CONFIG_LTQ_HAS_GPIO_BANK3
++
++/* FLASH driver */
++#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH)
++#define CONFIG_SYS_MAX_FLASH_BANKS	1
++#define CONFIG_SYS_MAX_FLASH_SECT	256
++#define CONFIG_SYS_FLASH_BASE		0xB0000000
++#define CONFIG_FLASH_16BIT
++#define CONFIG_SYS_FLASH_CFI
++#define CONFIG_FLASH_CFI_DRIVER
++#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
++#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
++#define CONFIG_FLASH_SHOW_PROGRESS	50
++#define CONFIG_SYS_FLASH_PROTECTION
++#define CONFIG_CFI_FLASH_USE_WEAK_ADDR_SWAP
++
++#define CONFIG_CMD_FLASH
++#else
++#define CONFIG_SYS_NO_FLASH
++#endif /* CONFIG_NOR_FLASH */
++
++#if defined(CONFIG_LTQ_SUPPORT_SPI_FLASH)
++#define CONFIG_LANTIQ_SPI
++#define CONFIG_SPI_FLASH
++
++#define CONFIG_CMD_SF
++#define CONFIG_CMD_SPI
++#endif
++
++#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH)
++#define CONFIG_NAND_LANTIQ
++#define CONFIG_SYS_MAX_NAND_DEVICE	1
++#define CONFIG_SYS_NAND_BASE		0xB4000000
++
++#define CONFIG_CMD_NAND
++#endif
++
++#if defined(CONFIG_LTQ_SUPPORT_ETHERNET)
++#define CONFIG_LANTIQ_DMA
++#define CONFIG_LANTIQ_ARX100_SWITCH
++
++#define CONFIG_PHYLIB
++#define CONFIG_MII
++#define CONFIG_UDP_CHECKSUM
++
++#define CONFIG_CMD_MII
++#define CONFIG_CMD_NET
++#endif
++
++#define CONFIG_SPL_MAX_SIZE		(32 * 1024)
++#define CONFIG_SPL_BSS_MAX_SIZE		(8 * 1024)
++#define CONFIG_SPL_STACK_MAX_SIZE	(8 * 1024)
++#define CONFIG_SPL_MALLOC_MAX_SIZE	(32 * 1024)
++#define CONFIG_SPL_STACK_BSS_IN_SRAM
++
++#if defined(CONFIG_SPL_STACK_BSS_IN_SRAM)
++#define CONFIG_SPL_STACK_BASE		(CONFIG_SYS_SRAM_BASE + \
++					CONFIG_SPL_MAX_SIZE + \
++					CONFIG_SPL_STACK_MAX_SIZE - 1)
++#define CONFIG_SPL_BSS_BASE	  	(CONFIG_SPL_STACK_BASE + 1)
++#define CONFIG_SPL_MALLOC_BASE		(CONFIG_SYS_SDRAM_BASE + \
++					CONFIG_SYS_INIT_SP_OFFSET)
++#else
++#define CONFIG_SPL_STACK_BASE		(CONFIG_SYS_SDRAM_BASE + \
++					CONFIG_SYS_INIT_SP_OFFSET + \
++					CONFIG_SPL_STACK_MAX_SIZE - 1)
++#define CONFIG_SPL_BSS_BASE		(CONFIG_SPL_STACK_BASE + 1)
++#define CONFIG_SPL_MALLOC_BASE		(CONFIG_SPL_BSS_BASE + \
++					CONFIG_SPL_BSS_MAX_SIZE)
++#endif
++
++#if defined(CONFIG_SYS_BOOT_RAM)
++#define CONFIG_SYS_TEXT_BASE		0xA0100000
++#define CONFIG_SKIP_LOWLEVEL_INIT
++#define CONFIG_SYS_DISABLE_CACHE
++#endif
++
++#if defined(CONFIG_SYS_BOOT_NOR)
++#define CONFIG_SYS_TEXT_BASE		0xB0000000
++#endif
++
++#if defined(CONFIG_SYS_BOOT_SFSPL) || defined(CONFIG_SYS_BOOT_NANDSPL)
++#define CONFIG_SYS_TEXT_BASE		0x80100000
++#define CONFIG_SPL_TEXT_BASE		0xBE1A0000
++#endif
++
++#if defined(CONFIG_SYS_BOOT_NORSPL)
++#define CONFIG_SYS_TEXT_BASE		0x80100000
++#define CONFIG_SPL_TEXT_BASE		0xB0000000
++#endif
++
++#if defined(CONFIG_SYS_BOOT_NOR) || defined(CONFIG_SYS_BOOT_NORSPL)
++#define CONFIG_SYS_XWAY_EBU_BOOTCFG	0x688C688C
++#define CONFIG_XWAY_SWAP_BYTES
++#endif
++
++#define	CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
++
++#endif /* __ARX100_CONFIG_H__ */
+diff --git a/arch/mips/include/asm/arch-arx100/gpio.h b/arch/mips/include/asm/arch-arx100/gpio.h
+new file mode 100644
+index 0000000..f6b6409
+--- /dev/null
++++ b/arch/mips/include/asm/arch-arx100/gpio.h
+@@ -0,0 +1,12 @@
++/*
++ * Copyright (C) 2012 Daniel Schwierzeck, [email protected]
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#ifndef __ARX100_GPIO_H__
++#define __ARX100_GPIO_H__
++
++#include <asm/lantiq/gpio.h>
++
++#endif /* __ARX100_GPIO_H__ */
+diff --git a/arch/mips/include/asm/arch-arx100/nand.h b/arch/mips/include/asm/arch-arx100/nand.h
+new file mode 100644
+index 0000000..231b68f
+--- /dev/null
++++ b/arch/mips/include/asm/arch-arx100/nand.h
+@@ -0,0 +1,13 @@
++/*
++ * Copyright (C) 2012-2013 Daniel Schwierzeck, [email protected]
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#ifndef __VRX200_NAND_H__
++#define __VRX200_NAND_H__
++
++struct nand_chip;
++int ltq_nand_init(struct nand_chip *nand);
++
++#endif /* __VRX200_NAND_H__ */
+diff --git a/arch/mips/include/asm/arch-arx100/soc.h b/arch/mips/include/asm/arch-arx100/soc.h
+new file mode 100644
+index 0000000..3ccaf3f
+--- /dev/null
++++ b/arch/mips/include/asm/arch-arx100/soc.h
+@@ -0,0 +1,37 @@
++/*
++ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
++ * Copyright (C) 2012 Daniel Schwierzeck, [email protected]
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#ifndef __ARX100_SOC_H__
++#define __ARX100_SOC_H__
++
++#define LTQ_ASC0_BASE			0x1E100400
++#define LTQ_SPI_BASE			0x1E100800
++#define LTQ_GPIO_BASE			0x1E100B00
++#define LTQ_SSIO_BASE			0x1E100BB0
++#define LTQ_ASC1_BASE			0x1E100C00
++#define LTQ_DMA_BASE			0x1E104100
++
++#define LTQ_EBU_BASE			0x1E105300
++#define LTQ_EBU_REGION0_BASE		0x10000000
++#define LTQ_EBU_REGION1_BASE		0x14000000
++#define LTQ_EBU_NAND_BASE		(LTQ_EBU_BASE + 0xB0)
++
++#define LTQ_PPE_BASE			0x1E180000
++#define LTQ_SWITCH_BASE			0x1E108000
++
++#define LTQ_PMU_BASE			0x1F102000
++#define LTQ_CGU_BASE			0x1F103000
++#define LTQ_MPS_BASE			0x1F107000
++#define LTQ_CHIPID_BASE			(LTQ_MPS_BASE + 0x340)
++#define LTQ_RCU_BASE			0x1F203000
++
++#define LTQ_MC_GEN_BASE			0x1F800000
++#define LTQ_MC_SDR_BASE			0x1F800200
++#define LTQ_MC_DDR_BASE			0x1F801000
++#define LTQ_MC_DDR_DC_OFFSET(x)		(x * 0x10)
++
++#endif /* __ARX100_SOC_H__ */
+diff --git a/arch/mips/include/asm/lantiq/chipid.h b/arch/mips/include/asm/lantiq/chipid.h
+index c9921b0..19adf97 100644
+--- a/arch/mips/include/asm/lantiq/chipid.h
++++ b/arch/mips/include/asm/lantiq/chipid.h
+@@ -15,6 +15,10 @@ enum ltq_chip_partnum {
+ 	LTQ_SOC_DANUBE = 0x0129,
+ 	LTQ_SOC_DANUBE_S = 0x012B,
+ 	LTQ_SOC_TWINPASS = 0x012D,
++	LTQ_SOC_ARX188 = 0x016C,	/* ARX188 */
++	LTQ_SOC_ARX186 = 0x016D,	/* ARX186 v1.1 */
++	LTQ_SOC_ARX186_2 = 0x016E,	/* ARX186 v1.2 */
++	LTQ_SOC_ARX182 = 0x016F,	/* ARX182 */
+ 	LTQ_SOC_VRX288 = 0x01C0,	/* VRX288 v1.1 */
+ 	LTQ_SOC_VRX268 = 0x01C2,	/* VRX268 v1.1 */
+ 	LTQ_SOC_GRX288 = 0x01C9,	/* GRX288 v1.1 */
+@@ -38,6 +42,38 @@ static inline int ltq_soc_is_danube(void)
+ }
+ #endif
+ 
++#ifdef CONFIG_SOC_XWAY_ARX100
++static inline int ltq_soc_is_arx100(void)
++{
++	return 1;
++}
++
++static inline int ltq_soc_is_arx100_v1(void)
++{
++	return ltq_chip_version_get() == 1;
++}
++
++static inline int ltq_soc_is_arx100_v2(void)
++{
++	return ltq_chip_version_get() == 2;
++}
++#else
++static inline int ltq_soc_is_arx100(void)
++{
++	return 0;
++}
++
++static inline int ltq_soc_is_arx100_v1(void)
++{
++	return 0;
++}
++
++static inline int ltq_soc_is_arx100_v2(void)
++{
++	return 0;
++}
++#endif
++
+ #ifdef CONFIG_SOC_XWAY_VRX200
+ static inline int ltq_soc_is_vrx200(void)
+ {
+diff --git a/arch/mips/include/asm/lantiq/clk.h b/arch/mips/include/asm/lantiq/clk.h
+index e13f000..5aea603 100644
+--- a/arch/mips/include/asm/lantiq/clk.h
++++ b/arch/mips/include/asm/lantiq/clk.h
+@@ -13,9 +13,10 @@ enum ltq_clk {
+ 	CLOCK_83_MHZ = 83333333,
+ 	CLOCK_111_MHZ = 111111111,
+ 	CLOCK_125_MHZ = 125000000,
++	CLOCK_131_MHZ = 131073000,
+ 	CLOCK_133_MHZ = 133333333,
+ 	CLOCK_166_MHZ = 166666667,
+-	CLOCK_197_MHZ = 197000000,
++	CLOCK_197_MHZ = 196609500,
+ 	CLOCK_333_MHZ = 333333333,
+ 	CLOCK_393_MHZ = 393219000,
+ 	CLOCK_500_MHZ = 500000000,
+diff --git a/arch/mips/include/asm/lantiq/cpu.h b/arch/mips/include/asm/lantiq/cpu.h
+index b3a504e..e3b0312 100644
+--- a/arch/mips/include/asm/lantiq/cpu.h
++++ b/arch/mips/include/asm/lantiq/cpu.h
+@@ -17,6 +17,7 @@ enum ltq_boot_select {
+ 	BOOT_PCI,
+ 	BOOT_MII0,
+ 	BOOT_RMII0,
++	BOOT_RGMII0,
+ 	BOOT_RGMII1,
+ 	BOOT_UNKNOWN,
+ };
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0015-sf-macronix-add-support-for-MX66L51235L.patch

@@ -1,21 +0,0 @@
-From a2d80b6b91ac63beea31455ce8d136230c030500 Mon Sep 17 00:00:00 2001
-From: Daniel Schwierzeck <[email protected]>
-Date: Wed, 7 Nov 2012 15:14:40 +0100
-Subject: sf: macronix: add support for MX66L51235L
-
-Signed-off-by: Daniel Schwierzeck <[email protected]>
-
---- a/drivers/mtd/spi/macronix.c
-+++ b/drivers/mtd/spi/macronix.c
-@@ -84,6 +84,11 @@ static const struct macronix_spi_flash_p
- 		.nr_blocks = 512,
- 		.name = "MX25L25635E",
- 	},
-+	{
-+		.idcode = 0x201A,
-+		.nr_blocks = 1024,
-+		.name = "MX66L51235L",
-+	},
- };
- 
- static __maybe_unused int macronix_set_4byte_mode(struct spi_flash *flash)

package/boot/uboot-lantiq/patches/0016-net-add-driver-for-Lantiq-XWAY-ARX100-switch.patch

@@ -0,0 +1,559 @@
+From 7288414298b34dcda1216fee1fe38d05ea0027a2 Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <[email protected]>
+Date: Mon, 17 Dec 2012 23:32:39 +0100
+Subject: net: add driver for Lantiq XWAY ARX100 switch
+
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/arch/mips/include/asm/arch-arx100/config.h b/arch/mips/include/asm/arch-arx100/config.h
+index 1a6c9bc..8f955e8 100644
+--- a/arch/mips/include/asm/arch-arx100/config.h
++++ b/arch/mips/include/asm/arch-arx100/config.h
+@@ -10,17 +10,21 @@
+  * and drivers for this SoC:
+  *
+  * CONFIG_LTQ_SUPPORT_UART
+- * - support the Danube ASC/UART interface and console
++ * - support the ARX100 ASC/UART interface and console
+  *
+  * CONFIG_LTQ_SUPPORT_NOR_FLASH
+  * - support a parallel NOR flash via the CFI interface in flash bank 0
+  *
+  * CONFIG_LTQ_SUPPORT_ETHERNET
+- * - support the Danube ETOP and MAC interface
++ * - support the ARX100 ETOP and MAC interface
+  *
+  * CONFIG_LTQ_SUPPORT_SPI_FLASH
+- * - support the Danube SPI interface and serial flash drivers
++ * - support the ARX100 SPI interface and serial flash drivers
+  * - specific SPI flash drivers must be configured separately
++ *
++ * CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH
++ * - build a preloader that runs in the internal SRAM and loads
++ *   the U-Boot from SPI flash into RAM
+  */
+ 
+ #ifndef __ARX100_CONFIG_H__
+diff --git a/arch/mips/include/asm/arch-arx100/switch.h b/arch/mips/include/asm/arch-arx100/switch.h
+new file mode 100644
+index 0000000..301056c
+--- /dev/null
++++ b/arch/mips/include/asm/arch-arx100/switch.h
+@@ -0,0 +1,86 @@
++/*
++ *   Copyright (C) 2012-2013 Daniel Schwierzeck <[email protected]>
++ *
++ *   SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#ifndef __ARX100_SWITCH_H__
++#define __ARX100_SWITCH_H__
++
++struct ar9_switch_regs {
++	__be32	ps;		/* Port status*/
++	__be32	p0_ctl;		/* Port 0 control */
++	__be32	p1_ctl;		/* Port 1 control */
++	__be32	p2_ctl;		/* Port 2 control */
++	__be32	p0_vlan;	/* Port 0 VLAN control */
++	__be32	p1_vlan;	/* Port 1 VLAN control */
++	__be32	p2_vlan;	/* Port 2 VLAN control */
++	__be32	p0_inctl;	/* Port 0 ingress control */
++	__be32	p1_inctl;	/* Port 1 ingress control */
++	__be32	p2_inctl;	/* Port 2 ingress control */
++	u32	rsvd0[16];
++	__be32	sw_gctl0;	/* Switch global control 0 */
++	__be32	sw_gctl1;	/* Switch global control 1 */
++	__be32	arp;		/* ARP/RARP */
++	__be32	strm_ctl;	/* Storm control */
++	__be32	rgmii_ctl;	/* RGMII/GMII port control */
++	u32	rsvd1[4];
++	__be32	pmac_hd_ctl;	/* PMAC header control */
++	u32	rsvd2[15];
++	__be32	mdio_ctrl;	/* MDIO indirect access control */
++	__be32	mdio_data;	/* MDIO indirect read data */
++};
++
++#define BUILD_CHECK_AR9_REG(name, offset)	\
++	BUILD_BUG_ON(offsetof(struct ar9_switch_regs, name) != (offset))
++
++static inline void build_check_ar9_registers(void)
++{
++	BUILD_CHECK_AR9_REG(sw_gctl0, 0x68);
++	BUILD_CHECK_AR9_REG(rgmii_ctl, 0x78);
++	BUILD_CHECK_AR9_REG(pmac_hd_ctl, 0x8c);
++	BUILD_CHECK_AR9_REG(mdio_ctrl, 0xcc);
++	BUILD_CHECK_AR9_REG(mdio_data, 0xd0);
++}
++
++#define P0_CTL_FLP		(1 << 18)
++#define P0_CTL_FLD		(1 << 17)
++
++#define SW_GCTL0_SE		(1 << 31)
++
++#define RGMII_CTL_P1_SHIFT	10
++#define RGMII_CTL_P1_MASK	(0x3FF << RGMII_CTL_P1_SHIFT)
++#define RGMII_CTL_P0_MASK	0x3FF
++#define RGMII_CTL_P0IS_SHIFT	8
++#define RGMII_CTL_P0IS_RGMII	(0x0 << RGMII_CTL_P0IS_SHIFT)
++#define RGMII_CTL_P0IS_MII	(0x1 << RGMII_CTL_P0IS_SHIFT)
++#define RGMII_CTL_P0IS_REVMII	(0x2 << RGMII_CTL_P0IS_SHIFT)
++#define RGMII_CTL_P0IS_RMII	(0x3 << RGMII_CTL_P0IS_SHIFT)
++#define RGMII_CTL_P0RDLY_SHIFT	6
++#define RGMII_CTL_P0RDLY_0_0	(0x0 << RGMII_CTL_P0RDLY_SHIFT)
++#define RGMII_CTL_P0RDLY_1_5	(0x1 << RGMII_CTL_P0RDLY_SHIFT)
++#define RGMII_CTL_P0RDLY_1_75	(0x2 << RGMII_CTL_P0RDLY_SHIFT)
++#define RGMII_CTL_P0RDLY_2_0	(0x3 << RGMII_CTL_P0RDLY_SHIFT)
++#define RGMII_CTL_P0TDLY_SHIFT	4
++#define RGMII_CTL_P0TDLY_0_0	(0x0 << RGMII_CTL_P0TDLY_SHIFT)
++#define RGMII_CTL_P0TDLY_1_5	(0x1 << RGMII_CTL_P0TDLY_SHIFT)
++#define RGMII_CTL_P0TDLY_1_75	(0x2 << RGMII_CTL_P0TDLY_SHIFT)
++#define RGMII_CTL_P0TDLY_2_0	(0x3 << RGMII_CTL_P0TDLY_SHIFT)
++#define RGMII_CTL_P0SPD_SHIFT	2
++#define RGMII_CTL_P0SPD_10	(0x0 << RGMII_CTL_P0SPD_SHIFT)
++#define RGMII_CTL_P0SPD_100	(0x1 << RGMII_CTL_P0SPD_SHIFT)
++#define RGMII_CTL_P0SPD_1000	(0x2 << RGMII_CTL_P0SPD_SHIFT)
++#define RGMII_CTL_P0DUP_FULL	(1 << 1)
++#define RGMII_CTL_P0FCE_EN	(1 << 0)
++
++#define PMAC_HD_CTL_AC		(1 << 18)
++
++#define MDIO_CTRL_WD_SHIFT	16
++#define MDIO_CTRL_MBUSY		(1 << 15)
++#define MDIO_CTRL_OP_READ	(1 << 11)
++#define MDIO_CTRL_OP_WRITE	(1 << 10)
++#define MDIO_CTRL_PHYAD_SHIFT	5
++#define MDIO_CTRL_PHYAD_MASK	(0x1f << MDIO_CTRL_PHYAD_SHIFT)
++#define MDIO_CTRL_REGAD_MASK	0x1f
++
++#endif /* __ARX100_SWITCH_H__ */
+diff --git a/drivers/net/Makefile b/drivers/net/Makefile
+index bbc2c92..926b8c2 100644
+--- a/drivers/net/Makefile
++++ b/drivers/net/Makefile
+@@ -38,6 +38,7 @@ COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
+ COBJS-$(CONFIG_KS8851_MLL) += ks8851_mll.o
+ COBJS-$(CONFIG_LAN91C96) += lan91c96.o
+ COBJS-$(CONFIG_LANTIQ_DANUBE_ETOP) += lantiq_danube_etop.o
++COBJS-$(CONFIG_LANTIQ_ARX100_SWITCH) += lantiq_arx100_switch.o
+ COBJS-$(CONFIG_LANTIQ_VRX200_SWITCH) += lantiq_vrx200_switch.o
+ COBJS-$(CONFIG_MACB) += macb.o
+ COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
+diff --git a/drivers/net/lantiq_arx100_switch.c b/drivers/net/lantiq_arx100_switch.c
+new file mode 100644
+index 0000000..cc65249
+--- /dev/null
++++ b/drivers/net/lantiq_arx100_switch.c
+@@ -0,0 +1,410 @@
++/*
++ * Copyright (C) 2011-2013 Daniel Schwierzeck, [email protected]
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++#define DEBUG
++#include <common.h>
++#include <malloc.h>
++#include <netdev.h>
++#include <miiphy.h>
++#include <switch.h>
++#include <linux/compiler.h>
++#include <asm/gpio.h>
++#include <asm/processor.h>
++#include <asm/lantiq/io.h>
++#include <asm/lantiq/eth.h>
++#include <asm/lantiq/pm.h>
++#include <asm/lantiq/reset.h>
++#include <asm/lantiq/dma.h>
++#include <asm/arch/soc.h>
++#include <asm/arch/switch.h>
++
++#define LTQ_ETH_RX_BUFFER_CNT		PKTBUFSRX
++#define LTQ_ETH_TX_BUFFER_CNT		8
++#define LTQ_ETH_RX_DATA_SIZE		PKTSIZE_ALIGN
++#define LTQ_ETH_IP_ALIGN		2
++
++#define LTQ_MDIO_DRV_NAME		"ltq-mdio"
++#define LTQ_ETH_DRV_NAME		"ltq-eth"
++
++#define LTQ_ETHSW_MAX_GMAC		2
++#define LTQ_ETHSW_PMAC			2
++
++struct ltq_eth_priv {
++	struct ltq_dma_device dma_dev;
++	struct mii_dev *bus;
++	struct eth_device *dev;
++	struct phy_device *phymap[LTQ_ETHSW_MAX_GMAC];
++	int rx_num;
++	int tx_num;
++};
++
++static struct ar9_switch_regs *switch_regs =
++	(struct ar9_switch_regs *) CKSEG1ADDR(LTQ_SWITCH_BASE);
++
++static int ltq_mdio_is_busy(void)
++{
++	u32 mdio_ctrl = ltq_readl(&switch_regs->mdio_ctrl);
++
++	return mdio_ctrl & MDIO_CTRL_MBUSY;
++}
++
++static void ltq_mdio_poll(void)
++{
++	while (ltq_mdio_is_busy())
++		cpu_relax();
++
++	__udelay(1000);
++}
++
++static int ltq_mdio_read(struct mii_dev *bus, int phyad, int devad,
++					int regad)
++{
++	u32 mdio_ctrl;
++	int retval;
++
++	mdio_ctrl = MDIO_CTRL_MBUSY | MDIO_CTRL_OP_READ |
++		((phyad << MDIO_CTRL_PHYAD_SHIFT) & MDIO_CTRL_PHYAD_MASK) |
++		(regad & MDIO_CTRL_REGAD_MASK);
++
++	ltq_mdio_poll();
++	ltq_writel(&switch_regs->mdio_ctrl, mdio_ctrl);
++	ltq_mdio_poll();
++	retval = ltq_readl(&switch_regs->mdio_data);
++	ltq_writel(&switch_regs->mdio_data, 0xFFFF);
++
++	debug("%s: phyad %02x, regad %02x, val %02x\n", __func__, phyad, regad, retval);
++
++	return retval;
++}
++
++static int ltq_mdio_write(struct mii_dev *bus, int phyad, int devad,
++					int regad, u16 val)
++{
++	u32 mdio_ctrl;
++
++	debug("%s: phyad %02x, regad %02x, val %02x\n", __func__, phyad, regad, val);
++
++	mdio_ctrl = (val << MDIO_CTRL_WD_SHIFT) | MDIO_CTRL_MBUSY |
++		MDIO_CTRL_OP_WRITE |
++		((phyad << MDIO_CTRL_PHYAD_SHIFT) & MDIO_CTRL_PHYAD_MASK) |
++		(regad & MDIO_CTRL_REGAD_MASK);
++
++	ltq_mdio_poll();
++	ltq_writel(&switch_regs->mdio_ctrl, mdio_ctrl);
++
++	return 0;
++}
++
++static void ltq_eth_gmac_update(struct phy_device *phydev, int num)
++{
++}
++
++static inline u8 *ltq_eth_rx_packet_align(int rx_num)
++{
++	u8 *packet = (u8 *) NetRxPackets[rx_num];
++
++	/*
++	 * IP header needs
++	 */
++	return packet + LTQ_ETH_IP_ALIGN;
++}
++
++static int ltq_eth_init(struct eth_device *dev, bd_t *bis)
++{
++	struct ltq_eth_priv *priv = dev->priv;
++	struct ltq_dma_device *dma_dev = &priv->dma_dev;
++	struct phy_device *phydev;
++	int i;
++
++	for (i = 0; i < LTQ_ETHSW_MAX_GMAC; i++) {
++		phydev = priv->phymap[i];
++		if (!phydev)
++			continue;
++
++		phy_startup(phydev);
++		ltq_eth_gmac_update(phydev, i);
++	}
++
++	for (i = 0; i < LTQ_ETH_RX_BUFFER_CNT; i++)
++		ltq_dma_rx_map(dma_dev, i, ltq_eth_rx_packet_align(i),
++			LTQ_ETH_RX_DATA_SIZE);
++
++	ltq_dma_enable(dma_dev);
++
++	priv->rx_num = 0;
++	priv->tx_num = 0;
++
++	return 0;
++}
++
++static void ltq_eth_halt(struct eth_device *dev)
++{
++	struct ltq_eth_priv *priv = dev->priv;
++	struct ltq_dma_device *dma_dev = &priv->dma_dev;
++	struct phy_device *phydev;
++	int i;
++
++	ltq_dma_reset(dma_dev);
++
++	for (i = 0; i < LTQ_ETHSW_MAX_GMAC; i++) {
++		phydev = priv->phymap[i];
++		if (!phydev)
++			continue;
++
++		phy_shutdown(phydev);
++		phydev->link = 0;
++		ltq_eth_gmac_update(phydev, i);
++	}
++}
++
++static int ltq_eth_send(struct eth_device *dev, void *packet, int length)
++{
++	struct ltq_eth_priv *priv = dev->priv;
++	struct ltq_dma_device *dma_dev = &priv->dma_dev;
++	int err;
++
++	err = ltq_dma_tx_map(dma_dev, priv->tx_num, packet, length, 10);
++	if (err) {
++		puts("NET: timeout on waiting for TX descriptor\n");
++		return -1;
++	}
++
++	priv->tx_num = (priv->tx_num + 1) % LTQ_ETH_TX_BUFFER_CNT;
++
++	return err;
++}
++
++static int ltq_eth_recv(struct eth_device *dev)
++{
++	struct ltq_eth_priv *priv = dev->priv;
++	struct ltq_dma_device *dma_dev = &priv->dma_dev;
++	u8 *packet;
++	int len;
++
++	if (!ltq_dma_rx_poll(dma_dev, priv->rx_num))
++		return 0;
++
++#if 0
++	printf("%s: rx_num %d\n", __func__, priv->rx_num);
++#endif
++
++	len = ltq_dma_rx_length(dma_dev, priv->rx_num);
++	packet = ltq_eth_rx_packet_align(priv->rx_num);
++
++#if 0
++	printf("%s: received: packet %p, len %u, rx_num %d\n",
++		__func__, packet, len, priv->rx_num);
++#endif
++
++	if (len)
++		NetReceive(packet, len);
++
++	ltq_dma_rx_map(dma_dev, priv->rx_num, packet,
++		LTQ_ETH_RX_DATA_SIZE);
++
++	priv->rx_num = (priv->rx_num + 1) % LTQ_ETH_RX_BUFFER_CNT;
++
++	return 0;
++}
++
++static void ltq_eth_pmac_init(void)
++{
++	/* Add CRC to packets from DMA to PMAC */
++	ltq_setbits(&switch_regs->pmac_hd_ctl, PMAC_HD_CTL_AC);
++
++	/* Force link up */
++	ltq_setbits(&switch_regs->p2_ctl, P0_CTL_FLP);
++}
++
++static void ltq_eth_hw_init(const struct ltq_eth_port_config *port)
++{
++	/* Power up ethernet subsystems */
++	ltq_pm_enable(LTQ_PM_ETH);
++
++	/* Enable switch core */
++	ltq_setbits(&switch_regs->sw_gctl0, SW_GCTL0_SE);
++
++	/* MII/MDIO */
++	gpio_set_altfunc(42, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
++	/* MII/MDC */
++	gpio_set_altfunc(43, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
++
++	ltq_eth_pmac_init();
++}
++
++static void ltq_eth_port_config(struct ltq_eth_priv *priv,
++				const struct ltq_eth_port_config *port)
++{
++	struct phy_device *phydev;
++	struct switch_device *sw;
++	u32 rgmii_ctl;
++	unsigned int port_ctl, port_xmii = 0;
++
++	if (port->num > 1)
++		return;
++
++	rgmii_ctl = ltq_readl(&switch_regs->rgmii_ctl);
++
++	if (port->num == 1)
++		port_ctl = ltq_readl(&switch_regs->p1_ctl);
++	else
++		port_ctl = ltq_readl(&switch_regs->p0_ctl);
++
++	switch (port->phy_if) {
++	case PHY_INTERFACE_MODE_RGMII:
++		port_xmii = RGMII_CTL_P0IS_RGMII;
++
++		switch (port->rgmii_tx_delay) {
++		case 1:
++			port_xmii |= RGMII_CTL_P0TDLY_1_5;
++			break;
++		case 2:
++			port_xmii |= RGMII_CTL_P0TDLY_1_75;
++			break;
++		case 3:
++			port_xmii |= RGMII_CTL_P0TDLY_2_0;
++			break;
++		default:
++			break;
++		}
++
++		switch (port->rgmii_rx_delay) {
++		case 1:
++			port_xmii |= RGMII_CTL_P0RDLY_1_5;
++			break;
++		case 2:
++			port_xmii |= RGMII_CTL_P0RDLY_1_75;
++			break;
++		case 3:
++			port_xmii |= RGMII_CTL_P0RDLY_2_0;
++			break;
++		default:
++			break;
++		}
++
++		if (!(port->flags & LTQ_ETH_PORT_PHY)) {
++			port_xmii |= (RGMII_CTL_P0SPD_1000 |
++					RGMII_CTL_P0DUP_FULL);
++			port_ctl |= P0_CTL_FLP;
++		}
++
++		break;
++	case PHY_INTERFACE_MODE_MII:
++		port_xmii = RGMII_CTL_P0IS_MII;
++
++		if (!(port->flags & LTQ_ETH_PORT_PHY)) {
++			port_xmii |= (RGMII_CTL_P0SPD_100 |
++					RGMII_CTL_P0DUP_FULL);
++			port_ctl |= P0_CTL_FLP;
++		}
++
++		break;
++	default:
++		break;
++	}
++
++	if (port->num == 1) {
++		ltq_writel(&switch_regs->p1_ctl, port_ctl);
++
++		rgmii_ctl &= ~RGMII_CTL_P1_MASK;
++		rgmii_ctl |= (port_xmii << RGMII_CTL_P1_SHIFT);
++	} else {
++		ltq_writel(&switch_regs->p0_ctl, port_ctl);
++
++		rgmii_ctl &= ~RGMII_CTL_P0_MASK;
++		rgmii_ctl |= port_xmii;
++	}
++
++	ltq_writel(&switch_regs->rgmii_ctl, rgmii_ctl);
++
++	/* Connect to external switch */
++	if (port->flags & LTQ_ETH_PORT_SWITCH) {
++		sw = switch_connect(priv->bus);
++		if (sw)
++			switch_setup(sw);
++	}
++
++	/* Connect to internal/external PHYs */
++	if (port->flags & LTQ_ETH_PORT_PHY) {
++		phydev = phy_connect(priv->bus, port->phy_addr, priv->dev,
++					port->phy_if);
++		if (phydev)
++			phy_config(phydev);
++
++		priv->phymap[port->num] = phydev;
++	}
++}
++
++int ltq_eth_initialize(const struct ltq_eth_board_config *board_config)
++{
++	struct eth_device *dev;
++	struct mii_dev *bus;
++	struct ltq_eth_priv *priv;
++	struct ltq_dma_device *dma_dev;
++	const struct ltq_eth_port_config *port = &board_config->ports[0];
++	int i, ret;
++
++	build_check_ar9_registers();
++
++	ltq_dma_init();
++	ltq_eth_hw_init(port);
++
++	dev = calloc(1, sizeof(*dev));
++	if (!dev)
++		return -1;
++
++	priv = calloc(1, sizeof(*priv));
++	if (!priv)
++		return -1;
++
++	bus = mdio_alloc();
++	if (!bus)
++		return -1;
++
++	sprintf(dev->name, LTQ_ETH_DRV_NAME);
++	dev->priv = priv;
++	dev->init = ltq_eth_init;
++	dev->halt = ltq_eth_halt;
++	dev->recv = ltq_eth_recv;
++	dev->send = ltq_eth_send;
++
++	sprintf(bus->name, LTQ_MDIO_DRV_NAME);
++	bus->read = ltq_mdio_read;
++	bus->write = ltq_mdio_write;
++	bus->priv = priv;
++
++	dma_dev = &priv->dma_dev;
++	dma_dev->port = 0;
++	dma_dev->rx_chan.chan_no = 0;
++	dma_dev->rx_chan.class = 0;
++	dma_dev->rx_chan.num_desc = LTQ_ETH_RX_BUFFER_CNT;
++	dma_dev->rx_endian_swap = LTQ_DMA_ENDIANESS_B3_B2_B1_B0;
++	dma_dev->rx_burst_len = LTQ_DMA_BURST_2WORDS;
++	dma_dev->tx_chan.chan_no = 1;
++	dma_dev->tx_chan.class = 0;
++	dma_dev->tx_chan.num_desc = LTQ_ETH_TX_BUFFER_CNT;
++	dma_dev->tx_endian_swap = LTQ_DMA_ENDIANESS_B3_B2_B1_B0;
++	dma_dev->tx_burst_len = LTQ_DMA_BURST_2WORDS;
++
++	priv->bus = bus;
++	priv->dev = dev;
++
++	ret = ltq_dma_register(dma_dev);
++	if (ret)
++		return ret;
++
++	ret = mdio_register(bus);
++	if (ret)
++		return ret;
++
++	ret = eth_register(dev);
++	if (ret)
++		return ret;
++
++	for (i = 0; i < board_config->num_ports; i++)
++		ltq_eth_port_config(priv, &board_config->ports[i]);
++
++	return 0;
++}
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0016-sf-add-MTD-layer-driver-for-SPI-flash-devices.patch

@@ -1,133 +0,0 @@
-From 7f6ded11965b09daf6da44d4fa98da17b9fba36c Mon Sep 17 00:00:00 2001
-From: Daniel Schwierzeck <[email protected]>
-Date: Tue, 6 Nov 2012 19:41:26 +0100
-Subject: sf: add MTD layer driver for SPI flash devices
-
-Signed-off-by: Daniel Schwierzeck <[email protected]>
-
---- a/drivers/mtd/spi/Makefile
-+++ b/drivers/mtd/spi/Makefile
-@@ -30,6 +30,7 @@ COBJS-$(CONFIG_SPL_SPI_LOAD)	+= spi_spl_
- endif
- 
- COBJS-$(CONFIG_SPI_FLASH)	+= spi_flash.o
-+COBJS-$(CONFIG_SPI_FLASH_MTD)	+= spi_flash_mtd.o
- COBJS-$(CONFIG_SPI_FLASH_ATMEL)	+= atmel.o
- COBJS-$(CONFIG_SPI_FLASH_EON)	+= eon.o
- COBJS-$(CONFIG_SPI_FLASH_MACRONIX)	+= macronix.o
---- a/drivers/mtd/spi/spi_flash_internal.h
-+++ b/drivers/mtd/spi/spi_flash_internal.h
-@@ -122,6 +122,9 @@ static inline int spi_flash_set_4byte_mo
- }
- #endif
- 
-+/* SPI flash MTD adapter init */
-+int spi_flash_mtd_init(struct spi_flash *flash);
-+
- /* Manufacturer-specific probe functions */
- int spi_flash_probe_spansion(struct spi_flash *flash, u8 *idcode);
- int spi_flash_probe_atmel(struct spi_flash *flash, u8 *idcode);
---- /dev/null
-+++ b/drivers/mtd/spi/spi_flash_mtd.c
-@@ -0,0 +1,101 @@
-+/*
-+ * (C) Copyright 2012 Daniel Schwierzeck, [email protected]
-+ *
-+ * MTD layer driver for SPI flash devices
-+ *
-+ * This file is released under the terms of GPL v2 and any later version.
-+ * See the file COPYING in the root directory of the source tree for details.
-+ */
-+
-+#include <common.h>
-+#include <malloc.h>
-+#include <asm/errno.h>
-+#include <linux/mtd/mtd.h>
-+#include <spi_flash.h>
-+
-+static struct mtd_info sf_mtd_info;
-+static char sf_mtd_name[8];
-+
-+static int spi_flash_mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
-+{
-+	struct spi_flash *flash = mtd->priv;
-+	int err;
-+
-+	instr->state = MTD_ERASING;
-+
-+	err = spi_flash_erase(flash, instr->addr, instr->len);
-+	if (err) {
-+		instr->state = MTD_ERASE_FAILED;
-+		instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
-+		return -EIO;
-+	}
-+
-+	instr->state = MTD_ERASE_DONE;
-+	mtd_erase_callback(instr);
-+
-+	return 0;
-+}
-+
-+static int spi_flash_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
-+	size_t *retlen, u_char *buf)
-+{
-+	struct spi_flash *flash = mtd->priv;
-+	int err;
-+
-+	err = spi_flash_read(flash, from, len, buf);
-+	if (!err)
-+		*retlen = len;
-+
-+	return err;
-+}
-+
-+static int spi_flash_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,
-+	size_t *retlen, const u_char *buf)
-+{
-+	struct spi_flash *flash = mtd->priv;
-+	int err;
-+
-+	err = spi_flash_write(flash, to, len, buf);
-+	if (!err)
-+		*retlen = len;
-+
-+	return err;
-+}
-+
-+static void spi_flash_mtd_sync(struct mtd_info *mtd)
-+{
-+}
-+
-+static int spi_flash_mtd_number(void)
-+{
-+#ifdef CONFIG_SYS_MAX_FLASH_BANKS
-+	return CONFIG_SYS_MAX_FLASH_BANKS;
-+#else
-+	return 0;
-+#endif
-+}
-+
-+int spi_flash_mtd_init(struct spi_flash *flash)
-+{
-+	memset(&sf_mtd_info, 0, sizeof(sf_mtd_info));
-+	sprintf(sf_mtd_name, "nor%d", spi_flash_mtd_number());
-+
-+	sf_mtd_info.name = sf_mtd_name;
-+	sf_mtd_info.type = MTD_NORFLASH;
-+	sf_mtd_info.flags = MTD_CAP_NORFLASH;
-+	sf_mtd_info.writesize = 1;
-+
-+	sf_mtd_info.erase = spi_flash_mtd_erase;
-+	sf_mtd_info.read = spi_flash_mtd_read;
-+	sf_mtd_info.write = spi_flash_mtd_write;
-+	sf_mtd_info.sync = spi_flash_mtd_sync;
-+
-+	sf_mtd_info.size = flash->size;
-+	sf_mtd_info.priv = flash;
-+
-+	/* Only uniform flash devices for now */
-+	sf_mtd_info.numeraseregions = 0;
-+	sf_mtd_info.erasesize = flash->sector_size;
-+
-+	return add_mtd_device(&sf_mtd_info);
-+}

package/boot/uboot-lantiq/patches/0017-sf-add-init-function.patch

@@ -1,57 +0,0 @@
-From aa9d5d64ca6441cb24e22dc3c1f707da62da2887 Mon Sep 17 00:00:00 2001
-From: Daniel Schwierzeck <[email protected]>
-Date: Tue, 6 Nov 2012 19:35:17 +0100
-Subject: sf: add init function
-
-Signed-off-by: Daniel Schwierzeck <[email protected]>
-
---- a/drivers/mtd/spi/spi_flash.c
-+++ b/drivers/mtd/spi/spi_flash.c
-@@ -482,3 +482,36 @@ void spi_flash_free(struct spi_flash *fl
- 	spi_flash_free_spl(flash);
- 	free(flash);
- }
-+
-+#ifdef CONFIG_SPI_FLASH_MTD
-+static int spi_flash_mtd_register(void)
-+{
-+	struct spi_flash *flash;
-+	int err;
-+
-+	flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
-+			CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
-+	if (!flash)
-+		return -1;
-+
-+	err = spi_flash_mtd_init(flash);
-+	if (err)
-+		spi_flash_free(flash);
-+
-+	return err;
-+}
-+#else
-+static int spi_flash_mtd_register(void)
-+{
-+	return 0;
-+}
-+#endif
-+
-+int spi_flash_init(void)
-+{
-+	int err;
-+
-+	err = spi_flash_mtd_register();
-+
-+	return err;
-+}
---- a/include/spi_flash.h
-+++ b/include/spi_flash.h
-@@ -51,6 +51,8 @@ struct spi_flash {
- #endif
- };
- 
-+int spi_flash_init(void);
-+
- struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
- 		unsigned int max_hz, unsigned int spi_mode);
- void spi_flash_free(struct spi_flash *flash);

package/boot/uboot-lantiq/patches/0029-tools-add-some-helper-tools-for-Lantiq-SoCs.patch → package/boot/uboot-lantiq/patches/0017-tools-add-some-helper-tools-for-Lantiq-SoCs.patch

@@ -1,11 +1,14 @@
-From 1b77d4249b5addbf3b0848db6992a445019a1865 Mon Sep 17 00:00:00 2001
+From 1da5479d59b39d7931a2b0efabdfa314f6788b6d Mon Sep 17 00:00:00 2001
 From: Luka Perkov <[email protected]>
-Date: Wed, 29 Aug 2012 22:08:42 +0200
+Date: Sat, 2 Mar 2013 23:34:00 +0100
 Subject: tools: add some helper tools for Lantiq SoCs
 
 Signed-off-by: Luka Perkov Luka Perkov <[email protected]>
 Signed-off-by: Daniel Schwierzeck <[email protected]>
 
+diff --git a/tools/gct.pl b/tools/gct.pl
+new file mode 100755
+index 0000000..33fa6f7
 --- /dev/null
 +++ b/tools/gct.pl
 @@ -0,0 +1,155 @@
@@ -164,44 +167,150 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +		$holder="";
 +	}
 +}
+diff --git a/tools/lantiq_bdi_conf.awk b/tools/lantiq_bdi_conf.awk
+new file mode 100755
+index 0000000..c732289
 --- /dev/null
-+++ b/tools/lantiq_extract_openwrt_patches.sh
-@@ -0,0 +1,15 @@
-+#!/bin/bash
++++ b/tools/lantiq_bdi_conf.awk
+@@ -0,0 +1,116 @@
++#!/usr/bin/awk -f
++#
++# Copyright (C) 2013 Luka Perkov <[email protected]>
++# Copyright (C) 2013 Daniel Schwierzeck <[email protected]>
++#
++# Usage:
++#  awk -f lantiq_bdi_conf.awk -v soc=ar9 board=<name> PATH_TO_BOARD/ddr_settings.h
++#
++# Additional information:
++#  http://www.abatron.ch/fileadmin/user_upload/products/pdf/ManGDBR4K-3000.pdf
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++function print_header()
++{
++	print ";                                                                         "
++	print "; Copyright (C) 2013 Luka Perkov <[email protected]>                       "
++	print "; Copyright (C) 2013 Daniel Schwierzeck <[email protected]>    "
++	print ";                                                                         "
++	print "; This file has been generated with lantiq_bdi_conf.awk script.           "
++	print ";                                                                         "
++	print "; SPDX-License-Identifier:	GPL-2.0+                                 "
++	print ";                                                                         "
++	print ""
++}
++
++function init_ar9_prologue()
++{
++	print "WM32 0xBF103010 0x80		; CGU for CPU 333Mhz, DDR 167Mhz"
++	print "WM32 0xBF103014 0x01		; CGU update"
++	print "WM32 0xBF800010 0x0		; Clear error access log register"
++	print "WM32 0xBF800020 0x0		; Clear error access log register"
++	print "WM32 0xBF800060 0xD		; Enable FPI, DDR and SRAM module in memory controller"
++	print "WM32 0xBF801030 0x0		; Clear start bit of DDR memory controller"
++}
++
++function init_ar9_epilogue()
++{
++	print "WM32 0xBE105360 0x4001D7FF	; EBU setup"
++}
 +
-+set -e
-+set -x
++function init_ddr1_epilogue()
++{
++	print "WM32 0xBF801030 0x100		; Set start bit of DDR memory controller"
++}
++
++function ar9_target()
++{
++	print "CPUTYPE		M34K"
++	print "ENDIAN		BIG"
++	print "JTAGCLOCK	1"
++	print "BDIMODE		AGENT		; [ LOADONLY, AGENT ]"
++	print "RESET		JTAG		; [ NONE, JTAG, HARD ]"
++	print "POWERUP		100"
++	print "WAKEUP		100"
++	print "BREAKMODE	HARD		; [ SOFT, HARD ]"
++	print  "STEPMODE	SWBP		; [ JTAG, HWBP, SWBP ]"
++	print "VECTOR		CATCH"
++	print  "SCANSUCC	1 5"
++}
++
++function flash_p2601hnfx()
++{
++	print "CHIPTYPE	MIRRORX16"
++	print "CHIPSIZE	0x1000000"
++	print "BUSWIDTH	16"
++}
++
++BEGIN {
++	switch (soc) {
++	case "ar9":
++		reg_base = 0xbf801000
++		print_header()
++		print "[INIT]"
++		init_ar9_prologue()
++		break
++	default:
++		print "Invalid or no value for SoC specified!"
++		exit 1
++	}
++}
 +
-+test $# -eq 1
++/^#define/ {
++	/* DC03 contains MC enable bit and must not be set here */
++	if (tolower($2) != "mc_dc03_value")
++		printf("WM32 0x%x %s\n", reg_base, tolower($3))
 +
-+openwrt_root=$(readlink -f $1)
-+test -d $openwrt_root
++	reg_base += 0x10
++}
 +
-+uboot_lantiq_dir=$openwrt_root/package/boot/uboot-lantiq/patches
-+test -d $uboot_lantiq_dir
++END {
++	switch (soc) {
++	case "ar9":
++		init_ddr1_epilogue()
++		init_ar9_epilogue()
++		print ""
++		print "[TARGET]"
++		ar9_target()
++		print ""
++		print "[HOST]"
++		print "PROMPT		\"ar9> \""
++		print ""
++		break
++	default:
++	}
 +
-+rm -vf $uboot_lantiq_dir/*
-+git format-patch -k -p --no-renames --text --full-index -o $uboot_lantiq_dir v2012.10..openwrt/v2013.01
++	switch (board) {
++	case "p2601hnfx":
++		print "[FLASH]"
++		flash_p2601hnfx()
++		print ""
++		break
++	default:
++	}
++}
+diff --git a/tools/lantiq_ram_extract_magic.awk b/tools/lantiq_ram_extract_magic.awk
+new file mode 100755
+index 0000000..64f1cbc
 --- /dev/null
 +++ b/tools/lantiq_ram_extract_magic.awk
-@@ -0,0 +1,70 @@
+@@ -0,0 +1,69 @@
 +#
-+# This file is released under the terms of GPL v2 and any later version.
-+# See the file COPYING in the root directory of the source tree for details.
++# Copyright (C) 2011-2013 Luka Perkov <[email protected]>
 +#
-+# Copyright (C) 2011 Luka Perkov <[email protected]>
++# Usage:
++# mips-openwrt-linux-objdump -EB -b binary -m mips:isa32r2 -D YOUR_IMAGE_DUMP | awk -f lantiq_ram_extract_magic.awk
 +#
-+# usage: mips-openwrt-linux-objdump -EB -b binary -m mips:isa32r2 -D YOUR_IMAGE_DUMP | awk -f lantiq_ram_extract_magic.awk
++# SPDX-License-Identifier:	GPL-2.0+
 +#
 +
 +BEGIN {
 +	print "/*                                                                            "
-+	print " * This file is released under the terms of GPL v2 and any later version.     "
-+	print " * See the file COPYING in the root directory of the source tree for details. "
++	print " * Copyright (C) 2011-2013 Luka Perkov <[email protected]>                     "
 +	print " *                                                                            "
-+	print " * generated with lantiq_ram_extract_magic.awk                                "
++	print " * This file has been generated with lantiq_ram_extract_magic.awk script.     "
 +	print " *                                                                            "
-+	print " * Copyright (C) 2011 Luka Perkov <[email protected]>                          "
++	print " * SPDX-License-Identifier:	GPL-2.0+                                     "
 +	print " */                                                                           "
 +	print ""
 +
@@ -255,35 +364,36 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +	if ($4 == "t2,736(t1)")
 +		right_section=0
 +}
+diff --git a/tools/lantiq_ram_init_uart.awk b/tools/lantiq_ram_init_uart.awk
+new file mode 100755
+index 0000000..dc82645
 --- /dev/null
 +++ b/tools/lantiq_ram_init_uart.awk
-@@ -0,0 +1,101 @@
+@@ -0,0 +1,117 @@
 +#!/usr/bin/awk -f
 +#
-+# This file is released under the terms of GPL v2 and any later version.
-+# See the file COPYING in the root directory of the source tree for details.
-+#
 +# Copyright (C) 2011-2012 Luka Perkov <[email protected]>
 +# Copyright (C) 2012 Daniel Schwierzeck <[email protected]>
 +#
-+# usage: awk -f lantiq_ram_init_uart.awk -v soc=<danube|ar9|vr9> PATH_TO_BOARD/ddr_settings.h
++# Usage:
++# awk -f lantiq_ram_init_uart.awk -v soc=<danube|ar9|vr9> PATH_TO_BOARD/ddr_settings.h
++#
++# SPDX-License-Identifier:	GPL-2.0+
 +#
 +
 +function print_header()
 +{
 +	print ";                                                                            "
-+	print "; This file is released under the terms of GPL v2 and any later version.     "
-+	print "; See the file COPYING in the root directory of the source tree for details. "
++	print "; Copyright (C) 2011-2013 Luka Perkov <[email protected]>                     "
++	print "; Copyright (C) 2012-2013 Daniel Schwierzeck <[email protected]>  "
 +	print ";                                                                            "
-+	print "; generated with lantiq_ram_init_uart.awk                                    "
-+	print ";                                                                            "
-+	print "; Copyright (C) 2011-2012 Luka Perkov <[email protected]>                     "
-+	print "; Copyright (C) 2012 Daniel Schwierzeck <[email protected]>       "
++	print "; This file has been generated with lantiq_ram_init_uart.awk script.         "
 +	print ";                                                                            "
++	print "; SPDX-License-Identifier:	GPL-2.0+                                    "
 +	print ""
 +}
 +
-+function mc_ddr1_prologue()
++function mc_danube_prologue()
 +{
 +	/* Clear access error log registers */
 +	print "0xbf800010", "0x0"
@@ -296,6 +406,19 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +	print "0xbf801030", "0x0"
 +}
 +
++function mc_ar9_prologue()
++{
++	/* Clear access error log registers */
++	print "0xbf800010", "0x0"
++	print "0xbf800020", "0x0"
++
++	/* Enable FPI, DDR and SRAM module in memory controller */
++	print "0xbf800060", "0xD"
++
++	/* Clear start bit of DDR memory controller */
++	print "0xbf801030", "0x0"
++}
++
 +function mc_ddr1_epilogue()
 +{
 +	/* Set start bit of DDR memory controller */
@@ -318,10 +441,14 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +BEGIN {
 +	switch (soc) {
 +	case "danube":
++		reg_base = 0xbf801000
++		print_header()
++		mc_danube_prologue()
++		break
 +	case "ar9":
 +		reg_base = 0xbf801000
 +		print_header()
-+		mc_ddr1_prologue()
++		mc_ar9_prologue()
 +		break
 +	case "vr9":
 +		reg_base = 0xbf401000
@@ -337,14 +464,15 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +}
 +
 +/^#define/ {
-+	printf("0x%x %s\n", reg_base, tolower($3))
-+	reg_base += 0x10
-+}
++	/* CCR07 contains MC enable bit and must not be set here */
++	if (tolower($2) == "mc_ccr07_value")
++		mc_ccr07_value = strtonum($3)
++	if (tolower($2) == "mc_dc03_value")
++		/* CCR07 contains MC enable bit and must not be set here */
++	else
++		printf("0x%x %s\n", reg_base, tolower($3))
 +
-+/^#define(.*)MC_CCR07_VALUE/ {
-+	printf("0x%x %s\n", reg_base, tolower($3))
 +	reg_base += 0x10
-+	mc_ccr07_value = strtonum($3)
 +}
 +
 +END {
@@ -359,3 +487,6 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +	default:
 +	}
 +}
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0018-MIPS-add-SPI-flash-init-hook.patch

@@ -1,47 +0,0 @@
-From 888b33e84082fe72d60d528c05c885c0c9d70bc4 Mon Sep 17 00:00:00 2001
-From: Daniel Schwierzeck <[email protected]>
-Date: Tue, 6 Nov 2012 21:19:43 +0100
-Subject: MIPS: add SPI flash init hook
-
-Signed-off-by: Daniel Schwierzeck <[email protected]>
-
---- a/arch/mips/lib/board.c
-+++ b/arch/mips/lib/board.c
-@@ -32,6 +32,7 @@
- #include <nand.h>
- #include <onenand_uboot.h>
- #include <spi.h>
-+#include <spi_flash.h>
- 
- #ifdef CONFIG_BITBANGMII
- #include <miiphy.h>
-@@ -312,6 +313,16 @@ void board_init_r(gd_t *id, ulong dest_a
- 	onenand_init();
- #endif
- 
-+#ifdef CONFIG_CMD_SPI
-+	puts("SPI:   ");
-+	spi_init();		/* go init the SPI */
-+	puts("ready\n");
-+#endif
-+
-+#if defined(CONFIG_SPI_FLASH)
-+	spi_flash_init();
-+#endif
-+
- 	/* relocate environment function pointers etc. */
- 	env_relocate();
- 
-@@ -335,12 +346,6 @@ void board_init_r(gd_t *id, ulong dest_a
- 	/* Initialize from environment */
- 	load_addr = getenv_ulong("loadaddr", 16, load_addr);
- 
--#ifdef CONFIG_CMD_SPI
--	puts("SPI:   ");
--	spi_init();		/* go init the SPI */
--	puts("ready\n");
--#endif
--
- #if defined(CONFIG_MISC_INIT_R)
- 	/* miscellaneous platform dependent initialisations */
- 	misc_init_r();

package/boot/uboot-lantiq/patches/0018-tools-lantiq-add-NAND-SPL-support.patch

@@ -0,0 +1,228 @@
+From 43b9a7c9b903302c56d0a1d292a146dbf4de8e49 Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <[email protected]>
+Date: Mon, 12 Aug 2013 01:17:08 +0200
+Subject: tools: lantiq: add NAND SPL support
+
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/tools/ltq-boot-image.c b/tools/ltq-boot-image.c
+index 75a188c..743fc6f 100644
+--- a/tools/ltq-boot-image.c
++++ b/tools/ltq-boot-image.c
+@@ -14,7 +14,8 @@
+ 
+ enum image_types {
+ 	IMAGE_NONE,
+-	IMAGE_SFSPL
++	IMAGE_SFSPL,
++	IMAGE_NANDSPL
+ };
+ 
+ /* Lantiq non-volatile bootstrap command IDs */
+@@ -43,6 +44,8 @@ enum nvb_cmd_flags {
+ struct args {
+ 	enum image_types type;
+ 	__u32		entry_addr;
++	loff_t		uboot_offset;
++	unsigned int	page_size;
+ 	const char	*uboot_bin;
+ 	const char	*spl_bin;
+ 	const char	*out_bin;
+@@ -50,10 +53,11 @@ struct args {
+ 
+ static void usage_msg(const char *name)
+ {
+-	fprintf(stderr, "%s: [-h] -t type -e entry-addr -u uboot-bin [-s spl-bin] -o out-bin\n",
++	fprintf(stderr, "%s: [-h] -t type -e entry-addr [-x uboot-offset] [-p page-size] -u uboot-bin [-s spl-bin] -o out-bin\n",
+ 		name);
+ 	fprintf(stderr, " Image types:\n"
+-			"  sfspl  - SPL + [compressed] U-Boot for SPI flash\n");
++			"  sfspl   - SPL + [compressed] U-Boot for SPI flash\n"
++			"  nandspl - SPL + [compressed] U-Boot for NAND flash\n");
+ }
+ 
+ static enum image_types parse_image_type(const char *type)
+@@ -64,6 +68,9 @@ static enum image_types parse_image_type(const char *type)
+ 	if (!strncmp(type, "sfspl", 6))
+ 		return IMAGE_SFSPL;
+ 
++	if (!strncmp(type, "nandspl", 6))
++		return IMAGE_NANDSPL;
++
+ 	return IMAGE_NONE;
+ }
+ 
+@@ -73,7 +80,7 @@ static int parse_args(int argc, char *argv[], struct args *arg)
+ 
+ 	memset(arg, 0, sizeof(*arg));
+ 
+-	while ((opt = getopt(argc, argv, "ht:e:u:s:o:")) != -1) {
++	while ((opt = getopt(argc, argv, "ht:e:x:p:u:s:o:")) != -1) {
+ 		switch (opt) {
+ 		case 'h':
+ 			usage_msg(argv[0]);
+@@ -84,6 +91,12 @@ static int parse_args(int argc, char *argv[], struct args *arg)
+ 		case 'e':
+ 			arg->entry_addr = strtoul(optarg, NULL, 16);
+ 			break;
++		case 'x':
++			arg->uboot_offset = strtoul(optarg, NULL, 16);
++			break;
++		case 'p':
++			arg->page_size = strtoul(optarg, NULL, 10);
++			break;
+ 		case 'u':
+ 			arg->uboot_bin = optarg;
+ 			break;
+@@ -114,11 +127,22 @@ static int parse_args(int argc, char *argv[], struct args *arg)
+ 		goto parse_error;
+ 	}
+ 
+-	if (arg->type == IMAGE_SFSPL && !arg->spl_bin) {
++	if ((arg->type == IMAGE_SFSPL || arg->type == IMAGE_NANDSPL) &&
++		!arg->spl_bin) {
+ 		fprintf(stderr, "Missing SPL binary\n");
+ 		goto parse_error;
+ 	}
+ 
++	if (arg->type == IMAGE_NANDSPL && !arg->uboot_offset) {
++		fprintf(stderr, "Missing U-Boot offset\n");
++		goto parse_error;
++	}
++
++	if (arg->type == IMAGE_NANDSPL && !arg->page_size) {
++		fprintf(stderr, "Missing NAND page size\n");
++		goto parse_error;
++	}
++
+ 	return 0;
+ 
+ parse_error:
+@@ -174,6 +198,19 @@ static int write_nvb_start_header(int fd, __u32 addr)
+ 	return write_header(fd, hdr, sizeof(hdr));
+ }
+ 
++#if 0
++static int write_nvb_regcfg_header(int fd, __u32 addr)
++{
++	__u32 hdr[2];
++
++	hdr[0] = build_nvb_command(NVB_CMD_REGCFG, NVB_FLAG_SDBG |
++					NVB_FLAG_DBG);
++	hdr[1] = cpu_to_be32(addr);
++
++	return write_header(fd, hdr, sizeof(hdr));
++}
++#endif
++
+ static int open_input_bin(const char *name, void **ptr, size_t *size)
+ {
+ 	struct stat sbuf;
+@@ -238,9 +275,37 @@ static int open_output_bin(const char *name)
+ 	return fd;
+ }
+ 
+-static int create_sfspl(const struct args *arg)
++static int pad_to_offset(int fd, loff_t offset)
+ {
+-	int out_fd, uboot_fd, spl_fd, ret;
++	loff_t pos;
++	size_t size;
++	ssize_t n;
++	__u8 *buf;
++
++	pos = lseek(fd, 0, SEEK_CUR);
++	size = offset - pos;
++
++	buf = malloc(size);
++	if (!buf) {
++		fprintf(stderr, "Failed to malloc buffer\n");
++		return -1;
++	}
++
++	memset(buf, 0xff, size);
++	n = write(fd, buf, size);
++	free(buf);
++
++	if (n != size) {
++		fprintf(stderr, "Failed to write pad bytes\n");
++		return -1;
++	}
++
++	return 0;
++}
++
++static int create_spl_image(const struct args *arg)
++{
++	int out_fd, uboot_fd, spl_fd, ret = 0;
+ 	void *uboot_ptr, *spl_ptr;
+ 	size_t uboot_size, spl_size;
+ 
+@@ -256,9 +321,22 @@ static int create_sfspl(const struct args *arg)
+ 	if (0 > uboot_fd)
+ 		goto err_uboot;
+ 
++#if 0
++	ret = write_nvb_regcfg_header(out_fd, 0);
++	if (ret)
++		goto err_write;
++#endif
++
+ 	ret = write_nvb_dwnld_header(out_fd, spl_size, arg->entry_addr);
+ 	if (ret)
+ 		goto err_write;
++#if 0
++	if (arg->page_size) {
++		ret = pad_to_offset(out_fd, arg->page_size);
++		if (ret)
++			goto err_write;
++	}
++#endif
+ 
+ 	ret = copy_bin(out_fd, spl_ptr, spl_size);
+ 	if (ret)
+@@ -268,16 +346,16 @@ static int create_sfspl(const struct args *arg)
+ 	if (ret)
+ 		goto err_write;
+ 
++	if (arg->uboot_offset) {
++		ret = pad_to_offset(out_fd, arg->uboot_offset);
++		if (ret)
++			goto err_write;
++	}
++
+ 	ret = copy_bin(out_fd, uboot_ptr, uboot_size);
+ 	if (ret)
+ 		goto err_write;
+ 
+-	close_input_bin(uboot_fd, uboot_ptr, uboot_size);
+-	close_input_bin(spl_fd, spl_ptr, spl_size);
+-	close(out_fd);
+-
+-	return 0;
+-
+ err_write:
+ 	close_input_bin(uboot_fd, uboot_ptr, uboot_size);
+ err_uboot:
+@@ -285,7 +363,7 @@ err_uboot:
+ err_spl:
+ 	close(out_fd);
+ err:
+-	return -1;
++	return ret;
+ }
+ 
+ int main(int argc, char *argv[])
+@@ -299,7 +377,8 @@ int main(int argc, char *argv[])
+ 
+ 	switch (arg.type) {
+ 	case IMAGE_SFSPL:
+-		ret = create_sfspl(&arg);
++	case IMAGE_NANDSPL:
++		ret = create_spl_image(&arg);
+ 		break;
+ 	default:
+ 		fprintf(stderr, "Image type not implemented\n");
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0019-Makefile-add-Lantiq-NAND-SPL-images.patch

@@ -0,0 +1,53 @@
+From 2e01dc015bc8bb9ca45f369025c342ede990863e Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <[email protected]>
+Date: Mon, 12 Aug 2013 01:16:09 +0200
+Subject: Makefile: add Lantiq NAND SPL images
+
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/.gitignore b/.gitignore
+index 7abdc37..869b1b8 100644
+--- a/.gitignore
++++ b/.gitignore
+@@ -54,6 +54,9 @@
+ /u-boot.ltq.lzma.norspl
+ /u-boot.ltq.lzo.norspl
+ /u-boot.ltq.norspl
++/u-boot.ltq.lzma.nandspl
++/u-boot.ltq.lzo.nandspl
++/u-boot.ltq.nandspl
+ /u-boot.lzma.img
+ /u-boot.lzo.img
+ 
+diff --git a/Makefile b/Makefile
+index 73ec67d..0445035 100644
+--- a/Makefile
++++ b/Makefile
+@@ -599,6 +599,24 @@ $(obj)u-boot.ltq.lzma.sfspl: $(obj)u-boot.lzma.img $(obj)spl/u-boot-spl.bin
+ 		$(obj)tools/ltq-boot-image -t sfspl -e $(CONFIG_SPL_TEXT_BASE) \
+ 			-s $(obj)spl/u-boot-spl.bin -u $< -o $@
+ 
++$(obj)u-boot.ltq.nandspl:	$(obj)u-boot.img $(obj)spl/u-boot-spl.bin
++		$(obj)tools/ltq-boot-image -t nandspl -e $(CONFIG_SPL_TEXT_BASE) \
++			-x $(CONFIG_SYS_NAND_U_BOOT_OFFS) \
++			-p $(CONFIG_SYS_NAND_PAGE_SIZE) \
++			-s $(obj)spl/u-boot-spl.bin -u $< -o $@
++
++$(obj)u-boot.ltq.lzo.nandspl: $(obj)u-boot.lzo.img $(obj)spl/u-boot-spl.bin
++		$(obj)tools/ltq-boot-image -t nandspl -e $(CONFIG_SPL_TEXT_BASE) \
++			-x $(CONFIG_SYS_NAND_U_BOOT_OFFS) \
++			-p $(CONFIG_SYS_NAND_PAGE_SIZE) \
++			-s $(obj)spl/u-boot-spl.bin -u $< -o $@
++
++$(obj)u-boot.ltq.lzma.nandspl: $(obj)u-boot.lzma.img $(obj)spl/u-boot-spl.bin
++		$(obj)tools/ltq-boot-image -t nandspl -e $(CONFIG_SPL_TEXT_BASE) \
++			-x $(CONFIG_SYS_NAND_U_BOOT_OFFS) \
++			-p $(CONFIG_SYS_NAND_PAGE_SIZE) \
++			-s $(obj)spl/u-boot-spl.bin -u $< -o $@
++
+ $(obj)u-boot.ltq.norspl: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin
+ 	cat $(obj)spl/u-boot-spl.bin $< > $@
+ 
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0020-MIPS-lantiq-add-NAND-SPL-support.patch

@@ -0,0 +1,172 @@
+From e17398316e82d8b28217232b4fd6030c65138e74 Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <[email protected]>
+Date: Mon, 12 Aug 2013 01:18:00 +0200
+Subject: MIPS: lantiq: add NAND SPL support
+
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/arch/mips/cpu/mips32/lantiq-common/spl.c b/arch/mips/cpu/mips32/lantiq-common/spl.c
+index 489a82b..3d9d4d4 100644
+--- a/arch/mips/cpu/mips32/lantiq-common/spl.c
++++ b/arch/mips/cpu/mips32/lantiq-common/spl.c
+@@ -8,6 +8,7 @@
+ #include <image.h>
+ #include <version.h>
+ #include <spi_flash.h>
++#include <nand.h>
+ #include <linux/compiler.h>
+ #include <lzma/LzmaDec.h>
+ #include <linux/lzo.h>
+@@ -63,6 +64,18 @@
+ #define spl_boot_nor_flash	0
+ #endif
+ 
++#if defined(CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH) && defined(CONFIG_SYS_BOOT_NANDSPL)
++#define spl_boot_nand_flash	1
++#else
++#define spl_boot_nand_flash	0
++#ifndef CONFIG_SYS_NAND_U_BOOT_OFFS
++#define CONFIG_SYS_NAND_U_BOOT_OFFS	0
++#endif
++#ifndef CONFIG_SYS_NAND_PAGE_SIZE
++#define CONFIG_SYS_NAND_PAGE_SIZE	0
++#endif
++#endif
++
+ #define spl_sync()	__asm__ __volatile__("sync");
+ 
+ struct spl_image {
+@@ -337,6 +350,58 @@ static int spl_load_nor_flash(struct spl_image *spl)
+ 	return ret;
+ }
+ 
++static int spl_load_nand_flash(struct spl_image *spl)
++{
++	image_header_t *hdr;
++	int ret;
++	unsigned long loadaddr;
++
++	/*
++	 * Image format:
++	 *
++	 * - 12 byte non-volatile bootstrap header
++	 * - SPL binary
++	 * - 12 byte non-volatile bootstrap header
++	 * - padding bytes up to CONFIG_SYS_NAND_U_BOOT_OFFS
++	 * - 64 byte U-Boot mkimage header
++	 * - U-Boot binary
++	 */
++	spl->data_addr = CONFIG_SYS_NAND_U_BOOT_OFFS;
++
++	spl_puts("SPL: initializing NAND flash\n");
++	nand_init();
++
++	spl_debug("SPL: reading image header at page offset %lx\n",
++		  spl->data_addr);
++
++	hdr = (image_header_t *) CONFIG_LOADADDR;
++	ret = nand_spl_load_image(spl->data_addr,
++				  CONFIG_SYS_NAND_PAGE_SIZE, hdr);
++	if (ret)
++		return ret;
++
++	spl_debug("SPL: checking image header at address %p\n", hdr);
++
++	ret = spl_parse_image(hdr, spl);
++	if (ret)
++		return ret;
++
++	if (spl_is_compressed(spl))
++		loadaddr = CONFIG_LOADADDR;
++	else
++		loadaddr = spl->entry_addr;
++
++	spl_puts("SPL: loading U-Boot to RAM\n");
++
++	ret = nand_spl_load_image(spl->data_addr, spl->data_size,
++				  (void *) loadaddr);
++
++	if (spl_is_compressed(spl))
++		ret = spl_uncompress(spl, loadaddr);
++
++	return ret;
++}
++
+ static int spl_load(struct spl_image *spl)
+ {
+ 	int ret;
+@@ -345,6 +410,8 @@ static int spl_load(struct spl_image *spl)
+ 		ret = spl_load_spi_flash(spl);
+ 	else if (spl_boot_nor_flash)
+ 		ret = spl_load_nor_flash(spl);
++	else if (spl_boot_nand_flash)
++		ret = spl_load_nand_flash(spl);
+ 	else
+ 		ret = 1;
+ 
+diff --git a/arch/mips/include/asm/lantiq/config.h b/arch/mips/include/asm/lantiq/config.h
+index feac30d..483cc94 100644
+--- a/arch/mips/include/asm/lantiq/config.h
++++ b/arch/mips/include/asm/lantiq/config.h
+@@ -40,6 +40,26 @@
+ #define CONFIG_SPI_SPL_SIMPLE
+ #endif
+ 
++/*
++ * NAND flash SPL
++ * BOOT CFG 06 only (address cycle based probing, 2KB or 512B page size)
++ */
++#if defined(CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH) && defined(CONFIG_SYS_BOOT_NANDSPL)
++#define CONFIG_SPL
++#define CONFIG_SPL_NAND_SUPPORT
++#define CONFIG_SPL_NAND_DRIVERS
++#define CONFIG_SPL_NAND_SIMPLE
++#define CONFIG_SPL_NAND_ECC
++
++/* use software ECC until driver supports HW ECC */
++#define CONFIG_SPL_NAND_SOFTECC
++#define CONFIG_SYS_NAND_ECCSIZE		256
++#define CONFIG_SYS_NAND_ECCBYTES	3
++#define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47, \
++					48, 49, 50, 51, 52, 53, 54, 55, \
++					56, 57, 58, 59, 60, 61, 62, 63}
++#endif
++
+ #if defined(CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH) && defined(CONFIG_SYS_BOOT_NORSPL)
+ #define CONFIG_SPL
+ #endif
+@@ -148,6 +168,21 @@
+ #define CONFIG_ENV_LOAD_UBOOT_SF
+ #endif
+ 
++#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH)
++#define CONFIG_ENV_WRITE_UBOOT_NAND				\
++	"write-uboot-nand="					\
++	"nand erase 0 $filesize && "				\
++	"nand write $fileaddr 0 $filesize\0"
++
++#define CONFIG_ENV_LOAD_UBOOT_NAND						\
++	"load-uboot-nandspl=tftpboot u-boot.ltq.nandspl\0"			\
++	"load-uboot-nandspl-lzo=tftpboot u-boot.ltq.lzo.nandspl\0"		\
++	"load-uboot-nandspl-lzma=tftpboot u-boot.ltq.lzma.nandspl\0"
++#else
++#define CONFIG_ENV_WRITE_UBOOT_NAND
++#define CONFIG_ENV_LOAD_UBOOT_NAND
++#endif
++
+ #define CONFIG_ENV_LANTIQ_DEFAULTS	\
+ 	CONFIG_ENV_CONSOLEDEV		\
+ 	CONFIG_ENV_ADDCONSOLE		\
+@@ -159,6 +194,8 @@
+ 	CONFIG_ENV_LOAD_UBOOT_NOR	\
+ 	CONFIG_ENV_SF_PROBE		\
+ 	CONFIG_ENV_WRITE_UBOOT_SF	\
+-	CONFIG_ENV_LOAD_UBOOT_SF
++	CONFIG_ENV_LOAD_UBOOT_SF	\
++	CONFIG_ENV_WRITE_UBOOT_NAND	\
++	CONFIG_ENV_LOAD_UBOOT_NAND
+ 
+ #endif /* __LANTIQ_CONFIG_H__ */
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0021-MIPS-vrx200-add-NAND-SPL-support.patch

@@ -0,0 +1,37 @@
+From 7361581a1baaec43058f5b9350c32c7ac4e58064 Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <[email protected]>
+Date: Mon, 12 Aug 2013 00:11:16 +0200
+Subject: MIPS: vrx200: add NAND SPL support
+
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/arch/mips/cpu/mips32/vrx200/config.mk b/arch/mips/cpu/mips32/vrx200/config.mk
+index 442156a..b0fc882 100644
+--- a/arch/mips/cpu/mips32/vrx200/config.mk
++++ b/arch/mips/cpu/mips32/vrx200/config.mk
+@@ -27,4 +27,9 @@ ALL-y += $(obj)u-boot.ltq.norspl
+ ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.norspl
+ ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.norspl
+ endif
++ifdef CONFIG_SYS_BOOT_NANDSPL
++ALL-y += $(obj)u-boot.ltq.nandspl
++ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.nandspl
++ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.nandspl
++endif
+ endif
+diff --git a/arch/mips/include/asm/arch-vrx200/config.h b/arch/mips/include/asm/arch-vrx200/config.h
+index 88ef256..4ec6092 100644
+--- a/arch/mips/include/asm/arch-vrx200/config.h
++++ b/arch/mips/include/asm/arch-vrx200/config.h
+@@ -164,7 +164,7 @@
+ #define CONFIG_SYS_TEXT_BASE		0xB0000000
+ #endif
+ 
+-#if defined(CONFIG_SYS_BOOT_SFSPL)
++#if defined(CONFIG_SYS_BOOT_SFSPL) || defined(CONFIG_SYS_BOOT_NANDSPL)
+ #define CONFIG_SYS_TEXT_BASE		0x80100000
+ #define CONFIG_SPL_TEXT_BASE		0xBE220000
+ #endif
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0022-MIPS-lantiq-easy80920-add-support-for-NAND-SPL.patch

@@ -0,0 +1,68 @@
+From 6fa1c350fa19a054371eccef84e4885cfdd6a2d7 Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <[email protected]>
+Date: Mon, 19 Aug 2013 18:11:31 +0200
+Subject: MIPS: lantiq: easy80920: add support for NAND SPL
+
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/boards.cfg b/boards.cfg
+index f090726..394ede7 100644
+--- a/boards.cfg
++++ b/boards.cfg
+@@ -509,6 +509,7 @@ Active  mips        mips32         incaip      -               incaip
+ Active  mips        mips32         incaip      -               incaip              incaip_100MHz                        incaip:CPU_CLOCK_RATE=100000000                                                                                                   Wolfgang Denk <[email protected]>
+ Active  mips        mips32         incaip      -               incaip              incaip_133MHz                        incaip:CPU_CLOCK_RATE=133000000                                                                                                   Wolfgang Denk <[email protected]>
+ Active  mips        mips32         incaip      -               incaip              incaip_150MHz                        incaip:CPU_CLOCK_RATE=150000000                                                                                                   Wolfgang Denk <[email protected]>
++Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_nandspl                    easy80920:SYS_BOOT_NANDSPL                                                                                                        Daniel Schwierzeck <[email protected]>
+ Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_nor                        easy80920:SYS_BOOT_NOR                                                                                                            Daniel Schwierzeck <[email protected]>
+ Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_norspl                     easy80920:SYS_BOOT_NORSPL                                                                                                         Daniel Schwierzeck <[email protected]>
+ Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_ram                        easy80920:SYS_BOOT_RAM                                                                                                            Daniel Schwierzeck <[email protected]>
+diff --git a/include/configs/easy80920.h b/include/configs/easy80920.h
+index ad69bc2..56ceedb 100644
+--- a/include/configs/easy80920.h
++++ b/include/configs/easy80920.h
+@@ -31,6 +31,14 @@
+ 
+ #define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH	/* Build NOR flash SPL */
+ 
++#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH	/* Build NAND flash SPL */
++#define CONFIG_SYS_NAND_PAGE_COUNT	128
++#define CONFIG_SYS_NAND_PAGE_SIZE	2048
++#define CONFIG_SYS_NAND_OOBSIZE		64
++#define CONFIG_SYS_NAND_BLOCK_SIZE	(256 * 1024)
++#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
++#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x4000
++
+ #define CONFIG_LTQ_SPL_COMP_LZO
+ #define CONFIG_LTQ_SPL_CONSOLE
+ 
+@@ -57,6 +65,11 @@
+ #define CONFIG_ENV_OVERWRITE
+ #define CONFIG_ENV_OFFSET		(192 * 1024)
+ #define CONFIG_ENV_SECT_SIZE		(64 * 1024)
++#elif defined(CONFIG_SYS_BOOT_NANDSPL)
++#define CONFIG_ENV_IS_IN_NAND
++#define CONFIG_ENV_OVERWRITE
++#define CONFIG_ENV_OFFSET		(256 * 1024)
++#define CONFIG_ENV_SECT_SIZE		(256 * 1024)
+ #else
+ #define CONFIG_ENV_IS_NOWHERE
+ #endif
+@@ -84,9 +97,13 @@
+ #define CONFIG_ENV_UPDATE_UBOOT_SF					\
+ 	"update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0"
+ 
++#define CONFIG_ENV_UPDATE_UBOOT_NAND					\
++	"update-uboot-nand=run load-uboot-nandspl-lzo write-uboot-nand\0"
++
+ #define CONFIG_EXTRA_ENV_SETTINGS	\
+ 	CONFIG_ENV_LANTIQ_DEFAULTS	\
+ 	CONFIG_ENV_UPDATE_UBOOT_NOR	\
+-	CONFIG_ENV_UPDATE_UBOOT_SF
++	CONFIG_ENV_UPDATE_UBOOT_SF	\
++	CONFIG_ENV_UPDATE_UBOOT_NAND
+ 
+ #endif /* __CONFIG_H */
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0023-MIPS-lantiq-add-default-openwrt-config.patch

@@ -0,0 +1,56 @@
+From 8f584936adad0fca8beece5f55eadcdcd02fad0a Mon Sep 17 00:00:00 2001
+From: Luka Perkov <[email protected]>
+Date: Sat, 17 Aug 2013 03:44:46 +0200
+Subject: MIPS: lantiq: add default openwrt config
+
+Signed-off-by: Luka Perkov <[email protected]>
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/include/configs/openwrt-lantiq-common.h b/include/configs/openwrt-lantiq-common.h
+new file mode 100644
+index 0000000..d119bef
+--- /dev/null
++++ b/include/configs/openwrt-lantiq-common.h
+@@ -0,0 +1,39 @@
++/*
++ * Copyright (C) 2013 Luka Perkov <[email protected]>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#ifndef __OPENWRT_LANTIQ_COMMON_H
++#define __OPENWRT_LANTIQ_COMMON_H
++
++/* Commands */
++#if defined(CONFIG_LTQ_SUPPORT_ETHERNET)
++#define CONFIG_CMD_PING
++#endif
++
++/* Compression */
++#define CONFIG_LZMA
++
++/* Auto boot */
++#define CONFIG_BOOTDELAY	2
++
++/* Environment */
++#if !defined(CONFIG_SYS_BOOT_RAM)
++#define CONFIG_BOOTCOMMAND \
++	"bootm ${kernel_addr}"
++#endif
++
++/* Ethernet */
++#if defined(CONFIG_LTQ_SUPPORT_ETHERNET)
++#define CONFIG_ETHADDR		00:01:02:03:04:05
++#define CONFIG_SERVERIP		192.168.1.2
++#define CONFIG_IPADDR		192.168.1.1
++#endif
++
++/* Unnecessary */
++#undef CONFIG_BOOTM_NETBSD
++#undef CONFIG_BOOTM_PLAN9
++#undef CONFIG_BOOTM_RTEMS
++
++#endif /* __OPENWRT_LANTIQ_COMMON_H */
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0024-MIPS-VRX200-add-option-to-boot-from-AVM-EVA-loader.patch

@@ -1,33 +0,0 @@
-From 2c6115188c7353a601835885a6c544240cfc479e Mon Sep 17 00:00:00 2001
-From: Daniel Schwierzeck <[email protected]>
-Date: Fri, 30 Nov 2012 18:09:25 +0100
-Subject: MIPS: VRX200: add option to boot from AVM EVA loader
-
-Signed-off-by: Daniel Schwierzeck <[email protected]>
-
---- a/arch/mips/cpu/mips32/vrx200/config.mk
-+++ b/arch/mips/cpu/mips32/vrx200/config.mk
-@@ -17,6 +17,9 @@ endif
- LIBS-y += $(CPUDIR)/lantiq-common/liblantiq-common.o
- 
- ifndef CONFIG_SPL_BUILD
-+ifdef CONFIG_SYS_BOOT_EVA
-+ALL-y += $(obj)u-boot.bin.lzma
-+endif
- ifdef CONFIG_SYS_BOOT_SFSPL
- ALL-y += $(obj)u-boot.ltq.sfspl
- ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.sfspl
---- a/arch/mips/include/asm/arch-vrx200/config.h
-+++ b/arch/mips/include/asm/arch-vrx200/config.h
-@@ -161,6 +161,11 @@
- #define CONFIG_SYS_DISABLE_CACHE
- #endif
- 
-+#if defined(CONFIG_SYS_BOOT_EVA)
-+#define CONFIG_SYS_TEXT_BASE		0x80100000
-+#define CONFIG_SKIP_LOWLEVEL_INIT
-+#endif
-+
- #if defined(CONFIG_SYS_BOOT_NOR)
- #define CONFIG_SYS_TEXT_BASE		0xB0000000
- #endif

package/boot/uboot-lantiq/patches/0024-MIPS-lantiq-easy50712-add-openwrt-lantiq-common.h.patch

@@ -0,0 +1,31 @@
+From ac6896098d9dd62a248340e6a090574399e1fd87 Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <[email protected]>
+Date: Mon, 19 Aug 2013 18:46:47 +0200
+Subject: MIPS: lantiq: easy50712: add openwrt-lantiq-common.h
+
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/include/configs/easy50712.h b/include/configs/easy50712.h
+index 6d7988c..bc8820a 100644
+--- a/include/configs/easy50712.h
++++ b/include/configs/easy50712.h
+@@ -62,13 +62,13 @@
+ #define CONFIG_CONSOLE_ASC		1
+ #define CONFIG_CONSOLE_DEV		"ttyLTQ1"
+ 
+-/* Commands */
+-#define CONFIG_CMD_PING
+-
+ /* Pull in default board configs for Lantiq XWAY Danube */
+ #include <asm/lantiq/config.h>
+ #include <asm/arch/config.h>
+ 
++/* Pull in default OpenWrt configs for Lantiq SoC */
++#include "openwrt-lantiq-common.h"
++
+ #define CONFIG_ENV_UPDATE_UBOOT_NOR					\
+ 	"update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0"
+ 
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0025-MIPS-lantiq-easy80920-add-openwrt-lantiq-common.h.patch

@@ -0,0 +1,31 @@
+From 7afbe4633773905ef94a8404510fb5a459926000 Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <[email protected]>
+Date: Mon, 19 Aug 2013 18:11:57 +0200
+Subject: MIPS: lantiq: easy80920: add openwrt-lantiq-common.h
+
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/include/configs/easy80920.h b/include/configs/easy80920.h
+index 56ceedb..6f5ac03 100644
+--- a/include/configs/easy80920.h
++++ b/include/configs/easy80920.h
+@@ -84,13 +84,13 @@
+ #define CONFIG_CONSOLE_ASC		1
+ #define CONFIG_CONSOLE_DEV		"ttyLTQ1"
+ 
+-/* Commands */
+-#define CONFIG_CMD_PING
+-
+ /* Pull in default board configs for Lantiq XWAY VRX200 */
+ #include <asm/lantiq/config.h>
+ #include <asm/arch/config.h>
+ 
++/* Pull in default OpenWrt configs for Lantiq SoC */
++#include "openwrt-lantiq-common.h"
++
+ #define CONFIG_ENV_UPDATE_UBOOT_NOR					\
+ 	"update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0"
+ 
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0028-MIPS-add-board-support-for-Arcadyan-ARV4519.patch → package/boot/uboot-lantiq/patches/0026-MIPS-add-board-support-for-Arcadyan-ARV4519.patch

@@ -1,20 +1,21 @@
-From 4a738c02a7190756e01ba58c93c4b07bc6d6c2aa Mon Sep 17 00:00:00 2001
+From 9f915cf9550a6234adecaf3031c2b279835e14af Mon Sep 17 00:00:00 2001
 From: Luka Perkov <[email protected]>
-Date: Wed, 29 Aug 2012 22:08:42 +0200
+Date: Sat, 2 Mar 2013 23:34:00 +0100
 Subject: MIPS: add board support for Arcadyan ARV4519
 
 Signed-off-by: Luka Perkov <[email protected]>
 Signed-off-by: Daniel Schwierzeck <[email protected]>
 
+diff --git a/board/arcadyan/arv4519pw/Makefile b/board/arcadyan/arv4519pw/Makefile
+new file mode 100644
+index 0000000..3a547c2
 --- /dev/null
 +++ b/board/arcadyan/arv4519pw/Makefile
-@@ -0,0 +1,29 @@
-+#
-+# This file is released under the terms of GPL v2 and any later version.
-+# See the file COPYING in the root directory of the source tree for details.
+@@ -0,0 +1,27 @@
 +#
 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, [email protected]
-+# Copyright (C) 2011 Daniel Schwierzeck, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
 +#
 +
 +include $(TOPDIR)/config.mk
@@ -38,14 +39,16 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +sinclude $(obj).depend
 +
 +#########################################################################
+diff --git a/board/arcadyan/arv4519pw/arv4519pw.c b/board/arcadyan/arv4519pw/arv4519pw.c
+new file mode 100644
+index 0000000..a9dfd03
 --- /dev/null
 +++ b/board/arcadyan/arv4519pw/arv4519pw.c
-@@ -0,0 +1,52 @@
+@@ -0,0 +1,51 @@
 +/*
-+ * This file is released under the terms of GPL v2 and any later version.
-+ * See the file COPYING in the root directory of the source tree for details.
-+ *
 + * Copyright (C) 2012 Luka Perkov <[email protected]>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <common.h>
@@ -93,27 +96,31 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +{
 +	return switch_device_register(&ar8216_dev);
 +}
+diff --git a/board/arcadyan/arv4519pw/config.mk b/board/arcadyan/arv4519pw/config.mk
+new file mode 100644
+index 0000000..9d8953b
 --- /dev/null
 +++ b/board/arcadyan/arv4519pw/config.mk
-@@ -0,0 +1,8 @@
+@@ -0,0 +1,7 @@
 +#
-+# This file is released under the terms of GPL v2 and any later version.
-+# See the file COPYING in the root directory of the source tree for details.
++# Copyright (C) 2011-2013 Daniel Schwierzeck, [email protected]
 +#
-+# Copyright (C) 2011 Daniel Schwierzeck, [email protected]
++# SPDX-License-Identifier:	GPL-2.0+
 +#
 +
 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
+diff --git a/board/arcadyan/arv4519pw/ddr_settings.h b/board/arcadyan/arv4519pw/ddr_settings.h
+new file mode 100644
+index 0000000..c5e88b3
 --- /dev/null
 +++ b/board/arcadyan/arv4519pw/ddr_settings.h
-@@ -0,0 +1,56 @@
+@@ -0,0 +1,55 @@
 +/*
-+ * This file is released under the terms of GPL v2 and any later version.
-+ * See the file COPYING in the root directory of the source tree for details.
++ * Copyright (C) 2012-2013 Luka Perkov <[email protected]>
 + *
-+ * generated with lantiq_ram_extract_magic.awk
++ * This file has been generated with lantiq_ram_extract_magic.awk script.
 + *
-+ * Copyright (C) 2011 Luka Perkov <[email protected]>
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#define MC_DC00_VALUE	0x1B1B
@@ -163,25 +170,30 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +#define MC_DC44_VALUE	0x0
 +#define MC_DC45_VALUE	0x500
 +#define MC_DC46_VALUE	0x0
+diff --git a/boards.cfg b/boards.cfg
+index 394ede7..f300d5a 100644
 --- a/boards.cfg
 +++ b/boards.cfg
-@@ -438,6 +438,8 @@ vct_premium                  mips
- vct_premium_onenand          mips        mips32      vct                 micronas       -           vct:VCT_PREMIUM,VCT_ONENAND
- vct_premium_onenand_small    mips        mips32      vct                 micronas       -           vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE
- vct_premium_small            mips        mips32      vct                 micronas       -           vct:VCT_PREMIUM,VCT_SMALL_IMAGE
-+arv4519pw_ram                mips        mips32      arv4519pw           arcadyan       danube      arv4519pw:SYS_BOOT_RAM
-+arv4519pw_nor                mips        mips32      arv4519pw           arcadyan       danube      arv4519pw:SYS_BOOT_NOR
- arv7518pw_ram                mips        mips32      arv7518pw           arcadyan       danube      arv7518pw:SYS_BOOT_RAM
- arv7518pw_nor                mips        mips32      arv7518pw           arcadyan       danube      arv7518pw:SYS_BOOT_NOR
- dbau1000                     mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1000
+@@ -502,6 +502,9 @@ Active  mips        mips32         au1x00      -               dbau1x00
+ Active  mips        mips32         au1x00      -               dbau1x00            dbau1550                             dbau1x00:DBAU1550                                                                                                                 Thomas Lange <[email protected]>
+ Active  mips        mips32         au1x00      -               dbau1x00            dbau1550_el                          dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN                                                                                               Thomas Lange <[email protected]>
+ Active  mips        mips32         au1x00      -               pb1x00              pb1000                               pb1x00:PB1000                                                                                                                     -
++Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_brn                        arv4519pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <[email protected]>
++Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_nor                        arv4519pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <[email protected]>
++Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_ram                        arv4519pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <[email protected]>
+ Active  mips        mips32         danube      lantiq          easy50712           easy50712_nor                        easy50712:SYS_BOOT_NOR                                                                                                            Daniel Schwierzeck <[email protected]>
+ Active  mips        mips32         danube      lantiq          easy50712           easy50712_norspl                     easy50712:SYS_BOOT_NORSPL                                                                                                         Daniel Schwierzeck <[email protected]>
+ Active  mips        mips32         danube      lantiq          easy50712           easy50712_ram                        easy50712:SYS_BOOT_RAM                                                                                                            Daniel Schwierzeck <[email protected]>
+diff --git a/include/configs/arv4519pw.h b/include/configs/arv4519pw.h
+new file mode 100644
+index 0000000..6907108
 --- /dev/null
 +++ b/include/configs/arv4519pw.h
-@@ -0,0 +1,69 @@
+@@ -0,0 +1,67 @@
 +/*
-+ * This file is released under the terms of GPL v2 and any later version.
-+ * See the file COPYING in the root directory of the source tree for details.
++ * Copyright (C) 2012-2013 Luka Perkov <[email protected]>
 + *
-+ * Copyright (C) 2012 Luka Perkov <[email protected]>
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#ifndef __CONFIG_H
@@ -193,7 +205,9 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +
 +/* Configure SoC */
 +#define CONFIG_LTQ_SUPPORT_UART		/* Enable ASC and UART */
++
 +#define CONFIG_LTQ_SUPPORT_ETHERNET	/* Enable ethernet */
++
 +#define CONFIG_LTQ_SUPPORT_NOR_FLASH	/* Have a parallel NOR flash */
 +
 +/* Switch devices */
@@ -205,44 +219,44 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +#define CONFIG_ENV_IS_IN_FLASH
 +#define CONFIG_ENV_OVERWRITE
 +#define CONFIG_ENV_OFFSET		(192 * 1024)
-+#define CONFIG_ENV_SIZE			(64 * 1024)
 +#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
 +#else
 +#define CONFIG_ENV_IS_NOWHERE
-+#define CONFIG_ENV_SIZE			(2 * 1024)
 +#endif
 +
++#define CONFIG_ENV_SIZE			(8 * 1024)
 +#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
 +
++/* Brnboot loadable image */
++#if defined(CONFIG_SYS_BOOT_BRN)
++#define CONFIG_SYS_TEXT_BASE		0x80002000
++#define CONFIG_SKIP_LOWLEVEL_INIT
++#define CONFIG_SYS_DISABLE_CACHE
++#define CONFIG_ENV_OVERWRITE 1
++#endif
++
 +/* Console */
 +#define CONFIG_LTQ_ADVANCED_CONSOLE
 +#define CONFIG_BAUDRATE			115200
 +#define CONFIG_CONSOLE_ASC		1
 +#define CONFIG_CONSOLE_DEV		"ttyLTQ1"
 +
-+/* Commands */
-+#define CONFIG_CMD_PING
-+
 +/* Pull in default board configs for Lantiq XWAY Danube */
 +#include <asm/lantiq/config.h>
 +#include <asm/arch/config.h>
 +
-+/* Compression */
-+#define CONFIG_LZMA
-+
-+/* Auto boot */
-+#define CONFIG_BOOTDELAY		2
-+
-+/* Environment configuration */
-+#define CONFIG_BOOTCOMMAND			\
-+	"run addeth; bootm ${kernel_addr}"
++/* Pull in default OpenWrt configs for Lantiq SoC */
++#include "openwrt-lantiq-common.h"
 +
 +#define CONFIG_ENV_UPDATE_UBOOT_NOR		\
 +	"update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
 +
-+#define CONFIG_EXTRA_ENV_SETTINGS		\
-+	CONFIG_ENV_LANTIQ_DEFAULTS		\
-+	CONFIG_ENV_UPDATE_UBOOT_NOR		\
++#define CONFIG_EXTRA_ENV_SETTINGS	\
++	CONFIG_ENV_LANTIQ_DEFAULTS	\
++	CONFIG_ENV_UPDATE_UBOOT_NOR	\
 +	"kernel_addr=0xB0040000\0"
 +
 +#endif /* __CONFIG_H */
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0027-MIPS-add-board-support-for-Arcadyan-ARV7518.patch

@@ -1,20 +1,21 @@
-From 289f7ed5d725067b4eb4b1a105bb63d55bf20392 Mon Sep 17 00:00:00 2001
+From 54a31b334162e8dc2ea891057ddeab42978db8b3 Mon Sep 17 00:00:00 2001
 From: Luka Perkov <[email protected]>
-Date: Wed, 29 Aug 2012 22:08:41 +0200
+Date: Sat, 2 Mar 2013 23:34:00 +0100
 Subject: MIPS: add board support for Arcadyan ARV7518
 
 Signed-off-by: Luka Perkov <[email protected]>
 Signed-off-by: Daniel Schwierzeck <[email protected]>
 
+diff --git a/board/arcadyan/arv7518pw/Makefile b/board/arcadyan/arv7518pw/Makefile
+new file mode 100644
+index 0000000..3a547c2
 --- /dev/null
 +++ b/board/arcadyan/arv7518pw/Makefile
-@@ -0,0 +1,29 @@
-+#
-+# This file is released under the terms of GPL v2 and any later version.
-+# See the file COPYING in the root directory of the source tree for details.
+@@ -0,0 +1,27 @@
 +#
 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, [email protected]
-+# Copyright (C) 2011 Daniel Schwierzeck, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
 +#
 +
 +include $(TOPDIR)/config.mk
@@ -38,14 +39,16 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +sinclude $(obj).depend
 +
 +#########################################################################
+diff --git a/board/arcadyan/arv7518pw/arv7518pw.c b/board/arcadyan/arv7518pw/arv7518pw.c
+new file mode 100644
+index 0000000..a9dfd03
 --- /dev/null
 +++ b/board/arcadyan/arv7518pw/arv7518pw.c
-@@ -0,0 +1,52 @@
+@@ -0,0 +1,51 @@
 +/*
-+ * This file is released under the terms of GPL v2 and any later version.
-+ * See the file COPYING in the root directory of the source tree for details.
-+ *
 + * Copyright (C) 2012 Luka Perkov <[email protected]>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <common.h>
@@ -93,27 +96,31 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +{
 +	return switch_device_register(&ar8216_dev);
 +}
+diff --git a/board/arcadyan/arv7518pw/config.mk b/board/arcadyan/arv7518pw/config.mk
+new file mode 100644
+index 0000000..9d8953b
 --- /dev/null
 +++ b/board/arcadyan/arv7518pw/config.mk
-@@ -0,0 +1,8 @@
+@@ -0,0 +1,7 @@
 +#
-+# This file is released under the terms of GPL v2 and any later version.
-+# See the file COPYING in the root directory of the source tree for details.
++# Copyright (C) 2011-2013 Daniel Schwierzeck, [email protected]
 +#
-+# Copyright (C) 2011 Daniel Schwierzeck, [email protected]
++# SPDX-License-Identifier:	GPL-2.0+
 +#
 +
 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
+diff --git a/board/arcadyan/arv7518pw/ddr_settings.h b/board/arcadyan/arv7518pw/ddr_settings.h
+new file mode 100644
+index 0000000..8b5e9c5
 --- /dev/null
 +++ b/board/arcadyan/arv7518pw/ddr_settings.h
-@@ -0,0 +1,56 @@
+@@ -0,0 +1,55 @@
 +/*
-+ * This file is released under the terms of GPL v2 and any later version.
-+ * See the file COPYING in the root directory of the source tree for details.
++ * Copyright (C) 2012-2013 Luka Perkov <[email protected]>
 + *
-+ * generated with lantiq_ram_extract_magic.awk
++ * This file has been generated with lantiq_ram_extract_magic.awk script.
 + *
-+ * Copyright (C) 2012 Luka Perkov <[email protected]>
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#define MC_DC00_VALUE	0x1B1B
@@ -163,25 +170,30 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +#define MC_DC44_VALUE	0x0
 +#define MC_DC45_VALUE	0x500
 +#define MC_DC46_VALUE	0x0
+diff --git a/boards.cfg b/boards.cfg
+index f300d5a..e832423 100644
 --- a/boards.cfg
 +++ b/boards.cfg
-@@ -438,6 +438,8 @@ vct_premium                  mips
- vct_premium_onenand          mips        mips32      vct                 micronas       -           vct:VCT_PREMIUM,VCT_ONENAND
- vct_premium_onenand_small    mips        mips32      vct                 micronas       -           vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE
- vct_premium_small            mips        mips32      vct                 micronas       -           vct:VCT_PREMIUM,VCT_SMALL_IMAGE
-+arv7518pw_ram                mips        mips32      arv7518pw           arcadyan       danube      arv7518pw:SYS_BOOT_RAM
-+arv7518pw_nor                mips        mips32      arv7518pw           arcadyan       danube      arv7518pw:SYS_BOOT_NOR
- dbau1000                     mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1000
- dbau1100                     mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1100
- dbau1500                     mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1500
+@@ -505,6 +505,9 @@ Active  mips        mips32         au1x00      -               pb1x00
+ Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_brn                        arv4519pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <[email protected]>
+ Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_nor                        arv4519pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <[email protected]>
+ Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_ram                        arv4519pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <[email protected]>
++Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_brn                        arv7518pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <[email protected]>
++Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_nor                        arv7518pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <[email protected]>
++Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_ram                        arv7518pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <[email protected]>
+ Active  mips        mips32         danube      lantiq          easy50712           easy50712_nor                        easy50712:SYS_BOOT_NOR                                                                                                            Daniel Schwierzeck <[email protected]>
+ Active  mips        mips32         danube      lantiq          easy50712           easy50712_norspl                     easy50712:SYS_BOOT_NORSPL                                                                                                         Daniel Schwierzeck <[email protected]>
+ Active  mips        mips32         danube      lantiq          easy50712           easy50712_ram                        easy50712:SYS_BOOT_RAM                                                                                                            Daniel Schwierzeck <[email protected]>
+diff --git a/include/configs/arv7518pw.h b/include/configs/arv7518pw.h
+new file mode 100644
+index 0000000..8cf1708
 --- /dev/null
 +++ b/include/configs/arv7518pw.h
-@@ -0,0 +1,69 @@
+@@ -0,0 +1,67 @@
 +/*
-+ * This file is released under the terms of GPL v2 and any later version.
-+ * See the file COPYING in the root directory of the source tree for details.
++ * Copyright (C) 2012-2013 Luka Perkov <[email protected]>
 + *
-+ * Copyright (C) 2012 Luka Perkov <[email protected]>
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#ifndef __CONFIG_H
@@ -193,7 +205,9 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +
 +/* Configure SoC */
 +#define CONFIG_LTQ_SUPPORT_UART		/* Enable ASC and UART */
++
 +#define CONFIG_LTQ_SUPPORT_ETHERNET	/* Enable ethernet */
++
 +#define CONFIG_LTQ_SUPPORT_NOR_FLASH	/* Have a parallel NOR flash */
 +
 +/* Switch devices */
@@ -205,44 +219,44 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +#define CONFIG_ENV_IS_IN_FLASH
 +#define CONFIG_ENV_OVERWRITE
 +#define CONFIG_ENV_OFFSET		(192 * 1024)
-+#define CONFIG_ENV_SIZE			(64 * 1024)
 +#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
 +#else
 +#define CONFIG_ENV_IS_NOWHERE
-+#define CONFIG_ENV_SIZE			(2 * 1024)
 +#endif
 +
++#define CONFIG_ENV_SIZE			(8 * 1024)
 +#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
 +
++/* Brnboot loadable image */
++#if defined(CONFIG_SYS_BOOT_BRN)
++#define CONFIG_SYS_TEXT_BASE		0x80002000
++#define CONFIG_SKIP_LOWLEVEL_INIT
++#define CONFIG_SYS_DISABLE_CACHE
++#define CONFIG_ENV_OVERWRITE 1
++#endif
++
 +/* Console */
 +#define CONFIG_LTQ_ADVANCED_CONSOLE
 +#define CONFIG_BAUDRATE			115200
 +#define CONFIG_CONSOLE_ASC		1
 +#define CONFIG_CONSOLE_DEV		"ttyLTQ1"
 +
-+/* Commands */
-+#define CONFIG_CMD_PING
-+
 +/* Pull in default board configs for Lantiq XWAY Danube */
 +#include <asm/lantiq/config.h>
 +#include <asm/arch/config.h>
 +
-+/* Compression */
-+#define CONFIG_LZMA
-+
-+/* Auto boot */
-+#define CONFIG_BOOTDELAY		2
-+
-+/* Environment configuration */
-+#define CONFIG_BOOTCOMMAND			\
-+	"run addeth; bootm ${kernel_addr}"
++/* Pull in default OpenWrt configs for Lantiq SoC */
++#include "openwrt-lantiq-common.h"
 +
 +#define CONFIG_ENV_UPDATE_UBOOT_NOR		\
 +	"update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
 +
-+#define CONFIG_EXTRA_ENV_SETTINGS		\
-+	CONFIG_ENV_LANTIQ_DEFAULTS		\
-+	CONFIG_ENV_UPDATE_UBOOT_NOR		\
++#define CONFIG_EXTRA_ENV_SETTINGS	\
++	CONFIG_ENV_LANTIQ_DEFAULTS	\
++	CONFIG_ENV_UPDATE_UBOOT_NOR	\
 +	"kernel_addr=0xB0040000\0"
 +
 +#endif /* __CONFIG_H */
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0028-MIPS-add-board-support-for-AudioCodes-MP-252.patch

@@ -0,0 +1,268 @@
+From 4bacfc80eae768be45f9ddf7588ec55281354648 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Fri, 8 Mar 2013 13:29:04 +0200
+Subject: MIPS: add board support for AudioCodes MP-252
+
+Signed-off-by: Daniel Golle <[email protected]>
+
+diff --git a/board/audiocodes/acmp252/Makefile b/board/audiocodes/acmp252/Makefile
+new file mode 100644
+index 0000000..3a547c2
+--- /dev/null
++++ b/board/audiocodes/acmp252/Makefile
+@@ -0,0 +1,27 @@
++#
++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++include $(TOPDIR)/config.mk
++
++LIB	= $(obj)lib$(BOARD).o
++
++COBJS	= $(BOARD).o
++
++SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS	:= $(addprefix $(obj),$(COBJS))
++SOBJS	:= $(addprefix $(obj),$(SOBJS))
++
++$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
++	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/board/audiocodes/acmp252/acmp252.c b/board/audiocodes/acmp252/acmp252.c
+new file mode 100644
+index 0000000..3368506
+--- /dev/null
++++ b/board/audiocodes/acmp252/acmp252.c
+@@ -0,0 +1,66 @@
++/*
++ * Copyright (C) 2013 Daniel Golle <[email protected]>
++ * Copyright (C) 2011 Luka Perkov <[email protected]>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <common.h>
++#include <switch.h>
++#include <asm/gpio.h>
++#include <asm/lantiq/eth.h>
++#include <asm/lantiq/reset.h>
++#include <asm/lantiq/chipid.h>
++
++static void gpio_init(void)
++{
++	/* Activate reset line of ADM6996I switch */
++	gpio_direction_output(19, 0);
++}
++
++int board_early_init_f(void)
++{
++	gpio_init();
++
++	return 0;
++}
++
++int checkboard(void)
++{
++	puts("Board: " CONFIG_BOARD_NAME "\n");
++	ltq_chip_print_info();
++
++	return 0;
++}
++
++static const struct ltq_eth_port_config eth_port_config[] = {
++	/* MAC0: Lantiq ADM6996I switch */
++	{ 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
++};
++
++static const struct ltq_eth_board_config eth_board_config = {
++	.ports = eth_port_config,
++	.num_ports = ARRAY_SIZE(eth_port_config),
++};
++
++int board_eth_init(bd_t *bis)
++{
++	return ltq_eth_initialize(&eth_board_config);
++}
++
++static struct switch_device adm6996i_dev = {
++	.name = "adm6996i",
++	.cpu_port = 5,
++	.port_mask = 0xF,
++};
++
++int board_switch_init(void)
++{
++	/* Deactivate reset line of ADM6996I switch */
++	gpio_set_value(19, 1);
++
++	/* ADM6996I needs some time to come out of reset */
++	__udelay(50000);
++
++	return switch_device_register(&adm6996i_dev);
++}
+diff --git a/board/audiocodes/acmp252/config.mk b/board/audiocodes/acmp252/config.mk
+new file mode 100644
+index 0000000..9d8953b
+--- /dev/null
++++ b/board/audiocodes/acmp252/config.mk
+@@ -0,0 +1,7 @@
++#
++# Copyright (C) 2011-2013 Daniel Schwierzeck, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
+diff --git a/board/audiocodes/acmp252/ddr_settings.h b/board/audiocodes/acmp252/ddr_settings.h
+new file mode 100644
+index 0000000..d0b4f20
+--- /dev/null
++++ b/board/audiocodes/acmp252/ddr_settings.h
+@@ -0,0 +1,55 @@
++/*
++ * Copyright (C) 2011-2013 Luka Perkov <[email protected]>
++ *
++ * This file has been generated with lantiq_ram_extract_magic.awk script.
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#define MC_DC00_VALUE	0x1B1B
++#define MC_DC01_VALUE	0x0
++#define MC_DC02_VALUE	0x0
++#define MC_DC03_VALUE	0x0
++#define MC_DC04_VALUE	0x0
++#define MC_DC05_VALUE	0x200
++#define MC_DC06_VALUE	0x605
++#define MC_DC07_VALUE	0x403
++#define MC_DC08_VALUE	0x103
++#define MC_DC09_VALUE	0x80B
++#define MC_DC10_VALUE	0x304
++#define MC_DC11_VALUE	0xD03
++#define MC_DC12_VALUE	0x2C8
++#define MC_DC13_VALUE	0x1
++#define MC_DC14_VALUE	0x0
++#define MC_DC15_VALUE	0x13C
++#define MC_DC16_VALUE	0xC800
++#define MC_DC17_VALUE	0xD
++#define MC_DC18_VALUE	0x402
++#define MC_DC19_VALUE	0x200
++#define MC_DC20_VALUE	0xA03
++#define MC_DC21_VALUE	0x1700
++#define MC_DC22_VALUE	0x1717
++#define MC_DC23_VALUE	0x0
++#define MC_DC24_VALUE	0x5C
++#define MC_DC25_VALUE	0x0
++#define MC_DC26_VALUE	0x0
++#define MC_DC27_VALUE	0x0
++#define MC_DC28_VALUE	0x510
++#define MC_DC29_VALUE	0x2D93
++#define MC_DC30_VALUE	0x8300
++#define MC_DC31_VALUE	0x0
++#define MC_DC32_VALUE	0x0
++#define MC_DC33_VALUE	0x0
++#define MC_DC34_VALUE	0x0
++#define MC_DC35_VALUE	0x0
++#define MC_DC36_VALUE	0x0
++#define MC_DC37_VALUE	0x0
++#define MC_DC38_VALUE	0x0
++#define MC_DC39_VALUE	0x0
++#define MC_DC40_VALUE	0x0
++#define MC_DC41_VALUE	0x0
++#define MC_DC42_VALUE	0x0
++#define MC_DC43_VALUE	0x0
++#define MC_DC44_VALUE	0x0
++#define MC_DC45_VALUE	0x500
++#define MC_DC46_VALUE	0x0
+diff --git a/boards.cfg b/boards.cfg
+index e832423..9f407b8 100644
+--- a/boards.cfg
++++ b/boards.cfg
+@@ -508,6 +508,8 @@ Active  mips        mips32         danube      arcadyan        arv4519pw
+ Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_brn                        arv7518pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <[email protected]>
+ Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_nor                        arv7518pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <[email protected]>
+ Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_ram                        arv7518pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <[email protected]>
++Active  mips        mips32         danube      audiocodes      acmp252             acmp252_nor                          acmp252:SYS_BOOT_NOR                                                                                                              Daniel Golle <[email protected]>
++Active  mips        mips32         danube      audiocodes      acmp252             acmp252_ram                          acmp252:SYS_BOOT_RAM                                                                                                              Daniel Golle <[email protected]>
+ Active  mips        mips32         danube      lantiq          easy50712           easy50712_nor                        easy50712:SYS_BOOT_NOR                                                                                                            Daniel Schwierzeck <[email protected]>
+ Active  mips        mips32         danube      lantiq          easy50712           easy50712_norspl                     easy50712:SYS_BOOT_NORSPL                                                                                                         Daniel Schwierzeck <[email protected]>
+ Active  mips        mips32         danube      lantiq          easy50712           easy50712_ram                        easy50712:SYS_BOOT_RAM                                                                                                            Daniel Schwierzeck <[email protected]>
+diff --git a/include/configs/acmp252.h b/include/configs/acmp252.h
+new file mode 100644
+index 0000000..2c9ab19
+--- /dev/null
++++ b/include/configs/acmp252.h
+@@ -0,0 +1,60 @@
++/*
++ * Copyright (C) 2013 Daniel Golle <[email protected]>
++ * Copyright (C) 2011 Luka Perkov <[email protected]>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#define CONFIG_MACH_TYPE	"ACMP252"
++#define CONFIG_IDENT_STRING	" "CONFIG_MACH_TYPE
++#define CONFIG_BOARD_NAME	"AudioCodes MP-252"
++
++/* Configure SoC */
++#define CONFIG_LTQ_SUPPORT_UART		/* Enable ASC and UART */
++
++#define CONFIG_LTQ_SUPPORT_ETHERNET	/* Enable ethernet */
++
++#define CONFIG_LTQ_SUPPORT_NOR_FLASH	/* Have a parallel NOR flash */
++
++/* Switch devices */
++#define CONFIG_SWITCH_MULTI
++#define CONFIG_SWITCH_ADM6996I
++
++/* Environment */
++#if defined(CONFIG_SYS_BOOT_NOR)
++#define CONFIG_ENV_IS_IN_FLASH
++#define CONFIG_ENV_OVERWRITE
++#define CONFIG_ENV_OFFSET		(256 * 1024)
++#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
++#else
++#define CONFIG_ENV_IS_NOWHERE
++#endif
++
++#define CONFIG_ENV_SIZE			(8 * 1024)
++#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
++
++/* Console */
++#define CONFIG_LTQ_ADVANCED_CONSOLE
++#define CONFIG_BAUDRATE			115200
++#define CONFIG_CONSOLE_ASC		1
++#define CONFIG_CONSOLE_DEV		"ttyLTQ1"
++
++/* Pull in default board configs for Lantiq XWAY Danube */
++#include <asm/lantiq/config.h>
++#include <asm/arch/config.h>
++
++/* Pull in default OpenWrt configs for Lantiq SoC */
++#include "openwrt-lantiq-common.h"
++
++#define CONFIG_ENV_UPDATE_UBOOT_NOR		\
++	"update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
++
++#define CONFIG_EXTRA_ENV_SETTINGS	\
++	CONFIG_ENV_LANTIQ_DEFAULTS	\
++	CONFIG_ENV_UPDATE_UBOOT_NOR	\
++	"kernel_addr=0xB0040000\0"
++
++#endif /* __CONFIG_H */
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0025-MIPS-add-board-support-for-AVM-FritzBox-3370.patch → package/boot/uboot-lantiq/patches/0029-MIPS-add-board-support-for-AVM-FritzBox-3370.patch

@@ -1,20 +1,22 @@
-From 51f04c00e831b49587f9f766ff1af67d2122feb2 Mon Sep 17 00:00:00 2001
+From 37a95ae4ba75407a26862ece6f48fa68aa6c5c78 Mon Sep 17 00:00:00 2001
 From: Daniel Schwierzeck <[email protected]>
-Date: Fri, 30 Nov 2012 18:09:47 +0100
+Date: Sat, 2 Mar 2013 23:34:00 +0100
 Subject: MIPS: add board support for AVM FritzBox 3370
 
 Signed-off-by: Daniel Schwierzeck <[email protected]>
 
+diff --git a/board/avm/fb3370/Makefile b/board/avm/fb3370/Makefile
+new file mode 100644
+index 0000000..e3d621e
 --- /dev/null
 +++ b/board/avm/fb3370/Makefile
-@@ -0,0 +1,29 @@
-+#
-+# This file is released under the terms of GPL v2 and any later version.
-+# See the file COPYING in the root directory of the source tree for details.
+@@ -0,0 +1,28 @@
 +#
 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, [email protected]
 +# Copyright (C) 2011 Daniel Schwierzeck, [email protected]
 +#
++# SPDX-License-Identifier:	GPL-2.0+
++#
 +
 +include $(TOPDIR)/config.mk
 +
@@ -37,26 +39,30 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +sinclude $(obj).depend
 +
 +#########################################################################
+diff --git a/board/avm/fb3370/config.mk b/board/avm/fb3370/config.mk
+new file mode 100644
+index 0000000..4dcfd05
 --- /dev/null
 +++ b/board/avm/fb3370/config.mk
-@@ -0,0 +1,8 @@
-+#
-+# This file is released under the terms of GPL v2 and any later version.
-+# See the file COPYING in the root directory of the source tree for details.
+@@ -0,0 +1,7 @@
 +#
 +# Copyright (C) 2011 Daniel Schwierzeck, [email protected]
 +#
++# SPDX-License-Identifier:	GPL-2.0+
++#
 +
 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
+diff --git a/board/avm/fb3370/ddr_settings.h b/board/avm/fb3370/ddr_settings.h
+new file mode 100644
+index 0000000..307c084
 --- /dev/null
 +++ b/board/avm/fb3370/ddr_settings.h
-@@ -0,0 +1,70 @@
+@@ -0,0 +1,69 @@
 +/*
-+ * This file is released under the terms of GPL v2 and any later version.
-+ * See the file COPYING in the root directory of the source tree for details.
-+ *
 + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
 + * Copyright (C) 2011 Daniel Schwierzeck, [email protected]
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#define	MC_CCR00_VALUE	0x101
@@ -100,8 +106,8 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +#define	MC_CCR38_VALUE	0x0
 +#define	MC_CCR39_VALUE	0x141F04
 +#define	MC_CCR40_VALUE	0x142704
-+#define	MC_CCR41_VALUE	0x141b42
-+#define	MC_CCR42_VALUE	0x141b42
++#define	MC_CCR41_VALUE	0x141B42
++#define	MC_CCR42_VALUE	0x141B42
 +#define	MC_CCR43_VALUE	0x566504
 +#define	MC_CCR44_VALUE	0x566504
 +#define	MC_CCR45_VALUE	0x565F17
@@ -121,14 +127,16 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +#define	MC_CCR59_VALUE	0x7800301
 +#define	MC_CCR60_VALUE	0x7800301
 +#define	MC_CCR61_VALUE	0x4
+diff --git a/board/avm/fb3370/fb3370.c b/board/avm/fb3370/fb3370.c
+new file mode 100644
+index 0000000..ff44c68
 --- /dev/null
 +++ b/board/avm/fb3370/fb3370.c
-@@ -0,0 +1,139 @@
+@@ -0,0 +1,138 @@
 +/*
-+ * This file is released under the terms of GPL v2 and any later version.
-+ * See the file COPYING in the root directory of the source tree for details.
-+ *
 + * Copyright (C) 2011 Daniel Schwierzeck, [email protected]
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <common.h>
@@ -263,26 +271,30 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +		break;
 +	}
 +}
+diff --git a/boards.cfg b/boards.cfg
+index 9f407b8..ea5c4f9 100644
 --- a/boards.cfg
 +++ b/boards.cfg
-@@ -451,6 +451,9 @@ incaip                       mips
- incaip_100MHz                mips        mips32      incaip              -              incaip      incaip:CPU_CLOCK_RATE=100000000
- incaip_133MHz                mips        mips32      incaip              -              incaip      incaip:CPU_CLOCK_RATE=133000000
- incaip_150MHz                mips        mips32      incaip              -              incaip      incaip:CPU_CLOCK_RATE=150000000
-+fb3370_ram                   mips        mips32      fb3370              avm            vrx200      fb3370:SYS_BOOT_RAM
-+fb3370_eva                   mips        mips32      fb3370              avm            vrx200      fb3370:SYS_BOOT_EVA
-+fb3370_sfspl                 mips        mips32      fb3370              avm            vrx200      fb3370:SYS_BOOT_SFSPL
- easy80920_nor                mips        mips32      easy80920           lantiq         vrx200      easy80920:SYS_BOOT_NOR
- easy80920_norspl             mips        mips32      easy80920           lantiq         vrx200      easy80920:SYS_BOOT_NORSPL
- easy80920_ram                mips        mips32      easy80920           lantiq         vrx200      easy80920:SYS_BOOT_RAM
+@@ -517,6 +517,9 @@ Active  mips        mips32         incaip      -               incaip
+ Active  mips        mips32         incaip      -               incaip              incaip_100MHz                        incaip:CPU_CLOCK_RATE=100000000                                                                                                   Wolfgang Denk <[email protected]>
+ Active  mips        mips32         incaip      -               incaip              incaip_133MHz                        incaip:CPU_CLOCK_RATE=133000000                                                                                                   Wolfgang Denk <[email protected]>
+ Active  mips        mips32         incaip      -               incaip              incaip_150MHz                        incaip:CPU_CLOCK_RATE=150000000                                                                                                   Wolfgang Denk <[email protected]>
++Active  mips        mips32         vrx200      avm             fb3370              fb3370_eva                           fb3370:SYS_BOOT_EVA                                                                                                               Daniel Schwierzeck <[email protected]>
++Active  mips        mips32         vrx200      avm             fb3370              fb3370_ram                           fb3370:SYS_BOOT_RAM                                                                                                               Daniel Schwierzeck <[email protected]>
++Active  mips        mips32         vrx200      avm             fb3370              fb3370_sfspl                         fb3370:SYS_BOOT_SFSPL                                                                                                             Daniel Schwierzeck <[email protected]>
+ Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_nandspl                    easy80920:SYS_BOOT_NANDSPL                                                                                                        Daniel Schwierzeck <[email protected]>
+ Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_nor                        easy80920:SYS_BOOT_NOR                                                                                                            Daniel Schwierzeck <[email protected]>
+ Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_norspl                     easy80920:SYS_BOOT_NORSPL                                                                                                         Daniel Schwierzeck <[email protected]>
+diff --git a/include/configs/fb3370.h b/include/configs/fb3370.h
+new file mode 100644
+index 0000000..8ae1373
 --- /dev/null
 +++ b/include/configs/fb3370.h
-@@ -0,0 +1,75 @@
+@@ -0,0 +1,78 @@
 +/*
-+ * This file is released under the terms of GPL v2 and any later version.
-+ * See the file COPYING in the root directory of the source tree for details.
++ * Copyright (C) 2011-2013 Daniel Schwierzeck, [email protected]
 + *
-+ * Copyright (C) 2011 Daniel Schwierzeck, [email protected]
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#ifndef __CONFIG_H
@@ -293,24 +305,24 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +#define CONFIG_BOARD_NAME	"AVM FritzBox 3370"
 +
 +/* Configure SoC */
-+#define CONFIG_LTQ_SUPPORT_UART		/* Enable ASC and UART */
++#define CONFIG_LTQ_SUPPORT_UART			/* Enable ASC and UART */
 +
-+#define CONFIG_LTQ_SUPPORT_ETHERNET	/* Enable ethernet */
++#define CONFIG_LTQ_SUPPORT_ETHERNET		/* Enable ethernet */
 +
 +#define CONFIG_LTQ_SUPPORT_SPI_FLASH
-+#define CONFIG_SPI_FLASH_MACRONIX	/* Have a MX29LV620 serial flash */
++#define CONFIG_SPI_FLASH_MACRONIX		/* Have a MX29LV620 serial flash */
 +
 +#define CONFIG_LTQ_SUPPORT_NAND_FLASH
 +
 +#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH	/* Build SPI flash SPL */
++#define CONFIG_LTQ_SPL_COMP_LZO			/* Compress SPL with LZO */
++#define CONFIG_LTQ_SPL_CONSOLE			/* Enable SPL console */
++
 +#define CONFIG_SPL_SPI_BUS		0
 +#define CONFIG_SPL_SPI_CS		4
 +#define CONFIG_SPL_SPI_MAX_HZ		25000000
 +#define CONFIG_SPL_SPI_MODE		0
 +
-+#define CONFIG_LTQ_SPL_COMP_LZO
-+#define CONFIG_LTQ_SPL_CONSOLE
-+
 +#define CONFIG_SYS_DRAM_PROBE
 +
 +/* Environment */
@@ -329,22 +341,26 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +#endif
 +
 +#define CONFIG_ENV_SIZE			(8 * 1024)
-+
 +#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
 +
++#if defined(CONFIG_SYS_BOOT_EVA)
++#define CONFIG_SYS_TEXT_BASE		0x80100000
++#define CONFIG_SKIP_LOWLEVEL_INIT
++#endif
++
 +/* Console */
 +#define CONFIG_LTQ_ADVANCED_CONSOLE
 +#define CONFIG_BAUDRATE			115200
 +#define CONFIG_CONSOLE_ASC		1
 +#define CONFIG_CONSOLE_DEV		"ttyLTQ1"
 +
-+/* Commands */
-+#define CONFIG_CMD_PING
-+
 +/* Pull in default board configs for Lantiq XWAY VRX200 */
 +#include <asm/lantiq/config.h>
 +#include <asm/arch/config.h>
 +
++/* Pull in default OpenWrt configs for Lantiq SoC */
++#include "openwrt-lantiq-common.h"
++
 +#define CONFIG_ENV_UPDATE_UBOOT_SF					\
 +	"update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0"
 +
@@ -353,3 +369,6 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +	CONFIG_ENV_UPDATE_UBOOT_SF
 +
 +#endif /* __CONFIG_H */
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0026-MIPS-add-board-support-for-Gigaset-SX76X.patch → package/boot/uboot-lantiq/patches/0030-MIPS-add-board-support-for-Gigaset-SX76X.patch

@@ -1,20 +1,21 @@
-From 66b56aa3a4810f10e0b0c77bb87279a8d64b566b Mon Sep 17 00:00:00 2001
+From 9e9dec563e4d061e7b34d2d59a89eb05c60f43a7 Mon Sep 17 00:00:00 2001
 From: Luka Perkov <[email protected]>
-Date: Fri, 16 Dec 2011 11:55:45 +0100
+Date: Sat, 2 Mar 2013 23:34:00 +0100
 Subject: MIPS: add board support for Gigaset SX76X
 
 Signed-off-by: Luka Perkov <[email protected]>
 Signed-off-by: Daniel Schwierzeck <[email protected]>
 
+diff --git a/board/gigaset/sx76x/Makefile b/board/gigaset/sx76x/Makefile
+new file mode 100644
+index 0000000..3a547c2
 --- /dev/null
 +++ b/board/gigaset/sx76x/Makefile
-@@ -0,0 +1,29 @@
-+#
-+# This file is released under the terms of GPL v2 and any later version.
-+# See the file COPYING in the root directory of the source tree for details.
+@@ -0,0 +1,27 @@
 +#
 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, [email protected]
-+# Copyright (C) 2011 Daniel Schwierzeck, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
 +#
 +
 +include $(TOPDIR)/config.mk
@@ -38,27 +39,31 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +sinclude $(obj).depend
 +
 +#########################################################################
+diff --git a/board/gigaset/sx76x/config.mk b/board/gigaset/sx76x/config.mk
+new file mode 100644
+index 0000000..9d8953b
 --- /dev/null
 +++ b/board/gigaset/sx76x/config.mk
-@@ -0,0 +1,8 @@
+@@ -0,0 +1,7 @@
 +#
-+# This file is released under the terms of GPL v2 and any later version.
-+# See the file COPYING in the root directory of the source tree for details.
++# Copyright (C) 2011-2013 Daniel Schwierzeck, [email protected]
 +#
-+# Copyright (C) 2011 Daniel Schwierzeck, [email protected]
++# SPDX-License-Identifier:	GPL-2.0+
 +#
 +
 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
+diff --git a/board/gigaset/sx76x/ddr_settings.h b/board/gigaset/sx76x/ddr_settings.h
+new file mode 100644
+index 0000000..13cd81b
 --- /dev/null
 +++ b/board/gigaset/sx76x/ddr_settings.h
-@@ -0,0 +1,56 @@
+@@ -0,0 +1,55 @@
 +/*
-+ * This file is released under the terms of GPL v2 and any later version.
-+ * See the file COPYING in the root directory of the source tree for details.
++ * Copyright (C) 2011-2013 Luka Perkov <[email protected]>
 + *
-+ * generated with lantiq_ram_extract_magic.awk
++ * This file has been generated with lantiq_ram_extract_magic.awk script.
 + *
-+ * Copyright (C) 2011 Luka Perkov <[email protected]>
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#define MC_DC00_VALUE	0x1B1B
@@ -108,14 +113,16 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +#define MC_DC44_VALUE	0x0
 +#define MC_DC45_VALUE	0x500
 +#define MC_DC46_VALUE	0x0
+diff --git a/board/gigaset/sx76x/sx76x.c b/board/gigaset/sx76x/sx76x.c
+new file mode 100644
+index 0000000..71996a1
 --- /dev/null
 +++ b/board/gigaset/sx76x/sx76x.c
-@@ -0,0 +1,66 @@
+@@ -0,0 +1,65 @@
 +/*
-+ * This file is released under the terms of GPL v2 and any later version.
-+ * See the file COPYING in the root directory of the source tree for details.
-+ *
 + * Copyright (C) 2011 Luka Perkov <[email protected]>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <common.h>
@@ -177,32 +184,36 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +
 +	return switch_device_register(&adm6996i_dev);
 +}
+diff --git a/boards.cfg b/boards.cfg
+index ea5c4f9..2163cdb 100644
 --- a/boards.cfg
 +++ b/boards.cfg
-@@ -447,6 +447,8 @@ pb1000                       mips
- easy50712_nor                mips        mips32      easy50712           lantiq         danube      easy50712:SYS_BOOT_NOR
- easy50712_norspl             mips        mips32      easy50712           lantiq         danube      easy50712:SYS_BOOT_NORSPL
- easy50712_ram                mips        mips32      easy50712           lantiq         danube      easy50712:SYS_BOOT_RAM
-+gigasx76x_nor                mips        mips32      sx76x               gigaset        danube      sx76x:SYS_BOOT_NOR
-+gigasx76x_ram                mips        mips32      sx76x               gigaset        danube      sx76x:SYS_BOOT_RAM
- incaip                       mips        mips32      incaip              -              incaip
- incaip_100MHz                mips        mips32      incaip              -              incaip      incaip:CPU_CLOCK_RATE=100000000
- incaip_133MHz                mips        mips32      incaip              -              incaip      incaip:CPU_CLOCK_RATE=133000000
+@@ -510,6 +510,8 @@ Active  mips        mips32         danube      arcadyan        arv7518pw
+ Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_ram                        arv7518pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <[email protected]>
+ Active  mips        mips32         danube      audiocodes      acmp252             acmp252_nor                          acmp252:SYS_BOOT_NOR                                                                                                              Daniel Golle <[email protected]>
+ Active  mips        mips32         danube      audiocodes      acmp252             acmp252_ram                          acmp252:SYS_BOOT_RAM                                                                                                              Daniel Golle <[email protected]>
++Active  mips        mips32         danube      gigaset         sx76x               gigasx76x_nor                        sx76x:SYS_BOOT_NOR                                                                                                                Luka Perkov <[email protected]>
++Active  mips        mips32         danube      gigaset         sx76x               gigasx76x_ram                        sx76x:SYS_BOOT_RAM                                                                                                                Luka Perkov <[email protected]>
+ Active  mips        mips32         danube      lantiq          easy50712           easy50712_nor                        easy50712:SYS_BOOT_NOR                                                                                                            Daniel Schwierzeck <[email protected]>
+ Active  mips        mips32         danube      lantiq          easy50712           easy50712_norspl                     easy50712:SYS_BOOT_NORSPL                                                                                                         Daniel Schwierzeck <[email protected]>
+ Active  mips        mips32         danube      lantiq          easy50712           easy50712_ram                        easy50712:SYS_BOOT_RAM                                                                                                            Daniel Schwierzeck <[email protected]>
+diff --git a/include/configs/sx76x.h b/include/configs/sx76x.h
+new file mode 100644
+index 0000000..236851e
 --- /dev/null
 +++ b/include/configs/sx76x.h
-@@ -0,0 +1,71 @@
+@@ -0,0 +1,59 @@
 +/*
-+ * This file is released under the terms of GPL v2 and any later version.
-+ * See the file COPYING in the root directory of the source tree for details.
++ * Copyright (C) 2011-2013 Luka Perkov <[email protected]>
 + *
-+ * Copyright (C) 2011 Luka Perkov <[email protected]>
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#ifndef __CONFIG_H
 +#define __CONFIG_H
 +
 +#define CONFIG_MACH_TYPE	"GIGASX76X"
-+#define CONFIG_IDENT_STRING	" sx76x"
++#define CONFIG_IDENT_STRING	" "CONFIG_MACH_TYPE
 +#define CONFIG_BOARD_NAME	"Gigaset sx76x"
 +
 +/* Configure SoC */
@@ -221,13 +232,12 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +#define CONFIG_ENV_IS_IN_FLASH
 +#define CONFIG_ENV_OVERWRITE
 +#define CONFIG_ENV_OFFSET		(256 * 1024)
-+#define CONFIG_ENV_SIZE			(8 * 1024)
 +#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
 +#else
 +#define CONFIG_ENV_IS_NOWHERE
-+#define CONFIG_ENV_SIZE			(2 * 1024)
 +#endif
 +
++#define CONFIG_ENV_SIZE			(8 * 1024)
 +#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
 +
 +/* Console */
@@ -236,22 +246,12 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +#define CONFIG_CONSOLE_ASC		1
 +#define CONFIG_CONSOLE_DEV		"ttyLTQ1"
 +
-+/* Commands */
-+#define CONFIG_CMD_PING
-+
 +/* Pull in default board configs for Lantiq XWAY Danube */
 +#include <asm/lantiq/config.h>
 +#include <asm/arch/config.h>
 +
-+/* Compression */
-+#define CONFIG_LZMA
-+
-+/* Auto boot */
-+#define CONFIG_BOOTDELAY		2
-+
-+/* Environment configuration */
-+#define CONFIG_BOOTCOMMAND			\
-+	"run addeth; bootm ${kernel_addr}"
++/* Pull in default OpenWrt configs for Lantiq SoC */
++#include "openwrt-lantiq-common.h"
 +
 +#define CONFIG_ENV_UPDATE_UBOOT_NOR		\
 +	"update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
@@ -262,3 +262,6 @@ Signed-off-by: Daniel Schwierzeck <[email protected]>
 +	"kernel_addr=0xB0040000\0"
 +
 +#endif /* __CONFIG_H */
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0031-MIPS-add-board-support-for-ZTE-ZXHN-H367N.patch

@@ -0,0 +1,327 @@
+From 0597056e2ba19ea783ef5c3d14c75c4722740e48 Mon Sep 17 00:00:00 2001
+From: Luka Perkov <[email protected]>
+Date: Sun, 10 Mar 2013 17:59:56 +0100
+Subject: MIPS: add board support for ZTE ZXHN H367N
+
+Signed-off-by: Luka Perkov <[email protected]>
+
+diff --git a/board/zte/zxhnh367n/Makefile b/board/zte/zxhnh367n/Makefile
+new file mode 100644
+index 0000000..3a547c2
+--- /dev/null
++++ b/board/zte/zxhnh367n/Makefile
+@@ -0,0 +1,27 @@
++#
++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++include $(TOPDIR)/config.mk
++
++LIB	= $(obj)lib$(BOARD).o
++
++COBJS	= $(BOARD).o
++
++SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS	:= $(addprefix $(obj),$(COBJS))
++SOBJS	:= $(addprefix $(obj),$(SOBJS))
++
++$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
++	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/board/zte/zxhnh367n/config.mk b/board/zte/zxhnh367n/config.mk
+new file mode 100644
+index 0000000..9d33739
+--- /dev/null
++++ b/board/zte/zxhnh367n/config.mk
+@@ -0,0 +1,7 @@
++#
++# Copyright (C) 2012-2013 Daniel Schwierzeck, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
+diff --git a/board/zte/zxhnh367n/ddr_settings.h b/board/zte/zxhnh367n/ddr_settings.h
+new file mode 100644
+index 0000000..b3f81de
+--- /dev/null
++++ b/board/zte/zxhnh367n/ddr_settings.h
+@@ -0,0 +1,70 @@
++/*
++ * Copyright (C) 2013 Luka Perkov <[email protected]>
++ *
++ * The values have been extracted from original ZTE U-Boot.
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#define	MC_CCR00_VALUE	0x101
++#define	MC_CCR01_VALUE	0x1000101
++#define	MC_CCR02_VALUE	0x1010000
++#define	MC_CCR03_VALUE	0x100
++#define	MC_CCR04_VALUE	0x1000000
++#define	MC_CCR05_VALUE	0x1000101
++#define	MC_CCR06_VALUE	0x1000100
++#define	MC_CCR07_VALUE	0x1010000
++#define	MC_CCR08_VALUE	0x1000101
++#define	MC_CCR09_VALUE	0x0
++#define	MC_CCR10_VALUE	0x2000100
++#define	MC_CCR11_VALUE	0x2000401
++#define	MC_CCR12_VALUE	0x30000
++#define	MC_CCR13_VALUE	0x202
++#define	MC_CCR14_VALUE	0x7080A0F
++#define	MC_CCR15_VALUE	0x2040F
++#define	MC_CCR16_VALUE	0x40000
++#define	MC_CCR17_VALUE	0x70102
++#define	MC_CCR18_VALUE	0x4020002
++#define	MC_CCR19_VALUE	0x30302
++#define	MC_CCR20_VALUE	0x8000700
++#define	MC_CCR21_VALUE	0x40F020A
++#define	MC_CCR22_VALUE	0x0
++#define	MC_CCR23_VALUE	0xC020000
++#define	MC_CCR24_VALUE	0x4401B04
++#define	MC_CCR25_VALUE	0x0
++#define	MC_CCR26_VALUE	0x0
++#define	MC_CCR27_VALUE	0x6420000
++#define	MC_CCR28_VALUE	0x0
++#define	MC_CCR29_VALUE	0x0
++#define	MC_CCR30_VALUE	0x798
++#define	MC_CCR31_VALUE	0x0
++#define	MC_CCR32_VALUE	0x0
++#define	MC_CCR33_VALUE	0x650000
++#define	MC_CCR34_VALUE	0x200C8
++#define	MC_CCR35_VALUE	0x1D445D
++#define	MC_CCR36_VALUE	0xC8
++#define	MC_CCR37_VALUE	0xC351
++#define	MC_CCR38_VALUE	0x0
++#define	MC_CCR39_VALUE	0x141F04
++#define	MC_CCR40_VALUE	0x142704
++#define	MC_CCR41_VALUE	0x141B42
++#define	MC_CCR42_VALUE	0x141B42
++#define	MC_CCR43_VALUE	0x566504
++#define	MC_CCR44_VALUE	0x566504
++#define	MC_CCR45_VALUE	0x565F17
++#define	MC_CCR46_VALUE	0x565F17
++#define	MC_CCR47_VALUE	0x0
++#define	MC_CCR48_VALUE	0x0
++#define	MC_CCR49_VALUE	0x0
++#define	MC_CCR50_VALUE	0x0
++#define	MC_CCR51_VALUE	0x0
++#define	MC_CCR52_VALUE	0x133
++#define	MC_CCR53_VALUE	0xF3014B27
++#define	MC_CCR54_VALUE	0xF3014B27
++#define	MC_CCR55_VALUE	0xF3014B27
++#define	MC_CCR56_VALUE	0xF3014B27
++#define	MC_CCR57_VALUE	0x7800301
++#define	MC_CCR58_VALUE	0x7800301
++#define	MC_CCR59_VALUE	0x7800301
++#define	MC_CCR60_VALUE	0x7800301
++#define	MC_CCR61_VALUE	0x4
+diff --git a/board/zte/zxhnh367n/zxhnh367n.c b/board/zte/zxhnh367n/zxhnh367n.c
+new file mode 100644
+index 0000000..f64f105
+--- /dev/null
++++ b/board/zte/zxhnh367n/zxhnh367n.c
+@@ -0,0 +1,97 @@
++/*
++ * Copyright (C) 2013 Luka Perkov <[email protected]>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/gpio.h>
++#include <asm/lantiq/eth.h>
++#include <asm/lantiq/chipid.h>
++#include <asm/lantiq/cpu.h>
++#include <asm/arch/gphy.h>
++
++#if defined(CONFIG_SPL_BUILD)
++#define do_gpio_init	1
++#define do_pll_init	1
++#define do_dcdc_init	0
++#elif defined(CONFIG_SYS_BOOT_RAM)
++#define do_gpio_init	1
++#define do_pll_init	0
++#define do_dcdc_init	1
++#else
++#define do_gpio_init	0
++#define do_pll_init	0
++#define do_dcdc_init	1
++#endif
++
++static void gpio_init(void)
++{
++	/* EBU.FL_CS1 as output for NAND CE */
++	gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
++	/* EBU.FL_A23 as output for NAND CLE */
++	gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
++	/* EBU.FL_A24 as output for NAND ALE */
++	gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
++	/* GPIO 3.0 as input for NAND Ready Busy */
++	gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
++	/* GPIO 3.1 as output for NAND Read */
++	gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
++}
++
++int board_early_init_f(void)
++{
++	if (do_gpio_init)
++		gpio_init();
++
++	if (do_pll_init)
++		ltq_pll_init();
++
++	if (do_dcdc_init)
++		ltq_dcdc_init(0x7F);
++
++	return 0;
++}
++
++int checkboard(void)
++{
++	puts("Board: " CONFIG_BOARD_NAME "\n");
++	ltq_chip_print_info();
++
++	return 0;
++}
++
++static const struct ltq_eth_port_config eth_port_config[] = {
++	/* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */
++	{ 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
++	/* GMAC1: unused */
++	{ 1, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
++	/* GMAC2: internal GPHY0 with 10/100 firmware for LAN port 1 */
++	{ 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
++	/* GMAC3: internal GPHY0 with 10/100 firmware for LAN port 2 */
++	{ 3, 0x12, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
++	/* GMAC4: internal GPHY1 with 10/100 firmware for LAN port 3 */
++	{ 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
++	/* GMAC5: internal GPHY1 with 10/100 firmware for LAN port 4 */
++	{ 5, 0x14, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
++};
++
++static const struct ltq_eth_board_config eth_board_config = {
++	.ports = eth_port_config,
++	.num_ports = ARRAY_SIZE(eth_port_config),
++};
++
++int board_eth_init(bd_t * bis)
++{
++	const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
++	const ulong fw_addr = 0x80FF0000;
++
++	ltq_gphy_phy22f_a2x_load(fw_addr);
++
++	ltq_cgu_gphy_clk_src(clk);
++
++	ltq_rcu_gphy_boot(0, fw_addr);
++	ltq_rcu_gphy_boot(1, fw_addr);
++
++	return ltq_eth_initialize(&eth_board_config);
++}
+diff --git a/boards.cfg b/boards.cfg
+index 2163cdb..4b18a26 100644
+--- a/boards.cfg
++++ b/boards.cfg
+@@ -527,6 +527,9 @@ Active  mips        mips32         vrx200      lantiq          easy80920
+ Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_norspl                     easy80920:SYS_BOOT_NORSPL                                                                                                         Daniel Schwierzeck <[email protected]>
+ Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_ram                        easy80920:SYS_BOOT_RAM                                                                                                            Daniel Schwierzeck <[email protected]>
+ Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_sfspl                      easy80920:SYS_BOOT_SFSPL                                                                                                          Daniel Schwierzeck <[email protected]>
++Active  mips        mips32         vrx200      zte             zxhnh367n           zxhnh367n_nandspl                    zxhnh367n:SYS_BOOT_NANDSPL                                                                                                        Luka Perkov <[email protected]>
++Active  mips        mips32         vrx200      zte             zxhnh367n           zxhnh367n_ram                        zxhnh367n:SYS_BOOT_RAM                                                                                                            Luka Perkov <[email protected]>
++Active  mips        mips32         vrx200      zte             zxhnh367n           zxhnh367n_zte                        zxhnh367n:SYS_BOOT_ZTE                                                                                                            Luka Perkov <[email protected]>
+ Active  mips        mips64         -           -               qemu-mips           qemu_mips64                          qemu-mips64:SYS_BIG_ENDIAN                                                                                                        -
+ Active  mips        mips64         -           -               qemu-mips           qemu_mips64el                        qemu-mips64:SYS_LITTLE_ENDIAN                                                                                                     -
+ Active  nds32       n1213          ag101       AndesTech       adp-ag101           adp-ag101                            -                                                                                                                                 Andes <[email protected]>
+diff --git a/include/configs/zxhnh367n.h b/include/configs/zxhnh367n.h
+new file mode 100644
+index 0000000..55d2e2a
+--- /dev/null
++++ b/include/configs/zxhnh367n.h
+@@ -0,0 +1,72 @@
++/*
++ * Copyright (C) 2013 Luka Perkov <[email protected]>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#define CONFIG_MACH_TYPE	"ZXHN H367N"
++#define CONFIG_IDENT_STRING	" "CONFIG_MACH_TYPE
++#define CONFIG_BOARD_NAME	"ZTE ZXHN H367N"
++
++/* Configure SoC */
++#define CONFIG_LTQ_SUPPORT_UART			/* Enable ASC and UART */
++
++#define CONFIG_LTQ_SUPPORT_ETHERNET		/* Enable ethernet */
++
++#define CONFIG_LTQ_SUPPORT_NAND_FLASH		/* Have a  NAND flash */
++
++#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH	/* Build NAND flash SPL */
++#define CONFIG_LTQ_SPL_COMP_LZO			/* Compress SPL with LZO */
++#define CONFIG_LTQ_SPL_CONSOLE			/* Enable SPL console */
++
++#define CONFIG_SYS_NAND_PAGE_COUNT	128
++#define CONFIG_SYS_NAND_PAGE_SIZE	2048
++#define CONFIG_SYS_NAND_OOBSIZE		64
++#define CONFIG_SYS_NAND_BLOCK_SIZE	(256 * 1024)
++#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
++#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x4000
++
++#define CONFIG_SYS_DRAM_PROBE
++
++/* Environment */
++#if defined(CONFIG_SYS_BOOT_NANDSPL)
++#define CONFIG_ENV_IS_IN_NAND
++#define CONFIG_ENV_OVERWRITE
++#define CONFIG_ENV_OFFSET		(256 * 1024)
++#define CONFIG_ENV_SECT_SIZE		(256 * 1024)
++#else
++#define CONFIG_ENV_IS_NOWHERE
++#endif
++
++#define CONFIG_ENV_SIZE			(8 * 1024)
++#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
++
++#if defined(CONFIG_SYS_BOOT_ZTE)
++#define CONFIG_SYS_TEXT_BASE		0x80800000
++#define CONFIG_SKIP_LOWLEVEL_INIT
++#endif
++
++/* Console */
++#define CONFIG_LTQ_ADVANCED_CONSOLE
++#define CONFIG_BAUDRATE			115200
++#define CONFIG_CONSOLE_ASC		1
++#define CONFIG_CONSOLE_DEV		"ttyLTQ1"
++
++/* Pull in default board configs for Lantiq XWAY VRX200 */
++#include <asm/lantiq/config.h>
++#include <asm/arch/config.h>
++
++/* Pull in default OpenWrt configs for Lantiq SoC */
++#include "openwrt-lantiq-common.h"
++
++#define CONFIG_ENV_UPDATE_UBOOT_NAND					\
++	"update-uboot-nand=run load-uboot-nandspl-lzo write-uboot-nand\0"
++
++#define CONFIG_EXTRA_ENV_SETTINGS	\
++	CONFIG_ENV_LANTIQ_DEFAULTS	\
++	CONFIG_ENV_UPDATE_UBOOT_NAND
++
++#endif /* __CONFIG_H */
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0032-MIPS-add-board-support-for-ZTE-ZXV10-H201L.patch

@@ -0,0 +1,271 @@
+From 2473526cf879ead429c6aa1fb7fb77ed3407baaa Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <[email protected]>
+Date: Sun, 9 Dec 2012 17:35:09 +0100
+Subject: MIPS: add board support for ZTE ZXV10 H201L
+
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/board/zte/zxv10h201l/Makefile b/board/zte/zxv10h201l/Makefile
+new file mode 100644
+index 0000000..3a547c2
+--- /dev/null
++++ b/board/zte/zxv10h201l/Makefile
+@@ -0,0 +1,27 @@
++#
++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++include $(TOPDIR)/config.mk
++
++LIB	= $(obj)lib$(BOARD).o
++
++COBJS	= $(BOARD).o
++
++SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS	:= $(addprefix $(obj),$(COBJS))
++SOBJS	:= $(addprefix $(obj),$(SOBJS))
++
++$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
++	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/board/zte/zxv10h201l/config.mk b/board/zte/zxv10h201l/config.mk
+new file mode 100644
+index 0000000..9d33739
+--- /dev/null
++++ b/board/zte/zxv10h201l/config.mk
+@@ -0,0 +1,7 @@
++#
++# Copyright (C) 2012-2013 Daniel Schwierzeck, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
+diff --git a/board/zte/zxv10h201l/ddr_settings.h b/board/zte/zxv10h201l/ddr_settings.h
+new file mode 100644
+index 0000000..8814957
+--- /dev/null
++++ b/board/zte/zxv10h201l/ddr_settings.h
+@@ -0,0 +1,55 @@
++/*
++ * Copyright (C) 2012 Daniel Schwierzeck, [email protected]
++ *
++ * The values have been extracted from original ZTE U-Boot.
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#define MC_DC00_VALUE	0x1B1B
++#define MC_DC01_VALUE	0x0
++#define MC_DC02_VALUE	0x0
++#define MC_DC03_VALUE	0x0
++#define MC_DC04_VALUE	0x0
++#define MC_DC05_VALUE	0x200
++#define MC_DC06_VALUE	0x307
++#define MC_DC07_VALUE	0x303
++#define MC_DC08_VALUE	0x103
++#define MC_DC09_VALUE	0x80B
++#define MC_DC10_VALUE	0x203
++#define MC_DC11_VALUE	0xE02
++#define MC_DC12_VALUE	0x2C8
++#define MC_DC13_VALUE	0x1
++#define MC_DC14_VALUE	0x0
++#define MC_DC15_VALUE	0x100
++#define MC_DC16_VALUE	0xC800
++#define MC_DC17_VALUE	0xF
++#define MC_DC18_VALUE	0x301
++#define MC_DC19_VALUE	0x200
++#define MC_DC20_VALUE	0xA04
++#define MC_DC21_VALUE	0x1600
++#define MC_DC22_VALUE	0x1616
++#define MC_DC23_VALUE	0x0
++#define MC_DC24_VALUE	0x5D
++#define MC_DC25_VALUE	0x0
++#define MC_DC26_VALUE	0x0
++#define MC_DC27_VALUE	0x0
++#define MC_DC28_VALUE	0x5FB
++#define MC_DC29_VALUE	0x35DF
++#define MC_DC30_VALUE	0x99E9
++#define MC_DC31_VALUE	0x0
++#define MC_DC32_VALUE	0x0
++#define MC_DC33_VALUE	0x0
++#define MC_DC34_VALUE	0x0
++#define MC_DC35_VALUE	0x0
++#define MC_DC36_VALUE	0x0
++#define MC_DC37_VALUE	0x0
++#define MC_DC38_VALUE	0x0
++#define MC_DC39_VALUE	0x0
++#define MC_DC40_VALUE	0x0
++#define MC_DC41_VALUE	0x0
++#define MC_DC42_VALUE	0x0
++#define MC_DC43_VALUE	0x0
++#define MC_DC44_VALUE	0x0
++#define MC_DC45_VALUE	0x600
++#define MC_DC46_VALUE	0x0
+diff --git a/board/zte/zxv10h201l/zxv10h201l.c b/board/zte/zxv10h201l/zxv10h201l.c
+new file mode 100644
+index 0000000..8218a9d
+--- /dev/null
++++ b/board/zte/zxv10h201l/zxv10h201l.c
+@@ -0,0 +1,51 @@
++/*
++ * Copyright (C) 2012 Daniel Schwierzeck, [email protected]
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <common.h>
++#include <switch.h>
++#include <asm/gpio.h>
++#include <asm/lantiq/eth.h>
++#include <asm/lantiq/reset.h>
++#include <asm/lantiq/chipid.h>
++
++int board_early_init_f(void)
++{
++	return 0;
++}
++
++int checkboard(void)
++{
++	puts("Board: " CONFIG_BOARD_NAME "\n");
++	ltq_chip_print_info();
++
++	return 0;
++}
++
++static const struct ltq_eth_port_config eth_port_config[] = {
++	/* MAC0: REALTEK RTL8306 switch */
++	{ 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
++};
++
++static const struct ltq_eth_board_config eth_board_config = {
++	.ports = eth_port_config,
++	.num_ports = ARRAY_SIZE(eth_port_config),
++};
++
++int board_eth_init(bd_t *bis)
++{
++	return ltq_eth_initialize(&eth_board_config);
++}
++
++static struct switch_device rtl8306_dev = {
++	.name = "rtl8306",
++	.cpu_port = 5,
++	.port_mask = 0xF,
++};
++
++int board_switch_init(void)
++{
++	return switch_device_register(&rtl8306_dev);
++}
+diff --git a/boards.cfg b/boards.cfg
+index 4b18a26..4362856 100644
+--- a/boards.cfg
++++ b/boards.cfg
+@@ -496,6 +496,9 @@ Active  mips        mips32         -           micronas        vct
+ Active  mips        mips32         -           micronas        vct                 vct_premium_onenand                  vct:VCT_PREMIUM,VCT_ONENAND                                                                                                       -
+ Active  mips        mips32         -           micronas        vct                 vct_premium_onenand_small            vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE                                                                                       -
+ Active  mips        mips32         -           micronas        vct                 vct_premium_small                    vct:VCT_PREMIUM,VCT_SMALL_IMAGE                                                                                                   -
++Active  mips        mips32         arx100      zte             zxv10h201l          zxv10h201l_nor                       zxv10h201l:SYS_BOOT_NOR                                                                                                           Luka Perkov <[email protected]>
++Active  mips        mips32         arx100      zte             zxv10h201l          zxv10h201l_ram                       zxv10h201l:SYS_BOOT_RAM                                                                                                           Luka Perkov <[email protected]>
++Active  mips        mips32         arx100      zte             zxv10h201l          zxv10h201l_zte                       zxv10h201l:SYS_BOOT_ZTE                                                                                                           Luka Perkov <[email protected]>
+ Active  mips        mips32         au1x00      -               dbau1x00            dbau1000                             dbau1x00:DBAU1000                                                                                                                 Thomas Lange <[email protected]>
+ Active  mips        mips32         au1x00      -               dbau1x00            dbau1100                             dbau1x00:DBAU1100                                                                                                                 Thomas Lange <[email protected]>
+ Active  mips        mips32         au1x00      -               dbau1x00            dbau1500                             dbau1x00:DBAU1500                                                                                                                 Thomas Lange <[email protected]>
+diff --git a/include/configs/zxv10h201l.h b/include/configs/zxv10h201l.h
+new file mode 100644
+index 0000000..bfe116d
+--- /dev/null
++++ b/include/configs/zxv10h201l.h
+@@ -0,0 +1,77 @@
++/*
++ * Copyright (C) 2011 Daniel Schwierzeck, [email protected]
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#define CONFIG_MACH_TYPE	"ZXV10 H201L"
++#define CONFIG_IDENT_STRING	" "CONFIG_MACH_TYPE
++#define CONFIG_BOARD_NAME	"ZTE ZXV10 H201L"
++
++/* Configure SoC */
++#define CONFIG_LTQ_SUPPORT_UART			/* Enable ASC and UART */
++
++#define CONFIG_LTQ_SUPPORT_ETHERNET		/* Enable ethernet */
++
++#define CONFIG_LTQ_SUPPORT_NOR_FLASH		/* Have a parallel NOR flash */
++
++#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH	/* Build NOR flash SPL */
++#define CONFIG_LTQ_SPL_COMP_LZO			/* Compress SPL with LZO */
++#define CONFIG_LTQ_SPL_CONSOLE			/* Enable SPL console */
++
++/* Switch devices */
++#define CONFIG_SWITCH_MULTI
++#define CONFIG_SWITCH_RTL8306
++
++/* Environment */
++#if defined(CONFIG_SYS_BOOT_NOR)
++#define CONFIG_ENV_IS_IN_FLASH
++#define CONFIG_ENV_OVERWRITE
++#define CONFIG_ENV_OFFSET		(256 * 1024)
++#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
++#elif defined(CONFIG_SYS_BOOT_NORSPL)
++#define CONFIG_ENV_IS_IN_FLASH
++#define CONFIG_ENV_OVERWRITE
++#define CONFIG_ENV_OFFSET		(128 * 1024)
++#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
++#else
++#define CONFIG_ENV_IS_NOWHERE
++#endif
++
++#define CONFIG_ENV_SIZE			(8 * 1024)
++#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
++
++#if defined(CONFIG_SYS_BOOT_ZTE)
++#define CONFIG_SYS_TEXT_BASE		0x80800000
++#define CONFIG_SKIP_LOWLEVEL_INIT
++#endif
++
++/* Console */
++#define CONFIG_LTQ_ADVANCED_CONSOLE
++#define CONFIG_BAUDRATE			115200
++#define CONFIG_CONSOLE_ASC		1
++#define CONFIG_CONSOLE_DEV		"ttyLTQ1"
++
++/* Pull in default board configs for Lantiq XWAY Danube */
++#include <asm/lantiq/config.h>
++#include <asm/arch/config.h>
++
++#if defined(CONFIG_SYS_BOOT_ZTE)
++#define CONFIG_SYS_TEXT_BASE		0x80800000
++#define CONFIG_SKIP_LOWLEVEL_INIT
++#endif
++
++/* Pull in default OpenWrt configs for Lantiq SoC */
++#include "openwrt-lantiq-common.h"
++
++#define CONFIG_ENV_UPDATE_UBOOT_NOR \
++	"update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0"
++
++#define CONFIG_EXTRA_ENV_SETTINGS	\
++	CONFIG_ENV_LANTIQ_DEFAULTS	\
++	CONFIG_ENV_UPDATE_UBOOT_NOR
++
++#endif /* __CONFIG_H */
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0033-MIPS-add-board-support-for-ZyXEL-P-661HNU-Fx.patch

@@ -0,0 +1,324 @@
+From a18f994f373db4467a4680f83ead997c8122908e Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <[email protected]>
+Date: Wed, 22 May 2013 17:48:08 +0200
+Subject: MIPS: add board support for ZyXEL P-661HNU-Fx
+
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/board/zyxel/p661hnufx/Makefile b/board/zyxel/p661hnufx/Makefile
+new file mode 100644
+index 0000000..3a547c2
+--- /dev/null
++++ b/board/zyxel/p661hnufx/Makefile
+@@ -0,0 +1,27 @@
++#
++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++include $(TOPDIR)/config.mk
++
++LIB	= $(obj)lib$(BOARD).o
++
++COBJS	= $(BOARD).o
++
++SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS	:= $(addprefix $(obj),$(COBJS))
++SOBJS	:= $(addprefix $(obj),$(SOBJS))
++
++$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
++	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/board/zyxel/p661hnufx/config.mk b/board/zyxel/p661hnufx/config.mk
+new file mode 100644
+index 0000000..9d33739
+--- /dev/null
++++ b/board/zyxel/p661hnufx/config.mk
+@@ -0,0 +1,7 @@
++#
++# Copyright (C) 2012-2013 Daniel Schwierzeck, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
+diff --git a/board/zyxel/p661hnufx/ddr_settings.h b/board/zyxel/p661hnufx/ddr_settings.h
+new file mode 100644
+index 0000000..83693b8
+--- /dev/null
++++ b/board/zyxel/p661hnufx/ddr_settings.h
+@@ -0,0 +1,55 @@
++/*
++ * Copyright (C) 2013 Daniel Schwierzeck, [email protected]
++ *
++ * The values have been extracted from original ZyXEL U-Boot.
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#define MC_DC00_VALUE	0x1B1B
++#define MC_DC01_VALUE	0x0
++#define MC_DC02_VALUE	0x0
++#define MC_DC03_VALUE	0x0
++#define MC_DC04_VALUE	0x0
++#define MC_DC05_VALUE	0x200
++#define MC_DC06_VALUE	0x307
++#define MC_DC07_VALUE	0x303
++#define MC_DC08_VALUE	0x103
++#define MC_DC09_VALUE	0x80B
++#define MC_DC10_VALUE	0x203
++#define MC_DC11_VALUE	0xE02
++#define MC_DC12_VALUE	0x2C8
++#define MC_DC13_VALUE	0x1
++#define MC_DC14_VALUE	0x0
++#define MC_DC15_VALUE	0x100
++#define MC_DC16_VALUE	0xC800
++#define MC_DC17_VALUE	0xF
++#define MC_DC18_VALUE	0x301
++#define MC_DC19_VALUE	0x200
++#define MC_DC20_VALUE	0xA04
++#define MC_DC21_VALUE	0x1600
++#define MC_DC22_VALUE	0x1616
++#define MC_DC23_VALUE	0x0
++#define MC_DC24_VALUE	0x5D
++#define MC_DC25_VALUE	0x0
++#define MC_DC26_VALUE	0x0
++#define MC_DC27_VALUE	0x0
++#define MC_DC28_VALUE	0x5FB
++#define MC_DC29_VALUE	0x35DF
++#define MC_DC30_VALUE	0x99E9
++#define MC_DC31_VALUE	0x0
++#define MC_DC32_VALUE	0x0
++#define MC_DC33_VALUE	0x0
++#define MC_DC34_VALUE	0x0
++#define MC_DC35_VALUE	0x0
++#define MC_DC36_VALUE	0x0
++#define MC_DC37_VALUE	0x0
++#define MC_DC38_VALUE	0x0
++#define MC_DC39_VALUE	0x0
++#define MC_DC40_VALUE	0x0
++#define MC_DC41_VALUE	0x0
++#define MC_DC42_VALUE	0x0
++#define MC_DC43_VALUE	0x0
++#define MC_DC44_VALUE	0x0
++#define MC_DC45_VALUE	0x600
++#define MC_DC46_VALUE	0x0
+diff --git a/board/zyxel/p661hnufx/p661hnufx.c b/board/zyxel/p661hnufx/p661hnufx.c
+new file mode 100644
+index 0000000..dfaca51
+--- /dev/null
++++ b/board/zyxel/p661hnufx/p661hnufx.c
+@@ -0,0 +1,102 @@
++/*
++ * Copyright (C) 2013 Daniel Schwierzeck, [email protected]
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <common.h>
++#include <switch.h>
++#include <spi.h>
++#include <asm/gpio.h>
++#include <asm/lantiq/eth.h>
++#include <asm/lantiq/reset.h>
++#include <asm/lantiq/chipid.h>
++
++static void gpio_init(void)
++{
++	/* SPI CS 0.4 to serial flash */
++	gpio_direction_output(10, 1);
++}
++
++int board_early_init_f(void)
++{
++	gpio_init();
++
++	return 0;
++}
++
++int checkboard(void)
++{
++	puts("Board: " CONFIG_BOARD_NAME "\n");
++	ltq_chip_print_info();
++
++	return 0;
++}
++
++static const struct ltq_eth_port_config eth_port_config[] = {
++	/* MAC0: Lantiq Tantos switch */
++	{ 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
++	/* MAC1: unused */
++	{ 1, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
++};
++
++static const struct ltq_eth_board_config eth_board_config = {
++	.ports = eth_port_config,
++	.num_ports = ARRAY_SIZE(eth_port_config),
++};
++
++int board_eth_init(bd_t *bis)
++{
++	return ltq_eth_initialize(&eth_board_config);
++}
++
++static struct switch_device psb697x_dev = {
++	.name = "psb697x",
++	.cpu_port = 5,
++	.port_mask = 0xF,
++};
++
++int board_switch_init(void)
++{
++	printf("%s\n", __func__);
++
++#if 0
++	ltq_reset_once(LTQ_RESET_HARD, 200000);
++	__udelay(50000);
++#endif
++
++	return switch_device_register(&psb697x_dev);
++}
++
++int spi_cs_is_valid(unsigned int bus, unsigned int cs)
++{
++	if (bus)
++		return 0;
++
++	if (cs == 4)
++		return 1;
++
++	return 0;
++}
++
++void spi_cs_activate(struct spi_slave *slave)
++{
++	switch (slave->cs) {
++	case 4:
++		gpio_set_value(10, 0);
++		break;
++	default:
++		break;
++	}
++}
++
++void spi_cs_deactivate(struct spi_slave *slave)
++{
++	switch (slave->cs) {
++	case 4:
++		gpio_set_value(10, 1);
++		break;
++	default:
++		break;
++	}
++}
+diff --git a/boards.cfg b/boards.cfg
+index 4362856..e505203 100644
+--- a/boards.cfg
++++ b/boards.cfg
+@@ -499,6 +499,9 @@ Active  mips        mips32         -           micronas        vct
+ Active  mips        mips32         arx100      zte             zxv10h201l          zxv10h201l_nor                       zxv10h201l:SYS_BOOT_NOR                                                                                                           Luka Perkov <[email protected]>
+ Active  mips        mips32         arx100      zte             zxv10h201l          zxv10h201l_ram                       zxv10h201l:SYS_BOOT_RAM                                                                                                           Luka Perkov <[email protected]>
+ Active  mips        mips32         arx100      zte             zxv10h201l          zxv10h201l_zte                       zxv10h201l:SYS_BOOT_ZTE                                                                                                           Luka Perkov <[email protected]>
++Active  mips        mips32         arx100      zyxel           p661hnufx           p661hnufx_ram                        p661hnufx:SYS_BOOT_RAM                                                                                                            Luka Perkov <[email protected]>
++Active  mips        mips32         arx100      zyxel           p661hnufx           p661hnufx_sfspl                      p661hnufx:SYS_BOOT_SFSPL                                                                                                          Luka Perkov <[email protected]>
++Active  mips        mips32         arx100      zyxel           p661hnufx           p661hnufx_zyxel                      p661hnufx:SYS_BOOT_ZYXEL                                                                                                          Luka Perkov <[email protected]>
+ Active  mips        mips32         au1x00      -               dbau1x00            dbau1000                             dbau1x00:DBAU1000                                                                                                                 Thomas Lange <[email protected]>
+ Active  mips        mips32         au1x00      -               dbau1x00            dbau1100                             dbau1x00:DBAU1100                                                                                                                 Thomas Lange <[email protected]>
+ Active  mips        mips32         au1x00      -               dbau1x00            dbau1500                             dbau1x00:DBAU1500                                                                                                                 Thomas Lange <[email protected]>
+diff --git a/include/configs/p661hnufx.h b/include/configs/p661hnufx.h
+new file mode 100644
+index 0000000..85e3e1e
+--- /dev/null
++++ b/include/configs/p661hnufx.h
+@@ -0,0 +1,79 @@
++/*
++ * Copyright (C) 2013 Daniel Schwierzeck, [email protected]
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#define CONFIG_MACH_TYPE	"P-661HNU-Fx"
++#define CONFIG_IDENT_STRING	" "CONFIG_MACH_TYPE
++#define CONFIG_BOARD_NAME	"ZyXEL P-661HNU-Fx"
++
++/* Configure SoC */
++#define CONFIG_LTQ_SUPPORT_UART		/* Enable ASC and UART */
++
++#define CONFIG_LTQ_SUPPORT_ETHERNET	/* Enable ethernet */
++
++#define CONFIG_LTQ_SUPPORT_SPI_FLASH
++#define CONFIG_SPI_FLASH_MACRONIX	/* Supports Macronix serial flash */
++#define CONFIG_SPI_FLASH_4BYTE_MODE
++
++#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH	/* Build SPI flash SPL */
++#define CONFIG_LTQ_SPL_COMP_LZO			/* Compress SPL with LZO */
++#define CONFIG_LTQ_SPL_CONSOLE			/* Enable SPL console */
++
++#define CONFIG_SPL_SPI_BUS		0
++#define CONFIG_SPL_SPI_CS		4
++#define CONFIG_SPL_SPI_MAX_HZ		25000000
++#define CONFIG_SPL_SPI_MODE		0
++
++/* Switch devices */
++#define CONFIG_SWITCH_MULTI
++#define CONFIG_SWITCH_PSB697X
++
++/* Environment */
++#define CONFIG_ENV_SPI_BUS		CONFIG_SPL_SPI_BUS
++#define CONFIG_ENV_SPI_CS		CONFIG_SPL_SPI_CS
++#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SPL_SPI_MAX_HZ
++#define CONFIG_ENV_SPI_MODE		CONFIG_SPL_SPI_MODE
++
++#if defined(CONFIG_SYS_BOOT_SFSPL)
++#define CONFIG_ENV_IS_IN_SPI_FLASH
++#define CONFIG_ENV_OVERWRITE
++#define CONFIG_ENV_OFFSET		(512 * 1024)
++#define CONFIG_ENV_SECT_SIZE		(256 * 1024)
++#else
++#define CONFIG_ENV_IS_NOWHERE
++#endif
++
++#define CONFIG_ENV_SIZE			(8 * 1024)
++#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
++
++#if defined(CONFIG_SYS_BOOT_ZYXEL)
++#define CONFIG_SYS_TEXT_BASE		0x80800000
++#define CONFIG_SKIP_LOWLEVEL_INIT
++#endif
++
++/* Console */
++#define CONFIG_LTQ_ADVANCED_CONSOLE
++#define CONFIG_BAUDRATE			115200
++#define CONFIG_CONSOLE_ASC		1
++#define CONFIG_CONSOLE_DEV		"ttyLTQ1"
++
++/* Pull in default board configs for Lantiq XWAY Danube */
++#include <asm/lantiq/config.h>
++#include <asm/arch/config.h>
++
++/* Pull in default OpenWrt configs for Lantiq SoC */
++#include "openwrt-lantiq-common.h"
++
++#define CONFIG_ENV_UPDATE_UBOOT_SF					\
++	"update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0"
++
++#define CONFIG_EXTRA_ENV_SETTINGS	\
++	CONFIG_ENV_LANTIQ_DEFAULTS	\
++	CONFIG_ENV_UPDATE_UBOOT_SF
++
++#endif /* __CONFIG_H */
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0034-MIPS-add-board-support-for-ZyXEL-P-2601HN-Fx.patch

@@ -0,0 +1,262 @@
+From 4bfa74583bc938d2da41f255f22baa1845332893 Mon Sep 17 00:00:00 2001
+From: Luka Perkov <[email protected]>
+Date: Tue, 12 Mar 2013 01:42:46 +0100
+Subject: MIPS: add board support for ZyXEL P-2601HN-Fx
+
+Signed-off-by: Luka Perkov <[email protected]>
+
+diff --git a/board/zyxel/p2601hnfx/Makefile b/board/zyxel/p2601hnfx/Makefile
+new file mode 100644
+index 0000000..3a547c2
+--- /dev/null
++++ b/board/zyxel/p2601hnfx/Makefile
+@@ -0,0 +1,27 @@
++#
++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++include $(TOPDIR)/config.mk
++
++LIB	= $(obj)lib$(BOARD).o
++
++COBJS	= $(BOARD).o
++
++SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS	:= $(addprefix $(obj),$(COBJS))
++SOBJS	:= $(addprefix $(obj),$(SOBJS))
++
++$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
++	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/board/zyxel/p2601hnfx/config.mk b/board/zyxel/p2601hnfx/config.mk
+new file mode 100644
+index 0000000..9d33739
+--- /dev/null
++++ b/board/zyxel/p2601hnfx/config.mk
+@@ -0,0 +1,7 @@
++#
++# Copyright (C) 2012-2013 Daniel Schwierzeck, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
+diff --git a/board/zyxel/p2601hnfx/ddr_settings.h b/board/zyxel/p2601hnfx/ddr_settings.h
+new file mode 100644
+index 0000000..92af4fa
+--- /dev/null
++++ b/board/zyxel/p2601hnfx/ddr_settings.h
+@@ -0,0 +1,55 @@
++/*
++ * Copyright (C) 2013 Luka Perkov <[email protected]>
++ *
++ * The values have been extracted from original ZyXEL U-Boot.
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#define MC_DC00_VALUE	0x1B1B
++#define MC_DC01_VALUE	0x0
++#define MC_DC02_VALUE	0x0
++#define MC_DC03_VALUE	0x0
++#define MC_DC04_VALUE	0x0
++#define MC_DC05_VALUE	0x200
++#define MC_DC06_VALUE	0x306
++#define MC_DC07_VALUE	0x303
++#define MC_DC08_VALUE	0x102
++#define MC_DC09_VALUE	0x70A
++#define MC_DC10_VALUE	0x203
++#define MC_DC11_VALUE	0xC02
++#define MC_DC12_VALUE	0x1C8
++#define MC_DC13_VALUE	0x1
++#define MC_DC14_VALUE	0x0
++#define MC_DC15_VALUE	0x144
++#define MC_DC16_VALUE	0xC800
++#define MC_DC17_VALUE	0xD
++#define MC_DC18_VALUE	0x301
++#define MC_DC19_VALUE	0x200
++#define MC_DC20_VALUE	0xA03
++#define MC_DC21_VALUE	0x1900
++#define MC_DC22_VALUE	0x1919
++#define MC_DC23_VALUE	0x0
++#define MC_DC24_VALUE	0x66
++#define MC_DC25_VALUE	0x0
++#define MC_DC26_VALUE	0x0
++#define MC_DC27_VALUE	0x0
++#define MC_DC28_VALUE	0x50A
++#define MC_DC29_VALUE	0x2D65
++#define MC_DC30_VALUE	0x81B1
++#define MC_DC31_VALUE	0x0
++#define MC_DC32_VALUE	0x0
++#define MC_DC33_VALUE	0x0
++#define MC_DC34_VALUE	0x0
++#define MC_DC35_VALUE	0x0
++#define MC_DC36_VALUE	0x0
++#define MC_DC37_VALUE	0x0
++#define MC_DC38_VALUE	0x0
++#define MC_DC39_VALUE	0x0
++#define MC_DC40_VALUE	0x0
++#define MC_DC41_VALUE	0x0
++#define MC_DC42_VALUE	0x0
++#define MC_DC43_VALUE	0x0
++#define MC_DC44_VALUE	0x0
++#define MC_DC45_VALUE	0x600
++#define MC_DC46_VALUE	0x0
+diff --git a/board/zyxel/p2601hnfx/p2601hnfx.c b/board/zyxel/p2601hnfx/p2601hnfx.c
+new file mode 100644
+index 0000000..6a69af9
+--- /dev/null
++++ b/board/zyxel/p2601hnfx/p2601hnfx.c
+@@ -0,0 +1,51 @@
++/*
++ * Copyright (C) 2013 Luka Perkov <[email protected]>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <common.h>
++#include <switch.h>
++#include <asm/gpio.h>
++#include <asm/lantiq/eth.h>
++#include <asm/lantiq/reset.h>
++#include <asm/lantiq/chipid.h>
++
++int board_early_init_f(void)
++{
++	return 0;
++}
++
++int checkboard(void)
++{
++	puts("Board: " CONFIG_BOARD_NAME "\n");
++	ltq_chip_print_info();
++
++	return 0;
++}
++
++static const struct ltq_eth_port_config eth_port_config[] = {
++	/* MAC0: REALTEK RTL8306 switch */
++	{ 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
++};
++
++static const struct ltq_eth_board_config eth_board_config = {
++	.ports = eth_port_config,
++	.num_ports = ARRAY_SIZE(eth_port_config),
++};
++
++int board_eth_init(bd_t *bis)
++{
++	return ltq_eth_initialize(&eth_board_config);
++}
++
++static struct switch_device rtl8306_dev = {
++	.name = "rtl8306",
++	.cpu_port = 5,
++	.port_mask = 0xF,
++};
++
++int board_switch_init(void)
++{
++	return switch_device_register(&rtl8306_dev);
++}
+diff --git a/boards.cfg b/boards.cfg
+index e505203..45c2aa0 100644
+--- a/boards.cfg
++++ b/boards.cfg
+@@ -499,6 +499,10 @@ Active  mips        mips32         -           micronas        vct
+ Active  mips        mips32         arx100      zte             zxv10h201l          zxv10h201l_nor                       zxv10h201l:SYS_BOOT_NOR                                                                                                           Luka Perkov <[email protected]>
+ Active  mips        mips32         arx100      zte             zxv10h201l          zxv10h201l_ram                       zxv10h201l:SYS_BOOT_RAM                                                                                                           Luka Perkov <[email protected]>
+ Active  mips        mips32         arx100      zte             zxv10h201l          zxv10h201l_zte                       zxv10h201l:SYS_BOOT_ZTE                                                                                                           Luka Perkov <[email protected]>
++Active  mips        mips32         arx100      zyxel           p2601hnfx           p2601hnfx_nor                        p2601hnfx:SYS_BOOT_NOR                                                                                                            Luka Perkov <[email protected]>
++Active  mips        mips32         arx100      zyxel           p2601hnfx           p2601hnfx_norspl                     p2601hnfx:SYS_BOOT_NORSPL                                                                                                         Luka Perkov <[email protected]>
++Active  mips        mips32         arx100      zyxel           p2601hnfx           p2601hnfx_ram                        p2601hnfx:SYS_BOOT_RAM                                                                                                            Luka Perkov <[email protected]>
++Active  mips        mips32         arx100      zyxel           p2601hnfx           p2601hnfx_zyxel                      p2601hnfx:SYS_BOOT_ZYXEL                                                                                                          Luka Perkov <[email protected]>
+ Active  mips        mips32         arx100      zyxel           p661hnufx           p661hnufx_ram                        p661hnufx:SYS_BOOT_RAM                                                                                                            Luka Perkov <[email protected]>
+ Active  mips        mips32         arx100      zyxel           p661hnufx           p661hnufx_sfspl                      p661hnufx:SYS_BOOT_SFSPL                                                                                                          Luka Perkov <[email protected]>
+ Active  mips        mips32         arx100      zyxel           p661hnufx           p661hnufx_zyxel                      p661hnufx:SYS_BOOT_ZYXEL                                                                                                          Luka Perkov <[email protected]>
+diff --git a/include/configs/p2601hnfx.h b/include/configs/p2601hnfx.h
+new file mode 100644
+index 0000000..5cba30f
+--- /dev/null
++++ b/include/configs/p2601hnfx.h
+@@ -0,0 +1,67 @@
++/*
++ * Copyright (C) 2013 Luka Perkov <[email protected]>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#define CONFIG_MACH_TYPE	"P-2601HN-Fx"
++#define CONFIG_IDENT_STRING	" "CONFIG_MACH_TYPE
++#define CONFIG_BOARD_NAME	"ZyXEL P-2601HN-Fx"
++
++/* Configure SoC */
++#define CONFIG_LTQ_SUPPORT_UART			/* Enable ASC and UART */
++
++#define CONFIG_LTQ_SUPPORT_NOR_FLASH		/* Have a parallel NOR flash */
++
++#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH	/* Build NOR flash SPL */
++#define CONFIG_LTQ_SPL_COMP_LZO			/* Compress SPL with LZO */
++#define CONFIG_LTQ_SPL_CONSOLE			/* Enable SPL console */
++
++/* Environment */
++#if defined(CONFIG_SYS_BOOT_NOR)
++#define CONFIG_ENV_IS_IN_FLASH
++#define CONFIG_ENV_OVERWRITE
++#define CONFIG_ENV_OFFSET		(256 * 1024)
++#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
++#elif defined(CONFIG_SYS_BOOT_NORSPL)
++#define CONFIG_ENV_IS_IN_FLASH
++#define CONFIG_ENV_OVERWRITE
++#define CONFIG_ENV_OFFSET		(128 * 1024)
++#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
++#else
++#define CONFIG_ENV_IS_NOWHERE
++#endif
++
++#define CONFIG_ENV_SIZE			(8 * 1024)
++#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
++
++#if defined(CONFIG_SYS_BOOT_ZYXEL)
++#define CONFIG_SYS_TEXT_BASE		0x80800000
++#define CONFIG_SKIP_LOWLEVEL_INIT
++#endif
++
++/* Console */
++#define CONFIG_LTQ_ADVANCED_CONSOLE
++#define CONFIG_BAUDRATE			115200
++#define CONFIG_CONSOLE_ASC		1
++#define CONFIG_CONSOLE_DEV		"ttyLTQ1"
++
++/* Pull in default board configs for Lantiq XWAY Danube */
++#include <asm/lantiq/config.h>
++#include <asm/arch/config.h>
++
++/* Pull in default OpenWrt configs for Lantiq SoC */
++#include "openwrt-lantiq-common.h"
++
++#define CONFIG_ENV_UPDATE_UBOOT_NOR \
++	"update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0"
++
++#define CONFIG_EXTRA_ENV_SETTINGS	\
++	CONFIG_ENV_LANTIQ_DEFAULTS	\
++	CONFIG_ENV_UPDATE_UBOOT_NOR	\
++	"kernel_addr=0xB0040000\0"
++
++#endif /* __CONFIG_H */
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0035-MIPS-add-board-support-for-ZyXEL-P-2812HNU-Fx.patch

@@ -0,0 +1,321 @@
+From 3f7be04a148d23cdb5fd320e0e2923983f8bd1f4 Mon Sep 17 00:00:00 2001
+From: Luka Perkov <[email protected]>
+Date: Tue, 6 Aug 2013 22:51:00 +0200
+Subject: MIPS: add board support for ZyXEL P-2812HNU-Fx
+
+Signed-off-by: Luka Perkov <[email protected]>
+
+diff --git a/board/zyxel/p2812hnufx/Makefile b/board/zyxel/p2812hnufx/Makefile
+new file mode 100644
+index 0000000..3a547c2
+--- /dev/null
++++ b/board/zyxel/p2812hnufx/Makefile
+@@ -0,0 +1,27 @@
++#
++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++include $(TOPDIR)/config.mk
++
++LIB	= $(obj)lib$(BOARD).o
++
++COBJS	= $(BOARD).o
++
++SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS	:= $(addprefix $(obj),$(COBJS))
++SOBJS	:= $(addprefix $(obj),$(SOBJS))
++
++$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
++	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/board/zyxel/p2812hnufx/config.mk b/board/zyxel/p2812hnufx/config.mk
+new file mode 100644
+index 0000000..9d33739
+--- /dev/null
++++ b/board/zyxel/p2812hnufx/config.mk
+@@ -0,0 +1,7 @@
++#
++# Copyright (C) 2012-2013 Daniel Schwierzeck, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
+diff --git a/board/zyxel/p2812hnufx/ddr_settings.h b/board/zyxel/p2812hnufx/ddr_settings.h
+new file mode 100644
+index 0000000..128c42e
+--- /dev/null
++++ b/board/zyxel/p2812hnufx/ddr_settings.h
+@@ -0,0 +1,70 @@
++/*
++ * Copyright (C) 2013 Luka Perkov <[email protected]>
++ *
++ * The values have been extracted from original ZyXEL U-Boot.
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#define	MC_CCR00_VALUE	0x101
++#define	MC_CCR01_VALUE	0x1000100
++#define	MC_CCR02_VALUE	0x1010000
++#define	MC_CCR03_VALUE	0x101
++#define	MC_CCR04_VALUE	0x1000000
++#define	MC_CCR05_VALUE	0x1000101
++#define	MC_CCR06_VALUE	0x1000100
++#define	MC_CCR07_VALUE	0x1010000
++#define	MC_CCR08_VALUE	0x1000101
++#define	MC_CCR09_VALUE	0x0
++#define	MC_CCR10_VALUE	0x2000100
++#define	MC_CCR11_VALUE	0x2000300
++#define	MC_CCR12_VALUE	0x30000
++#define	MC_CCR13_VALUE	0x202
++#define	MC_CCR14_VALUE	0x7080A0F
++#define	MC_CCR15_VALUE	0x2040F
++#define	MC_CCR16_VALUE	0x40000
++#define	MC_CCR17_VALUE	0x70102
++#define	MC_CCR18_VALUE	0x4020002
++#define	MC_CCR19_VALUE	0x30302
++#define	MC_CCR20_VALUE	0x8000700
++#define	MC_CCR21_VALUE	0x40F020A
++#define	MC_CCR22_VALUE	0x0
++#define	MC_CCR23_VALUE	0xC020000
++#define	MC_CCR24_VALUE	0x4401B04
++#define	MC_CCR25_VALUE	0x0
++#define	MC_CCR26_VALUE	0x0
++#define	MC_CCR27_VALUE	0x6420000
++#define	MC_CCR28_VALUE	0x0
++#define	MC_CCR29_VALUE	0x0
++#define	MC_CCR30_VALUE	0x798
++#define	MC_CCR31_VALUE	0x0
++#define	MC_CCR32_VALUE	0x0
++#define	MC_CCR33_VALUE	0x650000
++#define	MC_CCR34_VALUE	0x200C8
++#define	MC_CCR35_VALUE	0x1D445D
++#define	MC_CCR36_VALUE	0xC8
++#define	MC_CCR37_VALUE	0xC351
++#define	MC_CCR38_VALUE	0x0
++#define	MC_CCR39_VALUE	0x141F04
++#define	MC_CCR40_VALUE	0x142704
++#define	MC_CCR41_VALUE	0x141B42
++#define	MC_CCR42_VALUE	0x141B42
++#define	MC_CCR43_VALUE	0x566504
++#define	MC_CCR44_VALUE	0x566504
++#define	MC_CCR45_VALUE	0x565F17
++#define	MC_CCR46_VALUE	0x565F17
++#define	MC_CCR47_VALUE	0x0
++#define	MC_CCR48_VALUE	0x0
++#define	MC_CCR49_VALUE	0x0
++#define	MC_CCR50_VALUE	0x0
++#define	MC_CCR51_VALUE	0x0
++#define	MC_CCR52_VALUE	0x133
++#define	MC_CCR53_VALUE	0xF3014B27
++#define	MC_CCR54_VALUE	0xF3014B27
++#define	MC_CCR55_VALUE	0xF3014B27
++#define	MC_CCR56_VALUE	0xF3014B27
++#define	MC_CCR57_VALUE	0x7800301
++#define	MC_CCR58_VALUE	0x7800301
++#define	MC_CCR59_VALUE	0x7800301
++#define	MC_CCR60_VALUE	0x7800301
++#define	MC_CCR61_VALUE	0x4
+diff --git a/board/zyxel/p2812hnufx/p2812hnufx.c b/board/zyxel/p2812hnufx/p2812hnufx.c
+new file mode 100644
+index 0000000..cd2f819
+--- /dev/null
++++ b/board/zyxel/p2812hnufx/p2812hnufx.c
+@@ -0,0 +1,97 @@
++/*
++ * Copyright (C) 2013 Luka Perkov <[email protected]>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/gpio.h>
++#include <asm/lantiq/eth.h>
++#include <asm/lantiq/chipid.h>
++#include <asm/lantiq/cpu.h>
++#include <asm/arch/gphy.h>
++
++#if defined(CONFIG_SPL_BUILD)
++#define do_gpio_init	1
++#define do_pll_init	1
++#define do_dcdc_init	0
++#elif defined(CONFIG_SYS_BOOT_RAM)
++#define do_gpio_init	1
++#define do_pll_init	0
++#define do_dcdc_init	1
++#else
++#define do_gpio_init	0
++#define do_pll_init	0
++#define do_dcdc_init	1
++#endif
++
++static void gpio_init(void)
++{
++	/* EBU.FL_CS1 as output for NAND CE */
++	gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
++	/* EBU.FL_A23 as output for NAND CLE */
++	gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
++	/* EBU.FL_A24 as output for NAND ALE */
++	gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
++	/* GPIO 3.0 as input for NAND Ready Busy */
++	gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
++	/* GPIO 3.1 as output for NAND Read */
++	gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
++}
++
++int board_early_init_f(void)
++{
++	if (do_gpio_init)
++		gpio_init();
++
++	if (do_pll_init)
++		ltq_pll_init();
++
++	if (do_dcdc_init)
++		ltq_dcdc_init(0x7F);
++
++	return 0;
++}
++
++int checkboard(void)
++{
++	puts("Board: " CONFIG_BOARD_NAME "\n");
++	ltq_chip_print_info();
++
++	return 0;
++}
++
++static const struct ltq_eth_port_config eth_port_config[] = {
++	/* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */
++	{ 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
++	/* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */
++	{ 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
++	/* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */
++	{ 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
++	/* GMAC3: unused */
++	{ 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
++	/* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */
++	{ 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
++	/* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */
++	{ 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
++};
++
++static const struct ltq_eth_board_config eth_board_config = {
++	.ports = eth_port_config,
++	.num_ports = ARRAY_SIZE(eth_port_config),
++};
++
++int board_eth_init(bd_t * bis)
++{
++	const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
++	const ulong fw_addr = 0x80FF0000;
++
++	ltq_gphy_phy11g_a1x_load(fw_addr);
++
++	ltq_cgu_gphy_clk_src(clk);
++
++	ltq_rcu_gphy_boot(0, fw_addr);
++	ltq_rcu_gphy_boot(1, fw_addr);
++
++	return ltq_eth_initialize(&eth_board_config);
++}
+diff --git a/boards.cfg b/boards.cfg
+index 45c2aa0..0cbf756 100644
+--- a/boards.cfg
++++ b/boards.cfg
+@@ -540,6 +540,8 @@ Active  mips        mips32         vrx200      lantiq          easy80920
+ Active  mips        mips32         vrx200      zte             zxhnh367n           zxhnh367n_nandspl                    zxhnh367n:SYS_BOOT_NANDSPL                                                                                                        Luka Perkov <[email protected]>
+ Active  mips        mips32         vrx200      zte             zxhnh367n           zxhnh367n_ram                        zxhnh367n:SYS_BOOT_RAM                                                                                                            Luka Perkov <[email protected]>
+ Active  mips        mips32         vrx200      zte             zxhnh367n           zxhnh367n_zte                        zxhnh367n:SYS_BOOT_ZTE                                                                                                            Luka Perkov <[email protected]>
++Active  mips        mips32         vrx200      zyxel           p2812hnufx          p2812hnufx_nandspl                   p2812hnufx:SYS_BOOT_NANDSPL                                                                                                       Luka Perkov <[email protected]>
++Active  mips        mips32         vrx200      zyxel           p2812hnufx          p2812hnufx_ram                       p2812hnufx:SYS_BOOT_RAM                                                                                                           Luka Perkov <[email protected]>
+ Active  mips        mips64         -           -               qemu-mips           qemu_mips64                          qemu-mips64:SYS_BIG_ENDIAN                                                                                                        -
+ Active  mips        mips64         -           -               qemu-mips           qemu_mips64el                        qemu-mips64:SYS_LITTLE_ENDIAN                                                                                                     -
+ Active  nds32       n1213          ag101       AndesTech       adp-ag101           adp-ag101                            -                                                                                                                                 Andes <[email protected]>
+diff --git a/include/configs/p2812hnufx.h b/include/configs/p2812hnufx.h
+new file mode 100644
+index 0000000..6806eb1
+--- /dev/null
++++ b/include/configs/p2812hnufx.h
+@@ -0,0 +1,67 @@
++/*
++ * Copyright (C) 2013 Luka Perkov <[email protected]>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#define CONFIG_MACH_TYPE	"P-2812HNU-Fx"
++#define CONFIG_IDENT_STRING	" "CONFIG_MACH_TYPE
++#define CONFIG_BOARD_NAME	"ZyXEL P-2812HNU-Fx"
++
++/* Configure SoC */
++#define CONFIG_LTQ_SUPPORT_UART			/* Enable ASC and UART */
++
++#define CONFIG_LTQ_SUPPORT_ETHERNET		/* Enable ethernet */
++
++#define CONFIG_LTQ_SUPPORT_NAND_FLASH		/* Have a K9F1G08U0D NAND flash */
++
++#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH	/* Build NAND flash SPL */
++#define CONFIG_LTQ_SPL_COMP_LZO			/* Compress SPL with LZO */
++#define CONFIG_LTQ_SPL_CONSOLE			/* Enable SPL console */
++
++#define CONFIG_SYS_NAND_PAGE_COUNT	64
++#define CONFIG_SYS_NAND_PAGE_SIZE	2048
++#define CONFIG_SYS_NAND_OOBSIZE		64
++#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
++#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
++#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x4000
++
++#define CONFIG_SYS_DRAM_PROBE
++
++/* Environment */
++#if defined(CONFIG_SYS_BOOT_NANDSPL)
++#define CONFIG_ENV_IS_IN_NAND
++#define CONFIG_ENV_OVERWRITE
++#define CONFIG_ENV_OFFSET		(256 * 1024)
++#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
++#else
++#define CONFIG_ENV_IS_NOWHERE
++#endif
++
++#define CONFIG_ENV_SIZE			(8 * 1024)
++#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
++
++/* Console */
++#define CONFIG_LTQ_ADVANCED_CONSOLE
++#define CONFIG_BAUDRATE			115200
++#define CONFIG_CONSOLE_ASC		1
++#define CONFIG_CONSOLE_DEV		"ttyLTQ1"
++
++/* Pull in default board configs for Lantiq XWAY VRX200 */
++#include <asm/lantiq/config.h>
++#include <asm/arch/config.h>
++
++/* Pull in default OpenWrt configs for Lantiq SoC */
++#include "openwrt-lantiq-common.h"
++
++#define CONFIG_ENV_UPDATE_UBOOT_NAND					\
++	"update-uboot-nand=run load-uboot-nandspl-lzo write-uboot-nand\0"
++
++#define CONFIG_EXTRA_ENV_SETTINGS	\
++	CONFIG_ENV_LANTIQ_DEFAULTS	\
++	CONFIG_ENV_UPDATE_UBOOT_NAND
++
++#endif /* __CONFIG_H */
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0036-MIPS-add-board-support-for-Arcadyan-Easybox-904.patch

@@ -0,0 +1,297 @@
+From 60856fa8f9866f292df740ea98752a70738eb59a Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <[email protected]>
+Date: Fri, 9 Aug 2013 18:11:07 +0200
+Subject: MIPS: add board support for Arcadyan Easybox 904
+
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/board/arcadyan/easybox904/Makefile b/board/arcadyan/easybox904/Makefile
+new file mode 100644
+index 0000000..0380dea
+--- /dev/null
++++ b/board/arcadyan/easybox904/Makefile
+@@ -0,0 +1,27 @@
++#
++# Copyright (C) 2011-2013 Daniel Schwierzeck, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++include $(TOPDIR)/config.mk
++
++LIB	= $(obj)lib$(BOARD).o
++
++COBJS	= $(BOARD).o
++
++SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS	:= $(addprefix $(obj),$(COBJS))
++SOBJS	:= $(addprefix $(obj),$(SOBJS))
++
++$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
++	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/board/arcadyan/easybox904/config.mk b/board/arcadyan/easybox904/config.mk
+new file mode 100644
+index 0000000..9d8953b
+--- /dev/null
++++ b/board/arcadyan/easybox904/config.mk
+@@ -0,0 +1,7 @@
++#
++# Copyright (C) 2011-2013 Daniel Schwierzeck, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
+diff --git a/board/arcadyan/easybox904/ddr_settings.h b/board/arcadyan/easybox904/ddr_settings.h
+new file mode 100644
+index 0000000..24541bc
+--- /dev/null
++++ b/board/arcadyan/easybox904/ddr_settings.h
+@@ -0,0 +1,68 @@
++/*
++ * Copyright (C) 2011-2013 Daniel Schwierzeck, [email protected]
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#define	MC_CCR00_VALUE	0x101
++#define	MC_CCR01_VALUE	0x1000100
++#define	MC_CCR02_VALUE	0x1010000
++#define	MC_CCR03_VALUE	0x101
++#define	MC_CCR04_VALUE	0x1000000
++#define	MC_CCR05_VALUE	0x1000101
++#define	MC_CCR06_VALUE	0x1000100
++#define	MC_CCR07_VALUE	0x1010000
++#define	MC_CCR08_VALUE	0x1000101
++#define	MC_CCR09_VALUE	0x1000000
++#define	MC_CCR10_VALUE	0x2000100
++#define	MC_CCR11_VALUE	0x2000300
++#define	MC_CCR12_VALUE	0x30000
++#define	MC_CCR13_VALUE	0x202
++#define	MC_CCR14_VALUE	0x7080A0F
++#define	MC_CCR15_VALUE	0x2040F
++#define	MC_CCR16_VALUE	0x40000
++#define	MC_CCR17_VALUE	0x70102
++#define	MC_CCR18_VALUE	0x4020002
++#define	MC_CCR19_VALUE	0x30302
++#define	MC_CCR20_VALUE	0x8000700
++#define	MC_CCR21_VALUE	0x40F020A
++#define	MC_CCR22_VALUE	0x0
++#define	MC_CCR23_VALUE	0xC020000
++#define	MC_CCR24_VALUE	0x4401503
++#define	MC_CCR25_VALUE	0x0
++#define	MC_CCR26_VALUE	0x0
++#define	MC_CCR27_VALUE	0x6420000
++#define	MC_CCR28_VALUE	0x0
++#define	MC_CCR29_VALUE	0x0
++#define	MC_CCR30_VALUE	0x798
++#define	MC_CCR31_VALUE	0x0
++#define	MC_CCR32_VALUE	0x0
++#define	MC_CCR33_VALUE	0x650000
++#define	MC_CCR34_VALUE	0x200C8
++#define	MC_CCR35_VALUE	0x1536B0
++#define	MC_CCR36_VALUE	0xC8
++#define	MC_CCR37_VALUE	0xC351
++#define	MC_CCR38_VALUE	0x0
++#define	MC_CCR39_VALUE	0x142404
++#define	MC_CCR40_VALUE	0x142604
++#define	MC_CCR41_VALUE	0x141B42
++#define	MC_CCR42_VALUE	0x141B42
++#define	MC_CCR43_VALUE	0x566504
++#define	MC_CCR44_VALUE	0x566504
++#define	MC_CCR45_VALUE	0x565F17
++#define	MC_CCR46_VALUE	0x565F17
++#define	MC_CCR47_VALUE	0x0
++#define	MC_CCR48_VALUE	0x0
++#define	MC_CCR49_VALUE	0x0
++#define	MC_CCR50_VALUE	0x0
++#define	MC_CCR51_VALUE	0x0
++#define	MC_CCR52_VALUE	0x133
++#define	MC_CCR53_VALUE	0xF3014B27
++#define	MC_CCR54_VALUE	0xF3014B27
++#define	MC_CCR55_VALUE	0xF3014B27
++#define	MC_CCR56_VALUE	0xF3014B27
++#define	MC_CCR57_VALUE	0x7C00301
++#define	MC_CCR58_VALUE	0x7C00301
++#define	MC_CCR59_VALUE	0x7C00301
++#define	MC_CCR60_VALUE	0x7C00301
++#define	MC_CCR61_VALUE	0x4
+diff --git a/board/arcadyan/easybox904/easybox904.c b/board/arcadyan/easybox904/easybox904.c
+new file mode 100644
+index 0000000..4dbe044
+--- /dev/null
++++ b/board/arcadyan/easybox904/easybox904.c
+@@ -0,0 +1,98 @@
++/*
++ * Copyright (C) 2012-2013 Daniel Schwierzeck, [email protected]
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <common.h>
++#include <spi.h>
++#include <asm/gpio.h>
++#include <asm/lantiq/eth.h>
++#include <asm/lantiq/chipid.h>
++#include <asm/lantiq/cpu.h>
++#include <asm/arch/gphy.h>
++
++#if defined(CONFIG_SPL_BUILD)
++#define do_gpio_init	1
++#define do_pll_init	1
++#define do_dcdc_init	0
++#elif defined(CONFIG_SYS_BOOT_RAM)
++#define do_gpio_init	1
++#define do_pll_init	0
++#define do_dcdc_init	1
++#else
++#define do_gpio_init	0
++#define do_pll_init	0
++#define do_dcdc_init	1
++#endif
++
++static inline void gpio_init(void)
++{
++	/* EBU.FL_CS1 as output for NAND CE */
++	gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
++	/* EBU.FL_A23 as output for NAND CLE */
++	gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
++	/* EBU.FL_A24 as output for NAND ALE */
++	gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
++	/* GPIO 3.0 as input for NAND Ready Busy */
++	gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
++	/* GPIO 3.1 as output for NAND Read */
++	gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
++}
++
++int board_early_init_f(void)
++{
++	if (do_gpio_init)
++		gpio_init();
++
++	if (do_pll_init)
++		ltq_pll_init();
++
++	if (do_dcdc_init)
++		ltq_dcdc_init(0x7F);
++
++	return 0;
++}
++
++int checkboard(void)
++{
++	puts("Board: " CONFIG_BOARD_NAME "\n");
++	ltq_chip_print_info();
++
++	return 0;
++}
++
++static const struct ltq_eth_port_config eth_port_config[] = {
++	/* GMAC0: ??? */
++	{ 0, 0x0, LTQ_ETH_PORT_NONE, LTQ_ETH_PORT_NONE },
++	/* GMAC1: ??? */
++	{ 1, 0x1, LTQ_ETH_PORT_NONE, LTQ_ETH_PORT_NONE },
++	/* GMAC2: ??? */
++	{ 2, 0x11, LTQ_ETH_PORT_NONE, LTQ_ETH_PORT_NONE },
++	/* GMAC3: unused */
++	{ 3, 0x0, LTQ_ETH_PORT_NONE, LTQ_ETH_PORT_NONE },
++	/* GMAC4: internal GPHY1 with 10/100/1000 firmware for WANoE port */
++	{ 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
++	/* GMAC5: ??? */
++	{ 5, 0x5, LTQ_ETH_PORT_NONE, LTQ_ETH_PORT_NONE },
++};
++
++static const struct ltq_eth_board_config eth_board_config = {
++	.ports = eth_port_config,
++	.num_ports = ARRAY_SIZE(eth_port_config),
++};
++
++int board_eth_init(bd_t * bis)
++{
++	const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
++	const ulong fw_ge_addr = 0x80FE0000;
++
++	ltq_gphy_phy11g_a2x_load(fw_ge_addr);
++
++	ltq_cgu_gphy_clk_src(clk);
++
++	ltq_rcu_gphy_boot(0, fw_ge_addr);
++	ltq_rcu_gphy_boot(1, fw_ge_addr);
++
++	return ltq_eth_initialize(&eth_board_config);
++}
+diff --git a/boards.cfg b/boards.cfg
+index 0cbf756..f10be39 100644
+--- a/boards.cfg
++++ b/boards.cfg
+@@ -529,6 +529,7 @@ Active  mips        mips32         incaip      -               incaip
+ Active  mips        mips32         incaip      -               incaip              incaip_100MHz                        incaip:CPU_CLOCK_RATE=100000000                                                                                                   Wolfgang Denk <[email protected]>
+ Active  mips        mips32         incaip      -               incaip              incaip_133MHz                        incaip:CPU_CLOCK_RATE=133000000                                                                                                   Wolfgang Denk <[email protected]>
+ Active  mips        mips32         incaip      -               incaip              incaip_150MHz                        incaip:CPU_CLOCK_RATE=150000000                                                                                                   Wolfgang Denk <[email protected]>
++Active  mips        mips32         vrx200      arcadyan        easybox904          easybox904_ram                       easybox904:SYS_BOOT_RAM                                                                                                           Daniel Schwierzeck <[email protected]>
+ Active  mips        mips32         vrx200      avm             fb3370              fb3370_eva                           fb3370:SYS_BOOT_EVA                                                                                                               Daniel Schwierzeck <[email protected]>
+ Active  mips        mips32         vrx200      avm             fb3370              fb3370_ram                           fb3370:SYS_BOOT_RAM                                                                                                               Daniel Schwierzeck <[email protected]>
+ Active  mips        mips32         vrx200      avm             fb3370              fb3370_sfspl                         fb3370:SYS_BOOT_SFSPL                                                                                                             Daniel Schwierzeck <[email protected]>
+diff --git a/include/configs/easybox904.h b/include/configs/easybox904.h
+new file mode 100644
+index 0000000..c892d77
+--- /dev/null
++++ b/include/configs/easybox904.h
+@@ -0,0 +1,45 @@
++/*
++ * Copyright (C) 2012-2013 Daniel Schwierzeck, [email protected]
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#define CONFIG_MACH_TYPE	"EASYBOX904"
++#define CONFIG_IDENT_STRING	" "CONFIG_MACH_TYPE
++#define CONFIG_BOARD_NAME	"Arcadyan EasyBox 904"
++
++/* Configure SoC */
++#define CONFIG_LTQ_SUPPORT_UART			/* Enable ASC and UART */
++
++#define CONFIG_LTQ_SUPPORT_ETHERNET		/* Enable ethernet */
++
++#define CONFIG_LTQ_SUPPORT_NAND_FLASH
++
++#define CONFIG_SYS_DRAM_PROBE
++
++/* Environment */
++#define CONFIG_ENV_IS_NOWHERE
++
++#define CONFIG_ENV_SIZE			(8 * 1024)
++#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
++
++/* Console */
++#define CONFIG_LTQ_ADVANCED_CONSOLE
++#define CONFIG_BAUDRATE			115200
++#define CONFIG_CONSOLE_ASC		1
++#define CONFIG_CONSOLE_DEV		"ttyLTQ1"
++
++/* Pull in default board configs for Lantiq XWAY VRX200 */
++#include <asm/lantiq/config.h>
++#include <asm/arch/config.h>
++
++/* Pull in default OpenWrt configs for Lantiq SoC */
++#include "openwrt-lantiq-common.h"
++
++#define CONFIG_EXTRA_ENV_SETTINGS	\
++	CONFIG_ENV_LANTIQ_DEFAULTS
++
++#endif /* __CONFIG_H */
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0037-MIPS-add-board-support-for-Arcadyan-ARV752DPW.patch

@@ -0,0 +1,262 @@
+From fbdbf2ddf2b34d675d53de679c179788b0604c1a Mon Sep 17 00:00:00 2001
+From: Oliver Muth <[email protected]>
+Date: Sat, 12 Oct 2013 16:49:53 +0200
+Subject: MIPS: add board support for Arcadyan ARV752DPW
+
+Signed-off-by: Oliver Muth <[email protected]>
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/board/arcadyan/arv752dpw/Makefile b/board/arcadyan/arv752dpw/Makefile
+new file mode 100644
+index 0000000..3a547c2
+--- /dev/null
++++ b/board/arcadyan/arv752dpw/Makefile
+@@ -0,0 +1,27 @@
++#
++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++include $(TOPDIR)/config.mk
++
++LIB	= $(obj)lib$(BOARD).o
++
++COBJS	= $(BOARD).o
++
++SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS	:= $(addprefix $(obj),$(COBJS))
++SOBJS	:= $(addprefix $(obj),$(SOBJS))
++
++$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
++	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/board/arcadyan/arv752dpw/arv752dpw.c b/board/arcadyan/arv752dpw/arv752dpw.c
+new file mode 100644
+index 0000000..d555904
+--- /dev/null
++++ b/board/arcadyan/arv752dpw/arv752dpw.c
+@@ -0,0 +1,51 @@
++/*
++ * Copyright (C) 2012 Luka Perkov <[email protected]>
++ * Copyright (C) 2013 Oliver Muth <[email protected]>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <common.h>
++#include <switch.h>
++#include <asm/gpio.h>
++#include <asm/lantiq/eth.h>
++#include <asm/lantiq/reset.h>
++#include <asm/lantiq/chipid.h>
++
++int board_early_init_f(void)
++{
++	return 0;
++}
++
++int checkboard(void)
++{
++	puts("Board: " CONFIG_BOARD_NAME "\n");
++	ltq_chip_print_info();
++
++	return 0;
++}
++
++static const struct ltq_eth_port_config eth_port_config[] = {
++	/* MAC0: Realtek rtl8306 switch */
++	{ 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
++};
++
++static const struct ltq_eth_board_config eth_board_config = {
++	.ports = eth_port_config,
++	.num_ports = ARRAY_SIZE(eth_port_config),
++};
++
++int board_eth_init(bd_t *bis)
++{
++	return ltq_eth_initialize(&eth_board_config);
++}
++static struct switch_device rtl8306_dev = {
++	.name = "rtl8306",
++	.cpu_port = 5,
++	.port_mask = 0xF,
++};
++
++int board_switch_init(void)
++{
++	return switch_device_register(&rtl8306_dev);
++}
+diff --git a/board/arcadyan/arv752dpw/config.mk b/board/arcadyan/arv752dpw/config.mk
+new file mode 100644
+index 0000000..9d8953b
+--- /dev/null
++++ b/board/arcadyan/arv752dpw/config.mk
+@@ -0,0 +1,7 @@
++#
++# Copyright (C) 2011-2013 Daniel Schwierzeck, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
+diff --git a/board/arcadyan/arv752dpw/ddr_settings.h b/board/arcadyan/arv752dpw/ddr_settings.h
+new file mode 100644
+index 0000000..a226322
+--- /dev/null
++++ b/board/arcadyan/arv752dpw/ddr_settings.h
+@@ -0,0 +1,55 @@
++/*
++ * Copyright (C) 2011-2013 Luka Perkov <[email protected]>
++ *
++ * This file has been generated with lantiq_ram_extract_magic.awk script.     
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#define MC_DC00_VALUE	0x1B1B
++#define MC_DC01_VALUE	0x0
++#define MC_DC02_VALUE	0x0
++#define MC_DC03_VALUE	0x0
++#define MC_DC04_VALUE	0x0
++#define MC_DC05_VALUE	0x200
++#define MC_DC06_VALUE	0x605
++#define MC_DC07_VALUE	0x303
++#define MC_DC08_VALUE	0x102
++#define MC_DC09_VALUE	0x70A
++#define MC_DC10_VALUE	0x203
++#define MC_DC11_VALUE	0xC02
++#define MC_DC12_VALUE	0x1C8
++#define MC_DC13_VALUE	0x1
++#define MC_DC14_VALUE	0x0
++#define MC_DC15_VALUE	0x134
++#define MC_DC16_VALUE	0xC800
++#define MC_DC17_VALUE	0xD
++#define MC_DC18_VALUE	0x301
++#define MC_DC19_VALUE	0x200
++#define MC_DC20_VALUE	0xA03
++#define MC_DC21_VALUE	0x1400
++#define MC_DC22_VALUE	0x1414
++#define MC_DC23_VALUE	0x0
++#define MC_DC24_VALUE	0x5B
++#define MC_DC25_VALUE	0x0
++#define MC_DC26_VALUE	0x0
++#define MC_DC27_VALUE	0x0
++#define MC_DC28_VALUE	0x510
++#define MC_DC29_VALUE	0x4E20
++#define MC_DC30_VALUE	0x8235
++#define MC_DC31_VALUE	0x0
++#define MC_DC32_VALUE	0x0
++#define MC_DC33_VALUE	0x0
++#define MC_DC34_VALUE	0x0
++#define MC_DC35_VALUE	0x0
++#define MC_DC36_VALUE	0x0
++#define MC_DC37_VALUE	0x0
++#define MC_DC38_VALUE	0x0
++#define MC_DC39_VALUE	0x0
++#define MC_DC40_VALUE	0x0
++#define MC_DC41_VALUE	0x0
++#define MC_DC42_VALUE	0x0
++#define MC_DC43_VALUE	0x0
++#define MC_DC44_VALUE	0x0
++#define MC_DC45_VALUE	0x500
++#define MC_DC46_VALUE	0x0
+diff --git a/boards.cfg b/boards.cfg
+index f10be39..79cba2d 100644
+--- a/boards.cfg
++++ b/boards.cfg
+@@ -518,6 +518,9 @@ Active  mips        mips32         danube      arcadyan        arv4519pw
+ Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_brn                        arv7518pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <[email protected]>
+ Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_nor                        arv7518pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <[email protected]>
+ Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_ram                        arv7518pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <[email protected]>
++Active  mips        mips32         danube      arcadyan        arv752dpw           arv752dpw_brn                        arv752dpw:SYS_BOOT_BRN                                                                                                            -
++Active  mips        mips32         danube      arcadyan        arv752dpw           arv752dpw_nor                        arv752dpw:SYS_BOOT_NOR                                                                                                            -
++Active  mips        mips32         danube      arcadyan        arv752dpw           arv752dpw_ram                        arv752dpw:SYS_BOOT_RAM                                                                                                            -
+ Active  mips        mips32         danube      audiocodes      acmp252             acmp252_nor                          acmp252:SYS_BOOT_NOR                                                                                                              Daniel Golle <[email protected]>
+ Active  mips        mips32         danube      audiocodes      acmp252             acmp252_ram                          acmp252:SYS_BOOT_RAM                                                                                                              Daniel Golle <[email protected]>
+ Active  mips        mips32         danube      gigaset         sx76x               gigasx76x_nor                        sx76x:SYS_BOOT_NOR                                                                                                                Luka Perkov <[email protected]>
+diff --git a/include/configs/arv752dpw.h b/include/configs/arv752dpw.h
+new file mode 100644
+index 0000000..f6d6092
+--- /dev/null
++++ b/include/configs/arv752dpw.h
+@@ -0,0 +1,67 @@
++/*
++ * Copyright (C) 2012-2013 Luka Perkov <[email protected]>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#define CONFIG_MACH_TYPE	"ARV752DPW"
++#define CONFIG_IDENT_STRING	" "CONFIG_MACH_TYPE
++#define CONFIG_BOARD_NAME	"Arcadyan ARV752DPW"
++
++/* Configure SoC */
++#define CONFIG_LTQ_SUPPORT_UART		/* Enable ASC and UART */
++
++#define CONFIG_LTQ_SUPPORT_ETHERNET	/* Enable ethernet */
++
++#define CONFIG_LTQ_SUPPORT_NOR_FLASH	/* Have a parallel NOR flash */
++
++/* Switch devices */
++#define CONFIG_SWITCH_MULTI
++#define CONFIG_SWITCH_RTL8206
++
++/* Environment */
++#if defined(CONFIG_SYS_BOOT_NOR)
++#define CONFIG_ENV_IS_IN_FLASH
++#define CONFIG_ENV_OVERWRITE
++#define CONFIG_ENV_OFFSET		(192 * 1024)
++#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
++#else
++#define CONFIG_ENV_IS_NOWHERE
++#endif
++
++#define CONFIG_ENV_SIZE			(8 * 1024)
++#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
++
++/* Brnboot loadable image */
++#if defined(CONFIG_SYS_BOOT_BRN)
++#define CONFIG_SYS_TEXT_BASE		0x80002000
++#define CONFIG_SKIP_LOWLEVEL_INIT
++#define CONFIG_SYS_DISABLE_CACHE
++#define CONFIG_ENV_OVERWRITE 1
++#endif
++
++/* Console */
++#define CONFIG_LTQ_ADVANCED_CONSOLE
++#define CONFIG_BAUDRATE			115200
++#define CONFIG_CONSOLE_ASC		1
++#define CONFIG_CONSOLE_DEV		"ttyLTQ1"
++
++/* Pull in default board configs for Lantiq XWAY Danube */
++#include <asm/lantiq/config.h>
++#include <asm/arch/config.h>
++
++/* Pull in default OpenWrt configs for Lantiq SoC */
++#include "openwrt-lantiq-common.h"
++
++#define CONFIG_ENV_UPDATE_UBOOT_NOR		\
++	"update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
++
++#define CONFIG_EXTRA_ENV_SETTINGS	\
++	CONFIG_ENV_LANTIQ_DEFAULTS	\
++	CONFIG_ENV_UPDATE_UBOOT_NOR	\
++	"kernel_addr=0xB0040000\0"
++
++#endif /* __CONFIG_H */
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0038-MIPS-add-board-support-for-Arcadyan-ARV752DPW22.patch

@@ -0,0 +1,264 @@
+From 09f411b4d10f10a62f147264121bb853b4649c3e Mon Sep 17 00:00:00 2001
+From: Oliver Muth <[email protected]>
+Date: Sat, 12 Oct 2013 16:49:53 +0200
+Subject: MIPS: add board support for Arcadyan ARV752DPW22
+
+Signed-off-by: Oliver Muth <[email protected]>
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/board/arcadyan/arv752dpw22/Makefile b/board/arcadyan/arv752dpw22/Makefile
+new file mode 100644
+index 0000000..3a547c2
+--- /dev/null
++++ b/board/arcadyan/arv752dpw22/Makefile
+@@ -0,0 +1,27 @@
++#
++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++include $(TOPDIR)/config.mk
++
++LIB	= $(obj)lib$(BOARD).o
++
++COBJS	= $(BOARD).o
++
++SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS	:= $(addprefix $(obj),$(COBJS))
++SOBJS	:= $(addprefix $(obj),$(SOBJS))
++
++$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
++	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/board/arcadyan/arv752dpw22/arv752dpw22.c b/board/arcadyan/arv752dpw22/arv752dpw22.c
+new file mode 100644
+index 0000000..9b2d89f
+--- /dev/null
++++ b/board/arcadyan/arv752dpw22/arv752dpw22.c
+@@ -0,0 +1,52 @@
++/*
++ * Copyright (C) 2012 Luka Perkov <[email protected]>
++ * Copyright (C) 2013 Oliver Muth <[email protected]>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <common.h>
++#include <switch.h>
++#include <asm/gpio.h>
++#include <asm/lantiq/eth.h>
++#include <asm/lantiq/reset.h>
++#include <asm/lantiq/chipid.h>
++
++int board_early_init_f(void)
++{
++	return 0;
++}
++
++int checkboard(void)
++{
++	puts("Board: " CONFIG_BOARD_NAME "\n");
++	ltq_chip_print_info();
++
++	return 0;
++}
++
++static const struct ltq_eth_port_config eth_port_config[] = {
++	/* MAC0: Atheros ar8216 switch */
++	{ 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_MII },
++};
++
++static const struct ltq_eth_board_config eth_board_config = {
++	.ports = eth_port_config,
++	.num_ports = ARRAY_SIZE(eth_port_config),
++};
++
++int board_eth_init(bd_t *bis)
++{
++	return ltq_eth_initialize(&eth_board_config);
++}
++
++static struct switch_device ar8216_dev = {
++	.name = "ar8216",
++	.cpu_port = 0,
++	.port_mask = 0xF,
++};
++
++int board_switch_init(void)
++{
++	return switch_device_register(&ar8216_dev);
++}
+diff --git a/board/arcadyan/arv752dpw22/config.mk b/board/arcadyan/arv752dpw22/config.mk
+new file mode 100644
+index 0000000..9d8953b
+--- /dev/null
++++ b/board/arcadyan/arv752dpw22/config.mk
+@@ -0,0 +1,7 @@
++#
++# Copyright (C) 2011-2013 Daniel Schwierzeck, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
+diff --git a/board/arcadyan/arv752dpw22/ddr_settings.h b/board/arcadyan/arv752dpw22/ddr_settings.h
+new file mode 100644
+index 0000000..a226322
+--- /dev/null
++++ b/board/arcadyan/arv752dpw22/ddr_settings.h
+@@ -0,0 +1,55 @@
++/*
++ * Copyright (C) 2011-2013 Luka Perkov <[email protected]>
++ *
++ * This file has been generated with lantiq_ram_extract_magic.awk script.     
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#define MC_DC00_VALUE	0x1B1B
++#define MC_DC01_VALUE	0x0
++#define MC_DC02_VALUE	0x0
++#define MC_DC03_VALUE	0x0
++#define MC_DC04_VALUE	0x0
++#define MC_DC05_VALUE	0x200
++#define MC_DC06_VALUE	0x605
++#define MC_DC07_VALUE	0x303
++#define MC_DC08_VALUE	0x102
++#define MC_DC09_VALUE	0x70A
++#define MC_DC10_VALUE	0x203
++#define MC_DC11_VALUE	0xC02
++#define MC_DC12_VALUE	0x1C8
++#define MC_DC13_VALUE	0x1
++#define MC_DC14_VALUE	0x0
++#define MC_DC15_VALUE	0x134
++#define MC_DC16_VALUE	0xC800
++#define MC_DC17_VALUE	0xD
++#define MC_DC18_VALUE	0x301
++#define MC_DC19_VALUE	0x200
++#define MC_DC20_VALUE	0xA03
++#define MC_DC21_VALUE	0x1400
++#define MC_DC22_VALUE	0x1414
++#define MC_DC23_VALUE	0x0
++#define MC_DC24_VALUE	0x5B
++#define MC_DC25_VALUE	0x0
++#define MC_DC26_VALUE	0x0
++#define MC_DC27_VALUE	0x0
++#define MC_DC28_VALUE	0x510
++#define MC_DC29_VALUE	0x4E20
++#define MC_DC30_VALUE	0x8235
++#define MC_DC31_VALUE	0x0
++#define MC_DC32_VALUE	0x0
++#define MC_DC33_VALUE	0x0
++#define MC_DC34_VALUE	0x0
++#define MC_DC35_VALUE	0x0
++#define MC_DC36_VALUE	0x0
++#define MC_DC37_VALUE	0x0
++#define MC_DC38_VALUE	0x0
++#define MC_DC39_VALUE	0x0
++#define MC_DC40_VALUE	0x0
++#define MC_DC41_VALUE	0x0
++#define MC_DC42_VALUE	0x0
++#define MC_DC43_VALUE	0x0
++#define MC_DC44_VALUE	0x0
++#define MC_DC45_VALUE	0x500
++#define MC_DC46_VALUE	0x0
+diff --git a/boards.cfg b/boards.cfg
+index 79cba2d..287f974 100644
+--- a/boards.cfg
++++ b/boards.cfg
+@@ -521,6 +521,9 @@ Active  mips        mips32         danube      arcadyan        arv7518pw
+ Active  mips        mips32         danube      arcadyan        arv752dpw           arv752dpw_brn                        arv752dpw:SYS_BOOT_BRN                                                                                                            -
+ Active  mips        mips32         danube      arcadyan        arv752dpw           arv752dpw_nor                        arv752dpw:SYS_BOOT_NOR                                                                                                            -
+ Active  mips        mips32         danube      arcadyan        arv752dpw           arv752dpw_ram                        arv752dpw:SYS_BOOT_RAM                                                                                                            -
++Active  mips        mips32         danube      arcadyan        arv752dpw22         arv752dpw22_brn                      arv752dpw22:SYS_BOOT_BRN                                                                                                          -
++Active  mips        mips32         danube      arcadyan        arv752dpw22         arv752dpw22_nor                      arv752dpw22:SYS_BOOT_NOR                                                                                                          -
++Active  mips        mips32         danube      arcadyan        arv752dpw22         arv752dpw22_ram                      arv752dpw22:SYS_BOOT_RAM                                                                                                          -
+ Active  mips        mips32         danube      audiocodes      acmp252             acmp252_nor                          acmp252:SYS_BOOT_NOR                                                                                                              Daniel Golle <[email protected]>
+ Active  mips        mips32         danube      audiocodes      acmp252             acmp252_ram                          acmp252:SYS_BOOT_RAM                                                                                                              Daniel Golle <[email protected]>
+ Active  mips        mips32         danube      gigaset         sx76x               gigasx76x_nor                        sx76x:SYS_BOOT_NOR                                                                                                                Luka Perkov <[email protected]>
+diff --git a/include/configs/arv752dpw22.h b/include/configs/arv752dpw22.h
+new file mode 100644
+index 0000000..f17aa70
+--- /dev/null
++++ b/include/configs/arv752dpw22.h
+@@ -0,0 +1,68 @@
++/*
++ * Copyright (C) 2012-2013 Luka Perkov <[email protected]>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#define CONFIG_MACH_TYPE	"ARV752DPW22"
++#define CONFIG_IDENT_STRING	" "CONFIG_MACH_TYPE
++#define CONFIG_BOARD_NAME	"Arcadyan ARV752DPW22"
++
++/* Configure SoC */
++#define CONFIG_LTQ_SUPPORT_UART		/* Enable ASC and UART */
++
++#define CONFIG_LTQ_SUPPORT_ETHERNET	/* Enable ethernet */
++
++#define CONFIG_LTQ_SUPPORT_NOR_FLASH	/* Have a parallel NOR flash */
++
++/* Switch devices */
++#define CONFIG_SWITCH_MULTI
++#define CONFIG_SWITCH_AR8216
++
++/* Environment */
++#if defined(CONFIG_SYS_BOOT_NOR)
++#define CONFIG_ENV_IS_IN_FLASH
++#define CONFIG_ENV_OVERWRITE
++#define CONFIG_ENV_OFFSET		(192 * 1024)
++#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
++#else
++#define CONFIG_ENV_IS_NOWHERE
++#endif
++
++#define CONFIG_ENV_SIZE			(8 * 1024)
++#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
++
++/* Burnboot loadable image */
++#if defined(CONFIG_SYS_BOOT_BRN)
++#define CONFIG_SYS_TEXT_BASE		0x80002000
++#define CONFIG_SKIP_LOWLEVEL_INIT
++#define CONFIG_SYS_DISABLE_CACHE
++#define CONFIG_ENV_OVERWRITE 1
++#endif
++
++
++/* Console */
++#define CONFIG_LTQ_ADVANCED_CONSOLE
++#define CONFIG_BAUDRATE			115200
++#define CONFIG_CONSOLE_ASC		1
++#define CONFIG_CONSOLE_DEV		"ttyLTQ1"
++
++/* Pull in default board configs for Lantiq XWAY Danube */
++#include <asm/lantiq/config.h>
++#include <asm/arch/config.h>
++
++/* Pull in default OpenWrt configs for Lantiq SoC */
++#include "openwrt-lantiq-common.h"
++
++#define CONFIG_ENV_UPDATE_UBOOT_NOR		\
++	"update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
++
++#define CONFIG_EXTRA_ENV_SETTINGS	\
++	CONFIG_ENV_LANTIQ_DEFAULTS	\
++	CONFIG_ENV_UPDATE_UBOOT_NOR	\
++	"kernel_addr=0xB0040000\0"
++
++#endif /* __CONFIG_H */
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0039-MIPS-add-board-support-for-Arcadyan-ARV7510.patch

@@ -0,0 +1,289 @@
+From ba27086a5174130d138d645c2f4a49b08c3f2386 Mon Sep 17 00:00:00 2001
+From: Matti Laakso <[email protected]>
+Date: Sat, 2 Mar 2013 23:34:00 +0100
+Subject: MIPS: add board support for Arcadyan ARV7510
+
+Signed-off-by: Matti Laakso <[email protected]>
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/board/arcadyan/arv7510pw/Makefile b/board/arcadyan/arv7510pw/Makefile
+new file mode 100644
+index 0000000..3a547c2
+--- /dev/null
++++ b/board/arcadyan/arv7510pw/Makefile
+@@ -0,0 +1,27 @@
++#
++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++include $(TOPDIR)/config.mk
++
++LIB	= $(obj)lib$(BOARD).o
++
++COBJS	= $(BOARD).o
++
++SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS	:= $(addprefix $(obj),$(COBJS))
++SOBJS	:= $(addprefix $(obj),$(SOBJS))
++
++$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
++	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/board/arcadyan/arv7510pw/arv7510pw.c b/board/arcadyan/arv7510pw/arv7510pw.c
+new file mode 100644
+index 0000000..6880b4c
+--- /dev/null
++++ b/board/arcadyan/arv7510pw/arv7510pw.c
+@@ -0,0 +1,72 @@
++/*
++ * Copyright (C) 2013 Matti Laakso <[email protected]>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <common.h>
++#include <switch.h>
++#include <asm/gpio.h>
++#include <asm/lantiq/eth.h>
++#include <asm/lantiq/reset.h>
++#include <asm/lantiq/chipid.h>
++#include <asm/lantiq/cpu.h>
++
++static void gpio_init(void)
++{
++	/* Initialize SSIO GPIOs */
++	gpio_set_altfunc(4, 1, 0, 1);
++	gpio_set_altfunc(5, 1, 0, 1);
++	gpio_set_altfunc(6, 1, 0, 1);
++	ltq_gpio_init();
++
++	/* Power led on */
++	gpio_direction_output(76, 1);
++}
++
++int board_early_init_f(void)
++{
++	gpio_init();
++
++	return 0;
++}
++
++int checkboard(void)
++{
++	puts("Board: " CONFIG_BOARD_NAME "\n");
++	ltq_chip_print_info();
++
++	return 0;
++}
++
++static const struct ltq_eth_port_config eth_port_config[] = {
++	/* MAC0: ADM6996I */
++	{ 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
++};
++
++static const struct ltq_eth_board_config eth_board_config = {
++	.ports = eth_port_config,
++	.num_ports = ARRAY_SIZE(eth_port_config),
++};
++
++int board_eth_init(bd_t *bis)
++{
++	return ltq_eth_initialize(&eth_board_config);
++}
++
++static struct switch_device adm6996i_dev = {
++	.name = "adm6996i",
++	.cpu_port = 5,
++	.port_mask = 0xF,
++};
++
++int board_switch_init(void)
++{
++	/* Deactivate HRST line to release reset of ADM6996I switch */
++	ltq_reset_once(LTQ_RESET_HARD, 200000);
++
++	/* ADM6996I needs some time to come out of reset */
++	__udelay(50000);
++
++	return switch_device_register(&adm6996i_dev);
++}
+diff --git a/board/arcadyan/arv7510pw/config.mk b/board/arcadyan/arv7510pw/config.mk
+new file mode 100644
+index 0000000..9d8953b
+--- /dev/null
++++ b/board/arcadyan/arv7510pw/config.mk
+@@ -0,0 +1,7 @@
++#
++# Copyright (C) 2011-2013 Daniel Schwierzeck, [email protected]
++#
++# SPDX-License-Identifier:	GPL-2.0+
++#
++
++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
+diff --git a/board/arcadyan/arv7510pw/ddr_settings.h b/board/arcadyan/arv7510pw/ddr_settings.h
+new file mode 100644
+index 0000000..e63f591
+--- /dev/null
++++ b/board/arcadyan/arv7510pw/ddr_settings.h
+@@ -0,0 +1,53 @@
++/*
++ * Copyright (C) 2013 Matti Laakso <[email protected]>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#define MC_DC00_VALUE	0x1B1B
++#define MC_DC01_VALUE	0x0
++#define MC_DC02_VALUE	0x0
++#define MC_DC03_VALUE	0x0
++#define MC_DC04_VALUE	0x0
++#define MC_DC05_VALUE	0x200
++#define MC_DC06_VALUE	0x605
++#define MC_DC07_VALUE	0x303
++#define MC_DC08_VALUE	0x102
++#define MC_DC09_VALUE	0x70A
++#define MC_DC10_VALUE	0x203
++#define MC_DC11_VALUE	0xC02
++#define MC_DC12_VALUE	0x1C8
++#define MC_DC13_VALUE	0x1
++#define MC_DC14_VALUE	0x0
++#define MC_DC15_VALUE	0x120
++#define MC_DC16_VALUE	0xC800
++#define MC_DC17_VALUE	0xD
++#define MC_DC18_VALUE	0x301
++#define MC_DC19_VALUE	0x200
++#define MC_DC20_VALUE	0xA04
++#define MC_DC21_VALUE	0x1700
++#define MC_DC22_VALUE	0x1717
++#define MC_DC23_VALUE	0x0
++#define MC_DC24_VALUE	0x52
++#define MC_DC25_VALUE	0x0
++#define MC_DC26_VALUE	0x0
++#define MC_DC27_VALUE	0x0
++#define MC_DC28_VALUE	0x510
++#define MC_DC29_VALUE	0x4E20
++#define MC_DC30_VALUE	0x8235
++#define MC_DC31_VALUE	0x0
++#define MC_DC32_VALUE	0x0
++#define MC_DC33_VALUE	0x0
++#define MC_DC34_VALUE	0x0
++#define MC_DC35_VALUE	0x0
++#define MC_DC36_VALUE	0x0
++#define MC_DC37_VALUE	0x0
++#define MC_DC38_VALUE	0x0
++#define MC_DC39_VALUE	0x0
++#define MC_DC40_VALUE	0x0
++#define MC_DC41_VALUE	0x0
++#define MC_DC42_VALUE	0x0
++#define MC_DC43_VALUE	0x0
++#define MC_DC44_VALUE	0x0
++#define MC_DC45_VALUE	0x500
++#define MC_DC46_VALUE	0x0
+diff --git a/boards.cfg b/boards.cfg
+index 287f974..29156d4 100644
+--- a/boards.cfg
++++ b/boards.cfg
+@@ -515,6 +515,9 @@ Active  mips        mips32         au1x00      -               pb1x00
+ Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_brn                        arv4519pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <[email protected]>
+ Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_nor                        arv4519pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <[email protected]>
+ Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_ram                        arv4519pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <[email protected]>
++Active  mips        mips32         danube      arcadyan        arv7510pw           arv7510pw_brn                        arv7510pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <[email protected]>
++Active  mips        mips32         danube      arcadyan        arv7510pw           arv7510pw_nor                        arv7510pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <[email protected]>
++Active  mips        mips32         danube      arcadyan        arv7510pw           arv7510pw_ram                        arv7510pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <[email protected]>
+ Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_brn                        arv7518pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <[email protected]>
+ Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_nor                        arv7518pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <[email protected]>
+ Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_ram                        arv7518pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <[email protected]>
+diff --git a/include/configs/arv7510pw.h b/include/configs/arv7510pw.h
+new file mode 100644
+index 0000000..9eacfa1
+--- /dev/null
++++ b/include/configs/arv7510pw.h
+@@ -0,0 +1,75 @@
++/*
++ * Copyright (C) 2013 Matti Laakso <[email protected]>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#define CONFIG_MACH_TYPE	"ARV7510PW"
++#define CONFIG_IDENT_STRING	" "CONFIG_MACH_TYPE
++#define CONFIG_BOARD_NAME	"Arcadyan ARV7510PW"
++
++/* Configure SoC */
++#define CONFIG_LTQ_SUPPORT_UART		/* Enable ASC and UART */
++#define CONFIG_LTQ_SUPPORT_ETHERNET	/* Enable ethernet */
++#define CONFIG_LTQ_SUPPORT_NOR_FLASH	/* Have a parallel NOR flash */
++
++/* Switch devices */
++#define CONFIG_SWITCH_MULTI
++#define CONFIG_SWITCH_ADM6996I
++
++/* SSIO */
++#define CONFIG_LTQ_SSIO_SHIFT_REGS
++#define CONFIG_LTQ_SSIO_EDGE_FALLING
++#define CONFIG_LTQ_SSIO_GPHY1_MODE	0
++#define CONFIG_LTQ_SSIO_GPHY2_MODE	0
++#define CONFIG_LTQ_SSIO_INIT_VALUE	0
++
++/* Environment */
++#if defined(CONFIG_SYS_BOOT_NOR)
++#define CONFIG_ENV_IS_IN_FLASH
++#define CONFIG_ENV_OVERWRITE
++#define CONFIG_ENV_OFFSET		(256 * 1024)
++#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
++#else
++#define CONFIG_ENV_IS_NOWHERE
++#endif
++
++#define CONFIG_ENV_SIZE			(8 * 1024)
++#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
++
++/* Brnboot loadable image */
++#if defined(CONFIG_SYS_BOOT_BRN)
++#define CONFIG_SYS_TEXT_BASE		0x80002000
++#define CONFIG_SKIP_LOWLEVEL_INIT
++#define CONFIG_SYS_DISABLE_CACHE
++#define CONFIG_ENV_OVERWRITE 1
++#endif
++
++/* Console */
++#define CONFIG_LTQ_ADVANCED_CONSOLE
++#define CONFIG_BAUDRATE			115200
++#define CONFIG_CONSOLE_ASC		1
++#define CONFIG_CONSOLE_DEV		"ttyLTQ1"
++
++/* Pull in default board configs for Lantiq XWAY Danube */
++#include <asm/lantiq/config.h>
++#include <asm/arch/config.h>
++
++/* Buffered write broken in ARV7510PW */
++#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
++
++/* Pull in default OpenWrt configs for Lantiq SoC */
++#include "openwrt-lantiq-common.h"
++
++#define CONFIG_ENV_UPDATE_UBOOT_NOR		\
++	"update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
++
++#define CONFIG_EXTRA_ENV_SETTINGS		\
++	CONFIG_ENV_LANTIQ_DEFAULTS		\
++	CONFIG_ENV_UPDATE_UBOOT_NOR		\
++	"kernel_addr=0xB0060000\0"
++
++#endif /* __CONFIG_H */
+-- 
+1.8.3.2
+

package/boot/uboot-lantiq/patches/0040-Makefile-prepare-u-boot-lantiq-v2013.10-openwrt4.patch

@@ -0,0 +1,23 @@
+From 7e2f79bc40b572763a4a1ed69f63aa2eaa6df254 Mon Sep 17 00:00:00 2001
+From: Daniel Schwierzeck <[email protected]>
+Date: Sun, 20 Oct 2013 19:39:17 +0200
+Subject: Makefile: prepare u-boot-lantiq-v2013.10-openwrt4
+
+Signed-off-by: Daniel Schwierzeck <[email protected]>
+
+diff --git a/Makefile b/Makefile
+index 0445035..d5a55f8 100644
+--- a/Makefile
++++ b/Makefile
+@@ -8,7 +8,7 @@
+ VERSION = 2013
+ PATCHLEVEL = 10
+ SUBLEVEL =
+-EXTRAVERSION =
++EXTRAVERSION = -openwrt4
+ ifneq "$(SUBLEVEL)" ""
+ U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
+ else
+-- 
+1.8.3.2
+