kernel: remove support for kernel 4.19

We use 5.4 on all targets by default, and 4.19 has never been released
in a stable version. There is no reason to keep it.

Signed-off-by: Adrian Schmutzler <[email protected]>

include/kernel-version.mk

@@ -6,10 +6,8 @@ ifdef CONFIG_TESTING_KERNEL
   KERNEL_PATCHVER:=$(KERNEL_TESTING_PATCHVER)
 endif
 
-LINUX_VERSION-4.19 = .138
 LINUX_VERSION-5.4 = .72
 
-LINUX_KERNEL_HASH-4.19.138 = d15c27d05f6c527269b75b30cc72972748e55720e7e00ad8abbaa4fe3b1d5e02
 LINUX_KERNEL_HASH-5.4.72 = 0e24645bd56fe5b55a7a662895f5562c103d71b54d097281f0c9c71ff22c1172
 
 remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1))))

target/linux/apm821xx/config-4.19

@@ -1,335 +0,0 @@
-# CONFIG_40x is not set
-CONFIG_44x=y
-CONFIG_460EX=y
-CONFIG_4xx=y
-CONFIG_4xx_SOC=y
-# CONFIG_ADVANCED_OPTIONS is not set
-CONFIG_APM821xx=y
-CONFIG_APOLLO3G=y
-# CONFIG_ARCHES is not set
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
-CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
-CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
-CONFIG_ARCH_HAS_MEMBARRIER_CALLBACKS=y
-CONFIG_ARCH_HAS_PHYS_TO_DMA=y
-CONFIG_ARCH_HAS_PTE_SPECIAL=y
-CONFIG_ARCH_HAS_SG_CHAIN=y
-CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
-CONFIG_ARCH_HAS_WALK_MEMORY=y
-CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_ARCH_MMAP_RND_BITS=11
-CONFIG_ARCH_MMAP_RND_BITS_MAX=17
-CONFIG_ARCH_MMAP_RND_BITS_MIN=11
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y
-CONFIG_AUDIT_ARCH=y
-# CONFIG_BAMBOO is not set
-CONFIG_BCH=y
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLUESTONE=y
-CONFIG_BOOKE=y
-CONFIG_BOOKE_WDT=y
-# CONFIG_BOUNCE is not set
-CONFIG_BUILD_SALT=""
-# CONFIG_CANYONLANDS is not set
-CONFIG_CC_HAS_SANCOV_TRACE_PC=y
-CONFIG_CC_HAS_STACKPROTECTOR_NONE=y
-CONFIG_CLANG_VERSION=0
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs noinitrd"
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CONSISTENT_SIZE=0x00200000
-CONFIG_CONSOLE_LOGLEVEL_QUIET=4
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRYPTO_ACOMP2=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_AKCIPHER2=y
-CONFIG_CRYPTO_CCM=y
-CONFIG_CRYPTO_CFB=y
-CONFIG_CRYPTO_CTR=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DEV_PPC4XX=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_GCM=y
-CONFIG_CRYPTO_GF128MUL=y
-CONFIG_CRYPTO_GHASH=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_KPP2=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_MD5_PPC=y
-CONFIG_CRYPTO_NULL=y
-CONFIG_CRYPTO_NULL2=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_SHA1_PPC=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DTC=y
-# CONFIG_E200 is not set
-CONFIG_EARLY_PRINTK=y
-# CONFIG_EBONY is not set
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-# CONFIG_EIGER is not set
-CONFIG_EXTRA_TARGETS="uImage"
-CONFIG_FIXED_PHY=y
-CONFIG_FREEZER=y
-# CONFIG_FSL_LBC is not set
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_ISA_DMA=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_NVRAM=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-# CONFIG_GEN_RTC is not set
-# CONFIG_GLACIER is not set
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_FASTPATH_LIMIT=512
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_ARCH_AUDITSYSCALL=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_CBPF_JIT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_GUP=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IOREMAP_PROT=y
-CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KPROBES_ON_FTRACE=y
-CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_RSEQ=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_PPC4XX=y
-CONFIG_HZ=1000
-CONFIG_HZ_1000=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_IBM_IIC=y
-CONFIG_IBM_EMAC=y
-CONFIG_IBM_EMAC_EMAC4=y
-CONFIG_IBM_EMAC_POLL_WEIGHT=32
-CONFIG_IBM_EMAC_RGMII=y
-CONFIG_IBM_EMAC_RXB=128
-CONFIG_IBM_EMAC_RX_COPY_THRESHOLD=256
-CONFIG_IBM_EMAC_RX_SKB_HEADROOM=0
-CONFIG_IBM_EMAC_TAH=y
-CONFIG_IBM_EMAC_TXB=128
-# CONFIG_ICE is not set
-# CONFIG_ICON is not set
-CONFIG_ILLEGAL_POINTER_VALUE=0
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_ISA_DMA_API=y
-# CONFIG_JFFS2_FS is not set
-# CONFIG_KATMAI is not set
-CONFIG_KERNEL_GZIP=y
-CONFIG_KERNEL_START=0xc0000000
-CONFIG_LEDS_TRIGGER_MTD=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOWMEM_SIZE=0x30000000
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-# CONFIG_MATH_EMULATION is not set
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-# CONFIG_MTD_CFI_GEOMETRY is not set
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_BCH=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_BCH=y
-CONFIG_MTD_NAND_ECC_SMC=y
-CONFIG_MTD_NAND_NDFC=y
-# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-# CONFIG_NF_LOG_BRIDGE is not set
-CONFIG_NOT_COHERENT_CACHE=y
-CONFIG_NO_BOOTMEM=y
-CONFIG_NR_IRQS=512
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_NET=y
-CONFIG_OF_RESERVED_MEM=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND=y
-# CONFIG_OVERLAY_FS_METACOPY is not set
-CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
-# CONFIG_OVERLAY_FS_XINO_AUTO is not set
-CONFIG_PAGE_OFFSET=0xc0000000
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_MSI=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYSICAL_START=0x00000000
-CONFIG_PHYS_64BIT=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PM=y
-CONFIG_PM_AUTOSLEEP=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_PM_WAKELOCKS=y
-CONFIG_PM_WAKELOCKS_GC=y
-CONFIG_PM_WAKELOCKS_LIMIT=100
-CONFIG_PPC=y
-CONFIG_PPC32=y
-CONFIG_PPC44x_SIMPLE=y
-CONFIG_PPC4xx_CPM=y
-CONFIG_PPC4xx_GPIO=y
-CONFIG_PPC4xx_MSI=y
-CONFIG_PPC4xx_OCM=y
-CONFIG_PPC4xx_PCI_EXPRESS=y
-# CONFIG_PPC64 is not set
-# CONFIG_PPC_47x is not set
-# CONFIG_PPC_85xx is not set
-# CONFIG_PPC_8xx is not set
-CONFIG_PPC_ADV_DEBUG_DACS=2
-CONFIG_PPC_ADV_DEBUG_DAC_RANGE=y
-CONFIG_PPC_ADV_DEBUG_DVCS=2
-CONFIG_PPC_ADV_DEBUG_IACS=4
-CONFIG_PPC_ADV_DEBUG_REGS=y
-# CONFIG_PPC_BOOK3S_32 is not set
-CONFIG_PPC_DCR=y
-CONFIG_PPC_DCR_NATIVE=y
-# CONFIG_PPC_EARLY_DEBUG is not set
-CONFIG_PPC_FPU=y
-CONFIG_PPC_INDIRECT_PCI=y
-# CONFIG_PPC_IRQ_SOFT_MASK_DEBUG is not set
-CONFIG_PPC_LIB_RHEAP=y
-CONFIG_PPC_MMU_NOHASH=y
-CONFIG_PPC_MSI_BITMAP=y
-CONFIG_PPC_PCI_CHOICE=y
-# CONFIG_PPC_PTDUMP is not set
-CONFIG_PPC_UDBG_16550=y
-CONFIG_PPC_WERROR=y
-CONFIG_PTE_64BIT=y
-# CONFIG_RAINIER is not set
-# CONFIG_RANDOM_TRUST_CPU is not set
-CONFIG_RAS=y
-CONFIG_RD_GZIP=y
-# CONFIG_RENESAS_PHY is not set
-# CONFIG_RPMSG_VIRTIO is not set
-CONFIG_RSEQ=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-# CONFIG_SAM440EP is not set
-# CONFIG_SEQUOIA is not set
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SIMPLE_GPIO=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SRCU=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-# CONFIG_TAISHAN is not set
-CONFIG_TASK_SIZE=0xc0000000
-CONFIG_THREAD_SHIFT=13
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TINY_SRCU=y
-CONFIG_USB_SUPPORT=y
-CONFIG_VDSO32=y
-# CONFIG_VIRTIO_MENU is not set
-# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set
-# CONFIG_WARP is not set
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WNDR4700 is not set
-# CONFIG_XILINX_SYSACE is not set
-# CONFIG_XILINX_VCU is not set
-# CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set
-# CONFIG_XIL_AXIS_FIFO is not set
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_XZ_DEC_POWERPC=y
-# CONFIG_YOSEMITE is not set
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y

target/linux/apm821xx/patches-4.19/010-dt-bindings-dmaengine-dw-dmac-add-protection-control.patch

@@ -1,74 +0,0 @@
-From 538098281ce884a51d2aa4ab445056a41741c6ad Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <[email protected]>
-Date: Sat, 17 Nov 2018 17:17:20 +0100
-Subject: [PATCH] dt-bindings: dmaengine: dw-dmac: add protection control
- property
-
-This patch for the DesignWare AHB Central
-Direct Memory Access Controller adds the dma
-protection control property:
-	"snps,dma-protection-control"
-
-as well as the properties specific values defines into
-a new include file: include/dt-bindings/dma/dw-dmac.h
-
-Note: The protection control signals are one-to-one
-mapped to the AHB HPROT[1:3] signals for this controller.
-The HPROT0 (Data Access) is always hardwired to 1.
-
-Reviewed-by: Andy Shevchenko <[email protected]>
-Reviewed-by: Rob Herring <[email protected]>
-Signed-off-by: Christian Lamparter <[email protected]>
-Signed-off-by: Vinod Koul <[email protected]>
----
- Documentation/devicetree/bindings/dma/snps-dma.txt |  4 ++++
- MAINTAINERS                                        |  4 +++-
- include/dt-bindings/dma/dw-dmac.h                  | 14 ++++++++++++++
- 3 files changed, 21 insertions(+), 1 deletion(-)
- create mode 100644 include/dt-bindings/dma/dw-dmac.h
-
---- a/Documentation/devicetree/bindings/dma/snps-dma.txt
-+++ b/Documentation/devicetree/bindings/dma/snps-dma.txt
-@@ -27,6 +27,10 @@ Optional properties:
-   general purpose DMA channel allocator. False if not passed.
- - multi-block: Multi block transfers supported by hardware. Array property with
-   one cell per channel. 0: not supported, 1 (default): supported.
-+- snps,dma-protection-control: AHB HPROT[3:1] protection setting.
-+  The default value is 0 (for non-cacheable, non-buffered,
-+  unprivileged data access).
-+  Refer to include/dt-bindings/dma/dw-dmac.h for possible values.
- 
- Example:
- 
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -14075,9 +14075,11 @@ SYNOPSYS DESIGNWARE DMAC DRIVER
- M:	Viresh Kumar <[email protected]>
- R:	Andy Shevchenko <[email protected]>
- S:	Maintained
-+F:	Documentation/devicetree/bindings/dma/snps-dma.txt
-+F:	drivers/dma/dw/
-+F:	include/dt-bindings/dma/dw-dmac.h
- F:	include/linux/dma/dw.h
- F:	include/linux/platform_data/dma-dw.h
--F:	drivers/dma/dw/
- 
- SYNOPSYS DESIGNWARE ENTERPRISE ETHERNET DRIVER
- M:	Jose Abreu <[email protected]>
---- /dev/null
-+++ b/include/dt-bindings/dma/dw-dmac.h
-@@ -0,0 +1,14 @@
-+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
-+
-+#ifndef __DT_BINDINGS_DMA_DW_DMAC_H__
-+#define __DT_BINDINGS_DMA_DW_DMAC_H__
-+
-+/*
-+ * Protection Control bits provide protection against illegal transactions.
-+ * The protection bits[0:2] are one-to-one mapped to AHB HPROT[3:1] signals.
-+ */
-+#define DW_DMAC_HPROT1_PRIVILEGED_MODE	(1 << 0)	/* Privileged Mode */
-+#define DW_DMAC_HPROT2_BUFFERABLE	(1 << 1)	/* DMA is bufferable */
-+#define DW_DMAC_HPROT3_CACHEABLE	(1 << 2)	/* DMA is cacheable */
-+
-+#endif /* __DT_BINDINGS_DMA_DW_DMAC_H__ */

target/linux/apm821xx/patches-4.19/023-0003-crypto-drop-mask-CRYPTO_ALG_ASYNC-from-cipher-tfm-al.patch

@@ -1,34 +0,0 @@
-From 1ad0f1603a6b2afb62a1c065409aaa4e43ca7627 Mon Sep 17 00:00:00 2001
-From: Eric Biggers <[email protected]>
-Date: Wed, 14 Nov 2018 12:19:39 -0800
-Subject: [PATCH 03/15] crypto: drop mask=CRYPTO_ALG_ASYNC from 'cipher' tfm
- allocations
-
-'cipher' algorithms (single block ciphers) are always synchronous, so
-passing CRYPTO_ALG_ASYNC in the mask to crypto_alloc_cipher() has no
-effect.  Many users therefore already don't pass it, but some still do.
-This inconsistency can cause confusion, especially since the way the
-'mask' argument works is somewhat counterintuitive.
-
-Thus, just remove the unneeded CRYPTO_ALG_ASYNC flags.
-
-This patch shouldn't change any actual behavior.
-
-Signed-off-by: Eric Biggers <[email protected]>
-Signed-off-by: Herbert Xu <[email protected]>
----
- drivers/crypto/amcc/crypto4xx_alg.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
---- a/drivers/crypto/amcc/crypto4xx_alg.c
-+++ b/drivers/crypto/amcc/crypto4xx_alg.c
-@@ -540,8 +540,7 @@ static int crypto4xx_compute_gcm_hash_ke
- 	uint8_t src[16] = { 0 };
- 	int rc = 0;
- 
--	aes_tfm = crypto_alloc_cipher("aes", 0, CRYPTO_ALG_ASYNC |
--				      CRYPTO_ALG_NEED_FALLBACK);
-+	aes_tfm = crypto_alloc_cipher("aes", 0, CRYPTO_ALG_NEED_FALLBACK);
- 	if (IS_ERR(aes_tfm)) {
- 		rc = PTR_ERR(aes_tfm);
- 		pr_warn("could not load aes cipher driver: %d\n", rc);

target/linux/apm821xx/patches-4.19/023-0004-crypto4xx_core-don-t-abuse-__dma_sync_page.patch

@@ -1,30 +0,0 @@
-From 67d8208fba1324fa0198f9fc58a9edbe09596947 Mon Sep 17 00:00:00 2001
-From: Christoph Hellwig <[email protected]>
-Date: Sun, 16 Dec 2018 18:19:46 +0100
-Subject: [PATCH 04/15] crypto4xx_core: don't abuse __dma_sync_page
-
-This function is internal to the DMA API implementation. Instead use
-the DMA API to properly unmap. Note that the DMA API usage in this
-driver is a disaster and urgently needs some work - it is missing all
-the unmaps, seems to do a secondary map where it looks like it should
-to a unmap in one place to work around cache coherency and the
-directions passed in seem to be partially wrong.
-
-Signed-off-by: Christoph Hellwig <[email protected]>
-Tested-by: Christian Lamparter <[email protected]>
-Signed-off-by: Michael Ellerman <[email protected]>
----
- drivers/crypto/amcc/crypto4xx_core.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/crypto/amcc/crypto4xx_core.c
-+++ b/drivers/crypto/amcc/crypto4xx_core.c
-@@ -592,7 +592,7 @@ static void crypto4xx_aead_done(struct c
- 					  pd->pd_ctl_len.bf.pkt_len,
- 					  dst);
- 	} else {
--		__dma_sync_page(sg_page(dst), dst->offset, dst->length,
-+		dma_unmap_page(dev->core_dev->device, pd->dest, dst->length,
- 				DMA_FROM_DEVICE);
- 	}
- 

target/linux/apm821xx/patches-4.19/023-0005-cross-tree-phase-out-dma_zalloc_coherent.patch

@@ -1,40 +0,0 @@
-From 750afb08ca71310fcf0c4e2cb1565c63b8235b60 Mon Sep 17 00:00:00 2001
-From: Luis Chamberlain <[email protected]>
-Date: Fri, 4 Jan 2019 09:23:09 +0100
-Subject: [PATCH 05/15] cross-tree: phase out dma_zalloc_coherent()
-
-We already need to zero out memory for dma_alloc_coherent(), as such
-using dma_zalloc_coherent() is superflous. Phase it out.
-
-This change was generated with the following Coccinelle SmPL patch:
-
-@ replace_dma_zalloc_coherent @
-expression dev, size, data, handle, flags;
-@@
-
--dma_zalloc_coherent(dev, size, handle, flags)
-+dma_alloc_coherent(dev, size, handle, flags)
-
-Suggested-by: Christoph Hellwig <[email protected]>
-Signed-off-by: Luis Chamberlain <[email protected]>
-[hch: re-ran the script on the latest tree]
-Signed-off-by: Christoph Hellwig <[email protected]>
----
- drivers/crypto/amcc/crypto4xx_core.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/drivers/crypto/amcc/crypto4xx_core.c
-+++ b/drivers/crypto/amcc/crypto4xx_core.c
-@@ -283,9 +283,9 @@ static u32 crypto4xx_put_pd_to_pdr(struc
-  */
- static u32 crypto4xx_build_gdr(struct crypto4xx_device *dev)
- {
--	dev->gdr = dma_zalloc_coherent(dev->core_dev->device,
--				       sizeof(struct ce_gd) * PPC4XX_NUM_GD,
--				       &dev->gdr_pa, GFP_ATOMIC);
-+	dev->gdr = dma_alloc_coherent(dev->core_dev->device,
-+				      sizeof(struct ce_gd) * PPC4XX_NUM_GD,
-+				      &dev->gdr_pa, GFP_ATOMIC);
- 	if (!dev->gdr)
- 		return -ENOMEM;
- 

target/linux/apm821xx/patches-4.19/023-0006-crypto-crypto4xx-add-prng-crypto-support.patch

@@ -1,199 +0,0 @@
-From d072bfa4885354fff86aa1fb1dbc4f1533c9e0bf Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <[email protected]>
-Date: Sun, 23 Dec 2018 02:16:13 +0100
-Subject: [PATCH 06/15] crypto: crypto4xx - add prng crypto support
-
-This patch adds support for crypto4xx's ANSI X9.17 Annex C compliant
-pseudo random number generator which provides a pseudo random source
-for the purpose of generating  Initialization Vectors (IV's) for AES
-algorithms to the Packet Engine and other pseudo random number
-requirements.
-
-Signed-off-by: Christian Lamparter <[email protected]>
-Signed-off-by: Herbert Xu <[email protected]>
----
- drivers/crypto/amcc/crypto4xx_core.c    | 87 +++++++++++++++++++++++++
- drivers/crypto/amcc/crypto4xx_core.h    |  4 ++
- drivers/crypto/amcc/crypto4xx_reg_def.h |  1 +
- 3 files changed, 92 insertions(+)
-
---- a/drivers/crypto/amcc/crypto4xx_core.c
-+++ b/drivers/crypto/amcc/crypto4xx_core.c
-@@ -40,9 +40,11 @@
- #include <crypto/ctr.h>
- #include <crypto/gcm.h>
- #include <crypto/sha.h>
-+#include <crypto/rng.h>
- #include <crypto/scatterwalk.h>
- #include <crypto/skcipher.h>
- #include <crypto/internal/aead.h>
-+#include <crypto/internal/rng.h>
- #include <crypto/internal/skcipher.h>
- #include "crypto4xx_reg_def.h"
- #include "crypto4xx_core.h"
-@@ -1042,6 +1044,10 @@ static int crypto4xx_register_alg(struct
- 			rc = crypto_register_ahash(&alg->alg.u.hash);
- 			break;
- 
-+		case CRYPTO_ALG_TYPE_RNG:
-+			rc = crypto_register_rng(&alg->alg.u.rng);
-+			break;
-+
- 		default:
- 			rc = crypto_register_skcipher(&alg->alg.u.cipher);
- 			break;
-@@ -1071,6 +1077,10 @@ static void crypto4xx_unregister_alg(str
- 			crypto_unregister_aead(&alg->alg.u.aead);
- 			break;
- 
-+		case CRYPTO_ALG_TYPE_RNG:
-+			crypto_unregister_rng(&alg->alg.u.rng);
-+			break;
-+
- 		default:
- 			crypto_unregister_skcipher(&alg->alg.u.cipher);
- 		}
-@@ -1129,6 +1139,69 @@ static irqreturn_t crypto4xx_ce_interrup
- 		PPC4XX_TMO_ERR_INT);
- }
- 
-+static int ppc4xx_prng_data_read(struct crypto4xx_device *dev,
-+				 u8 *data, unsigned int max)
-+{
-+	unsigned int i, curr = 0;
-+	u32 val[2];
-+
-+	do {
-+		/* trigger PRN generation */
-+		writel(PPC4XX_PRNG_CTRL_AUTO_EN,
-+		       dev->ce_base + CRYPTO4XX_PRNG_CTRL);
-+
-+		for (i = 0; i < 1024; i++) {
-+			/* usually 19 iterations are enough */
-+			if ((readl(dev->ce_base + CRYPTO4XX_PRNG_STAT) &
-+			     CRYPTO4XX_PRNG_STAT_BUSY))
-+				continue;
-+
-+			val[0] = readl_be(dev->ce_base + CRYPTO4XX_PRNG_RES_0);
-+			val[1] = readl_be(dev->ce_base + CRYPTO4XX_PRNG_RES_1);
-+			break;
-+		}
-+		if (i == 1024)
-+			return -ETIMEDOUT;
-+
-+		if ((max - curr) >= 8) {
-+			memcpy(data, &val, 8);
-+			data += 8;
-+			curr += 8;
-+		} else {
-+			/* copy only remaining bytes */
-+			memcpy(data, &val, max - curr);
-+			break;
-+		}
-+	} while (curr < max);
-+
-+	return curr;
-+}
-+
-+static int crypto4xx_prng_generate(struct crypto_rng *tfm,
-+				   const u8 *src, unsigned int slen,
-+				   u8 *dstn, unsigned int dlen)
-+{
-+	struct rng_alg *alg = crypto_rng_alg(tfm);
-+	struct crypto4xx_alg *amcc_alg;
-+	struct crypto4xx_device *dev;
-+	int ret;
-+
-+	amcc_alg = container_of(alg, struct crypto4xx_alg, alg.u.rng);
-+	dev = amcc_alg->dev;
-+
-+	mutex_lock(&dev->core_dev->rng_lock);
-+	ret = ppc4xx_prng_data_read(dev, dstn, dlen);
-+	mutex_unlock(&dev->core_dev->rng_lock);
-+	return ret;
-+}
-+
-+
-+static int crypto4xx_prng_seed(struct crypto_rng *tfm, const u8 *seed,
-+			unsigned int slen)
-+{
-+	return 0;
-+}
-+
- /**
-  * Supported Crypto Algorithms
-  */
-@@ -1298,6 +1371,18 @@ static struct crypto4xx_alg_common crypt
- 			.cra_module	= THIS_MODULE,
- 		},
- 	} },
-+	{ .type = CRYPTO_ALG_TYPE_RNG, .u.rng = {
-+		.base = {
-+			.cra_name		= "stdrng",
-+			.cra_driver_name        = "crypto4xx_rng",
-+			.cra_priority		= 300,
-+			.cra_ctxsize		= 0,
-+			.cra_module		= THIS_MODULE,
-+		},
-+		.generate               = crypto4xx_prng_generate,
-+		.seed                   = crypto4xx_prng_seed,
-+		.seedsize               = 0,
-+	} },
- };
- 
- /**
-@@ -1367,6 +1452,7 @@ static int crypto4xx_probe(struct platfo
- 	core_dev->dev->core_dev = core_dev;
- 	core_dev->dev->is_revb = is_revb;
- 	core_dev->device = dev;
-+	mutex_init(&core_dev->rng_lock);
- 	spin_lock_init(&core_dev->lock);
- 	INIT_LIST_HEAD(&core_dev->dev->alg_list);
- 	ratelimit_default_init(&core_dev->dev->aead_ratelimit);
-@@ -1446,6 +1532,7 @@ static int crypto4xx_remove(struct platf
- 	tasklet_kill(&core_dev->tasklet);
- 	/* Un-register with Linux CryptoAPI */
- 	crypto4xx_unregister_alg(core_dev->dev);
-+	mutex_destroy(&core_dev->rng_lock);
- 	/* Free all allocated memory */
- 	crypto4xx_stop_all(core_dev);
- 
---- a/drivers/crypto/amcc/crypto4xx_core.h
-+++ b/drivers/crypto/amcc/crypto4xx_core.h
-@@ -23,8 +23,10 @@
- #define __CRYPTO4XX_CORE_H__
- 
- #include <linux/ratelimit.h>
-+#include <linux/mutex.h>
- #include <crypto/internal/hash.h>
- #include <crypto/internal/aead.h>
-+#include <crypto/internal/rng.h>
- #include <crypto/internal/skcipher.h>
- #include "crypto4xx_reg_def.h"
- #include "crypto4xx_sa.h"
-@@ -119,6 +121,7 @@ struct crypto4xx_core_device {
- 	u32 irq;
- 	struct tasklet_struct tasklet;
- 	spinlock_t lock;
-+	struct mutex rng_lock;
- };
- 
- struct crypto4xx_ctx {
-@@ -143,6 +146,7 @@ struct crypto4xx_alg_common {
- 		struct skcipher_alg cipher;
- 		struct ahash_alg hash;
- 		struct aead_alg aead;
-+		struct rng_alg rng;
- 	} u;
- };
- 
---- a/drivers/crypto/amcc/crypto4xx_reg_def.h
-+++ b/drivers/crypto/amcc/crypto4xx_reg_def.h
-@@ -100,6 +100,7 @@
- #define CRYPTO4XX_ENDIAN_CFG			0x000600d8
- 
- #define CRYPTO4XX_PRNG_STAT			0x00070000
-+#define CRYPTO4XX_PRNG_STAT_BUSY		0x1
- #define CRYPTO4XX_PRNG_CTRL			0x00070004
- #define CRYPTO4XX_PRNG_SEED_L			0x00070008
- #define CRYPTO4XX_PRNG_SEED_H			0x0007000c

target/linux/apm821xx/patches-4.19/023-0012-crypto-crypto4xx-get-rid-of-redundant-using_sd-varia.patch

@@ -1,63 +0,0 @@
-From 38cf5533d7a876f75088bacc1277046f30005f28 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <[email protected]>
-Date: Mon, 22 Apr 2019 13:26:01 +0200
-Subject: [PATCH 12/15] crypto: crypto4xx - get rid of redundant using_sd
- variable
-
-using_sd is used as a stand-in for sa_command_0.bf.scatter
-that we need to set anyway, so we might as well just prevent
-double-accounting.
-
-Signed-off-by: Christian Lamparter <[email protected]>
-Signed-off-by: Herbert Xu <[email protected]>
----
- drivers/crypto/amcc/crypto4xx_core.c | 6 ++----
- drivers/crypto/amcc/crypto4xx_core.h | 1 -
- 2 files changed, 2 insertions(+), 5 deletions(-)
-
---- a/drivers/crypto/amcc/crypto4xx_core.c
-+++ b/drivers/crypto/amcc/crypto4xx_core.c
-@@ -535,7 +535,7 @@ static void crypto4xx_cipher_done(struct
- 
- 	req = skcipher_request_cast(pd_uinfo->async_req);
- 
--	if (pd_uinfo->using_sd) {
-+	if (pd_uinfo->sa_va->sa_command_0.bf.scatter) {
- 		crypto4xx_copy_pkt_to_dst(dev, pd, pd_uinfo,
- 					  req->cryptlen, req->dst);
- 	} else {
-@@ -589,7 +589,7 @@ static void crypto4xx_aead_done(struct c
- 	u32 icv[AES_BLOCK_SIZE];
- 	int err = 0;
- 
--	if (pd_uinfo->using_sd) {
-+	if (pd_uinfo->sa_va->sa_command_0.bf.scatter) {
- 		crypto4xx_copy_pkt_to_dst(dev, pd, pd_uinfo,
- 					  pd->pd_ctl_len.bf.pkt_len,
- 					  dst);
-@@ -883,7 +883,6 @@ int crypto4xx_build_pd(struct crypto_asy
- 		 * we know application give us dst a whole piece of memory
- 		 * no need to use scatter ring.
- 		 */
--		pd_uinfo->using_sd = 0;
- 		pd_uinfo->first_sd = 0xffffffff;
- 		sa->sa_command_0.bf.scatter = 0;
- 		pd->dest = (u32)dma_map_page(dev->core_dev->device,
-@@ -897,7 +896,6 @@ int crypto4xx_build_pd(struct crypto_asy
- 		u32 sd_idx = fst_sd;
- 		nbytes = datalen;
- 		sa->sa_command_0.bf.scatter = 1;
--		pd_uinfo->using_sd = 1;
- 		pd_uinfo->first_sd = fst_sd;
- 		sd = crypto4xx_get_sdp(dev, &sd_dma, sd_idx);
- 		pd->dest = sd_dma;
---- a/drivers/crypto/amcc/crypto4xx_core.h
-+++ b/drivers/crypto/amcc/crypto4xx_core.h
-@@ -64,7 +64,6 @@ union shadow_sa_buf {
- struct pd_uinfo {
- 	struct crypto4xx_device *dev;
- 	u32   state;
--	u32 using_sd;
- 	u32 first_gd;		/* first gather discriptor
- 				used by this packet */
- 	u32 num_gd;             /* number of gather discriptor

target/linux/apm821xx/patches-4.19/140-GPIO-add-named-gpio-exports.patch

@@ -1,169 +0,0 @@
-From cc809a441d8f2924f785eb863dfa6aef47a25b0b Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Tue, 12 Aug 2014 20:49:27 +0200
-Subject: [PATCH 30/36] GPIO: add named gpio exports
-
-Signed-off-by: John Crispin <[email protected]>
----
- drivers/gpio/gpiolib-of.c     |   68 +++++++++++++++++++++++++++++++++++++++++
- drivers/gpio/gpiolib.c        |   11 +++++--
- include/asm-generic/gpio.h    |    5 +++
- include/linux/gpio/consumer.h |    8 +++++
- 4 files changed, 90 insertions(+), 2 deletions(-)
-
---- a/drivers/gpio/gpiolib-of.c
-+++ b/drivers/gpio/gpiolib-of.c
-@@ -23,6 +23,8 @@
- #include <linux/pinctrl/pinctrl.h>
- #include <linux/slab.h>
- #include <linux/gpio/machine.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
- 
- #include "gpiolib.h"
- 
-@@ -660,3 +662,72 @@ void of_gpiochip_remove(struct gpio_chip
- 	gpiochip_remove_pin_ranges(chip);
- 	of_node_put(chip->of_node);
- }
-+
-+#ifdef CONFIG_GPIO_SYSFS
-+
-+static struct of_device_id gpio_export_ids[] = {
-+	{ .compatible = "gpio-export" },
-+	{ /* sentinel */ }
-+};
-+
-+static int of_gpio_export_probe(struct platform_device *pdev)
-+{
-+	struct device_node *np = pdev->dev.of_node;
-+	struct device_node *cnp;
-+	u32 val;
-+	int nb = 0;
-+
-+	for_each_child_of_node(np, cnp) {
-+		const char *name = NULL;
-+		int gpio;
-+		bool dmc;
-+		int max_gpio = 1;
-+		int i;
-+
-+		of_property_read_string(cnp, "gpio-export,name", &name);
-+
-+		if (!name)
-+			max_gpio = of_gpio_count(cnp);
-+
-+		for (i = 0; i < max_gpio; i++) {
-+			unsigned flags = 0;
-+			enum of_gpio_flags of_flags;
-+
-+			gpio = of_get_gpio_flags(cnp, i, &of_flags);
-+			if (!gpio_is_valid(gpio))
-+				return gpio;
-+
-+			if (of_flags == OF_GPIO_ACTIVE_LOW)
-+				flags |= GPIOF_ACTIVE_LOW;
-+
-+			if (!of_property_read_u32(cnp, "gpio-export,output", &val))
-+				flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
-+			else
-+				flags |= GPIOF_IN;
-+
-+			if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np)))
-+				continue;
-+
-+			dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change");
-+			gpio_export_with_name(gpio, dmc, name);
-+			nb++;
-+		}
-+	}
-+
-+	dev_info(&pdev->dev, "%d gpio(s) exported\n", nb);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver gpio_export_driver = {
-+	.driver		= {
-+		.name		= "gpio-export",
-+		.owner	= THIS_MODULE,
-+		.of_match_table	= of_match_ptr(gpio_export_ids),
-+	},
-+	.probe		= of_gpio_export_probe,
-+};
-+
-+module_platform_driver(gpio_export_driver);
-+
-+#endif
---- a/include/asm-generic/gpio.h
-+++ b/include/asm-generic/gpio.h
-@@ -127,6 +127,12 @@ static inline int gpio_export(unsigned g
- 	return gpiod_export(gpio_to_desc(gpio), direction_may_change);
- }
- 
-+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
-+static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name)
-+{
-+	return __gpiod_export(gpio_to_desc(gpio), direction_may_change, name);
-+}
-+
- static inline int gpio_export_link(struct device *dev, const char *name,
- 				   unsigned gpio)
- {
---- a/include/linux/gpio/consumer.h
-+++ b/include/linux/gpio/consumer.h
-@@ -533,6 +533,7 @@ struct gpio_desc *devm_fwnode_get_gpiod_
- 
- #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS)
- 
-+int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
- int gpiod_export(struct gpio_desc *desc, bool direction_may_change);
- int gpiod_export_link(struct device *dev, const char *name,
- 		      struct gpio_desc *desc);
-@@ -540,6 +541,13 @@ void gpiod_unexport(struct gpio_desc *de
- 
- #else  /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */
- 
-+static inline int _gpiod_export(struct gpio_desc *desc,
-+			       bool direction_may_change,
-+			       const char *name)
-+{
-+	return -ENOSYS;
-+}
-+
- static inline int gpiod_export(struct gpio_desc *desc,
- 			       bool direction_may_change)
- {
---- a/drivers/gpio/gpiolib-sysfs.c
-+++ b/drivers/gpio/gpiolib-sysfs.c
-@@ -568,7 +568,7 @@ static struct class gpio_class = {
-  *
-  * Returns zero on success, else an error.
-  */
--int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
-+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name)
- {
- 	struct gpio_chip	*chip;
- 	struct gpio_device	*gdev;
-@@ -630,6 +630,8 @@ int gpiod_export(struct gpio_desc *desc,
- 	offset = gpio_chip_hwgpio(desc);
- 	if (chip->names && chip->names[offset])
- 		ioname = chip->names[offset];
-+	if (name)
-+		ioname = name;
- 
- 	dev = device_create_with_groups(&gpio_class, &gdev->dev,
- 					MKDEV(0, 0), data, gpio_groups,
-@@ -651,6 +653,12 @@ err_unlock:
- 	gpiod_dbg(desc, "%s: status %d\n", __func__, status);
- 	return status;
- }
-+EXPORT_SYMBOL_GPL(__gpiod_export);
-+
-+int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
-+{
-+	return __gpiod_export(desc, direction_may_change, NULL);
-+}
- EXPORT_SYMBOL_GPL(gpiod_export);
- 
- static int match_export(struct device *dev, const void *desc)

target/linux/apm821xx/patches-4.19/201-add-amcc-apollo3g-support.patch

@@ -1,30 +0,0 @@
---- a/arch/powerpc/platforms/44x/Kconfig
-+++ b/arch/powerpc/platforms/44x/Kconfig
-@@ -131,6 +131,17 @@ config CANYONLANDS
- 	help
- 	  This option enables support for the AMCC PPC460EX evaluation board.
- 
-+config APOLLO3G
-+	bool "Apollo3G"
-+	depends on 44x
-+	default n
-+	select PPC44x_SIMPLE
-+	select APM821xx
-+	select IBM_EMAC_RGMII
-+	select 460EX
-+	help
-+	  This option enables support for the AMCC Apollo 3G board.
-+
- config GLACIER
- 	bool "Glacier"
- 	depends on 44x
---- a/arch/powerpc/platforms/44x/ppc44x_simple.c
-+++ b/arch/powerpc/platforms/44x/ppc44x_simple.c
-@@ -50,6 +50,7 @@ machine_device_initcall(ppc44x_simple, p
-  * board.c file for it rather than adding it to this list.
-  */
- static char *board[] __initdata = {
-+	"amcc,apollo3g",
- 	"amcc,arches",
- 	"amcc,bamboo",
- 	"apm,bluestone",

target/linux/apm821xx/patches-4.19/202-add-netgear-wndr4700-support.patch

@@ -1,32 +0,0 @@
---- a/arch/powerpc/platforms/44x/Makefile
-+++ b/arch/powerpc/platforms/44x/Makefile
-@@ -4,6 +4,7 @@ ifneq ($(CONFIG_PPC4xx_CPM),y)
- obj-y	+= idle.o
- endif
- obj-$(CONFIG_PPC44x_SIMPLE) += ppc44x_simple.o
-+obj-$(CONFIG_WNDR4700) += wndr4700.o
- obj-$(CONFIG_EBONY)	+= ebony.o
- obj-$(CONFIG_SAM440EP) 	+= sam440ep.o
- obj-$(CONFIG_WARP)	+= warp.o
---- a/arch/powerpc/platforms/44x/Kconfig
-+++ b/arch/powerpc/platforms/44x/Kconfig
-@@ -260,6 +260,19 @@ config ICON
- 	help
- 	  This option enables support for the AMCC PPC440SPe evaluation board.
- 
-+config WNDR4700
-+	bool "WNDR4700"
-+	depends on 44x
-+	default n
-+	select APM821xx
-+	select PCI_MSI
-+	select PPC4xx_MSI
-+	select PPC4xx_PCI_EXPRESS
-+	select IBM_EMAC_RGMII
-+	select 460EX
-+	help
-+	  This option enables support for the Netgear WNDR4700/WNDR4720 board.
-+
- config XILINX_VIRTEX440_GENERIC_BOARD
- 	bool "Generic Xilinx Virtex 5 FXT board support"
- 	depends on 44x

target/linux/apm821xx/patches-4.19/300-fix-atheros-nics-on-apm82181.patch

@@ -1,51 +0,0 @@
---- a/arch/powerpc/platforms/4xx/pci.c
-+++ b/arch/powerpc/platforms/4xx/pci.c
-@@ -1060,15 +1060,24 @@ static int __init apm821xx_pciex_init_po
- 	u32 val;
- 
- 	/*
--	 * Do a software reset on PCIe ports.
--	 * This code is to fix the issue that pci drivers doesn't re-assign
--	 * bus number for PCIE devices after Uboot
--	 * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
--	 * PT quad port, SAS LSI 1064E)
-+	 * Only reset the PHY when no link is currently established.
-+	 * This is for the Atheros PCIe board which has problems to establish
-+	 * the link (again) after this PHY reset. All other currently tested
-+	 * PCIe boards don't show this problem.
- 	 */
--
--	mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
--	mdelay(10);
-+	val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
-+	if (!(val & 0x00001000)) {
-+		/*
-+		 * Do a software reset on PCIe ports.
-+		 * This code is to fix the issue that pci drivers doesn't re-assign
-+		 * bus number for PCIE devices after Uboot
-+		 * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
-+		 * PT quad port, SAS LSI 1064E)
-+		 */
-+
-+		mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
-+		mdelay(10);
-+	}
- 
- 	if (port->endpoint)
- 		val = PTYPE_LEGACY_ENDPOINT << 20;
-@@ -1085,9 +1094,12 @@ static int __init apm821xx_pciex_init_po
- 	mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
- 	mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
- 
--	mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
--	mdelay(50);
--	mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
-+	val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
-+	if (!(val & 0x00001000)) {
-+		mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
-+		mdelay(50);
-+		mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
-+	}
- 
- 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
- 		mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |

target/linux/apm821xx/patches-4.19/301-fix-memory-map-wndr4700.patch

@@ -1,14 +0,0 @@
---- a/arch/powerpc/platforms/4xx/pci.c
-+++ b/arch/powerpc/platforms/4xx/pci.c
-@@ -1903,9 +1903,9 @@ static void __init ppc4xx_configure_pcie
- 		 * if it works
- 		 */
- 		out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
--		out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
-+		out_le32(mbase + PECFG_PIM0LAH, 0x00000008);
- 		out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
--		out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
-+		out_le32(mbase + PECFG_PIM1LAH, 0x0000000c);
- 		out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
- 		out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
- 

target/linux/apm821xx/patches-4.19/801-usb-xhci-add-firmware-loader-for-uPD720201-and-uPD72.patch

@@ -1,545 +0,0 @@
-From 419992bae5aaa4e06402e0b7c79fcf7bcb6b4764 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <[email protected]>
-Date: Thu, 2 Jun 2016 00:48:46 +0200
-Subject: [PATCH] usb: xhci: add firmware loader for uPD720201 and uPD720202
- w/o ROM
-
-This patch adds a firmware loader for the uPD720201K8-711-BAC-A
-and uPD720202K8-711-BAA-A variant. Both of these chips are listed
-in Renesas' R19UH0078EJ0500 Rev.5.00 "User's Manual: Hardware" as
-devices which need the firmware loader on page 2 in order to
-work as they "do not support the External ROM".
-
-The "Firmware Download Sequence" is describe in chapter
-"7.1 FW Download Interface" R19UH0078EJ0500 Rev.5.00 page 131.
-
-The firmware "K2013080.mem" is available from a USB3.0 Host to
-PCIe Adapter (PP2U-E card) "Firmware download" archive. An
-alternative version can be sourced from Netgear's WNDR4700 GPL
-archives.
-
-The release notes of the PP2U-E's "Firmware Download" ver 2.0.1.3
-(2012-06-15) state that the firmware is for the following devices:
- - uPD720201 ES 2.0 sample whose revision ID is 2.
- - uPD720201 ES 2.1 sample & CS sample & Mass product, ID is 3.
- - uPD720202 ES 2.0 sample & CS sample & Mass product, ID is 2.
-
-If someone from Renesas is listening: It would be great, if these
-firmwares could be added to linux-firmware.git.
-
-Cc: Yoshihiro Shimoda <[email protected]>
-Signed-off-by: Christian Lamparter <[email protected]>
----
- drivers/usb/host/xhci-pci.c | 492 ++++++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 492 insertions(+)
-
---- a/drivers/usb/host/xhci-pci.c
-+++ b/drivers/usb/host/xhci-pci.c
-@@ -12,6 +12,8 @@
- #include <linux/slab.h>
- #include <linux/module.h>
- #include <linux/acpi.h>
-+#include <linux/firmware.h>
-+#include <asm/unaligned.h>
- 
- #include "xhci.h"
- #include "xhci-trace.h"
-@@ -268,6 +270,458 @@ static void xhci_pme_acpi_rtd3_enable(st
- static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
- #endif /* CONFIG_ACPI */
- 
-+static const struct renesas_fw_entry {
-+	const char *firmware_name;
-+	u16 device;
-+	u8 revision;
-+	u16 expected_version;
-+} renesas_fw_table[] = {
-+	/*
-+	 * Only the uPD720201K8-711-BAC-A or uPD720202K8-711-BAA-A
-+	 * are listed in R19UH0078EJ0500 Rev.5.00 as devices which
-+	 * need the software loader.
-+	 *
-+	 * PP2U/ReleaseNote_USB3-201-202-FW.txt:
-+	 *
-+	 * Note: This firmware is for the following devices.
-+	 *  - uPD720201 ES 2.0 sample whose revision ID is 2.
-+	 *  - uPD720201 ES 2.1 sample & CS sample & Mass product, ID is 3.
-+	 *  - uPD720202 ES 2.0 sample & CS sample & Mass product, ID is 2.
-+	 */
-+	{ "K2013080.mem", 0x0014, 0x02, 0x2013 },
-+	{ "K2013080.mem", 0x0014, 0x03, 0x2013 },
-+	{ "K2013080.mem", 0x0015, 0x02, 0x2013 },
-+};
-+
-+static const struct renesas_fw_entry *renesas_needs_fw_dl(struct pci_dev *dev)
-+{
-+	const struct renesas_fw_entry *entry;
-+	size_t i;
-+
-+	/* This loader will only work with a RENESAS device. */
-+	if (!(dev->vendor == PCI_VENDOR_ID_RENESAS))
-+		return NULL;
-+
-+	for (i = 0; i < ARRAY_SIZE(renesas_fw_table); i++) {
-+		entry = &renesas_fw_table[i];
-+		if (entry->device == dev->device &&
-+		    entry->revision == dev->revision)
-+			return entry;
-+	}
-+
-+	return NULL;
-+}
-+
-+static int renesas_fw_download_image(struct pci_dev *dev,
-+				     const u32 *fw,
-+				     size_t step)
-+{
-+	size_t i;
-+	int err;
-+	u8 fw_status;
-+	bool data0_or_data1;
-+
-+	/*
-+	 * The hardware does alternate between two 32-bit pages.
-+	 * (This is because each row of the firmware is 8 bytes).
-+	 *
-+	 * for even steps we use DATA0, for odd steps DATA1.
-+	 */
-+	data0_or_data1 = (step & 1) == 1;
-+
-+	/* step+1. Read "Set DATAX" and confirm it is cleared. */
-+	for (i = 0; i < 10000; i++) {
-+		err = pci_read_config_byte(dev, 0xF5, &fw_status);
-+		if (err)
-+			return pcibios_err_to_errno(err);
-+		if (!(fw_status & BIT(data0_or_data1)))
-+			break;
-+
-+		udelay(1);
-+	}
-+	if (i == 10000)
-+		return -ETIMEDOUT;
-+
-+	/*
-+	 * step+2. Write FW data to "DATAX".
-+	 * "LSB is left" => force little endian
-+	 */
-+	err = pci_write_config_dword(dev, data0_or_data1 ? 0xFC : 0xF8,
-+				     (__force u32) cpu_to_le32(fw[step]));
-+	if (err)
-+		return pcibios_err_to_errno(err);
-+
-+	udelay(100);
-+
-+	/* step+3. Set "Set DATAX". */
-+	err = pci_write_config_byte(dev, 0xF5, BIT(data0_or_data1));
-+	if (err)
-+		return pcibios_err_to_errno(err);
-+
-+	return 0;
-+}
-+
-+static int renesas_fw_verify(struct pci_dev *dev,
-+			     const void *fw_data,
-+			     size_t length)
-+{
-+	const struct renesas_fw_entry *entry = renesas_needs_fw_dl(dev);
-+	u16 fw_version_pointer;
-+	u16 fw_version;
-+
-+	if (!entry)
-+		return -EINVAL;
-+
-+	/*
-+	 * The Firmware's Data Format is describe in
-+	 * "6.3 Data Format" R19UH0078EJ0500 Rev.5.00 page 124
-+	 */
-+
-+	/* "Each row is 8 bytes". => firmware size must be a multiple of 8. */
-+	if (length % 8 != 0) {
-+		dev_err(&dev->dev, "firmware size is not a multipe of 8.");
-+		return -EINVAL;
-+	}
-+
-+	/*
-+	 * The bootrom chips of the big brother have sizes up to 64k, let's
-+	 * assume that's the biggest the firmware can get.
-+	 */
-+	if (length < 0x1000 || length >= 0x10000) {
-+		dev_err(&dev->dev, "firmware is size %zd is not (4k - 64k).",
-+			length);
-+		return -EINVAL;
-+	}
-+
-+	/* The First 2 bytes are fixed value (55aa). "LSB on Left" */
-+	if (get_unaligned_le16(fw_data) != 0x55aa) {
-+		dev_err(&dev->dev, "no valid firmware header found.");
-+		return -EINVAL;
-+	}
-+
-+	/* verify the firmware version position and print it. */
-+	fw_version_pointer = get_unaligned_le16(fw_data + 4);
-+	if (fw_version_pointer + 2 >= length) {
-+		dev_err(&dev->dev, "firmware version pointer is outside of the firmware image.");
-+		return -EINVAL;
-+	}
-+
-+	fw_version = get_unaligned_le16(fw_data + fw_version_pointer);
-+	dev_dbg(&dev->dev, "got firmware version: %02x.", fw_version);
-+
-+	if (fw_version != entry->expected_version) {
-+		dev_err(&dev->dev, "firmware version mismatch, expected version: %02x.",
-+			 entry->expected_version);
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static int renesas_fw_check_running(struct pci_dev *pdev)
-+{
-+	int err;
-+	u8 fw_state;
-+
-+	/*
-+	 * Test if the device is actually needing the firmware. As most
-+	 * BIOSes will initialize the device for us. If the device is
-+	 * initialized.
-+	 */
-+	err = pci_read_config_byte(pdev, 0xF4, &fw_state);
-+	if (err)
-+		return pcibios_err_to_errno(err);
-+
-+	/*
-+	 * Check if "FW Download Lock" is locked. If it is and the FW is
-+	 * ready we can simply continue. If the FW is not ready, we have
-+	 * to give up.
-+	 */
-+	if (fw_state & BIT(1)) {
-+		dev_dbg(&pdev->dev, "FW Download Lock is engaged.");
-+
-+		if (fw_state & BIT(4))
-+			return 0;
-+
-+		dev_err(&pdev->dev, "FW Download Lock is set and FW is not ready. Giving Up.");
-+		return -EIO;
-+	}
-+
-+	/*
-+	 * Check if "FW Download Enable" is set. If someone (us?) tampered
-+	 * with it and it can't be resetted, we have to give up too... and
-+	 * ask for a forgiveness and a reboot.
-+	 */
-+	if (fw_state & BIT(0)) {
-+		dev_err(&pdev->dev, "FW Download Enable is stale. Giving Up (poweroff/reboot needed).");
-+		return -EIO;
-+	}
-+
-+	/* Otherwise, Check the "Result Code" Bits (6:4) and act accordingly */
-+	switch ((fw_state & 0x70)) {
-+	case 0: /* No result yet */
-+		dev_dbg(&pdev->dev, "FW is not ready/loaded yet.");
-+
-+		/* tell the caller, that this device needs the firmware. */
-+		return 1;
-+
-+	case BIT(4): /* Success, device should be working. */
-+		dev_dbg(&pdev->dev, "FW is ready.");
-+		return 0;
-+
-+	case BIT(5): /* Error State */
-+		dev_err(&pdev->dev, "hardware is in an error state. Giving up (poweroff/reboot needed).");
-+		return -ENODEV;
-+
-+	default: /* All other states are marked as "Reserved states" */
-+		dev_err(&pdev->dev, "hardware is in an invalid state %x. Giving up (poweroff/reboot needed).",
-+			(fw_state & 0x70) >> 4);
-+		return -EINVAL;
-+	}
-+}
-+
-+static int renesas_hw_check_run_stop_busy(struct pci_dev *pdev)
-+{
-+#if 0
-+	u32 val;
-+
-+	/*
-+	 * 7.1.3 Note 3: "... must not set 'FW Download Enable' when
-+	 * 'RUN/STOP' of USBCMD Register is set"
-+	 */
-+	val = readl(hcd->regs + 0x20);
-+	if (val & BIT(0)) {
-+		dev_err(&pdev->dev, "hardware is busy and can't receive a FW.");
-+		return -EBUSY;
-+	}
-+#endif
-+	return 0;
-+}
-+
-+static int renesas_fw_download(struct pci_dev *pdev,
-+	const struct firmware *fw, unsigned int retry_counter)
-+{
-+	const u32 *fw_data = (const u32 *) fw->data;
-+	size_t i;
-+	int err;
-+	u8 fw_status;
-+
-+	/*
-+	 * For more information and the big picture: please look at the
-+	 * "Firmware Download Sequence" in "7.1 FW Download Interface"
-+	 * of R19UH0078EJ0500 Rev.5.00 page 131
-+	 */
-+	err = renesas_hw_check_run_stop_busy(pdev);
-+	if (err)
-+		return err;
-+
-+	/*
-+	 * 0. Set "FW Download Enable" bit in the
-+	 * "FW Download Control & Status Register" at 0xF4
-+	 */
-+	err = pci_write_config_byte(pdev, 0xF4, BIT(0));
-+	if (err)
-+		return pcibios_err_to_errno(err);
-+
-+	/* 1 - 10 follow one step after the other. */
-+	for (i = 0; i < fw->size / 4; i++) {
-+		err = renesas_fw_download_image(pdev, fw_data, i);
-+		if (err) {
-+			dev_err(&pdev->dev, "Firmware Download Step %zd failed at position %zd bytes with (%d).",
-+				 i, i * 4, err);
-+			return err;
-+		}
-+	}
-+
-+	/*
-+	 * This sequence continues until the last data is written to
-+	 * "DATA0" or "DATA1". Naturally, we wait until "SET DATA0/1"
-+	 * is cleared by the hardware beforehand.
-+	 */
-+	for (i = 0; i < 10000; i++) {
-+		err = pci_read_config_byte(pdev, 0xF5, &fw_status);
-+		if (err)
-+			return pcibios_err_to_errno(err);
-+		if (!(fw_status & (BIT(0) | BIT(1))))
-+			break;
-+
-+		udelay(1);
-+	}
-+	if (i == 10000)
-+		dev_warn(&pdev->dev, "Final Firmware Download step timed out.");
-+
-+	/*
-+	 * 11. After finishing writing the last data of FW, the
-+	 * System Software must clear "FW Download Enable"
-+	 */
-+	err = pci_write_config_byte(pdev, 0xF4, 0);
-+	if (err)
-+		return pcibios_err_to_errno(err);
-+
-+	/* 12. Read "Result Code" and confirm it is good. */
-+	for (i = 0; i < 10000; i++) {
-+		err = pci_read_config_byte(pdev, 0xF4, &fw_status);
-+		if (err)
-+			return pcibios_err_to_errno(err);
-+		if (fw_status & BIT(4))
-+			break;
-+
-+		udelay(1);
-+	}
-+	if (i == 10000) {
-+		/* Timed out / Error - let's see if we can fix this */
-+		err = renesas_fw_check_running(pdev);
-+		switch (err) {
-+		case 0: /*
-+			 * we shouldn't end up here.
-+			 * maybe it took a little bit longer.
-+			 * But all should be well?
-+			 */
-+			break;
-+
-+		case 1: /* (No result yet? - we can try to retry) */
-+			if (retry_counter < 10) {
-+				retry_counter++;
-+				dev_warn(&pdev->dev, "Retry Firmware download: %d try.",
-+					  retry_counter);
-+				return renesas_fw_download(pdev, fw,
-+							   retry_counter);
-+			}
-+			return -ETIMEDOUT;
-+
-+		default:
-+			return err;
-+		}
-+	}
-+	/*
-+	 * Optional last step: Engage Firmware Lock
-+	 *
-+	 * err = pci_write_config_byte(pdev, 0xF4, BIT(2));
-+	 * if (err)
-+	 *	return pcibios_err_to_errno(err);
-+	 */
-+
-+	return 0;
-+}
-+
-+struct renesas_fw_ctx {
-+	struct pci_dev *pdev;
-+	const struct pci_device_id *id;
-+	bool resume;
-+};
-+
-+static int xhci_pci_probe(struct pci_dev *pdev,
-+			  const struct pci_device_id *id);
-+
-+static void renesas_fw_callback(const struct firmware *fw,
-+				void *context)
-+{
-+	struct renesas_fw_ctx *ctx = context;
-+	struct pci_dev *pdev = ctx->pdev;
-+	struct device *parent = pdev->dev.parent;
-+	int err = -ENOENT;
-+
-+	if (fw) {
-+		err = renesas_fw_verify(pdev, fw->data, fw->size);
-+		if (!err) {
-+			err = renesas_fw_download(pdev, fw, 0);
-+			release_firmware(fw);
-+			if (!err) {
-+				if (ctx->resume)
-+					return;
-+
-+				err = xhci_pci_probe(pdev, ctx->id);
-+				if (!err) {
-+					/* everything worked */
-+					devm_kfree(&pdev->dev, ctx);
-+					return;
-+				}
-+
-+				/* in case of an error - fall through */
-+			} else {
-+				dev_err(&pdev->dev, "firmware failed to download (%d).",
-+					err);
-+			}
-+		}
-+	} else {
-+		dev_err(&pdev->dev, "firmware failed to load (%d).", err);
-+	}
-+
-+	dev_info(&pdev->dev, "Unloading driver");
-+
-+	if (parent)
-+		device_lock(parent);
-+
-+	device_release_driver(&pdev->dev);
-+
-+	if (parent)
-+		device_unlock(parent);
-+
-+	pci_dev_put(pdev);
-+}
-+
-+static int renesas_fw_alive_check(struct pci_dev *pdev)
-+{
-+	const struct renesas_fw_entry *entry;
-+	int err;
-+
-+	/* check if we have a eligible RENESAS' uPD720201/2 w/o FW. */
-+	entry = renesas_needs_fw_dl(pdev);
-+	if (!entry)
-+		return 0;
-+
-+	err = renesas_fw_check_running(pdev);
-+	/* Also go ahead, if the firmware is running */
-+	if (err == 0)
-+		return 0;
-+
-+	/* At this point, we can be sure that the FW isn't ready. */
-+	return err;
-+}
-+
-+static int renesas_fw_download_to_hw(struct pci_dev *pdev,
-+				     const struct pci_device_id *id,
-+				     bool do_resume)
-+{
-+	const struct renesas_fw_entry *entry;
-+	struct renesas_fw_ctx *ctx;
-+	int err;
-+
-+	/* check if we have a eligible RENESAS' uPD720201/2 w/o FW. */
-+	entry = renesas_needs_fw_dl(pdev);
-+	if (!entry)
-+		return 0;
-+
-+	err = renesas_fw_check_running(pdev);
-+	/* Continue ahead, if the firmware is already running. */
-+	if (err == 0)
-+		return 0;
-+
-+	if (err != 1)
-+		return err;
-+
-+	ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
-+	if (!ctx)
-+		return -ENOMEM;
-+	ctx->pdev = pdev;
-+	ctx->resume = do_resume;
-+	ctx->id = id;
-+
-+	pci_dev_get(pdev);
-+	err = request_firmware_nowait(THIS_MODULE, 1, entry->firmware_name,
-+		&pdev->dev, GFP_KERNEL, ctx, renesas_fw_callback);
-+	if (err) {
-+		pci_dev_put(pdev);
-+		return err;
-+	}
-+
-+	/*
-+	 * The renesas_fw_callback() callback will continue the probe
-+	 * process, once it aquires the firmware.
-+	 */
-+	return 1;
-+}
-+
- /* called during probe() after chip reset completes */
- static int xhci_pci_setup(struct usb_hcd *hcd)
- {
-@@ -309,6 +763,22 @@ static int xhci_pci_probe(struct pci_dev
- 	struct hc_driver *driver;
- 	struct usb_hcd *hcd;
- 
-+	/*
-+	 * Check if this device is a RENESAS uPD720201/2 device.
-+	 * Otherwise, we can continue with xhci_pci_probe as usual.
-+	 */
-+	retval = renesas_fw_download_to_hw(dev, id, false);
-+	switch (retval) {
-+	case 0:
-+		break;
-+
-+	case 1: /* let it load the firmware and recontinue the probe. */
-+		return 0;
-+
-+	default:
-+		return retval;
-+	}
-+
- 	driver = (struct hc_driver *)id->driver_data;
- 
- 	/* Prevent runtime suspending between USB-2 and USB-3 initialization */
-@@ -367,6 +837,16 @@ static void xhci_pci_remove(struct pci_d
- {
- 	struct xhci_hcd *xhci;
- 
-+	if (renesas_fw_alive_check(dev)) {
-+		/*
-+		 * bail out early, if this was a renesas device w/o FW.
-+		 * Else we might hit the NMI watchdog in xhci_handsake
-+		 * during xhci_reset as part of the driver's unloading.
-+		 * which we forced in the renesas_fw_callback().
-+		 */
-+		return;
-+	}
-+
- 	xhci = hcd_to_xhci(pci_get_drvdata(dev));
- 	xhci->xhc_state |= XHCI_STATE_REMOVING;
- 	if (xhci->shared_hcd) {

target/linux/apm821xx/patches-4.19/802-usb-xhci-force-msi-renesas-xhci.patch

@@ -1,53 +0,0 @@
-From a0dc613140bab907a3d5787a7ae7b0638bf674d0 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <[email protected]>
-Date: Thu, 23 Jun 2016 20:28:20 +0200
-Subject: [PATCH] usb: xhci: force MSI for uPD720201 and
- uPD720202
-
-The APM82181 does not support MSI-X. When probed, it will
-produce a noisy warning.
-
----
- drivers/usb/host/pci-quirks.c | 362 ++++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 362 insertions(+)
-
---- a/drivers/usb/host/xhci-pci.c
-+++ b/drivers/usb/host/xhci-pci.c
-@@ -218,6 +218,7 @@ static void xhci_pci_quirks(struct devic
- 	    pdev->device == 0x0015) {
- 		xhci->quirks |= XHCI_RESET_ON_RESUME;
- 		xhci->quirks |= XHCI_ZERO_64B_REGS;
-+		xhci->quirks |= XHCI_FORCE_MSI;
- 	}
- 	if (pdev->vendor == PCI_VENDOR_ID_VIA)
- 		xhci->quirks |= XHCI_RESET_ON_RESUME;
---- a/drivers/usb/host/xhci.c
-+++ b/drivers/usb/host/xhci.c
-@@ -422,10 +422,14 @@ static int xhci_try_enable_msi(struct us
- 		free_irq(hcd->irq, hcd);
- 	hcd->irq = 0;
- 
--	ret = xhci_setup_msix(xhci);
--	if (ret)
--		/* fall back to msi*/
-+	if (xhci->quirks & XHCI_FORCE_MSI) {
- 		ret = xhci_setup_msi(xhci);
-+	} else {
-+		ret = xhci_setup_msix(xhci);
-+		if (ret)
-+			/* fall back to msi*/
-+			ret = xhci_setup_msi(xhci);
-+	}
- 
- 	if (!ret) {
- 		hcd->msi_enabled = 1;
---- a/drivers/usb/host/xhci.h
-+++ b/drivers/usb/host/xhci.h
-@@ -1883,6 +1883,7 @@ struct xhci_hcd {
- 	/* support xHCI 0.96 spec USB2 software LPM */
- 	unsigned		sw_lpm_support:1;
- 	/* support xHCI 1.0 spec USB2 hardware LPM */
-+#define XHCI_FORCE_MSI		(1 << 24)
- 	unsigned		hw_lpm_support:1;
- 	/* Broken Suspend flag for SNPS Suspend resume issue */
- 	unsigned		broken_suspend:1;

target/linux/apm821xx/patches-4.19/803-hwmon-tc654-add-detection-routine.patch

@@ -1,65 +0,0 @@
-From 694f9bfb8efaef8a33e8992015ff9d0866faf4a2 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <[email protected]>
-Date: Sun, 17 Dec 2017 17:27:15 +0100
-Subject: [PATCH 1/2] hwmon: tc654 add detection routine
-
-This patch adds a detection routine for the TC654/TC655
-chips.  Both IDs are listed in the Datasheet.
-
-Signed-off-by: Christian Lamparter <[email protected]>
----
- drivers/hwmon/tc654.c | 29 +++++++++++++++++++++++++++++
- 1 file changed, 29 insertions(+)
-
---- a/drivers/hwmon/tc654.c
-+++ b/drivers/hwmon/tc654.c
-@@ -64,6 +64,11 @@ enum tc654_regs {
- /* Register data is read (and cached) at most once per second. */
- #define TC654_UPDATE_INTERVAL		HZ
- 
-+/* Manufacturer and Version Identification Register Values */
-+#define TC654_MFR_ID_MICROCHIP		0x84
-+#define TC654_VER_ID			0x00
-+#define TC655_VER_ID			0x01
-+
- struct tc654_data {
- 	struct i2c_client *client;
- 
-@@ -497,6 +502,29 @@ static const struct i2c_device_id tc654_
- 	{}
- };
- 
-+static int
-+tc654_detect(struct i2c_client *new_client, struct i2c_board_info *info)
-+{
-+	struct i2c_adapter *adapter = new_client->adapter;
-+	int manufacturer, product;
-+
-+	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
-+		return -ENODEV;
-+
-+	manufacturer = i2c_smbus_read_byte_data(new_client, TC654_REG_MFR_ID);
-+	if (manufacturer != TC654_MFR_ID_MICROCHIP)
-+		return -ENODEV;
-+
-+	product = i2c_smbus_read_byte_data(new_client, TC654_REG_VER_ID);
-+	if (!((product == TC654_VER_ID) || (product == TC655_VER_ID)))
-+		return -ENODEV;
-+
-+	strlcpy(info->type, product == TC654_VER_ID ? "tc654" : "tc655",
-+		I2C_NAME_SIZE);
-+	return 0;
-+}
-+
-+
- MODULE_DEVICE_TABLE(i2c, tc654_id);
- 
- static struct i2c_driver tc654_driver = {
-@@ -505,6 +533,7 @@ static struct i2c_driver tc654_driver =
- 		   },
- 	.probe = tc654_probe,
- 	.id_table = tc654_id,
-+	.detect = tc654_detect,
- };
- 
- module_i2c_driver(tc654_driver);

target/linux/apm821xx/patches-4.19/804-hwmon-tc654-add-thermal_cooling-device.patch

@@ -1,174 +0,0 @@
-From 15ae701189744d321d3a1264ff46f8871e8765ee Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <[email protected]>
-Date: Sun, 17 Dec 2017 17:29:13 +0100
-Subject: [PATCH] hwmon: tc654: add thermal_cooling device
-
-This patch adds a thermaL_cooling device to the tc654 driver.
-This allows the chip to be used for DT-based cooling.
-
-Signed-off-by: Christian Lamparter <[email protected]>
----
- drivers/hwmon/tc654.c | 103 +++++++++++++++++++++++++++++++++++++++++---------
- 1 file changed, 86 insertions(+), 17 deletions(-)
-
---- a/drivers/hwmon/tc654.c
-+++ b/drivers/hwmon/tc654.c
-@@ -24,6 +24,7 @@
- #include <linux/module.h>
- #include <linux/mutex.h>
- #include <linux/slab.h>
-+#include <linux/thermal.h>
- #include <linux/util_macros.h>
- 
- enum tc654_regs {
-@@ -141,6 +142,9 @@ struct tc654_data {
- 			 * writable register used to control the duty
- 			 * cycle of the V OUT output.
- 			 */
-+
-+	/* optional cooling device */
-+	struct thermal_cooling_device *cdev;
- };
- 
- /* helper to grab and cache data, at most one time per second */
-@@ -376,36 +380,30 @@ static ssize_t set_pwm_mode(struct devic
- static const int tc654_pwm_map[16] = { 77,  88, 102, 112, 124, 136, 148, 160,
- 				      172, 184, 196, 207, 219, 231, 243, 255};
- 
-+static int get_pwm(struct tc654_data *data)
-+{
-+	if (data->config & TC654_REG_CONFIG_SDM)
-+		return 0;
-+	else
-+		return tc654_pwm_map[data->duty_cycle];
-+}
-+
- static ssize_t show_pwm(struct device *dev, struct device_attribute *da,
- 			char *buf)
- {
- 	struct tc654_data *data = tc654_update_client(dev);
--	int pwm;
- 
- 	if (IS_ERR(data))
- 		return PTR_ERR(data);
- 
--	if (data->config & TC654_REG_CONFIG_SDM)
--		pwm = 0;
--	else
--		pwm = tc654_pwm_map[data->duty_cycle];
--
--	return sprintf(buf, "%d\n", pwm);
-+	return sprintf(buf, "%d\n", get_pwm(data));
- }
- 
--static ssize_t set_pwm(struct device *dev, struct device_attribute *da,
--		       const char *buf, size_t count)
-+static int _set_pwm(struct tc654_data *data, unsigned long val)
- {
--	struct tc654_data *data = dev_get_drvdata(dev);
- 	struct i2c_client *client = data->client;
--	unsigned long val;
- 	int ret;
- 
--	if (kstrtoul(buf, 10, &val))
--		return -EINVAL;
--	if (val > 255)
--		return -EINVAL;
--
- 	mutex_lock(&data->update_lock);
- 
- 	if (val == 0)
-@@ -425,6 +423,22 @@ static ssize_t set_pwm(struct device *de
- 
- out:
- 	mutex_unlock(&data->update_lock);
-+	return ret;
-+}
-+
-+static ssize_t set_pwm(struct device *dev, struct device_attribute *da,
-+		       const char *buf, size_t count)
-+{
-+	struct tc654_data *data = dev_get_drvdata(dev);
-+	unsigned long val;
-+	int ret;
-+
-+	if (kstrtoul(buf, 10, &val))
-+		return -EINVAL;
-+	if (val > 255)
-+		return -EINVAL;
-+
-+	ret = _set_pwm(data, val);
- 	return ret < 0 ? ret : count;
- }
- 
-@@ -462,6 +476,47 @@ static struct attribute *tc654_attrs[] =
- 
- ATTRIBUTE_GROUPS(tc654);
- 
-+/* cooling device */
-+
-+static int tc654_get_max_state(struct thermal_cooling_device *cdev,
-+			       unsigned long *state)
-+{
-+	*state = 255;
-+	return 0;
-+}
-+
-+static int tc654_get_cur_state(struct thermal_cooling_device *cdev,
-+                              unsigned long *state)
-+{
-+	struct tc654_data *data = tc654_update_client(cdev->devdata);
-+
-+	if (IS_ERR(data))
-+		return PTR_ERR(data);
-+
-+	*state = get_pwm(data);
-+	return 0;
-+}
-+
-+static int tc654_set_cur_state(struct thermal_cooling_device *cdev,
-+			       unsigned long state)
-+{
-+	struct tc654_data *data = tc654_update_client(cdev->devdata);
-+
-+	if (IS_ERR(data))
-+		return PTR_ERR(data);
-+
-+	if (state > 255)
-+		return -EINVAL;
-+
-+	return _set_pwm(data, state);
-+}
-+
-+static const struct thermal_cooling_device_ops tc654_fan_cool_ops = {
-+	.get_max_state = tc654_get_max_state,
-+	.get_cur_state = tc654_get_cur_state,
-+	.set_cur_state = tc654_set_cur_state,
-+};
-+
- /*
-  * device probe and removal
-  */
-@@ -493,7 +548,21 @@ static int tc654_probe(struct i2c_client
- 	hwmon_dev =
- 	    devm_hwmon_device_register_with_groups(dev, client->name, data,
- 						   tc654_groups);
--	return PTR_ERR_OR_ZERO(hwmon_dev);
-+	if (IS_ERR(hwmon_dev))
-+		return PTR_ERR(hwmon_dev);
-+
-+#if IS_ENABLED(CONFIG_OF)
-+	/* Optional cooling device register for Device tree platforms */
-+	data->cdev = thermal_of_cooling_device_register(client->dev.of_node,
-+							"tc654", hwmon_dev,
-+							&tc654_fan_cool_ops);
-+#else /* CONFIG_OF */
-+	/* Optional cooling device register for non Device tree platforms */
-+	data->cdev = thermal_cooling_device_register("tc654", hwmon_dev,
-+						     &tc654_fan_cool_ops);
-+#endif /* CONFIG_OF */
-+
-+	return PTR_ERR_OR_ZERO(data->cdev);
- }
- 
- static const struct i2c_device_id tc654_id[] = {

target/linux/armvirt/32/config-4.19

@@ -1,91 +0,0 @@
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_ARCH_AXXIA is not set
-CONFIG_ARCH_HAS_PHYS_TO_DMA=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_VIRT=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARM=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_LPAE=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_PSCI=y
-CONFIG_ARM_THUMB=y
-# CONFIG_ARM_THUMBEE is not set
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-# CONFIG_DEBUG_USER is not set
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_HAVE_ARM_ARCH_TIMER=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_OPTPROBES=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_SMP=y
-# CONFIG_HUGETLBFS is not set
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_NEON=y
-CONFIG_NR_CPUS=4
-CONFIG_OLD_SIGACTION=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PCI_V3_SEMI is not set
-CONFIG_PERF_USE_VMALLOC=y
-# CONFIG_PL310_ERRATA_588369 is not set
-# CONFIG_PL310_ERRATA_727915 is not set
-# CONFIG_PL310_ERRATA_753970 is not set
-# CONFIG_PL310_ERRATA_769419 is not set
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0

target/linux/armvirt/64/config-4.19

@@ -1,230 +0,0 @@
-CONFIG_64BIT=y
-CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
-CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
-CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
-CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
-CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
-CONFIG_ARCH_INLINE_READ_LOCK=y
-CONFIG_ARCH_INLINE_READ_LOCK_BH=y
-CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y
-CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y
-CONFIG_ARCH_INLINE_READ_UNLOCK=y
-CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y
-CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y
-CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y
-CONFIG_ARCH_INLINE_SPIN_LOCK=y
-CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y
-CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y
-CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y
-CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y
-CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y
-CONFIG_ARCH_INLINE_SPIN_UNLOCK=y
-CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y
-CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y
-CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y
-CONFIG_ARCH_INLINE_WRITE_LOCK=y
-CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y
-CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y
-CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y
-CONFIG_ARCH_INLINE_WRITE_UNLOCK=y
-CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y
-CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y
-CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_DEFAULT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
-CONFIG_ARCH_SUPPORTS_INT128=y
-CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
-CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
-CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
-CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
-CONFIG_ARCH_VEXPRESS=y
-CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
-CONFIG_ARCH_WANT_FRAME_POINTERS=y
-CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
-CONFIG_ARM64=y
-# CONFIG_ARM64_16K_PAGES is not set
-CONFIG_ARM64_4K_PAGES=y
-# CONFIG_ARM64_64K_PAGES is not set
-CONFIG_ARM64_CONT_SHIFT=4
-CONFIG_ARM64_CRYPTO=y
-CONFIG_ARM64_ERRATUM_819472=y
-CONFIG_ARM64_ERRATUM_824069=y
-CONFIG_ARM64_ERRATUM_826319=y
-CONFIG_ARM64_ERRATUM_827319=y
-CONFIG_ARM64_ERRATUM_832075=y
-CONFIG_ARM64_ERRATUM_843419=y
-CONFIG_ARM64_HW_AFDBM=y
-# CONFIG_ARM64_LSE_ATOMICS is not set
-CONFIG_ARM64_MODULE_PLTS=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PAN=y
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-# CONFIG_ARM64_PMEM is not set
-# CONFIG_ARM64_PTDUMP_DEBUGFS is not set
-# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
-CONFIG_ARM64_SSBD=y
-CONFIG_ARM64_SVE=y
-CONFIG_ARM64_UAO=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-# CONFIG_ARM64_VA_BITS_48 is not set
-CONFIG_ARM64_VHE=y
-CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-CONFIG_ATOMIC64_SELFTEST=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_VERSATILE=y
-CONFIG_CLK_SP810=y
-CONFIG_CLK_VEXPRESS_OSC=y
-CONFIG_COMMON_CLK_VERSATILE=y
-# CONFIG_CPU_BIG_ENDIAN is not set
-CONFIG_CPU_IDLE=y
-# CONFIG_CPU_IDLE_GOV_LADDER is not set
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_PM=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_BS=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
-CONFIG_CRYPTO_CHACHA20=y
-CONFIG_CRYPTO_CHACHA20_NEON=y
-CONFIG_CRYPTO_CRC32_ARM64_CE=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_GF128MUL=y
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA1_ARM64_CE=y
-CONFIG_CRYPTO_SHA256_ARM64=y
-CONFIG_CRYPTO_SHA2_ARM64_CE=y
-# CONFIG_CRYPTO_SHA3_ARM64 is not set
-CONFIG_CRYPTO_SHA512_ARM64=y
-# CONFIG_CRYPTO_SHA512_ARM64_CE is not set
-CONFIG_CRYPTO_SIMD=y
-# CONFIG_CRYPTO_SM3_ARM64_CE is not set
-# CONFIG_CRYPTO_SM4_ARM64_CE is not set
-CONFIG_DMA_DIRECT_OPS=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DRM=y
-CONFIG_DRM_BOCHS=y
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-# CONFIG_DRM_PANEL_SIMPLE is not set
-CONFIG_DRM_QXL=y
-CONFIG_DRM_TTM=y
-CONFIG_DRM_VIRTIO_GPU=y
-CONFIG_FB=y
-CONFIG_FB_ARMCLCD=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_MODE_HELPERS=y
-# CONFIG_FLATMEM_MANUAL is not set
-CONFIG_FSL_ERRATUM_A008585=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
-CONFIG_HAVE_ARCH_HUGE_VMAP=y
-CONFIG_HAVE_ARCH_KASAN=y
-CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
-CONFIG_HAVE_ARCH_VMAP_STACK=y
-CONFIG_HAVE_CMPXCHG_DOUBLE=y
-CONFIG_HAVE_CMPXCHG_LOCAL=y
-CONFIG_HAVE_DEBUG_BUGVERBOSE=y
-CONFIG_HAVE_MEMORY_PRESENT=y
-CONFIG_HAVE_PATA_PLATFORM=y
-CONFIG_HDMI=y
-CONFIG_HOLES_IN_ZONE=y
-# CONFIG_HUGETLBFS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_VIRTIO=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_INLINE_READ_LOCK=y
-CONFIG_INLINE_READ_LOCK_BH=y
-CONFIG_INLINE_READ_LOCK_IRQ=y
-CONFIG_INLINE_READ_LOCK_IRQSAVE=y
-CONFIG_INLINE_READ_UNLOCK_BH=y
-CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y
-CONFIG_INLINE_SPIN_LOCK=y
-CONFIG_INLINE_SPIN_LOCK_BH=y
-CONFIG_INLINE_SPIN_LOCK_IRQ=y
-CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y
-CONFIG_INLINE_SPIN_TRYLOCK=y
-CONFIG_INLINE_SPIN_TRYLOCK_BH=y
-CONFIG_INLINE_SPIN_UNLOCK_BH=y
-CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y
-CONFIG_INLINE_WRITE_LOCK=y
-CONFIG_INLINE_WRITE_LOCK_BH=y
-CONFIG_INLINE_WRITE_LOCK_IRQ=y
-CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y
-CONFIG_INLINE_WRITE_UNLOCK_BH=y
-CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y
-CONFIG_LCD_CLASS_DEVICE=m
-# CONFIG_LCD_PLATFORM is not set
-CONFIG_MFD_CORE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MFD_VEXPRESS_SYSREG=y
-CONFIG_MMC=y
-CONFIG_MMC_ARMMMCI=y
-# CONFIG_MMC_TIFM_SD is not set
-CONFIG_MODULES_USE_ELF_RELA=y
-# CONFIG_MTD_PHYSMAP_OF is not set
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=64
-# CONFIG_NUMA is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_VEXPRESS=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-# CONFIG_RANDOMIZE_BASE is not set
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_SMC91X=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_MANUAL=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SYNC_FILE=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_VEXPRESS_CONFIG=y
-CONFIG_VEXPRESS_SYSCFG=y
-CONFIG_VIDEOMODE_HELPERS=y
-CONFIG_VMAP_STACK=y
-CONFIG_ZONE_DMA32=y

target/linux/armvirt/config-4.19

@@ -1,218 +0,0 @@
-CONFIG_9P_FS=y
-# CONFIG_9P_FS_POSIX_ACL is not set
-# CONFIG_9P_FS_SECURITY is not set
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_CLOCKSOURCE_DATA=y
-CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
-CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
-CONFIG_ARCH_HAS_KCOV=y
-CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
-CONFIG_ARCH_HAS_PTE_SPECIAL=y
-CONFIG_ARCH_HAS_SET_MEMORY=y
-CONFIG_ARCH_HAS_SG_CHAIN=y
-CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
-CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_PSCI_FW=y
-# CONFIG_ARM_SP805_WATCHDOG is not set
-CONFIG_BALLOON_COMPACTION=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_BLK_SCSI_REQUEST=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
-CONFIG_CPU_RMAP=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_NULL2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DTC=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EXT4_FS=y
-CONFIG_F2FS_FS=y
-CONFIG_FAILOVER=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_PL061=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_AUDITSYSCALL=y
-CONFIG_HAVE_ARCH_BITREVERSE=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
-CONFIG_HAVE_ARM_SMCCC=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_EBPF_JIT=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_GUP=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_RCU_TABLE_FREE=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_RSEQ=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HVC_DRIVER=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IOMMU_HELPER=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_MEMORY_BALLOON=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MIGRATION=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_9P=y
-# CONFIG_NET_9P_DEBUG is not set
-CONFIG_NET_9P_VIRTIO=y
-CONFIG_NET_FAILOVER=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NO_BOOTMEM=y
-CONFIG_NVMEM=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_NET=y
-CONFIG_OF_RESERVED_MEM=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PADATA=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_ECAM=y
-CONFIG_PCI_HOST_COMMON=y
-CONFIG_PCI_HOST_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_RATIONAL=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_RCU_NEED_SEGCBLIST=y
-CONFIG_REFCOUNT_FULL=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_PL031=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-# CONFIG_SCHED_INFO is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_VIRTIO=y
-CONFIG_SERIAL_8250_FSL=y
-# CONFIG_SERIAL_AMBA_PL010 is not set
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SRCU=y
-CONFIG_SWIOTLB=y
-CONFIG_SYS_SUPPORTS_HUGETLBFS=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_USB_SUPPORT=y
-CONFIG_VIRTIO=y
-CONFIG_VIRTIO_BALLOON=y
-CONFIG_VIRTIO_BLK=y
-CONFIG_VIRTIO_CONSOLE=y
-CONFIG_VIRTIO_MMIO=y
-# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
-CONFIG_VIRTIO_NET=y
-CONFIG_VIRTIO_PCI=y
-CONFIG_VIRTIO_PCI_LEGACY=y
-CONFIG_XPS=y

target/linux/ath79/config-4.19

@@ -1,239 +0,0 @@
-CONFIG_AG71XX=y
-# CONFIG_AG71XX_DEBUG is not set
-CONFIG_AG71XX_DEBUG_FS=y
-CONFIG_AR8216_PHY=y
-CONFIG_AR8216_PHY_LEDS=y
-CONFIG_ARCH_BINFMT_ELF_STATE=y
-CONFIG_ARCH_CLOCKSOURCE_DATA=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
-CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_AT803X_PHY=y
-CONFIG_ATH79=y
-CONFIG_ATH79_WDT=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_COMMON_CLK=y
-# CONFIG_COMMON_CLK_BOSTON is not set
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_RIXI=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_MIPS32=y
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CPU_SUPPORTS_MSA=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_CSRC_R4K=y
-CONFIG_DMA_DIRECT_OPS=y
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y
-CONFIG_DMA_NONCOHERENT_MMAP=y
-CONFIG_DMA_NONCOHERENT_OPS=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_ETHERNET_PACKET_MANGLE=y
-CONFIG_FIXED_PHY=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_LIB_ASHLDI3=y
-CONFIG_GENERIC_LIB_ASHRDI3=y
-CONFIG_GENERIC_LIB_CMPDI2=y
-CONFIG_GENERIC_LIB_LSHRDI3=y
-CONFIG_GENERIC_LIB_UCMPDI2=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_74X164=y
-CONFIG_GPIO_ATH79=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_ARCH_COMPILER_H=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_CBPF_JIT=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_COPY_THREAD_TLS=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_RSEQ=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_IMAGE_CMDLINE_HACK=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_LEDS_GPIO=y
-# CONFIG_LEDS_RESET is not set
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_GPIO=y
-CONFIG_MEMFD_CREATE=y
-# CONFIG_MFD_RB4XX_CPLD is not set
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MIPS=y
-CONFIG_MIPS_ASID_BITS=8
-CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_CBPF_JIT=y
-CONFIG_MIPS_CLOCK_VSYSCALL=y
-# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
-# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set
-# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_MIPS_CMDLINE_FROM_DTB=y
-# CONFIG_MIPS_ELF_APPENDED_DTB is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_NO_APPENDED_DTB is not set
-CONFIG_MIPS_RAW_APPENDED_DTB=y
-CONFIG_MIPS_SPRAM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_CFI_I2 is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
-# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-CONFIG_MTD_PARSER_CYBERTAN=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_ELF_FW=y
-CONFIG_MTD_SPLIT_LZMA_FW=y
-CONFIG_MTD_SPLIT_SEAMA_FW=y
-CONFIG_MTD_SPLIT_TPLINK_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_SPLIT_WRGG_FW=y
-CONFIG_MTD_VIRT_CONCAT=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_NVMEM=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_NET=y
-CONFIG_PCI=y
-CONFIG_PCI_AR71XX=y
-CONFIG_PCI_AR724X=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DRIVERS_LEGACY=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-# CONFIG_PHY_AR7100_USB is not set
-# CONFIG_PHY_AR7200_USB is not set
-# CONFIG_PHY_ATH79_USB is not set
-CONFIG_PINCTRL=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RESET_ATH79=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_SERIAL_8250_NR_UARTS=1
-CONFIG_SERIAL_8250_RUNTIME_UARTS=1
-CONFIG_SERIAL_AR933X=y
-CONFIG_SERIAL_AR933X_CONSOLE=y
-CONFIG_SERIAL_AR933X_NR_UARTS=2
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SPI=y
-CONFIG_SPI_AR934X=y
-CONFIG_SPI_ATH79=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_GPIO=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-# CONFIG_SPI_RB4XX is not set
-CONFIG_SRCU=y
-CONFIG_SWCONFIG=y
-CONFIG_SWCONFIG_LEDS=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_SYS_SUPPORTS_ZBOOT=y
-CONFIG_SYS_SUPPORTS_ZBOOT_UART_PROM=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TINY_SRCU=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y

target/linux/ath79/patches-4.19/0002-watchdog-ath79-fix-maximum-timeout.patch

@@ -1,32 +0,0 @@
-From 5f5c9858af167f842ee8df053920b98387a71af1 Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Mon, 5 Mar 2018 11:41:25 +0100
-Subject: [PATCH 02/27] watchdog: ath79: fix maximum timeout
-
-If the userland tries to set a timeout higher than the max_timeout,
-then we should fallback to max_timeout.
-
-Signed-off-by: John Crispin <[email protected]>
----
- drivers/watchdog/ath79_wdt.c | 8 ++++++--
- 1 file changed, 6 insertions(+), 2 deletions(-)
-
---- a/drivers/watchdog/ath79_wdt.c
-+++ b/drivers/watchdog/ath79_wdt.c
-@@ -115,10 +115,14 @@ static inline void ath79_wdt_disable(voi
- 
- static int ath79_wdt_set_timeout(int val)
- {
--	if (val < 1 || val > max_timeout)
-+	if (val < 1)
- 		return -EINVAL;
- 
--	timeout = val;
-+	if (val > max_timeout)
-+		timeout = max_timeout;
-+	else
-+		timeout = val;
-+
- 	ath79_wdt_keepalive();
- 
- 	return 0;

target/linux/ath79/patches-4.19/0003-leds-add-reset-controller-based-driver.patch

@@ -1,186 +0,0 @@
-From ecbd9c87f073f097d9fe56390353e64e963e866a Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Tue, 6 Mar 2018 10:03:03 +0100
-Subject: [PATCH 03/27] leds: add reset-controller based driver
-
-Signed-off-by: John Crispin <[email protected]>
----
- drivers/leds/Kconfig      |  11 ++++
- drivers/leds/Makefile     |   1 +
- drivers/leds/leds-reset.c | 137 ++++++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 149 insertions(+)
- create mode 100644 drivers/leds/leds-reset.c
-
---- a/drivers/leds/Kconfig
-+++ b/drivers/leds/Kconfig
-@@ -756,6 +756,17 @@ config LEDS_NIC78BX
- 	  To compile this driver as a module, choose M here: the module
- 	  will be called leds-nic78bx.
- 
-+config LEDS_RESET
-+	tristate "LED support for reset-controller API"
-+	depends on LEDS_CLASS
-+	depends on RESET_CONTROLLER
-+	help
-+	  This option enables support for LEDs connected to pins driven by reset
-+	  controllers. Yes, DNI actual built HW like that.
-+
-+	  To compile this driver as a module, choose M here: the module
-+	  will be called leds-reset.
-+
- comment "LED Triggers"
- source "drivers/leds/trigger/Kconfig"
- 
---- /dev/null
-+++ b/drivers/leds/leds-reset.c
-@@ -0,0 +1,140 @@
-+/*
-+ * Copyright (C) 2018 John Crispin <[email protected]>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+#include <linux/err.h>
-+#include <linux/reset.h>
-+#include <linux/kernel.h>
-+#include <linux/leds.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/reset.h>
-+
-+struct reset_led_data {
-+	struct led_classdev cdev;
-+	struct reset_control *rst;
-+};
-+
-+static inline struct reset_led_data *
-+			cdev_to_reset_led_data(struct led_classdev *led_cdev)
-+{
-+	return container_of(led_cdev, struct reset_led_data, cdev);
-+}
-+
-+static void reset_led_set(struct led_classdev *led_cdev,
-+	enum led_brightness value)
-+{
-+	struct reset_led_data *led_dat = cdev_to_reset_led_data(led_cdev);
-+
-+	if (value == LED_OFF)
-+		reset_control_assert(led_dat->rst);
-+	else
-+		reset_control_deassert(led_dat->rst);
-+}
-+
-+struct reset_leds_priv {
-+	int num_leds;
-+	struct reset_led_data leds[];
-+};
-+
-+static inline int sizeof_reset_leds_priv(int num_leds)
-+{
-+	return sizeof(struct reset_leds_priv) +
-+		(sizeof(struct reset_led_data) * num_leds);
-+}
-+
-+static struct reset_leds_priv *reset_leds_create(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct fwnode_handle *child;
-+	struct reset_leds_priv *priv;
-+	int count, ret;
-+
-+	count = device_get_child_node_count(dev);
-+	if (!count)
-+		return ERR_PTR(-ENODEV);
-+
-+	priv = devm_kzalloc(dev, sizeof_reset_leds_priv(count), GFP_KERNEL);
-+	if (!priv)
-+		return ERR_PTR(-ENOMEM);
-+
-+	device_for_each_child_node(dev, child) {
-+		struct reset_led_data *led = &priv->leds[priv->num_leds];
-+		struct device_node *np = to_of_node(child);
-+
-+		ret = fwnode_property_read_string(child, "label", &led->cdev.name);
-+		if (!led->cdev.name) {
-+			fwnode_handle_put(child);
-+			return ERR_PTR(-EINVAL);
-+		}
-+		led->rst = __of_reset_control_get(np, NULL, 0, 0, 0);
-+		if (IS_ERR(led->rst))
-+			return ERR_PTR(-EINVAL);
-+
-+		fwnode_property_read_string(child, "linux,default-trigger",
-+						&led->cdev.default_trigger);
-+
-+		led->cdev.brightness_set = reset_led_set;
-+		ret = devm_of_led_classdev_register(&pdev->dev, np, &led->cdev);
-+		if (ret < 0)
-+			return ERR_PTR(ret);
-+		led->cdev.dev->of_node = np;
-+		priv->num_leds++;
-+	}
-+
-+	return priv;
-+}
-+
-+static const struct of_device_id of_reset_leds_match[] = {
-+	{ .compatible = "reset-leds", },
-+	{},
-+};
-+
-+MODULE_DEVICE_TABLE(of, of_reset_leds_match);
-+
-+static int reset_led_probe(struct platform_device *pdev)
-+{
-+	struct reset_leds_priv *priv;
-+
-+	priv = reset_leds_create(pdev);
-+	if (IS_ERR(priv))
-+		return PTR_ERR(priv);
-+
-+	platform_set_drvdata(pdev, priv);
-+
-+	return 0;
-+}
-+
-+static void reset_led_shutdown(struct platform_device *pdev)
-+{
-+	struct reset_leds_priv *priv = platform_get_drvdata(pdev);
-+	int i;
-+
-+	for (i = 0; i < priv->num_leds; i++) {
-+		struct reset_led_data *led = &priv->leds[i];
-+
-+		if (!(led->cdev.flags & LED_RETAIN_AT_SHUTDOWN))
-+			reset_led_set(&led->cdev, LED_OFF);
-+	}
-+}
-+
-+static struct platform_driver reset_led_driver = {
-+	.probe		= reset_led_probe,
-+	.shutdown	= reset_led_shutdown,
-+	.driver		= {
-+		.name	= "leds-reset",
-+		.of_match_table = of_reset_leds_match,
-+	},
-+};
-+
-+module_platform_driver(reset_led_driver);
-+
-+MODULE_AUTHOR("John Crispin <[email protected]>");
-+MODULE_DESCRIPTION("reset controller LED driver");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("platform:leds-reset");
---- a/drivers/leds/Makefile
-+++ b/drivers/leds/Makefile
-@@ -78,6 +78,7 @@ obj-$(CONFIG_LEDS_MT6323)		+= leds-mt632
- obj-$(CONFIG_LEDS_LM3692X)		+= leds-lm3692x.o
- obj-$(CONFIG_LEDS_SC27XX_BLTC)		+= leds-sc27xx-bltc.o
- obj-$(CONFIG_LEDS_LM3601X)		+= leds-lm3601x.o
-+obj-$(CONFIG_LEDS_RESET)		+= leds-reset.o
- 
- # LED SPI Drivers
- obj-$(CONFIG_LEDS_CR0014114)		+= leds-cr0014114.o

target/linux/ath79/patches-4.19/0004-phy-add-ath79-usb-phys.patch

@@ -1,333 +0,0 @@
-From 08c9d6ceef01893678a5d2e8a15517c745417f21 Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Tue, 6 Mar 2018 10:04:05 +0100
-Subject: [PATCH 04/27] phy: add ath79 usb phys
-
-Signed-off-by: John Crispin <[email protected]>
----
- drivers/phy/Kconfig          |  16 ++++++
- drivers/phy/Makefile         |   2 +
- drivers/phy/phy-ar7100-usb.c | 124 +++++++++++++++++++++++++++++++++++++++++++
- drivers/phy/phy-ar7200-usb.c | 108 +++++++++++++++++++++++++++++++++++++
- 4 files changed, 250 insertions(+)
- create mode 100644 drivers/phy/phy-ar7100-usb.c
- create mode 100644 drivers/phy/phy-ar7200-usb.c
-
---- a/drivers/phy/Kconfig
-+++ b/drivers/phy/Kconfig
-@@ -15,6 +15,22 @@ config GENERIC_PHY
- 	  phy users can obtain reference to the PHY. All the users of this
- 	  framework should select this config.
- 
-+config PHY_AR7100_USB
-+	tristate "Atheros AR7100 USB PHY driver"
-+	depends on ATH79 || COMPILE_TEST
-+	default y if USB_EHCI_HCD_PLATFORM
-+	select PHY_SIMPLE
-+	help
-+	  Enable this to support the USB PHY on Atheros AR7100 SoCs.
-+
-+config PHY_AR7200_USB
-+	tristate "Atheros AR7200 USB PHY driver"
-+	depends on ATH79 || COMPILE_TEST
-+	default y if USB_EHCI_HCD_PLATFORM
-+	select PHY_SIMPLE
-+	help
-+	  Enable this to support the USB PHY on Atheros AR7200 SoCs.
-+
- config PHY_LPC18XX_USB_OTG
- 	tristate "NXP LPC18xx/43xx SoC USB OTG PHY driver"
- 	depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
---- a/drivers/phy/Makefile
-+++ b/drivers/phy/Makefile
-@@ -4,6 +4,8 @@
- #
- 
- obj-$(CONFIG_GENERIC_PHY)		+= phy-core.o
-+obj-$(CONFIG_PHY_AR7100_USB)		+= phy-ar7100-usb.o
-+obj-$(CONFIG_PHY_AR7200_USB)		+= phy-ar7200-usb.o
- obj-$(CONFIG_PHY_LPC18XX_USB_OTG)	+= phy-lpc18xx-usb-otg.o
- obj-$(CONFIG_PHY_XGENE)			+= phy-xgene.o
- obj-$(CONFIG_PHY_PISTACHIO_USB)		+= phy-pistachio-usb.o
---- /dev/null
-+++ b/drivers/phy/phy-ar7100-usb.c
-@@ -0,0 +1,140 @@
-+/*
-+ * Copyright (C) 2018 John Crispin <[email protected]>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/phy/phy.h>
-+#include <linux/delay.h>
-+#include <linux/reset.h>
-+#include <linux/of_gpio.h>
-+
-+#include <asm/mach-ath79/ath79.h>
-+#include <asm/mach-ath79/ar71xx_regs.h>
-+
-+struct ar7100_usb_phy {
-+	struct reset_control	*rst_phy;
-+	struct reset_control	*rst_host;
-+	struct reset_control	*rst_ohci_dll;
-+	void __iomem		*io_base;
-+	struct phy		*phy;
-+	int			gpio;
-+};
-+
-+static int ar7100_usb_phy_power_off(struct phy *phy)
-+{
-+	struct ar7100_usb_phy *priv = phy_get_drvdata(phy);
-+	int err = 0;
-+
-+	err |= reset_control_assert(priv->rst_host);
-+	err |= reset_control_assert(priv->rst_phy);
-+	err |= reset_control_assert(priv->rst_ohci_dll);
-+
-+	return err;
-+}
-+
-+static int ar7100_usb_phy_power_on(struct phy *phy)
-+{
-+	struct ar7100_usb_phy *priv = phy_get_drvdata(phy);
-+	int err = 0;
-+
-+	err |= ar7100_usb_phy_power_off(phy);
-+	mdelay(100);
-+	err |= reset_control_deassert(priv->rst_ohci_dll);
-+	err |= reset_control_deassert(priv->rst_phy);
-+	err |= reset_control_deassert(priv->rst_host);
-+	mdelay(500);
-+	iowrite32(0xf0000, priv->io_base + AR71XX_USB_CTRL_REG_CONFIG);
-+	iowrite32(0x20c00, priv->io_base + AR71XX_USB_CTRL_REG_FLADJ);
-+
-+	return err;
-+}
-+
-+static const struct phy_ops ar7100_usb_phy_ops = {
-+	.power_on	= ar7100_usb_phy_power_on,
-+	.power_off	= ar7100_usb_phy_power_off,
-+	.owner		= THIS_MODULE,
-+};
-+
-+static int ar7100_usb_phy_probe(struct platform_device *pdev)
-+{
-+	struct phy_provider *phy_provider;
-+	struct resource *res;
-+	struct ar7100_usb_phy *priv;
-+
-+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	priv->io_base = devm_ioremap_resource(&pdev->dev, res);
-+	if (IS_ERR(priv->io_base))
-+		return PTR_ERR(priv->io_base);
-+
-+	priv->rst_phy = devm_reset_control_get(&pdev->dev, "usb-phy");
-+	if (IS_ERR(priv->rst_phy)) {
-+		dev_err(&pdev->dev, "phy reset is missing\n");
-+		return PTR_ERR(priv->rst_phy);
-+	}
-+
-+	priv->rst_host = devm_reset_control_get(&pdev->dev, "usb-host");
-+	if (IS_ERR(priv->rst_host)) {
-+		dev_err(&pdev->dev, "host reset is missing\n");
-+		return PTR_ERR(priv->rst_host);
-+	}
-+
-+	priv->rst_ohci_dll = devm_reset_control_get(&pdev->dev, "usb-ohci-dll");
-+	if (IS_ERR(priv->rst_ohci_dll)) {
-+		dev_err(&pdev->dev, "ohci-dll reset is missing\n");
-+		return PTR_ERR(priv->rst_host);
-+	}
-+
-+	priv->phy = devm_phy_create(&pdev->dev, NULL, &ar7100_usb_phy_ops);
-+	if (IS_ERR(priv->phy)) {
-+		dev_err(&pdev->dev, "failed to create PHY\n");
-+		return PTR_ERR(priv->phy);
-+	}
-+
-+	priv->gpio = of_get_gpio(pdev->dev.of_node, 0);
-+	if (priv->gpio >= 0) {
-+		int ret = devm_gpio_request(&pdev->dev, priv->gpio, dev_name(&pdev->dev));
-+
-+		if (ret) {
-+			dev_err(&pdev->dev, "failed to request gpio\n");
-+			return ret;
-+		}
-+		gpio_export_with_name(priv->gpio, 0, dev_name(&pdev->dev));
-+		gpio_set_value(priv->gpio, 1);
-+	}
-+
-+	phy_set_drvdata(priv->phy, priv);
-+
-+	phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
-+
-+
-+	return PTR_ERR_OR_ZERO(phy_provider);
-+}
-+
-+static const struct of_device_id ar7100_usb_phy_of_match[] = {
-+	{ .compatible = "qca,ar7100-usb-phy" },
-+	{}
-+};
-+MODULE_DEVICE_TABLE(of, ar7100_usb_phy_of_match);
-+
-+static struct platform_driver ar7100_usb_phy_driver = {
-+	.probe	= ar7100_usb_phy_probe,
-+	.driver = {
-+		.of_match_table	= ar7100_usb_phy_of_match,
-+		.name		= "ar7100-usb-phy",
-+	}
-+};
-+module_platform_driver(ar7100_usb_phy_driver);
-+
-+MODULE_DESCRIPTION("ATH79 USB PHY driver");
-+MODULE_AUTHOR("Alban Bedel <[email protected]>");
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/drivers/phy/phy-ar7200-usb.c
-@@ -0,0 +1,136 @@
-+/*
-+ * Copyright (C) 2015 Alban Bedel <[email protected]>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/phy/phy.h>
-+#include <linux/reset.h>
-+#include <linux/of_gpio.h>
-+
-+struct ar7200_usb_phy {
-+	struct reset_control	*rst_phy;
-+	struct reset_control	*rst_phy_analog;
-+	struct reset_control	*suspend_override;
-+	struct phy		*phy;
-+	int			gpio;
-+};
-+
-+static int ar7200_usb_phy_power_on(struct phy *phy)
-+{
-+	struct ar7200_usb_phy *priv = phy_get_drvdata(phy);
-+	int err = 0;
-+
-+	if (priv->suspend_override)
-+		err = reset_control_assert(priv->suspend_override);
-+	if (priv->rst_phy)
-+		err |= reset_control_deassert(priv->rst_phy);
-+	if (priv->rst_phy_analog)
-+		err |= reset_control_deassert(priv->rst_phy_analog);
-+
-+	return err;
-+}
-+
-+static int ar7200_usb_phy_power_off(struct phy *phy)
-+{
-+	struct ar7200_usb_phy *priv = phy_get_drvdata(phy);
-+	int err = 0;
-+
-+	if (priv->suspend_override)
-+		err = reset_control_deassert(priv->suspend_override);
-+	if (priv->rst_phy)
-+		err |= reset_control_assert(priv->rst_phy);
-+	if (priv->rst_phy_analog)
-+		err |= reset_control_assert(priv->rst_phy_analog);
-+
-+	return err;
-+}
-+
-+static const struct phy_ops ar7200_usb_phy_ops = {
-+	.power_on	= ar7200_usb_phy_power_on,
-+	.power_off	= ar7200_usb_phy_power_off,
-+	.owner		= THIS_MODULE,
-+};
-+
-+static int ar7200_usb_phy_probe(struct platform_device *pdev)
-+{
-+	struct phy_provider *phy_provider;
-+	struct ar7200_usb_phy *priv;
-+
-+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	priv->rst_phy = devm_reset_control_get(&pdev->dev, "usb-phy");
-+	if (IS_ERR(priv->rst_phy)) {
-+		if (PTR_ERR(priv->rst_phy) != -EPROBE_DEFER)
-+			dev_err(&pdev->dev, "phy reset is missing\n");
-+		return PTR_ERR(priv->rst_phy);
-+	}
-+
-+	priv->rst_phy_analog = devm_reset_control_get_optional(
-+		&pdev->dev, "usb-phy-analog");
-+	if (IS_ERR(priv->rst_phy_analog)) {
-+		if (PTR_ERR(priv->rst_phy_analog) == -ENOENT)
-+			priv->rst_phy_analog = NULL;
-+		else
-+			return PTR_ERR(priv->rst_phy_analog);
-+	}
-+
-+	priv->suspend_override = devm_reset_control_get_optional(
-+		&pdev->dev, "usb-suspend-override");
-+	if (IS_ERR(priv->suspend_override)) {
-+		if (PTR_ERR(priv->suspend_override) == -ENOENT)
-+			priv->suspend_override = NULL;
-+		else
-+			return PTR_ERR(priv->suspend_override);
-+	}
-+
-+	priv->phy = devm_phy_create(&pdev->dev, NULL, &ar7200_usb_phy_ops);
-+	if (IS_ERR(priv->phy)) {
-+		dev_err(&pdev->dev, "failed to create PHY\n");
-+		return PTR_ERR(priv->phy);
-+	}
-+
-+	priv->gpio = of_get_gpio(pdev->dev.of_node, 0);
-+	if (priv->gpio >= 0) {
-+		int ret = devm_gpio_request(&pdev->dev, priv->gpio, dev_name(&pdev->dev));
-+
-+		if (ret) {
-+			dev_err(&pdev->dev, "failed to request gpio\n");
-+			return ret;
-+		}
-+		gpio_export_with_name(priv->gpio, 0, dev_name(&pdev->dev));
-+		gpio_set_value(priv->gpio, 1);
-+	}
-+
-+	phy_set_drvdata(priv->phy, priv);
-+
-+	phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
-+
-+	return PTR_ERR_OR_ZERO(phy_provider);
-+}
-+
-+static const struct of_device_id ar7200_usb_phy_of_match[] = {
-+	{ .compatible = "qca,ar7200-usb-phy" },
-+	{}
-+};
-+MODULE_DEVICE_TABLE(of, ar7200_usb_phy_of_match);
-+
-+static struct platform_driver ar7200_usb_phy_driver = {
-+	.probe	= ar7200_usb_phy_probe,
-+	.driver = {
-+		.of_match_table	= ar7200_usb_phy_of_match,
-+		.name		= "ar7200-usb-phy",
-+	}
-+};
-+module_platform_driver(ar7200_usb_phy_driver);
-+
-+MODULE_DESCRIPTION("ATH79 USB PHY driver");
-+MODULE_AUTHOR("Alban Bedel <[email protected]>");
-+MODULE_LICENSE("GPL");

target/linux/ath79/patches-4.19/0005-usb-add-more-OF-quirk-properties.patch

@@ -1,24 +0,0 @@
-From 2201818e5bd33f389beceb3943fdfcf5a698fc5b Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Tue, 6 Mar 2018 10:01:43 +0100
-Subject: [PATCH 05/27] usb: add more OF/quirk properties
-
-Signed-off-by: John Crispin <[email protected]>
----
- drivers/usb/host/ehci-platform.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/drivers/usb/host/ehci-platform.c
-+++ b/drivers/usb/host/ehci-platform.c
-@@ -271,6 +271,11 @@ static int ehci_platform_probe(struct pl
- 	ehci = hcd_to_ehci(hcd);
- 
- 	if (pdata == &ehci_platform_defaults && dev->dev.of_node) {
-+		of_property_read_u32(dev->dev.of_node, "caps-offset", &pdata->caps_offset);
-+
-+		if (of_property_read_bool(dev->dev.of_node, "has-synopsys-hc-bug"))
-+			pdata->has_synopsys_hc_bug = 1;
-+
- 		if (of_property_read_bool(dev->dev.of_node, "big-endian-regs"))
- 			ehci->big_endian_mmio = 1;
- 

target/linux/ath79/patches-4.19/0007-irqchip-irq-ath79-intc-add-irq-cascade-driver-for-QC.patch

@@ -1,168 +0,0 @@
-From f3eacff2310a60348a755c50a8da6fc251fc8587 Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Tue, 6 Mar 2018 09:55:13 +0100
-Subject: [PATCH 07/33] irqchip/irq-ath79-intc: add irq cascade driver for
- QCA9556 SoCs
-
-Signed-off-by: John Crispin <[email protected]>
----
- drivers/irqchip/Makefile         |   1 +
- drivers/irqchip/irq-ath79-intc.c | 142 +++++++++++++++++++++++++++++++++++++++
- 2 files changed, 143 insertions(+)
- create mode 100644 drivers/irqchip/irq-ath79-intc.c
-
---- a/drivers/irqchip/Makefile
-+++ b/drivers/irqchip/Makefile
-@@ -3,6 +3,7 @@ obj-$(CONFIG_IRQCHIP)			+= irqchip.o
- 
- obj-$(CONFIG_ALPINE_MSI)		+= irq-alpine-msi.o
- obj-$(CONFIG_ATH79)			+= irq-ath79-cpu.o
-+obj-$(CONFIG_ATH79)			+= irq-ath79-intc.o
- obj-$(CONFIG_ATH79)			+= irq-ath79-misc.o
- obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2835.o
- obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2836.o
---- /dev/null
-+++ b/drivers/irqchip/irq-ath79-intc.c
-@@ -0,0 +1,142 @@
-+/*
-+ *  Atheros AR71xx/AR724x/AR913x specific interrupt handling
-+ *
-+ *  Copyright (C) 2018 John Crispin <[email protected]>
-+ *
-+ *  This program is free software; you can redistribute it and/or modify it
-+ *  under the terms of the GNU General Public License version 2 as published
-+ *  by the Free Software Foundation.
-+ */
-+
-+#include <linux/interrupt.h>
-+#include <linux/irqchip.h>
-+#include <linux/of.h>
-+#include <linux/of_irq.h>
-+#include <linux/irqdomain.h>
-+
-+#include <asm/irq_cpu.h>
-+#include <asm/mach-ath79/ath79.h>
-+#include <asm/mach-ath79/ar71xx_regs.h>
-+
-+#define ATH79_MAX_INTC_CASCADE	3
-+
-+struct ath79_intc {
-+	struct irq_chip chip;
-+	u32 irq;
-+	u32 pending_mask;
-+	u32 int_status;
-+	u32 irq_mask[ATH79_MAX_INTC_CASCADE];
-+	u32 irq_wb_chan[ATH79_MAX_INTC_CASCADE];
-+};
-+
-+static void ath79_intc_irq_handler(struct irq_desc *desc)
-+{
-+	struct irq_domain *domain = irq_desc_get_handler_data(desc);
-+	struct ath79_intc *intc = domain->host_data;
-+	u32 pending;
-+
-+	pending = ath79_reset_rr(intc->int_status);
-+	pending &= intc->pending_mask;
-+
-+	if (pending) {
-+		int i;
-+
-+		for (i = 0; i < domain->hwirq_max; i++)
-+			if (pending & intc->irq_mask[i]) {
-+				if (intc->irq_wb_chan[i] != 0xffffffff)
-+					ath79_ddr_wb_flush(intc->irq_wb_chan[i]);
-+				generic_handle_irq(irq_find_mapping(domain, i));
-+			}
-+	} else {
-+		spurious_interrupt();
-+	}
-+}
-+
-+static void ath79_intc_irq_enable(struct irq_data *d)
-+{
-+	struct ath79_intc *intc = d->domain->host_data;
-+	enable_irq(intc->irq);
-+}
-+
-+static void ath79_intc_irq_disable(struct irq_data *d)
-+{
-+	struct ath79_intc *intc = d->domain->host_data;
-+	disable_irq(intc->irq);
-+}
-+
-+static int ath79_intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
-+{
-+	struct ath79_intc *intc = d->host_data;
-+
-+	irq_set_chip_and_handler(irq, &intc->chip, handle_level_irq);
-+
-+	return 0;
-+}
-+
-+static const struct irq_domain_ops ath79_irq_domain_ops = {
-+	.xlate = irq_domain_xlate_onecell,
-+	.map = ath79_intc_map,
-+};
-+
-+static int __init ath79_intc_of_init(
-+	struct device_node *node, struct device_node *parent)
-+{
-+	struct irq_domain *domain;
-+	struct ath79_intc *intc;
-+	int cnt, cntwb, i, err;
-+
-+	cnt = of_property_count_u32_elems(node, "qca,pending-bits");
-+	if (cnt > ATH79_MAX_INTC_CASCADE)
-+		panic("Too many INTC pending bits\n");
-+
-+	intc = kzalloc(sizeof(*intc), GFP_KERNEL);
-+	if (!intc)
-+		panic("Failed to allocate INTC memory\n");
-+	intc->chip = dummy_irq_chip;
-+	intc->chip.name = "INTC";
-+	intc->chip.irq_disable = ath79_intc_irq_disable;
-+	intc->chip.irq_enable = ath79_intc_irq_enable;
-+
-+	if (of_property_read_u32(node, "qca,int-status-addr", &intc->int_status) < 0) {
-+		panic("Missing address of interrupt status register\n");
-+	}
-+
-+	of_property_read_u32_array(node, "qca,pending-bits", intc->irq_mask, cnt);
-+	for (i = 0; i < cnt; i++) {
-+		intc->pending_mask |= intc->irq_mask[i];
-+		intc->irq_wb_chan[i] = 0xffffffff;
-+	}
-+
-+	cntwb = of_count_phandle_with_args(
-+		node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells");
-+
-+	for (i = 0; i < cntwb; i++) {
-+		struct of_phandle_args args;
-+		u32 irq = i;
-+
-+		of_property_read_u32_index(
-+			node, "qca,ddr-wb-channel-interrupts", i, &irq);
-+		if (irq >= ATH79_MAX_INTC_CASCADE)
-+			continue;
-+
-+		err = of_parse_phandle_with_args(
-+			node, "qca,ddr-wb-channels",
-+			"#qca,ddr-wb-channel-cells",
-+			i, &args);
-+		if (err)
-+			return err;
-+
-+		intc->irq_wb_chan[irq] = args.args[0];
-+	}
-+
-+	intc->irq = irq_of_parse_and_map(node, 0);
-+	if (!intc->irq)
-+		panic("Failed to get INTC IRQ");
-+
-+	domain = irq_domain_add_linear(node, cnt, &ath79_irq_domain_ops, intc);
-+	irq_set_chained_handler_and_data(intc->irq, ath79_intc_irq_handler, domain);
-+
-+	return 0;
-+}
-+IRQCHIP_DECLARE(ath79_intc, "qca,ar9340-intc",
-+		ath79_intc_of_init);

target/linux/ath79/patches-4.19/0008-irqchip-irq-ath79-cpu-drop-OF-init-helper.patch

@@ -1,23 +0,0 @@
-From e029f998594f151008ecbfa024e2957edd2a5189 Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Tue, 6 Mar 2018 09:58:19 +0100
-Subject: [PATCH 08/33] irqchip/irq-ath79-cpu: drop !OF init helper
-
-Signed-off-by: John Crispin <[email protected]>
----
- drivers/irqchip/irq-ath79-cpu.c | 7 -------
- 1 file changed, 7 deletions(-)
-
---- a/drivers/irqchip/irq-ath79-cpu.c
-+++ b/drivers/irqchip/irq-ath79-cpu.c
-@@ -88,10 +88,3 @@ static int __init ar79_cpu_intc_of_init(
- }
- IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc",
- 		ar79_cpu_intc_of_init);
--
--void __init ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3)
--{
--	irq_wb_chan[2] = irq_wb_chan2;
--	irq_wb_chan[3] = irq_wb_chan3;
--	mips_cpu_irq_init();
--}

target/linux/ath79/patches-4.19/0011-MIPS-ath79-select-the-PINCTRL-subsystem.patch

@@ -1,24 +0,0 @@
-From 0c8856211d26f84277f7fcb0b9595e5c646bc464 Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Tue, 6 Mar 2018 10:00:55 +0100
-Subject: [PATCH 11/33] MIPS: ath79: select the PINCTRL subsystem
-
-The pinmux on QCA SoCs is controlled by a single register. The
-"pinctrl-single" driver can be used but requires the target
-to select PINCTRL.
-
-Signed-off-by: John Crispin <[email protected]>
----
- arch/mips/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -288,6 +288,7 @@ config BCM63XX
- 	select SYS_HAS_EARLY_PRINTK
- 	select SWAP_IO_SPACE
- 	select GPIOLIB
-+	select PINCTRL
- 	select HAVE_CLK
- 	select MIPS_L1_CACHE_SHIFT_4
- 	select CLKDEV_LOOKUP

target/linux/ath79/patches-4.19/0017-dt-bindings-PCI-qcom-ar7100-adds-binding-doc.patch

@@ -1,57 +0,0 @@
-From 4a4f869ec58ed8910b9b2e68d0eee50957e9bb20 Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Mon, 25 Jun 2018 15:52:10 +0200
-Subject: [PATCH 17/33] dt-bindings: PCI: qcom,ar7100: adds binding doc
-
-With the driver being converted from platform_data to pure OF, we need to
-also add some docs.
-
-Cc: Rob Herring <[email protected]>
-Cc: [email protected]
-Signed-off-by: John Crispin <[email protected]>
----
- .../devicetree/bindings/pci/qcom,ar7100-pci.txt    | 38 ++++++++++++++++++++++
- 1 file changed, 38 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
-@@ -0,0 +1,38 @@
-+* Qualcomm Atheros AR7100 PCI express root complex
-+
-+Required properties:
-+- compatible: should contain "qcom,ar7100-pci" to identify the core.
-+- reg: Should contain the register ranges as listed in the reg-names property.
-+- reg-names: Definition: Must include the following entries
-+	- "cfg_base"	IO Memory
-+- #address-cells: set to <3>
-+- #size-cells: set to <2>
-+- ranges: ranges for the PCI memory and I/O regions
-+- interrupt-map-mask and interrupt-map: standard PCI
-+	properties to define the mapping of the PCIe interface to interrupt
-+	numbers.
-+- #interrupt-cells: set to <1>
-+- interrupt-controller: define to enable the builtin IRQ cascade.
-+
-+Optional properties:
-+- interrupt-parent: phandle to the MIPS IRQ controller
-+
-+* Example for ar7100
-+	pcie-controller@180c0000 {
-+		compatible = "qca,ar7100-pci";
-+		#address-cells = <3>;
-+		#size-cells = <2>;
-+		bus-range = <0x0 0x0>;
-+		reg = <0x17010000 0x100>;
-+		reg-names = "cfg_base";
-+		ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000
-+			  0x1000000 0 0x00000000 0x00000000 0 0x00000001>;
-+		interrupt-parent = <&cpuintc>;
-+		interrupts = <2>;
-+
-+		interrupt-controller;
-+		#interrupt-cells = <1>;
-+
-+		interrupt-map-mask = <0 0 0 1>;
-+		interrupt-map = <0 0 0 0 &pcie0 0>;
-+	};

target/linux/ath79/patches-4.19/0018-MIPS-pci-ar71xx-convert-to-OF.patch

@@ -1,202 +0,0 @@
-From 1855ab6b1d27f5b38a648baf57ff6a534afec26d Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Sat, 23 Jun 2018 15:07:23 +0200
-Subject: [PATCH 18/33] MIPS: pci-ar71xx: convert to OF
-
-With the ath79 target getting converted to pure OF, we can drop all the
-platform data code and add the missing OF bits to the driver. We also add
-a irq domain for the PCI/e controllers cascade, thus making it usable from
-dts files.
-
-Signed-off-by: John Crispin <[email protected]>
----
- arch/mips/pci/pci-ar71xx.c | 82 +++++++++++++++++++++++-----------------------
- 1 file changed, 41 insertions(+), 41 deletions(-)
-
---- a/arch/mips/pci/pci-ar71xx.c
-+++ b/arch/mips/pci/pci-ar71xx.c
-@@ -18,8 +18,11 @@
- #include <linux/pci.h>
- #include <linux/pci_regs.h>
- #include <linux/interrupt.h>
-+#include <linux/irqchip/chained_irq.h>
- #include <linux/init.h>
- #include <linux/platform_device.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_pci.h>
- 
- #include <asm/mach-ath79/ar71xx_regs.h>
- #include <asm/mach-ath79/ath79.h>
-@@ -49,12 +52,13 @@
- #define AR71XX_PCI_IRQ_COUNT		5
- 
- struct ar71xx_pci_controller {
-+	struct device_node *np;
- 	void __iomem *cfg_base;
- 	int irq;
--	int irq_base;
- 	struct pci_controller pci_ctrl;
- 	struct resource io_res;
- 	struct resource mem_res;
-+	struct irq_domain *domain;
- };
- 
- /* Byte lane enable bits */
-@@ -228,29 +232,30 @@ static struct pci_ops ar71xx_pci_ops = {
- 
- static void ar71xx_pci_irq_handler(struct irq_desc *desc)
- {
--	struct ar71xx_pci_controller *apc;
- 	void __iomem *base = ath79_reset_base;
-+	struct irq_chip *chip = irq_desc_get_chip(desc);
-+	struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);
- 	u32 pending;
- 
--	apc = irq_desc_get_handler_data(desc);
--
-+	chained_irq_enter(chip, desc);
- 	pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
- 		  __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
- 
- 	if (pending & AR71XX_PCI_INT_DEV0)
--		generic_handle_irq(apc->irq_base + 0);
-+		generic_handle_irq(irq_linear_revmap(apc->domain, 1));
- 
- 	else if (pending & AR71XX_PCI_INT_DEV1)
--		generic_handle_irq(apc->irq_base + 1);
-+		generic_handle_irq(irq_linear_revmap(apc->domain, 2));
- 
- 	else if (pending & AR71XX_PCI_INT_DEV2)
--		generic_handle_irq(apc->irq_base + 2);
-+		generic_handle_irq(irq_linear_revmap(apc->domain, 3));
- 
- 	else if (pending & AR71XX_PCI_INT_CORE)
--		generic_handle_irq(apc->irq_base + 4);
-+		generic_handle_irq(irq_linear_revmap(apc->domain, 4));
- 
- 	else
- 		spurious_interrupt();
-+	chained_irq_exit(chip, desc);
- }
- 
- static void ar71xx_pci_irq_unmask(struct irq_data *d)
-@@ -261,7 +266,7 @@ static void ar71xx_pci_irq_unmask(struct
- 	u32 t;
- 
- 	apc = irq_data_get_irq_chip_data(d);
--	irq = d->irq - apc->irq_base;
-+	irq = irq_linear_revmap(apc->domain, d->irq);
- 
- 	t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
- 	__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-@@ -278,7 +283,7 @@ static void ar71xx_pci_irq_mask(struct i
- 	u32 t;
- 
- 	apc = irq_data_get_irq_chip_data(d);
--	irq = d->irq - apc->irq_base;
-+	irq = irq_linear_revmap(apc->domain, d->irq);
- 
- 	t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
- 	__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-@@ -294,24 +299,31 @@ static struct irq_chip ar71xx_pci_irq_ch
- 	.irq_mask_ack	= ar71xx_pci_irq_mask,
- };
- 
-+static int ar71xx_pci_irq_map(struct irq_domain *d,
-+			      unsigned int irq, irq_hw_number_t hw)
-+{
-+	struct ar71xx_pci_controller *apc = d->host_data;
-+
-+	irq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq);
-+	irq_set_chip_data(irq, apc);
-+
-+	return 0;
-+}
-+
-+static const struct irq_domain_ops ar71xx_pci_domain_ops = {
-+	.xlate = irq_domain_xlate_onecell,
-+	.map = ar71xx_pci_irq_map,
-+};
-+
- static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
- {
- 	void __iomem *base = ath79_reset_base;
--	int i;
- 
- 	__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
- 	__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
- 
--	BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
--
--	apc->irq_base = ATH79_PCI_IRQ_BASE;
--	for (i = apc->irq_base;
--	     i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) {
--		irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
--					 handle_level_irq);
--		irq_set_chip_data(i, apc);
--	}
--
-+	apc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT,
-+					    &ar71xx_pci_domain_ops, apc);
- 	irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,
- 					 apc);
- }
-@@ -328,6 +340,11 @@ static void ar71xx_pci_reset(void)
- 	mdelay(100);
- }
- 
-+static const struct of_device_id ar71xx_pci_ids[] = {
-+	{ .compatible = "qca,ar7100-pci" },
-+	{},
-+};
-+
- static int ar71xx_pci_probe(struct platform_device *pdev)
- {
- 	struct ar71xx_pci_controller *apc;
-@@ -348,26 +365,6 @@ static int ar71xx_pci_probe(struct platf
- 	if (apc->irq < 0)
- 		return -EINVAL;
- 
--	res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
--	if (!res)
--		return -EINVAL;
--
--	apc->io_res.parent = res;
--	apc->io_res.name = "PCI IO space";
--	apc->io_res.start = res->start;
--	apc->io_res.end = res->end;
--	apc->io_res.flags = IORESOURCE_IO;
--
--	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
--	if (!res)
--		return -EINVAL;
--
--	apc->mem_res.parent = res;
--	apc->mem_res.name = "PCI memory space";
--	apc->mem_res.start = res->start;
--	apc->mem_res.end = res->end;
--	apc->mem_res.flags = IORESOURCE_MEM;
--
- 	ar71xx_pci_reset();
- 
- 	/* setup COMMAND register */
-@@ -380,9 +377,11 @@ static int ar71xx_pci_probe(struct platf
- 
- 	ar71xx_pci_irq_init(apc);
- 
-+	apc->np = pdev->dev.of_node;
- 	apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
- 	apc->pci_ctrl.mem_resource = &apc->mem_res;
- 	apc->pci_ctrl.io_resource = &apc->io_res;
-+	pci_load_of_ranges(&apc->pci_ctrl, pdev->dev.of_node);
- 
- 	register_pci_controller(&apc->pci_ctrl);
- 
-@@ -393,6 +392,7 @@ static struct platform_driver ar71xx_pci
- 	.probe = ar71xx_pci_probe,
- 	.driver = {
- 		.name = "ar71xx-pci",
-+		.of_match_table = of_match_ptr(ar71xx_pci_ids),
- 	},
- };
- 

target/linux/ath79/patches-4.19/0019-dt-bindings-PCI-qcom-ar7240-adds-binding-doc.patch

@@ -1,61 +0,0 @@
-From ea27764bc3ef2a05decf3ae05edffc289cd0d93c Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Mon, 25 Jun 2018 15:52:02 +0200
-Subject: [PATCH 19/33] dt-bindings: PCI: qcom,ar7240: adds binding doc
-
-With the driver being converted from platform_data to pure OF, we need to
-also add some docs.
-
-Cc: Rob Herring <[email protected]>
-Cc: [email protected]
-Signed-off-by: John Crispin <[email protected]>
----
- .../devicetree/bindings/pci/qcom,ar7240-pci.txt    | 42 ++++++++++++++++++++++
- 1 file changed, 42 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt
-@@ -0,0 +1,42 @@
-+* Qualcomm Atheros AR724X PCI express root complex
-+
-+Required properties:
-+- compatible: should contain "qcom,ar7240-pci" to identify the core.
-+- reg: Should contain the register ranges as listed in the reg-names property.
-+- reg-names: Definition: Must include the following entries
-+	- "crp_base"	Configuration registers
-+	- "ctrl_base"	Control registers
-+	- "cfg_base"	IO Memory
-+- #address-cells: set to <3>
-+- #size-cells: set to <2>
-+- ranges: ranges for the PCI memory and I/O regions
-+- interrupt-map-mask and interrupt-map: standard PCI
-+	properties to define the mapping of the PCIe interface to interrupt
-+	numbers.
-+- #interrupt-cells: set to <1>
-+- interrupt-parent: phandle to the MIPS IRQ controller
-+
-+Optional properties:
-+- interrupt-controller: define to enable the builtin IRQ cascade.
-+
-+* Example for qca9557
-+	pcie-controller@180c0000 {
-+		compatible = "qcom,ar7240-pci";
-+		#address-cells = <3>;
-+		#size-cells = <2>;
-+		bus-range = <0x0 0x0>;
-+		reg = <0x180c0000 0x1000>,
-+		      <0x180f0000 0x100>,
-+		      <0x14000000 0x1000>;
-+		reg-names = "crp_base", "ctrl_base", "cfg_base";
-+		ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000
-+			  0x1000000 0 0x00000000 0x00000000 0 0x00000001>;
-+		interrupt-parent = <&intc2>;
-+		interrupts = <1>;
-+
-+		interrupt-controller;
-+		#interrupt-cells = <1>;
-+
-+		interrupt-map-mask = <0 0 0 1>;
-+		interrupt-map = <0 0 0 0 &pcie0 0>;
-+	};

target/linux/ath79/patches-4.19/0020-MIPS-pci-ar724x-convert-to-OF.patch

@@ -1,205 +0,0 @@
-From a522ee0199d5d3ea114ca2e211f6ac398d3e8e0b Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Sat, 23 Jun 2018 15:07:37 +0200
-Subject: [PATCH 20/33] MIPS: pci-ar724x: convert to OF
-
-With the ath79 target getting converted to pure OF, we can drop all the
-platform data code and add the missing OF bits to the driver. We also add
-a irq domain for the PCI/e controllers cascade, thus making it usable from
-dts files.
-
-Signed-off-by: John Crispin <[email protected]>
----
- arch/mips/pci/pci-ar724x.c | 88 ++++++++++++++++++++++------------------------
- 1 file changed, 42 insertions(+), 46 deletions(-)
-
---- a/arch/mips/pci/pci-ar724x.c
-+++ b/arch/mips/pci/pci-ar724x.c
-@@ -14,8 +14,11 @@
- #include <linux/init.h>
- #include <linux/delay.h>
- #include <linux/platform_device.h>
-+#include <linux/irqchip/chained_irq.h>
- #include <asm/mach-ath79/ath79.h>
- #include <asm/mach-ath79/ar71xx_regs.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_pci.h>
- 
- #define AR724X_PCI_REG_APP		0x00
- #define AR724X_PCI_REG_RESET		0x18
-@@ -45,17 +48,20 @@ struct ar724x_pci_controller {
- 	void __iomem *crp_base;
- 
- 	int irq;
--	int irq_base;
- 
- 	bool link_up;
- 	bool bar0_is_cached;
- 	u32  bar0_value;
- 
-+	struct device_node *np;
- 	struct pci_controller pci_controller;
-+	struct irq_domain *domain;
- 	struct resource io_res;
- 	struct resource mem_res;
- };
- 
-+static struct irq_chip ar724x_pci_irq_chip;
-+
- static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
- {
- 	u32 reset;
-@@ -231,35 +237,31 @@ static struct pci_ops ar724x_pci_ops = {
- 
- static void ar724x_pci_irq_handler(struct irq_desc *desc)
- {
--	struct ar724x_pci_controller *apc;
--	void __iomem *base;
-+	struct irq_chip *chip = irq_desc_get_chip(desc);
-+	struct ar724x_pci_controller *apc = irq_desc_get_handler_data(desc);
- 	u32 pending;
- 
--	apc = irq_desc_get_handler_data(desc);
--	base = apc->ctrl_base;
--
--	pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
--		  __raw_readl(base + AR724X_PCI_REG_INT_MASK);
-+	chained_irq_enter(chip, desc);
-+	pending = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_STATUS) &
-+		  __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_MASK);
- 
- 	if (pending & AR724X_PCI_INT_DEV0)
--		generic_handle_irq(apc->irq_base + 0);
--
-+		generic_handle_irq(irq_linear_revmap(apc->domain, 1));
- 	else
- 		spurious_interrupt();
-+	chained_irq_exit(chip, desc);
- }
- 
- static void ar724x_pci_irq_unmask(struct irq_data *d)
- {
- 	struct ar724x_pci_controller *apc;
- 	void __iomem *base;
--	int offset;
- 	u32 t;
- 
- 	apc = irq_data_get_irq_chip_data(d);
- 	base = apc->ctrl_base;
--	offset = apc->irq_base - d->irq;
- 
--	switch (offset) {
-+	switch (irq_linear_revmap(apc->domain, d->irq)) {
- 	case 0:
- 		t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
- 		__raw_writel(t | AR724X_PCI_INT_DEV0,
-@@ -273,14 +275,12 @@ static void ar724x_pci_irq_mask(struct i
- {
- 	struct ar724x_pci_controller *apc;
- 	void __iomem *base;
--	int offset;
- 	u32 t;
- 
- 	apc = irq_data_get_irq_chip_data(d);
- 	base = apc->ctrl_base;
--	offset = apc->irq_base - d->irq;
- 
--	switch (offset) {
-+	switch (irq_linear_revmap(apc->domain, d->irq)) {
- 	case 0:
- 		t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
- 		__raw_writel(t & ~AR724X_PCI_INT_DEV0,
-@@ -305,26 +305,34 @@ static struct irq_chip ar724x_pci_irq_ch
- 	.irq_mask_ack	= ar724x_pci_irq_mask,
- };
- 
-+static int ar724x_pci_irq_map(struct irq_domain *d,
-+			      unsigned int irq, irq_hw_number_t hw)
-+{
-+	struct ar724x_pci_controller *apc = d->host_data;
-+
-+	irq_set_chip_and_handler(irq, &ar724x_pci_irq_chip, handle_level_irq);
-+	irq_set_chip_data(irq, apc);
-+
-+	return 0;
-+}
-+
-+static const struct irq_domain_ops ar724x_pci_domain_ops = {
-+	.xlate = irq_domain_xlate_onecell,
-+	.map = ar724x_pci_irq_map,
-+};
-+
- static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
- 				int id)
- {
- 	void __iomem *base;
--	int i;
- 
- 	base = apc->ctrl_base;
- 
- 	__raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
- 	__raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
- 
--	apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
--
--	for (i = apc->irq_base;
--	     i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
--		irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
--					 handle_level_irq);
--		irq_set_chip_data(i, apc);
--	}
--
-+	apc->domain = irq_domain_add_linear(apc->np, 2,
-+					    &ar724x_pci_domain_ops, apc);
- 	irq_set_chained_handler_and_data(apc->irq, ar724x_pci_irq_handler,
- 					 apc);
- }
-@@ -394,29 +402,11 @@ static int ar724x_pci_probe(struct platf
- 	if (apc->irq < 0)
- 		return -EINVAL;
- 
--	res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
--	if (!res)
--		return -EINVAL;
--
--	apc->io_res.parent = res;
--	apc->io_res.name = "PCI IO space";
--	apc->io_res.start = res->start;
--	apc->io_res.end = res->end;
--	apc->io_res.flags = IORESOURCE_IO;
--
--	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
--	if (!res)
--		return -EINVAL;
--
--	apc->mem_res.parent = res;
--	apc->mem_res.name = "PCI memory space";
--	apc->mem_res.start = res->start;
--	apc->mem_res.end = res->end;
--	apc->mem_res.flags = IORESOURCE_MEM;
--
-+	apc->np = pdev->dev.of_node;
- 	apc->pci_controller.pci_ops = &ar724x_pci_ops;
- 	apc->pci_controller.io_resource = &apc->io_res;
- 	apc->pci_controller.mem_resource = &apc->mem_res;
-+	pci_load_of_ranges(&apc->pci_controller, pdev->dev.of_node);
- 
- 	/*
- 	 * Do the full PCIE Root Complex Initialization Sequence if the PCIe
-@@ -438,10 +428,16 @@ static int ar724x_pci_probe(struct platf
- 	return 0;
- }
- 
-+static const struct of_device_id ar724x_pci_ids[] = {
-+	{ .compatible = "qcom,ar7240-pci" },
-+	{},
-+};
-+
- static struct platform_driver ar724x_pci_driver = {
- 	.probe = ar724x_pci_probe,
- 	.driver = {
- 		.name = "ar724x-pci",
-+		.of_match_table = of_match_ptr(ar724x_pci_ids),
- 	},
- };
- 

target/linux/ath79/patches-4.19/0021-MIPS-ath79-add-helpers-for-setting-clocks-and-expose.patch

@@ -1,243 +0,0 @@
-From 288a8eb0d41f09fda242e05f8a7bd1f5b3489477 Mon Sep 17 00:00:00 2001
-From: Felix Fietkau <[email protected]>
-Date: Tue, 6 Mar 2018 13:19:26 +0100
-Subject: [PATCH 21/33] MIPS: ath79: add helpers for setting clocks and expose
- the ref clock
-
-Preparation for transitioning the legacy clock setup code over
-to OF.
-
-Signed-off-by: Felix Fietkau <[email protected]>
-Signed-off-by: John Crispin <[email protected]>
----
- arch/mips/ath79/clock.c               | 128 ++++++++++++++++++----------------
- include/dt-bindings/clock/ath79-clk.h |   3 +-
- 2 files changed, 68 insertions(+), 63 deletions(-)
-
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -37,20 +37,46 @@ static struct clk_onecell_data clk_data
- 	.clk_num = ARRAY_SIZE(clks),
- };
- 
--static struct clk *__init ath79_add_sys_clkdev(
--	const char *id, unsigned long rate)
-+static const char * const clk_names[ATH79_CLK_END] = {
-+	[ATH79_CLK_CPU] = "cpu",
-+	[ATH79_CLK_DDR] = "ddr",
-+	[ATH79_CLK_AHB] = "ahb",
-+	[ATH79_CLK_REF] = "ref",
-+};
-+
-+static const char * __init ath79_clk_name(int type)
- {
--	struct clk *clk;
--	int err;
-+	BUG_ON(type >= ARRAY_SIZE(clk_names) || !clk_names[type]);
-+	return clk_names[type];
-+}
- 
--	clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
-+static void __init __ath79_set_clk(int type, const char *name, struct clk *clk)
-+{
- 	if (IS_ERR(clk))
--		panic("failed to allocate %s clock structure", id);
-+		panic("failed to allocate %s clock structure", clk_names[type]);
- 
--	err = clk_register_clkdev(clk, id, NULL);
--	if (err)
--		panic("unable to register %s clock device", id);
-+	clks[type] = clk;
-+	clk_register_clkdev(clk, name, NULL);
-+}
- 
-+static struct clk * __init ath79_set_clk(int type, unsigned long rate)
-+{
-+	const char *name = ath79_clk_name(type);
-+	struct clk *clk;
-+
-+	clk = clk_register_fixed_rate(NULL, name, NULL, 0, rate);
-+	__ath79_set_clk(type, name, clk);
-+	return clk;
-+}
-+
-+static struct clk * __init ath79_set_ff_clk(int type, const char *parent,
-+					    unsigned int mult, unsigned int div)
-+{
-+	const char *name = ath79_clk_name(type);
-+	struct clk *clk;
-+
-+	clk = clk_register_fixed_factor(NULL, name, parent, 0, mult, div);
-+	__ath79_set_clk(type, name, clk);
- 	return clk;
- }
- 
-@@ -80,27 +106,15 @@ static void __init ar71xx_clocks_init(vo
- 	div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
- 	ahb_rate = cpu_rate / div;
- 
--	ath79_add_sys_clkdev("ref", ref_rate);
--	clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
--	clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
--	clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
-+	ath79_set_clk(ATH79_CLK_REF, ref_rate);
-+	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
-+	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
-+	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
- 
- 	clk_add_alias("wdt", NULL, "ahb", NULL);
- 	clk_add_alias("uart", NULL, "ahb", NULL);
- }
- 
--static struct clk * __init ath79_reg_ffclk(const char *name,
--		const char *parent_name, unsigned int mult, unsigned int div)
--{
--	struct clk *clk;
--
--	clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
--	if (IS_ERR(clk))
--		panic("failed to allocate %s clock structure", name);
--
--	return clk;
--}
--
- static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
- {
- 	u32 pll;
-@@ -114,24 +128,19 @@ static void __init ar724x_clk_init(struc
- 	ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
- 	ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
- 
--	clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div);
--	clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div);
--	clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div);
-+	ath79_set_ff_clk(ATH79_CLK_CPU, "ref", mult, div);
-+	ath79_set_ff_clk(ATH79_CLK_DDR, "ref", mult, div * ddr_div);
-+	ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
- }
- 
- static void __init ar724x_clocks_init(void)
- {
- 	struct clk *ref_clk;
- 
--	ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ);
-+	ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
- 
- 	ar724x_clk_init(ref_clk, ath79_pll_base);
- 
--	/* just make happy plat_time_init() from arch/mips/ath79/setup.c */
--	clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
--	clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
--	clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
--
- 	clk_add_alias("wdt", NULL, "ahb", NULL);
- 	clk_add_alias("uart", NULL, "ahb", NULL);
- }
-@@ -186,12 +195,12 @@ static void __init ar9330_clk_init(struc
- 		     AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
- 	}
- 
--	clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref",
--					ninit_mul, ref_div * out_div * cpu_div);
--	clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref",
--					ninit_mul, ref_div * out_div * ddr_div);
--	clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref",
--					ninit_mul, ref_div * out_div * ahb_div);
-+	ath79_set_ff_clk(ATH79_CLK_CPU, "ref", ninit_mul,
-+			 ref_div * out_div * cpu_div);
-+	ath79_set_ff_clk(ATH79_CLK_DDR, "ref", ninit_mul,
-+			 ref_div * out_div * ddr_div);
-+	ath79_set_ff_clk(ATH79_CLK_AHB, "ref", ninit_mul,
-+			 ref_div * out_div * ahb_div);
- }
- 
- static void __init ar933x_clocks_init(void)
-@@ -206,15 +215,10 @@ static void __init ar933x_clocks_init(vo
- 	else
- 		ref_rate = (25 * 1000 * 1000);
- 
--	ref_clk = ath79_add_sys_clkdev("ref", ref_rate);
-+	ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
- 
- 	ar9330_clk_init(ref_clk, ath79_pll_base);
- 
--	/* just make happy plat_time_init() from arch/mips/ath79/setup.c */
--	clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
--	clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
--	clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
--
- 	clk_add_alias("wdt", NULL, "ahb", NULL);
- 	clk_add_alias("uart", NULL, "ref", NULL);
- }
-@@ -344,10 +348,10 @@ static void __init ar934x_clocks_init(vo
- 	else
- 		ahb_rate = cpu_pll / (postdiv + 1);
- 
--	ath79_add_sys_clkdev("ref", ref_rate);
--	clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
--	clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
--	clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
-+	ath79_set_clk(ATH79_CLK_REF, ref_rate);
-+	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
-+	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
-+	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
- 
- 	clk_add_alias("wdt", NULL, "ref", NULL);
- 	clk_add_alias("uart", NULL, "ref", NULL);
-@@ -431,10 +435,10 @@ static void __init qca953x_clocks_init(v
- 	else
- 		ahb_rate = cpu_pll / (postdiv + 1);
- 
--	ath79_add_sys_clkdev("ref", ref_rate);
--	ath79_add_sys_clkdev("cpu", cpu_rate);
--	ath79_add_sys_clkdev("ddr", ddr_rate);
--	ath79_add_sys_clkdev("ahb", ahb_rate);
-+	ath79_set_clk(ATH79_CLK_REF, ref_rate);
-+	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
-+	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
-+	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
- 
- 	clk_add_alias("wdt", NULL, "ref", NULL);
- 	clk_add_alias("uart", NULL, "ref", NULL);
-@@ -516,10 +520,10 @@ static void __init qca955x_clocks_init(v
- 	else
- 		ahb_rate = cpu_pll / (postdiv + 1);
- 
--	ath79_add_sys_clkdev("ref", ref_rate);
--	clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
--	clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
--	clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
-+	ath79_set_clk(ATH79_CLK_REF, ref_rate);
-+	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
-+	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
-+	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
- 
- 	clk_add_alias("wdt", NULL, "ref", NULL);
- 	clk_add_alias("uart", NULL, "ref", NULL);
-@@ -620,10 +624,10 @@ static void __init qca956x_clocks_init(v
- 	else
- 		ahb_rate = cpu_pll / (postdiv + 1);
- 
--	ath79_add_sys_clkdev("ref", ref_rate);
--	ath79_add_sys_clkdev("cpu", cpu_rate);
--	ath79_add_sys_clkdev("ddr", ddr_rate);
--	ath79_add_sys_clkdev("ahb", ahb_rate);
-+	ath79_set_clk(ATH79_CLK_REF, ref_rate);
-+	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
-+	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
-+	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
- 
- 	clk_add_alias("wdt", NULL, "ref", NULL);
- 	clk_add_alias("uart", NULL, "ref", NULL);
---- a/include/dt-bindings/clock/ath79-clk.h
-+++ b/include/dt-bindings/clock/ath79-clk.h
-@@ -13,7 +13,8 @@
- #define ATH79_CLK_CPU		0
- #define ATH79_CLK_DDR		1
- #define ATH79_CLK_AHB		2
-+#define ATH79_CLK_REF		3
- 
--#define ATH79_CLK_END		3
-+#define ATH79_CLK_END		4
- 
- #endif /* __DT_BINDINGS_ATH79_CLK_H */

target/linux/ath79/patches-4.19/0022-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch

@@ -1,114 +0,0 @@
-From 339c191a95e978353c9ba3aafab0261e14de109b Mon Sep 17 00:00:00 2001
-From: Felix Fietkau <[email protected]>
-Date: Tue, 6 Mar 2018 13:22:43 +0100
-Subject: [PATCH 22/33] MIPS: ath79: move legacy "wdt" and "uart" clock aliases
- out of soc init
-
-Preparation for reusing functions for DT
-
-Signed-off-by: Felix Fietkau <[email protected]>
-Signed-off-by: John Crispin <[email protected]>
----
- arch/mips/ath79/clock.c | 38 +++++++++++++++++---------------------
- 1 file changed, 17 insertions(+), 21 deletions(-)
-
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -110,9 +110,6 @@ static void __init ar71xx_clocks_init(vo
- 	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
- 	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
--
--	clk_add_alias("wdt", NULL, "ahb", NULL);
--	clk_add_alias("uart", NULL, "ahb", NULL);
- }
- 
- static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
-@@ -140,9 +137,6 @@ static void __init ar724x_clocks_init(vo
- 	ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
- 
- 	ar724x_clk_init(ref_clk, ath79_pll_base);
--
--	clk_add_alias("wdt", NULL, "ahb", NULL);
--	clk_add_alias("uart", NULL, "ahb", NULL);
- }
- 
- static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
-@@ -218,9 +212,6 @@ static void __init ar933x_clocks_init(vo
- 	ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
- 
- 	ar9330_clk_init(ref_clk, ath79_pll_base);
--
--	clk_add_alias("wdt", NULL, "ahb", NULL);
--	clk_add_alias("uart", NULL, "ref", NULL);
- }
- 
- static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
-@@ -353,9 +344,6 @@ static void __init ar934x_clocks_init(vo
- 	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
- 
--	clk_add_alias("wdt", NULL, "ref", NULL);
--	clk_add_alias("uart", NULL, "ref", NULL);
--
- 	iounmap(dpll_base);
- }
- 
-@@ -439,9 +427,6 @@ static void __init qca953x_clocks_init(v
- 	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
- 	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
--
--	clk_add_alias("wdt", NULL, "ref", NULL);
--	clk_add_alias("uart", NULL, "ref", NULL);
- }
- 
- static void __init qca955x_clocks_init(void)
-@@ -524,9 +509,6 @@ static void __init qca955x_clocks_init(v
- 	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
- 	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
--
--	clk_add_alias("wdt", NULL, "ref", NULL);
--	clk_add_alias("uart", NULL, "ref", NULL);
- }
- 
- static void __init qca956x_clocks_init(void)
-@@ -628,13 +610,13 @@ static void __init qca956x_clocks_init(v
- 	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
- 	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
--
--	clk_add_alias("wdt", NULL, "ref", NULL);
--	clk_add_alias("uart", NULL, "ref", NULL);
- }
- 
- void __init ath79_clocks_init(void)
- {
-+	const char *wdt;
-+	const char *uart;
-+
- 	if (soc_is_ar71xx())
- 		ar71xx_clocks_init();
- 	else if (soc_is_ar724x() || soc_is_ar913x())
-@@ -651,6 +633,20 @@ void __init ath79_clocks_init(void)
- 		qca956x_clocks_init();
- 	else
- 		BUG();
-+
-+	if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) {
-+		wdt = "ahb";
-+		uart = "ahb";
-+	} else if (soc_is_ar933x()) {
-+		wdt = "ahb";
-+		uart = "ref";
-+	} else {
-+		wdt = "ref";
-+		uart = "ref";
-+	}
-+
-+	clk_add_alias("wdt", NULL, wdt, NULL);
-+	clk_add_alias("uart", NULL, uart, NULL);
- }
- 
- unsigned long __init

target/linux/ath79/patches-4.19/0023-MIPS-ath79-pass-PLL-base-to-clock-init-functions.patch

@@ -1,242 +0,0 @@
-From 6350b2c36c522fecbc91a80b63f49319dafd2a72 Mon Sep 17 00:00:00 2001
-From: Felix Fietkau <[email protected]>
-Date: Tue, 6 Mar 2018 13:23:20 +0100
-Subject: [PATCH 23/33] MIPS: ath79: pass PLL base to clock init functions
-
-Preparation for passing the mapped base via DT
-
-Signed-off-by: Felix Fietkau <[email protected]>
-Signed-off-by: John Crispin <[email protected]>
----
- arch/mips/ath79/clock.c | 60 ++++++++++++++++++++++++-------------------------
- 1 file changed, 30 insertions(+), 30 deletions(-)
-
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -80,7 +80,7 @@ static struct clk * __init ath79_set_ff_
- 	return clk;
- }
- 
--static void __init ar71xx_clocks_init(void)
-+static void __init ar71xx_clocks_init(void __iomem *pll_base)
- {
- 	unsigned long ref_rate;
- 	unsigned long cpu_rate;
-@@ -92,7 +92,7 @@ static void __init ar71xx_clocks_init(vo
- 
- 	ref_rate = AR71XX_BASE_FREQ;
- 
--	pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
-+	pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
- 
- 	div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
- 	freq = div * ref_rate;
-@@ -130,13 +130,13 @@ static void __init ar724x_clk_init(struc
- 	ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
- }
- 
--static void __init ar724x_clocks_init(void)
-+static void __init ar724x_clocks_init(void __iomem *pll_base)
- {
- 	struct clk *ref_clk;
- 
- 	ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
- 
--	ar724x_clk_init(ref_clk, ath79_pll_base);
-+	ar724x_clk_init(ref_clk, pll_base);
- }
- 
- static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
-@@ -197,7 +197,7 @@ static void __init ar9330_clk_init(struc
- 			 ref_div * out_div * ahb_div);
- }
- 
--static void __init ar933x_clocks_init(void)
-+static void __init ar933x_clocks_init(void __iomem *pll_base)
- {
- 	struct clk *ref_clk;
- 	unsigned long ref_rate;
-@@ -234,7 +234,7 @@ static u32 __init ar934x_get_pll_freq(u3
- 	return ret;
- }
- 
--static void __init ar934x_clocks_init(void)
-+static void __init ar934x_clocks_init(void __iomem *pll_base)
- {
- 	unsigned long ref_rate;
- 	unsigned long cpu_rate;
-@@ -265,7 +265,7 @@ static void __init ar934x_clocks_init(vo
- 			  AR934X_SRIF_DPLL1_REFDIV_MASK;
- 		frac = 1 << 18;
- 	} else {
--		pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
-+		pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG);
- 		out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
- 			AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
- 		ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
-@@ -292,7 +292,7 @@ static void __init ar934x_clocks_init(vo
- 			  AR934X_SRIF_DPLL1_REFDIV_MASK;
- 		frac = 1 << 18;
- 	} else {
--		pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
-+		pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG);
- 		out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
- 			  AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
- 		ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
-@@ -307,7 +307,7 @@ static void __init ar934x_clocks_init(vo
- 	ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
- 				      nfrac, frac, out_div);
- 
--	clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
-+	clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
- 
- 	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
- 		  AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
-@@ -347,7 +347,7 @@ static void __init ar934x_clocks_init(vo
- 	iounmap(dpll_base);
- }
- 
--static void __init qca953x_clocks_init(void)
-+static void __init qca953x_clocks_init(void __iomem *pll_base)
- {
- 	unsigned long ref_rate;
- 	unsigned long cpu_rate;
-@@ -363,7 +363,7 @@ static void __init qca953x_clocks_init(v
- 	else
- 		ref_rate = 25 * 1000 * 1000;
- 
--	pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
-+	pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
- 	out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
- 		  QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
- 	ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
-@@ -377,7 +377,7 @@ static void __init qca953x_clocks_init(v
- 	cpu_pll += frac * (ref_rate >> 6) / ref_div;
- 	cpu_pll /= (1 << out_div);
- 
--	pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
-+	pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG);
- 	out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
- 		  QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
- 	ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
-@@ -391,7 +391,7 @@ static void __init qca953x_clocks_init(v
- 	ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
- 	ddr_pll /= (1 << out_div);
- 
--	clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
-+	clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG);
- 
- 	postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
- 		  QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
-@@ -429,7 +429,7 @@ static void __init qca953x_clocks_init(v
- 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
- }
- 
--static void __init qca955x_clocks_init(void)
-+static void __init qca955x_clocks_init(void __iomem *pll_base)
- {
- 	unsigned long ref_rate;
- 	unsigned long cpu_rate;
-@@ -445,7 +445,7 @@ static void __init qca955x_clocks_init(v
- 	else
- 		ref_rate = 25 * 1000 * 1000;
- 
--	pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
-+	pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
- 	out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
- 		  QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
- 	ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
-@@ -459,7 +459,7 @@ static void __init qca955x_clocks_init(v
- 	cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
- 	cpu_pll /= (1 << out_div);
- 
--	pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
-+	pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG);
- 	out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
- 		  QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
- 	ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
-@@ -473,7 +473,7 @@ static void __init qca955x_clocks_init(v
- 	ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
- 	ddr_pll /= (1 << out_div);
- 
--	clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
-+	clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG);
- 
- 	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
- 		  QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
-@@ -511,7 +511,7 @@ static void __init qca955x_clocks_init(v
- 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
- }
- 
--static void __init qca956x_clocks_init(void)
-+static void __init qca956x_clocks_init(void __iomem *pll_base)
- {
- 	unsigned long ref_rate;
- 	unsigned long cpu_rate;
-@@ -537,13 +537,13 @@ static void __init qca956x_clocks_init(v
- 	else
- 		ref_rate = 25 * 1000 * 1000;
- 
--	pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
-+	pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
- 	out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
- 		  QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
- 	ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
- 		  QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
- 
--	pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
-+	pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG);
- 	nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
- 	       QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
- 	hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
-@@ -556,12 +556,12 @@ static void __init qca956x_clocks_init(v
- 	cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
- 	cpu_pll /= (1 << out_div);
- 
--	pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
-+	pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG);
- 	out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
- 		  QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
- 	ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
- 		  QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
--	pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
-+	pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG);
- 	nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
- 	       QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
- 	hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
-@@ -574,7 +574,7 @@ static void __init qca956x_clocks_init(v
- 	ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
- 	ddr_pll /= (1 << out_div);
- 
--	clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
-+	clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG);
- 
- 	postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
- 		  QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
-@@ -618,19 +618,19 @@ void __init ath79_clocks_init(void)
- 	const char *uart;
- 
- 	if (soc_is_ar71xx())
--		ar71xx_clocks_init();
-+		ar71xx_clocks_init(ath79_pll_base);
- 	else if (soc_is_ar724x() || soc_is_ar913x())
--		ar724x_clocks_init();
-+		ar724x_clocks_init(ath79_pll_base);
- 	else if (soc_is_ar933x())
--		ar933x_clocks_init();
-+		ar933x_clocks_init(ath79_pll_base);
- 	else if (soc_is_ar934x())
--		ar934x_clocks_init();
-+		ar934x_clocks_init(ath79_pll_base);
- 	else if (soc_is_qca953x())
--		qca953x_clocks_init();
-+		qca953x_clocks_init(ath79_pll_base);
- 	else if (soc_is_qca955x())
--		qca955x_clocks_init();
-+		qca955x_clocks_init(ath79_pll_base);
- 	else if (soc_is_qca956x() || soc_is_tp9343())
--		qca956x_clocks_init();
-+		qca956x_clocks_init(ath79_pll_base);
- 	else
- 		BUG();
- 

target/linux/ath79/patches-4.19/0024-MIPS-ath79-make-specifying-the-reference-clock-in-DT.patch

@@ -1,229 +0,0 @@
-From 5fadb2544ed0bb72ddddd846aa303bb9ed2d211c Mon Sep 17 00:00:00 2001
-From: Felix Fietkau <[email protected]>
-Date: Tue, 6 Mar 2018 13:24:07 +0100
-Subject: [PATCH 24/33] MIPS: ath79: make specifying the reference clock in DT
- optional
-
-It can be autodetected for many SoCs using the strapping options.
-If the clock is specified in DT, the autodetected value is ignored
-
-Signed-off-by: Felix Fietkau <[email protected]>
-Signed-off-by: John Crispin <[email protected]>
----
- arch/mips/ath79/clock.c | 84 +++++++++++++++++++++++--------------------------
- 1 file changed, 40 insertions(+), 44 deletions(-)
-
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -80,6 +80,18 @@ static struct clk * __init ath79_set_ff_
- 	return clk;
- }
- 
-+static unsigned long __init ath79_setup_ref_clk(unsigned long rate)
-+{
-+	struct clk *clk = clks[ATH79_CLK_REF];
-+
-+	if (clk)
-+		rate = clk_get_rate(clk);
-+	else
-+		clk = ath79_set_clk(ATH79_CLK_REF, rate);
-+
-+	return rate;
-+}
-+
- static void __init ar71xx_clocks_init(void __iomem *pll_base)
- {
- 	unsigned long ref_rate;
-@@ -90,7 +102,7 @@ static void __init ar71xx_clocks_init(vo
- 	u32 freq;
- 	u32 div;
- 
--	ref_rate = AR71XX_BASE_FREQ;
-+	ref_rate = ath79_setup_ref_clk(AR71XX_BASE_FREQ);
- 
- 	pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
- 
-@@ -106,16 +118,17 @@ static void __init ar71xx_clocks_init(vo
- 	div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
- 	ahb_rate = cpu_rate / div;
- 
--	ath79_set_clk(ATH79_CLK_REF, ref_rate);
- 	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
- 	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
- }
- 
--static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
-+static void __init ar724x_clocks_init(void __iomem *pll_base)
- {
--	u32 pll;
- 	u32 mult, div, ddr_div, ahb_div;
-+	u32 pll;
-+
-+	ath79_setup_ref_clk(AR71XX_BASE_FREQ);
- 
- 	pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
- 
-@@ -130,17 +143,9 @@ static void __init ar724x_clk_init(struc
- 	ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
- }
- 
--static void __init ar724x_clocks_init(void __iomem *pll_base)
--{
--	struct clk *ref_clk;
--
--	ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
--
--	ar724x_clk_init(ref_clk, pll_base);
--}
--
--static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
-+static void __init ar933x_clocks_init(void __iomem *pll_base)
- {
-+	unsigned long ref_rate;
- 	u32 clock_ctrl;
- 	u32 ref_div;
- 	u32 ninit_mul;
-@@ -149,6 +154,15 @@ static void __init ar9330_clk_init(struc
- 	u32 cpu_div;
- 	u32 ddr_div;
- 	u32 ahb_div;
-+	u32 t;
-+
-+	t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
-+	if (t & AR933X_BOOTSTRAP_REF_CLK_40)
-+		ref_rate = (40 * 1000 * 1000);
-+	else
-+		ref_rate = (25 * 1000 * 1000);
-+
-+	ath79_setup_ref_clk(ref_rate);
- 
- 	clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
- 	if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
-@@ -197,23 +211,6 @@ static void __init ar9330_clk_init(struc
- 			 ref_div * out_div * ahb_div);
- }
- 
--static void __init ar933x_clocks_init(void __iomem *pll_base)
--{
--	struct clk *ref_clk;
--	unsigned long ref_rate;
--	u32 t;
--
--	t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
--	if (t & AR933X_BOOTSTRAP_REF_CLK_40)
--		ref_rate = (40 * 1000 * 1000);
--	else
--		ref_rate = (25 * 1000 * 1000);
--
--	ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
--
--	ar9330_clk_init(ref_clk, ath79_pll_base);
--}
--
- static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
- 				      u32 frac, u32 out_div)
- {
-@@ -253,6 +250,8 @@ static void __init ar934x_clocks_init(vo
- 	else
- 		ref_rate = 25 * 1000 * 1000;
- 
-+	ref_rate = ath79_setup_ref_clk(ref_rate);
-+
- 	pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
- 	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
- 		out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
-@@ -339,7 +338,6 @@ static void __init ar934x_clocks_init(vo
- 	else
- 		ahb_rate = cpu_pll / (postdiv + 1);
- 
--	ath79_set_clk(ATH79_CLK_REF, ref_rate);
- 	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
- 	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-@@ -363,6 +361,8 @@ static void __init qca953x_clocks_init(v
- 	else
- 		ref_rate = 25 * 1000 * 1000;
- 
-+	ref_rate = ath79_setup_ref_clk(ref_rate);
-+
- 	pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
- 	out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
- 		  QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
-@@ -423,7 +423,6 @@ static void __init qca953x_clocks_init(v
- 	else
- 		ahb_rate = cpu_pll / (postdiv + 1);
- 
--	ath79_set_clk(ATH79_CLK_REF, ref_rate);
- 	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
- 	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-@@ -445,6 +444,8 @@ static void __init qca955x_clocks_init(v
- 	else
- 		ref_rate = 25 * 1000 * 1000;
- 
-+	ref_rate = ath79_setup_ref_clk(ref_rate);
-+
- 	pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
- 	out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
- 		  QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
-@@ -505,7 +506,6 @@ static void __init qca955x_clocks_init(v
- 	else
- 		ahb_rate = cpu_pll / (postdiv + 1);
- 
--	ath79_set_clk(ATH79_CLK_REF, ref_rate);
- 	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
- 	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-@@ -537,6 +537,8 @@ static void __init qca956x_clocks_init(v
- 	else
- 		ref_rate = 25 * 1000 * 1000;
- 
-+	ref_rate = ath79_setup_ref_clk(ref_rate);
-+
- 	pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
- 	out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
- 		  QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
-@@ -606,7 +608,6 @@ static void __init qca956x_clocks_init(v
- 	else
- 		ahb_rate = cpu_pll / (postdiv + 1);
- 
--	ath79_set_clk(ATH79_CLK_REF, ref_rate);
- 	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
- 	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-@@ -682,10 +683,8 @@ static void __init ath79_clocks_init_dt_
- 	void __iomem *pll_base;
- 
- 	ref_clk = of_clk_get(np, 0);
--	if (IS_ERR(ref_clk)) {
--		pr_err("%pOF: of_clk_get failed\n", np);
--		goto err;
--	}
-+	if (!IS_ERR(ref_clk))
-+		clks[ATH79_CLK_REF] = ref_clk;
- 
- 	pll_base = of_iomap(np, 0);
- 	if (!pll_base) {
-@@ -694,9 +693,9 @@ static void __init ath79_clocks_init_dt_
- 	}
- 
- 	if (of_device_is_compatible(np, "qca,ar9130-pll"))
--		ar724x_clk_init(ref_clk, pll_base);
-+		ar724x_clocks_init(pll_base);
- 	else if (of_device_is_compatible(np, "qca,ar9330-pll"))
--		ar9330_clk_init(ref_clk, pll_base);
-+		ar933x_clocks_init(pll_base);
- 	else {
- 		pr_err("%pOF: could not find any appropriate clk_init()\n", np);
- 		goto err_iounmap;
-@@ -714,9 +713,6 @@ err_iounmap:
- 
- err_clk:
- 	clk_put(ref_clk);
--
--err:
--	return;
- }
- CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
- CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);

target/linux/ath79/patches-4.19/0025-MIPS-ath79-support-setting-up-clock-via-DT-on-all-So.patch

@@ -1,77 +0,0 @@
-From 6325626de001df98aebe51f3008b1aca05798d19 Mon Sep 17 00:00:00 2001
-From: Felix Fietkau <[email protected]>
-Date: Tue, 6 Mar 2018 13:26:27 +0100
-Subject: [PATCH 25/33] MIPS: ath79: support setting up clock via DT on all SoC
- types
-
-Use the same functions as the legacy code
-
-Signed-off-by: Felix Fietkau <[email protected]>
-Signed-off-by: John Crispin <[email protected]>
----
- arch/mips/ath79/clock.c | 39 ++++++++++++++++++++++-----------------
- 1 file changed, 22 insertions(+), 17 deletions(-)
-
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -669,16 +669,6 @@ ath79_get_sys_clk_rate(const char *id)
- #ifdef CONFIG_OF
- static void __init ath79_clocks_init_dt(struct device_node *np)
- {
--	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
--}
--
--CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
--CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
--CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
--CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
--
--static void __init ath79_clocks_init_dt_ng(struct device_node *np)
--{
- 	struct clk *ref_clk;
- 	void __iomem *pll_base;
- 
-@@ -692,14 +682,21 @@ static void __init ath79_clocks_init_dt_
- 		goto err_clk;
- 	}
- 
--	if (of_device_is_compatible(np, "qca,ar9130-pll"))
-+	if (of_device_is_compatible(np, "qca,ar7100-pll"))
-+		ar71xx_clocks_init(pll_base);
-+	else if (of_device_is_compatible(np, "qca,ar7240-pll") ||
-+		 of_device_is_compatible(np, "qca,ar9130-pll"))
- 		ar724x_clocks_init(pll_base);
- 	else if (of_device_is_compatible(np, "qca,ar9330-pll"))
- 		ar933x_clocks_init(pll_base);
--	else {
--		pr_err("%pOF: could not find any appropriate clk_init()\n", np);
--		goto err_iounmap;
--	}
-+	else if (of_device_is_compatible(np, "qca,ar9340-pll"))
-+		ar934x_clocks_init(pll_base);
-+	else if (of_device_is_compatible(np, "qca,qca9530-pll"))
-+		qca953x_clocks_init(pll_base);
-+	else if (of_device_is_compatible(np, "qca,qca9550-pll"))
-+		qca955x_clocks_init(pll_base);
-+	else if (of_device_is_compatible(np, "qca,qca9560-pll"))
-+		qca956x_clocks_init(pll_base);
- 
- 	if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
- 		pr_err("%pOF: could not register clk provider\n", np);
-@@ -714,6 +711,14 @@ err_iounmap:
- err_clk:
- 	clk_put(ref_clk);
- }
--CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
--CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);
-+
-+CLK_OF_DECLARE(ar7100_clk, "qca,ar7100-pll", ath79_clocks_init_dt);
-+CLK_OF_DECLARE(ar7240_clk, "qca,ar7240-pll", ath79_clocks_init_dt);
-+CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt);
-+CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt);
-+CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-pll", ath79_clocks_init_dt);
-+CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt);
-+CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt);
-+CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt);
-+
- #endif

target/linux/ath79/patches-4.19/0026-MIPS-ath79-export-switch-MDIO-reference-clock.patch

@@ -1,59 +0,0 @@
-From 78538d673801902108797f2c813e70cfbce280c9 Mon Sep 17 00:00:00 2001
-From: Felix Fietkau <[email protected]>
-Date: Tue, 6 Mar 2018 13:27:28 +0100
-Subject: [PATCH 26/33] MIPS: ath79: export switch MDIO reference clock
-
-On AR934x, the MDIO reference clock can be configured to a fixed 100 MHz
-clock. If that feature is not used, it defaults to the main reference
-clock, like on all other SoC.
-
-Signed-off-by: Felix Fietkau <[email protected]>
-Signed-off-by: John Crispin <[email protected]>
----
- arch/mips/ath79/clock.c               | 8 ++++++++
- include/dt-bindings/clock/ath79-clk.h | 3 ++-
- 2 files changed, 10 insertions(+), 1 deletion(-)
-
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -42,6 +42,7 @@ static const char * const clk_names[ATH7
- 	[ATH79_CLK_DDR] = "ddr",
- 	[ATH79_CLK_AHB] = "ahb",
- 	[ATH79_CLK_REF] = "ref",
-+	[ATH79_CLK_MDIO] = "mdio",
- };
- 
- static const char * __init ath79_clk_name(int type)
-@@ -342,6 +343,10 @@ static void __init ar934x_clocks_init(vo
- 	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
- 
-+	clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
-+	if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
-+		ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
-+
- 	iounmap(dpll_base);
- }
- 
-@@ -698,6 +703,9 @@ static void __init ath79_clocks_init_dt(
- 	else if (of_device_is_compatible(np, "qca,qca9560-pll"))
- 		qca956x_clocks_init(pll_base);
- 
-+	if (!clks[ATH79_CLK_MDIO])
-+		clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
-+
- 	if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
- 		pr_err("%pOF: could not register clk provider\n", np);
- 		goto err_iounmap;
---- a/include/dt-bindings/clock/ath79-clk.h
-+++ b/include/dt-bindings/clock/ath79-clk.h
-@@ -14,7 +14,8 @@
- #define ATH79_CLK_DDR		1
- #define ATH79_CLK_AHB		2
- #define ATH79_CLK_REF		3
-+#define ATH79_CLK_MDIO		4
- 
--#define ATH79_CLK_END		4
-+#define ATH79_CLK_END		5
- 
- #endif /* __DT_BINDINGS_ATH79_CLK_H */

target/linux/ath79/patches-4.19/0027-MIPS-ath79-drop-legacy-IRQ-code.patch

@@ -1,233 +0,0 @@
-From 3765b1f79593a0a9098ed15e48074c95403a53ee Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Sat, 23 Jun 2018 15:05:08 +0200
-Subject: [PATCH 27/33] MIPS: ath79: drop legacy IRQ code
-
-With the target now being fully OF based, we can drop the legacy IRQ code.
-All IRQs are now handled via the new irqchip drivers.
-
-Signed-off-by: John Crispin <[email protected]>
----
- arch/mips/ath79/Makefile                 |   2 +-
- arch/mips/ath79/irq.c                    | 169 -------------------------------
- arch/mips/ath79/setup.c                  |   6 ++
- arch/mips/include/asm/mach-ath79/ath79.h |   4 -
- 4 files changed, 7 insertions(+), 174 deletions(-)
- delete mode 100644 arch/mips/ath79/irq.c
-
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -8,7 +8,7 @@
- # under the terms of the GNU General Public License version 2 as published
- # by the Free Software Foundation.
- 
--obj-y	:= prom.o setup.o irq.o common.o clock.o
-+obj-y	:= prom.o setup.o common.o clock.o
- 
- obj-$(CONFIG_EARLY_PRINTK)		+= early_printk.o
- obj-$(CONFIG_PCI)			+= pci.o
---- a/arch/mips/ath79/irq.c
-+++ /dev/null
-@@ -1,169 +0,0 @@
--/*
-- *  Atheros AR71xx/AR724x/AR913x specific interrupt handling
-- *
-- *  Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]>
-- *  Copyright (C) 2008-2011 Gabor Juhos <[email protected]>
-- *  Copyright (C) 2008 Imre Kaloz <[email protected]>
-- *
-- *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
-- *
-- *  This program is free software; you can redistribute it and/or modify it
-- *  under the terms of the GNU General Public License version 2 as published
-- *  by the Free Software Foundation.
-- */
--
--#include <linux/kernel.h>
--#include <linux/init.h>
--#include <linux/interrupt.h>
--#include <linux/irqchip.h>
--#include <linux/of_irq.h>
--
--#include <asm/irq_cpu.h>
--#include <asm/mipsregs.h>
--
--#include <asm/mach-ath79/ath79.h>
--#include <asm/mach-ath79/ar71xx_regs.h>
--#include "common.h"
--#include "machtypes.h"
--
--
--static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
--{
--	u32 status;
--
--	status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
--
--	if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
--		ath79_ddr_wb_flush(3);
--		generic_handle_irq(ATH79_IP2_IRQ(0));
--	} else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
--		ath79_ddr_wb_flush(4);
--		generic_handle_irq(ATH79_IP2_IRQ(1));
--	} else {
--		spurious_interrupt();
--	}
--}
--
--static void ar934x_ip2_irq_init(void)
--{
--	int i;
--
--	for (i = ATH79_IP2_IRQ_BASE;
--	     i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
--		irq_set_chip_and_handler(i, &dummy_irq_chip,
--					 handle_level_irq);
--
--	irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
--}
--
--static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
--{
--	u32 status;
--
--	status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
--	status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
--
--	if (status == 0) {
--		spurious_interrupt();
--		return;
--	}
--
--	if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
--		/* TODO: flush DDR? */
--		generic_handle_irq(ATH79_IP2_IRQ(0));
--	}
--
--	if (status & QCA955X_EXT_INT_WMAC_ALL) {
--		/* TODO: flush DDR? */
--		generic_handle_irq(ATH79_IP2_IRQ(1));
--	}
--}
--
--static void qca955x_ip3_irq_dispatch(struct irq_desc *desc)
--{
--	u32 status;
--
--	status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
--	status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
--		  QCA955X_EXT_INT_USB1 |
--		  QCA955X_EXT_INT_USB2;
--
--	if (status == 0) {
--		spurious_interrupt();
--		return;
--	}
--
--	if (status & QCA955X_EXT_INT_USB1) {
--		/* TODO: flush DDR? */
--		generic_handle_irq(ATH79_IP3_IRQ(0));
--	}
--
--	if (status & QCA955X_EXT_INT_USB2) {
--		/* TODO: flush DDR? */
--		generic_handle_irq(ATH79_IP3_IRQ(1));
--	}
--
--	if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
--		/* TODO: flush DDR? */
--		generic_handle_irq(ATH79_IP3_IRQ(2));
--	}
--}
--
--static void qca955x_irq_init(void)
--{
--	int i;
--
--	for (i = ATH79_IP2_IRQ_BASE;
--	     i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
--		irq_set_chip_and_handler(i, &dummy_irq_chip,
--					 handle_level_irq);
--
--	irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
--
--	for (i = ATH79_IP3_IRQ_BASE;
--	     i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
--		irq_set_chip_and_handler(i, &dummy_irq_chip,
--					 handle_level_irq);
--
--	irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
--}
--
--void __init arch_init_irq(void)
--{
--	unsigned irq_wb_chan2 = -1;
--	unsigned irq_wb_chan3 = -1;
--	bool misc_is_ar71xx;
--
--	if (mips_machtype == ATH79_MACH_GENERIC_OF) {
--		irqchip_init();
--		return;
--	}
--
--	if (soc_is_ar71xx() || soc_is_ar724x() ||
--	    soc_is_ar913x() || soc_is_ar933x()) {
--		irq_wb_chan2 = 3;
--		irq_wb_chan3 = 2;
--	} else if (soc_is_ar934x()) {
--		irq_wb_chan3 = 2;
--	}
--
--	ath79_cpu_irq_init(irq_wb_chan2, irq_wb_chan3);
--
--	if (soc_is_ar71xx() || soc_is_ar913x())
--		misc_is_ar71xx = true;
--	else if (soc_is_ar724x() ||
--		 soc_is_ar933x() ||
--		 soc_is_ar934x() ||
--		 soc_is_qca955x())
--		misc_is_ar71xx = false;
--	else
--		BUG();
--	ath79_misc_irq_init(
--		ath79_reset_base + AR71XX_RESET_REG_MISC_INT_STATUS,
--		ATH79_CPU_IRQ(6), ATH79_MISC_IRQ_BASE, misc_is_ar71xx);
--
--	if (soc_is_ar934x())
--		ar934x_ip2_irq_init();
--	else if (soc_is_qca955x())
--		qca955x_irq_init();
--}
---- a/arch/mips/ath79/setup.c
-+++ b/arch/mips/ath79/setup.c
-@@ -19,6 +19,7 @@
- #include <linux/clk.h>
- #include <linux/clk-provider.h>
- #include <linux/of_fdt.h>
-+#include <linux/irqchip.h>
- 
- #include <asm/bootinfo.h>
- #include <asm/idle.h>
-@@ -305,6 +306,11 @@ void __init plat_time_init(void)
- 	mips_hpt_frequency = cpu_clk_rate / 2;
- }
- 
-+void __init arch_init_irq(void)
-+{
-+	irqchip_init();
-+}
-+
- static int __init ath79_setup(void)
- {
- 	if  (mips_machtype == ATH79_MACH_GENERIC_OF)
---- a/arch/mips/include/asm/mach-ath79/ath79.h
-+++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -178,8 +178,4 @@ static inline u32 ath79_reset_rr(unsigne
- void ath79_device_reset_set(u32 mask);
- void ath79_device_reset_clear(u32 mask);
- 
--void ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3);
--void ath79_misc_irq_init(void __iomem *regs, int irq,
--			int irq_base, bool is_ar71xx);
--
- #endif /* __ASM_MACH_ATH79_H */

target/linux/ath79/patches-4.19/0028-MIPS-ath79-drop-machfiles.patch

@@ -1,1048 +0,0 @@
-From badf28957b6dc400dff27bd23ba2ae75d9514be5 Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Sat, 23 Jun 2018 15:04:09 +0200
-Subject: [PATCH 28/33] MIPS: ath79: drop machfiles
-
-With the target now being fully OF based, we can drop the legacy mach
-files. Boards can now boot fully of devicetree files.
-
-Signed-off-by: John Crispin <[email protected]>
----
- arch/mips/Kconfig              |   1 -
- arch/mips/ath79/Kconfig        |  73 -------------------
- arch/mips/ath79/Makefile       |  10 ---
- arch/mips/ath79/clock.c        |   1 -
- arch/mips/ath79/mach-ap121.c   |  92 ------------------------
- arch/mips/ath79/mach-ap136.c   | 156 -----------------------------------------
- arch/mips/ath79/mach-ap81.c    | 100 --------------------------
- arch/mips/ath79/mach-db120.c   | 136 -----------------------------------
- arch/mips/ath79/mach-pb44.c    | 128 ---------------------------------
- arch/mips/ath79/mach-ubnt-xm.c | 126 ---------------------------------
- arch/mips/ath79/machtypes.h    |  28 --------
- arch/mips/ath79/setup.c        |  77 +++-----------------
- 12 files changed, 9 insertions(+), 919 deletions(-)
- delete mode 100644 arch/mips/ath79/mach-ap121.c
- delete mode 100644 arch/mips/ath79/mach-ap136.c
- delete mode 100644 arch/mips/ath79/mach-ap81.c
- delete mode 100644 arch/mips/ath79/mach-db120.c
- delete mode 100644 arch/mips/ath79/mach-pb44.c
- delete mode 100644 arch/mips/ath79/mach-ubnt-xm.c
- delete mode 100644 arch/mips/ath79/machtypes.h
-
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -202,7 +202,6 @@ config ATH79
- 	select COMMON_CLK
- 	select CLKDEV_LOOKUP
- 	select IRQ_MIPS_CPU
--	select MIPS_MACHINE
- 	select SYS_HAS_CPU_MIPS32_R2
- 	select SYS_HAS_EARLY_PRINTK
- 	select SYS_SUPPORTS_32BIT_KERNEL
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -1,79 +1,6 @@
- # SPDX-License-Identifier: GPL-2.0
- if ATH79
- 
--menu "Atheros AR71XX/AR724X/AR913X machine selection"
--
--config ATH79_MACH_AP121
--	bool "Atheros AP121 reference board"
--	select SOC_AR933X
--	select ATH79_DEV_GPIO_BUTTONS
--	select ATH79_DEV_LEDS_GPIO
--	select ATH79_DEV_SPI
--	select ATH79_DEV_USB
--	select ATH79_DEV_WMAC
--	help
--	  Say 'Y' here if you want your kernel to support the
--	  Atheros AP121 reference board.
--
--config ATH79_MACH_AP136
--	bool "Atheros AP136 reference board"
--	select SOC_QCA955X
--	select ATH79_DEV_GPIO_BUTTONS
--	select ATH79_DEV_LEDS_GPIO
--	select ATH79_DEV_SPI
--	select ATH79_DEV_USB
--	select ATH79_DEV_WMAC
--	help
--	  Say 'Y' here if you want your kernel to support the
--	  Atheros AP136 reference board.
--
--config ATH79_MACH_AP81
--	bool "Atheros AP81 reference board"
--	select SOC_AR913X
--	select ATH79_DEV_GPIO_BUTTONS
--	select ATH79_DEV_LEDS_GPIO
--	select ATH79_DEV_SPI
--	select ATH79_DEV_USB
--	select ATH79_DEV_WMAC
--	help
--	  Say 'Y' here if you want your kernel to support the
--	  Atheros AP81 reference board.
--
--config ATH79_MACH_DB120
--	bool "Atheros DB120 reference board"
--	select SOC_AR934X
--	select ATH79_DEV_GPIO_BUTTONS
--	select ATH79_DEV_LEDS_GPIO
--	select ATH79_DEV_SPI
--	select ATH79_DEV_USB
--	select ATH79_DEV_WMAC
--	help
--	  Say 'Y' here if you want your kernel to support the
--	  Atheros DB120 reference board.
--
--config ATH79_MACH_PB44
--	bool "Atheros PB44 reference board"
--	select SOC_AR71XX
--	select ATH79_DEV_GPIO_BUTTONS
--	select ATH79_DEV_LEDS_GPIO
--	select ATH79_DEV_SPI
--	select ATH79_DEV_USB
--	help
--	  Say 'Y' here if you want your kernel to support the
--	  Atheros PB44 reference board.
--
--config ATH79_MACH_UBNT_XM
--	bool "Ubiquiti Networks XM (rev 1.0) board"
--	select SOC_AR724X
--	select ATH79_DEV_GPIO_BUTTONS
--	select ATH79_DEV_LEDS_GPIO
--	select ATH79_DEV_SPI
--	help
--	  Say 'Y' here if you want your kernel to support the
--	  Ubiquiti Networks XM (rev 1.0) board.
--
--endmenu
--
- config SOC_AR71XX
- 	select HW_HAS_PCI
- 	def_bool n
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -22,13 +22,3 @@ obj-$(CONFIG_ATH79_DEV_LEDS_GPIO)	+= dev
- obj-$(CONFIG_ATH79_DEV_SPI)		+= dev-spi.o
- obj-$(CONFIG_ATH79_DEV_USB)		+= dev-usb.o
- obj-$(CONFIG_ATH79_DEV_WMAC)		+= dev-wmac.o
--
--#
--# Machines
--#
--obj-$(CONFIG_ATH79_MACH_AP121)		+= mach-ap121.o
--obj-$(CONFIG_ATH79_MACH_AP136)		+= mach-ap136.o
--obj-$(CONFIG_ATH79_MACH_AP81)		+= mach-ap81.o
--obj-$(CONFIG_ATH79_MACH_DB120)		+= mach-db120.o
--obj-$(CONFIG_ATH79_MACH_PB44)		+= mach-pb44.o
--obj-$(CONFIG_ATH79_MACH_UBNT_XM)	+= mach-ubnt-xm.o
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -26,7 +26,6 @@
- #include <asm/mach-ath79/ath79.h>
- #include <asm/mach-ath79/ar71xx_regs.h>
- #include "common.h"
--#include "machtypes.h"
- 
- #define AR71XX_BASE_FREQ	40000000
- #define AR724X_BASE_FREQ	40000000
---- a/arch/mips/ath79/mach-ap121.c
-+++ /dev/null
-@@ -1,92 +0,0 @@
--/*
-- *  Atheros AP121 board support
-- *
-- *  Copyright (C) 2011 Gabor Juhos <[email protected]>
-- *
-- *  This program is free software; you can redistribute it and/or modify it
-- *  under the terms of the GNU General Public License version 2 as published
-- *  by the Free Software Foundation.
-- */
--
--#include "machtypes.h"
--#include "dev-gpio-buttons.h"
--#include "dev-leds-gpio.h"
--#include "dev-spi.h"
--#include "dev-usb.h"
--#include "dev-wmac.h"
--
--#define AP121_GPIO_LED_WLAN		0
--#define AP121_GPIO_LED_USB		1
--
--#define AP121_GPIO_BTN_JUMPSTART	11
--#define AP121_GPIO_BTN_RESET		12
--
--#define AP121_KEYS_POLL_INTERVAL	20	/* msecs */
--#define AP121_KEYS_DEBOUNCE_INTERVAL	(3 * AP121_KEYS_POLL_INTERVAL)
--
--#define AP121_CAL_DATA_ADDR	0x1fff1000
--
--static struct gpio_led ap121_leds_gpio[] __initdata = {
--	{
--		.name		= "ap121:green:usb",
--		.gpio		= AP121_GPIO_LED_USB,
--		.active_low	= 0,
--	},
--	{
--		.name		= "ap121:green:wlan",
--		.gpio		= AP121_GPIO_LED_WLAN,
--		.active_low	= 0,
--	},
--};
--
--static struct gpio_keys_button ap121_gpio_keys[] __initdata = {
--	{
--		.desc		= "jumpstart button",
--		.type		= EV_KEY,
--		.code		= KEY_WPS_BUTTON,
--		.debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
--		.gpio		= AP121_GPIO_BTN_JUMPSTART,
--		.active_low	= 1,
--	},
--	{
--		.desc		= "reset button",
--		.type		= EV_KEY,
--		.code		= KEY_RESTART,
--		.debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
--		.gpio		= AP121_GPIO_BTN_RESET,
--		.active_low	= 1,
--	}
--};
--
--static struct spi_board_info ap121_spi_info[] = {
--	{
--		.bus_num	= 0,
--		.chip_select	= 0,
--		.max_speed_hz	= 25000000,
--		.modalias	= "mx25l1606e",
--	}
--};
--
--static struct ath79_spi_platform_data ap121_spi_data = {
--	.bus_num	= 0,
--	.num_chipselect = 1,
--};
--
--static void __init ap121_setup(void)
--{
--	u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR);
--
--	ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio),
--				 ap121_leds_gpio);
--	ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
--					ARRAY_SIZE(ap121_gpio_keys),
--					ap121_gpio_keys);
--
--	ath79_register_spi(&ap121_spi_data, ap121_spi_info,
--			   ARRAY_SIZE(ap121_spi_info));
--	ath79_register_usb();
--	ath79_register_wmac(cal_data);
--}
--
--MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
--	     ap121_setup);
---- a/arch/mips/ath79/mach-ap136.c
-+++ /dev/null
-@@ -1,156 +0,0 @@
--/*
-- * Qualcomm Atheros AP136 reference board support
-- *
-- * Copyright (c) 2012 Qualcomm Atheros
-- * Copyright (c) 2012-2013 Gabor Juhos <[email protected]>
-- *
-- * Permission to use, copy, modify, and/or distribute this software for any
-- * purpose with or without fee is hereby granted, provided that the above
-- * copyright notice and this permission notice appear in all copies.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-- *
-- */
--
--#include <linux/pci.h>
--#include <linux/ath9k_platform.h>
--
--#include "machtypes.h"
--#include "dev-gpio-buttons.h"
--#include "dev-leds-gpio.h"
--#include "dev-spi.h"
--#include "dev-usb.h"
--#include "dev-wmac.h"
--#include "pci.h"
--
--#define AP136_GPIO_LED_STATUS_RED	14
--#define AP136_GPIO_LED_STATUS_GREEN	19
--#define AP136_GPIO_LED_USB		4
--#define AP136_GPIO_LED_WLAN_2G		13
--#define AP136_GPIO_LED_WLAN_5G		12
--#define AP136_GPIO_LED_WPS_RED		15
--#define AP136_GPIO_LED_WPS_GREEN	20
--
--#define AP136_GPIO_BTN_WPS		16
--#define AP136_GPIO_BTN_RFKILL		21
--
--#define AP136_KEYS_POLL_INTERVAL	20	/* msecs */
--#define AP136_KEYS_DEBOUNCE_INTERVAL	(3 * AP136_KEYS_POLL_INTERVAL)
--
--#define AP136_WMAC_CALDATA_OFFSET 0x1000
--#define AP136_PCIE_CALDATA_OFFSET 0x5000
--
--static struct gpio_led ap136_leds_gpio[] __initdata = {
--	{
--		.name		= "qca:green:status",
--		.gpio		= AP136_GPIO_LED_STATUS_GREEN,
--		.active_low	= 1,
--	},
--	{
--		.name		= "qca:red:status",
--		.gpio		= AP136_GPIO_LED_STATUS_RED,
--		.active_low	= 1,
--	},
--	{
--		.name		= "qca:green:wps",
--		.gpio		= AP136_GPIO_LED_WPS_GREEN,
--		.active_low	= 1,
--	},
--	{
--		.name		= "qca:red:wps",
--		.gpio		= AP136_GPIO_LED_WPS_RED,
--		.active_low	= 1,
--	},
--	{
--		.name		= "qca:red:wlan-2g",
--		.gpio		= AP136_GPIO_LED_WLAN_2G,
--		.active_low	= 1,
--	},
--	{
--		.name		= "qca:red:usb",
--		.gpio		= AP136_GPIO_LED_USB,
--		.active_low	= 1,
--	}
--};
--
--static struct gpio_keys_button ap136_gpio_keys[] __initdata = {
--	{
--		.desc		= "WPS button",
--		.type		= EV_KEY,
--		.code		= KEY_WPS_BUTTON,
--		.debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL,
--		.gpio		= AP136_GPIO_BTN_WPS,
--		.active_low	= 1,
--	},
--	{
--		.desc		= "RFKILL button",
--		.type		= EV_KEY,
--		.code		= KEY_RFKILL,
--		.debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL,
--		.gpio		= AP136_GPIO_BTN_RFKILL,
--		.active_low	= 1,
--	},
--};
--
--static struct spi_board_info ap136_spi_info[] = {
--	{
--		.bus_num	= 0,
--		.chip_select	= 0,
--		.max_speed_hz	= 25000000,
--		.modalias	= "mx25l6405d",
--	}
--};
--
--static struct ath79_spi_platform_data ap136_spi_data = {
--	.bus_num	= 0,
--	.num_chipselect	= 1,
--};
--
--#ifdef CONFIG_PCI
--static struct ath9k_platform_data ap136_ath9k_data;
--
--static int ap136_pci_plat_dev_init(struct pci_dev *dev)
--{
--	if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
--		dev->dev.platform_data = &ap136_ath9k_data;
--
--	return 0;
--}
--
--static void __init ap136_pci_init(u8 *eeprom)
--{
--	memcpy(ap136_ath9k_data.eeprom_data, eeprom,
--	       sizeof(ap136_ath9k_data.eeprom_data));
--
--	ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
--	ath79_register_pci();
--}
--#else
--static inline void ap136_pci_init(u8 *eeprom) {}
--#endif /* CONFIG_PCI */
--
--static void __init ap136_setup(void)
--{
--	u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
--
--	ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
--				 ap136_leds_gpio);
--	ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
--					ARRAY_SIZE(ap136_gpio_keys),
--					ap136_gpio_keys);
--	ath79_register_spi(&ap136_spi_data, ap136_spi_info,
--			   ARRAY_SIZE(ap136_spi_info));
--	ath79_register_usb();
--	ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
--	ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
--}
--
--MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
--	     "Atheros AP136-010 reference board",
--	     ap136_setup);
---- a/arch/mips/ath79/mach-ap81.c
-+++ /dev/null
-@@ -1,100 +0,0 @@
--/*
-- *  Atheros AP81 board support
-- *
-- *  Copyright (C) 2009-2010 Gabor Juhos <[email protected]>
-- *  Copyright (C) 2009 Imre Kaloz <[email protected]>
-- *
-- *  This program is free software; you can redistribute it and/or modify it
-- *  under the terms of the GNU General Public License version 2 as published
-- *  by the Free Software Foundation.
-- */
--
--#include "machtypes.h"
--#include "dev-wmac.h"
--#include "dev-gpio-buttons.h"
--#include "dev-leds-gpio.h"
--#include "dev-spi.h"
--#include "dev-usb.h"
--
--#define AP81_GPIO_LED_STATUS	1
--#define AP81_GPIO_LED_AOSS	3
--#define AP81_GPIO_LED_WLAN	6
--#define AP81_GPIO_LED_POWER	14
--
--#define AP81_GPIO_BTN_SW4	12
--#define AP81_GPIO_BTN_SW1	21
--
--#define AP81_KEYS_POLL_INTERVAL		20	/* msecs */
--#define AP81_KEYS_DEBOUNCE_INTERVAL	(3 * AP81_KEYS_POLL_INTERVAL)
--
--#define AP81_CAL_DATA_ADDR	0x1fff1000
--
--static struct gpio_led ap81_leds_gpio[] __initdata = {
--	{
--		.name		= "ap81:green:status",
--		.gpio		= AP81_GPIO_LED_STATUS,
--		.active_low	= 1,
--	}, {
--		.name		= "ap81:amber:aoss",
--		.gpio		= AP81_GPIO_LED_AOSS,
--		.active_low	= 1,
--	}, {
--		.name		= "ap81:green:wlan",
--		.gpio		= AP81_GPIO_LED_WLAN,
--		.active_low	= 1,
--	}, {
--		.name		= "ap81:green:power",
--		.gpio		= AP81_GPIO_LED_POWER,
--		.active_low	= 1,
--	}
--};
--
--static struct gpio_keys_button ap81_gpio_keys[] __initdata = {
--	{
--		.desc		= "sw1",
--		.type		= EV_KEY,
--		.code		= BTN_0,
--		.debounce_interval = AP81_KEYS_DEBOUNCE_INTERVAL,
--		.gpio		= AP81_GPIO_BTN_SW1,
--		.active_low	= 1,
--	} , {
--		.desc		= "sw4",
--		.type		= EV_KEY,
--		.code		= BTN_1,
--		.debounce_interval = AP81_KEYS_DEBOUNCE_INTERVAL,
--		.gpio		= AP81_GPIO_BTN_SW4,
--		.active_low	= 1,
--	}
--};
--
--static struct spi_board_info ap81_spi_info[] = {
--	{
--		.bus_num	= 0,
--		.chip_select	= 0,
--		.max_speed_hz	= 25000000,
--		.modalias	= "m25p64",
--	}
--};
--
--static struct ath79_spi_platform_data ap81_spi_data = {
--	.bus_num	= 0,
--	.num_chipselect = 1,
--};
--
--static void __init ap81_setup(void)
--{
--	u8 *cal_data = (u8 *) KSEG1ADDR(AP81_CAL_DATA_ADDR);
--
--	ath79_register_leds_gpio(-1, ARRAY_SIZE(ap81_leds_gpio),
--				 ap81_leds_gpio);
--	ath79_register_gpio_keys_polled(-1, AP81_KEYS_POLL_INTERVAL,
--					ARRAY_SIZE(ap81_gpio_keys),
--					ap81_gpio_keys);
--	ath79_register_spi(&ap81_spi_data, ap81_spi_info,
--			   ARRAY_SIZE(ap81_spi_info));
--	ath79_register_wmac(cal_data);
--	ath79_register_usb();
--}
--
--MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board",
--	     ap81_setup);
---- a/arch/mips/ath79/mach-db120.c
-+++ /dev/null
-@@ -1,136 +0,0 @@
--/*
-- * Atheros DB120 reference board support
-- *
-- * Copyright (c) 2011 Qualcomm Atheros
-- * Copyright (c) 2011 Gabor Juhos <[email protected]>
-- *
-- * Permission to use, copy, modify, and/or distribute this software for any
-- * purpose with or without fee is hereby granted, provided that the above
-- * copyright notice and this permission notice appear in all copies.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-- *
-- */
--
--#include <linux/pci.h>
--#include <linux/ath9k_platform.h>
--
--#include "machtypes.h"
--#include "dev-gpio-buttons.h"
--#include "dev-leds-gpio.h"
--#include "dev-spi.h"
--#include "dev-usb.h"
--#include "dev-wmac.h"
--#include "pci.h"
--
--#define DB120_GPIO_LED_WLAN_5G		12
--#define DB120_GPIO_LED_WLAN_2G		13
--#define DB120_GPIO_LED_STATUS		14
--#define DB120_GPIO_LED_WPS		15
--
--#define DB120_GPIO_BTN_WPS		16
--
--#define DB120_KEYS_POLL_INTERVAL	20	/* msecs */
--#define DB120_KEYS_DEBOUNCE_INTERVAL	(3 * DB120_KEYS_POLL_INTERVAL)
--
--#define DB120_WMAC_CALDATA_OFFSET 0x1000
--#define DB120_PCIE_CALDATA_OFFSET 0x5000
--
--static struct gpio_led db120_leds_gpio[] __initdata = {
--	{
--		.name		= "db120:green:status",
--		.gpio		= DB120_GPIO_LED_STATUS,
--		.active_low	= 1,
--	},
--	{
--		.name		= "db120:green:wps",
--		.gpio		= DB120_GPIO_LED_WPS,
--		.active_low	= 1,
--	},
--	{
--		.name		= "db120:green:wlan-5g",
--		.gpio		= DB120_GPIO_LED_WLAN_5G,
--		.active_low	= 1,
--	},
--	{
--		.name		= "db120:green:wlan-2g",
--		.gpio		= DB120_GPIO_LED_WLAN_2G,
--		.active_low	= 1,
--	},
--};
--
--static struct gpio_keys_button db120_gpio_keys[] __initdata = {
--	{
--		.desc		= "WPS button",
--		.type		= EV_KEY,
--		.code		= KEY_WPS_BUTTON,
--		.debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL,
--		.gpio		= DB120_GPIO_BTN_WPS,
--		.active_low	= 1,
--	},
--};
--
--static struct spi_board_info db120_spi_info[] = {
--	{
--		.bus_num	= 0,
--		.chip_select	= 0,
--		.max_speed_hz	= 25000000,
--		.modalias	= "s25sl064a",
--	}
--};
--
--static struct ath79_spi_platform_data db120_spi_data = {
--	.bus_num	= 0,
--	.num_chipselect = 1,
--};
--
--#ifdef CONFIG_PCI
--static struct ath9k_platform_data db120_ath9k_data;
--
--static int db120_pci_plat_dev_init(struct pci_dev *dev)
--{
--	switch (PCI_SLOT(dev->devfn)) {
--	case 0:
--		dev->dev.platform_data = &db120_ath9k_data;
--		break;
--	}
--
--	return 0;
--}
--
--static void __init db120_pci_init(u8 *eeprom)
--{
--	memcpy(db120_ath9k_data.eeprom_data, eeprom,
--	       sizeof(db120_ath9k_data.eeprom_data));
--
--	ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
--	ath79_register_pci();
--}
--#else
--static inline void db120_pci_init(u8 *eeprom) {}
--#endif /* CONFIG_PCI */
--
--static void __init db120_setup(void)
--{
--	u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
--
--	ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
--				 db120_leds_gpio);
--	ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
--					ARRAY_SIZE(db120_gpio_keys),
--					db120_gpio_keys);
--	ath79_register_spi(&db120_spi_data, db120_spi_info,
--			   ARRAY_SIZE(db120_spi_info));
--	ath79_register_usb();
--	ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET);
--	db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
--}
--
--MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
--	     db120_setup);
---- a/arch/mips/ath79/mach-pb44.c
-+++ /dev/null
-@@ -1,128 +0,0 @@
--/*
-- *  Atheros PB44 reference board support
-- *
-- *  Copyright (C) 2009-2010 Gabor Juhos <[email protected]>
-- *
-- *  This program is free software; you can redistribute it and/or modify it
-- *  under the terms of the GNU General Public License version 2 as published
-- *  by the Free Software Foundation.
-- */
--
--#include <linux/init.h>
--#include <linux/platform_device.h>
--#include <linux/i2c.h>
--#include <linux/gpio/machine.h>
--#include <linux/platform_data/pcf857x.h>
--
--#include "machtypes.h"
--#include "dev-gpio-buttons.h"
--#include "dev-leds-gpio.h"
--#include "dev-spi.h"
--#include "dev-usb.h"
--#include "pci.h"
--
--#define PB44_GPIO_I2C_SCL	0
--#define PB44_GPIO_I2C_SDA	1
--
--#define PB44_GPIO_EXP_BASE	16
--#define PB44_GPIO_SW_RESET	(PB44_GPIO_EXP_BASE + 6)
--#define PB44_GPIO_SW_JUMP	(PB44_GPIO_EXP_BASE + 8)
--#define PB44_GPIO_LED_JUMP1	(PB44_GPIO_EXP_BASE + 9)
--#define PB44_GPIO_LED_JUMP2	(PB44_GPIO_EXP_BASE + 10)
--
--#define PB44_KEYS_POLL_INTERVAL		20	/* msecs */
--#define PB44_KEYS_DEBOUNCE_INTERVAL	(3 * PB44_KEYS_POLL_INTERVAL)
--
--static struct gpiod_lookup_table pb44_i2c_gpiod_table = {
--	.dev_id = "i2c-gpio.0",
--	.table = {
--		GPIO_LOOKUP_IDX("ath79-gpio", PB44_GPIO_I2C_SDA,
--				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
--		GPIO_LOOKUP_IDX("ath79-gpio", PB44_GPIO_I2C_SCL,
--				NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
--	},
--};
--
--static struct platform_device pb44_i2c_gpio_device = {
--	.name		= "i2c-gpio",
--	.id		= 0,
--	.dev = {
--		.platform_data	= NULL,
--	}
--};
--
--static struct pcf857x_platform_data pb44_pcf857x_data = {
--	.gpio_base	= PB44_GPIO_EXP_BASE,
--};
--
--static struct i2c_board_info pb44_i2c_board_info[] __initdata = {
--	{
--		I2C_BOARD_INFO("pcf8575", 0x20),
--		.platform_data	= &pb44_pcf857x_data,
--	},
--};
--
--static struct gpio_led pb44_leds_gpio[] __initdata = {
--	{
--		.name		= "pb44:amber:jump1",
--		.gpio		= PB44_GPIO_LED_JUMP1,
--		.active_low	= 1,
--	}, {
--		.name		= "pb44:green:jump2",
--		.gpio		= PB44_GPIO_LED_JUMP2,
--		.active_low	= 1,
--	},
--};
--
--static struct gpio_keys_button pb44_gpio_keys[] __initdata = {
--	{
--		.desc		= "soft_reset",
--		.type		= EV_KEY,
--		.code		= KEY_RESTART,
--		.debounce_interval = PB44_KEYS_DEBOUNCE_INTERVAL,
--		.gpio		= PB44_GPIO_SW_RESET,
--		.active_low	= 1,
--	} , {
--		.desc		= "jumpstart",
--		.type		= EV_KEY,
--		.code		= KEY_WPS_BUTTON,
--		.debounce_interval = PB44_KEYS_DEBOUNCE_INTERVAL,
--		.gpio		= PB44_GPIO_SW_JUMP,
--		.active_low	= 1,
--	}
--};
--
--static struct spi_board_info pb44_spi_info[] = {
--	{
--		.bus_num	= 0,
--		.chip_select	= 0,
--		.max_speed_hz	= 25000000,
--		.modalias	= "m25p64",
--	},
--};
--
--static struct ath79_spi_platform_data pb44_spi_data = {
--	.bus_num		= 0,
--	.num_chipselect		= 1,
--};
--
--static void __init pb44_init(void)
--{
--	gpiod_add_lookup_table(&pb44_i2c_gpiod_table);
--	i2c_register_board_info(0, pb44_i2c_board_info,
--				ARRAY_SIZE(pb44_i2c_board_info));
--	platform_device_register(&pb44_i2c_gpio_device);
--
--	ath79_register_leds_gpio(-1, ARRAY_SIZE(pb44_leds_gpio),
--				 pb44_leds_gpio);
--	ath79_register_gpio_keys_polled(-1, PB44_KEYS_POLL_INTERVAL,
--					ARRAY_SIZE(pb44_gpio_keys),
--					pb44_gpio_keys);
--	ath79_register_spi(&pb44_spi_data, pb44_spi_info,
--			   ARRAY_SIZE(pb44_spi_info));
--	ath79_register_usb();
--	ath79_register_pci();
--}
--
--MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
--	     pb44_init);
---- a/arch/mips/ath79/mach-ubnt-xm.c
-+++ /dev/null
-@@ -1,126 +0,0 @@
--/*
-- *  Ubiquiti Networks XM (rev 1.0) board support
-- *
-- *  Copyright (C) 2011 René Bolldorf <[email protected]>
-- *
-- *  Derived from: mach-pb44.c
-- *
-- *  This program is free software; you can redistribute it and/or modify it
-- *  under the terms of the GNU General Public License version 2 as published
-- *  by the Free Software Foundation.
-- */
--
--#include <linux/init.h>
--#include <linux/pci.h>
--#include <linux/ath9k_platform.h>
--
--#include <asm/mach-ath79/irq.h>
--
--#include "machtypes.h"
--#include "dev-gpio-buttons.h"
--#include "dev-leds-gpio.h"
--#include "dev-spi.h"
--#include "pci.h"
--
--#define UBNT_XM_GPIO_LED_L1		0
--#define UBNT_XM_GPIO_LED_L2		1
--#define UBNT_XM_GPIO_LED_L3		11
--#define UBNT_XM_GPIO_LED_L4		7
--
--#define UBNT_XM_GPIO_BTN_RESET		12
--
--#define UBNT_XM_KEYS_POLL_INTERVAL	20
--#define UBNT_XM_KEYS_DEBOUNCE_INTERVAL	(3 * UBNT_XM_KEYS_POLL_INTERVAL)
--
--#define UBNT_XM_EEPROM_ADDR		(u8 *) KSEG1ADDR(0x1fff1000)
--
--static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
--	{
--		.name		= "ubnt-xm:red:link1",
--		.gpio		= UBNT_XM_GPIO_LED_L1,
--		.active_low	= 0,
--	}, {
--		.name		= "ubnt-xm:orange:link2",
--		.gpio		= UBNT_XM_GPIO_LED_L2,
--		.active_low	= 0,
--	}, {
--		.name		= "ubnt-xm:green:link3",
--		.gpio		= UBNT_XM_GPIO_LED_L3,
--		.active_low	= 0,
--	}, {
--		.name		= "ubnt-xm:green:link4",
--		.gpio		= UBNT_XM_GPIO_LED_L4,
--		.active_low	= 0,
--	},
--};
--
--static struct gpio_keys_button ubnt_xm_gpio_keys[] __initdata = {
--	{
--		.desc			= "reset",
--		.type			= EV_KEY,
--		.code			= KEY_RESTART,
--		.debounce_interval	= UBNT_XM_KEYS_DEBOUNCE_INTERVAL,
--		.gpio			= UBNT_XM_GPIO_BTN_RESET,
--		.active_low		= 1,
--	}
--};
--
--static struct spi_board_info ubnt_xm_spi_info[] = {
--	{
--		.bus_num	= 0,
--		.chip_select	= 0,
--		.max_speed_hz	= 25000000,
--		.modalias	= "mx25l6405d",
--	}
--};
--
--static struct ath79_spi_platform_data ubnt_xm_spi_data = {
--	.bus_num		= 0,
--	.num_chipselect		= 1,
--};
--
--#ifdef CONFIG_PCI
--static struct ath9k_platform_data ubnt_xm_eeprom_data;
--
--static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev)
--{
--	switch (PCI_SLOT(dev->devfn)) {
--	case 0:
--		dev->dev.platform_data = &ubnt_xm_eeprom_data;
--		break;
--	}
--
--	return 0;
--}
--
--static void __init ubnt_xm_pci_init(void)
--{
--	memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
--	       sizeof(ubnt_xm_eeprom_data.eeprom_data));
--
--	ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init);
--	ath79_register_pci();
--}
--#else
--static inline void ubnt_xm_pci_init(void) {}
--#endif /* CONFIG_PCI */
--
--static void __init ubnt_xm_init(void)
--{
--	ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
--				 ubnt_xm_leds_gpio);
--
--	ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
--					ARRAY_SIZE(ubnt_xm_gpio_keys),
--					ubnt_xm_gpio_keys);
--
--	ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info,
--			   ARRAY_SIZE(ubnt_xm_spi_info));
--
--	ubnt_xm_pci_init();
--}
--
--MIPS_MACHINE(ATH79_MACH_UBNT_XM,
--	     "UBNT-XM",
--	     "Ubiquiti Networks XM (rev 1.0) board",
--	     ubnt_xm_init);
---- a/arch/mips/ath79/machtypes.h
-+++ /dev/null
-@@ -1,28 +0,0 @@
--/*
-- *  Atheros AR71XX/AR724X/AR913X machine type definitions
-- *
-- *  Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
-- *  Copyright (C) 2008 Imre Kaloz <[email protected]>
-- *
-- *  This program is free software; you can redistribute it and/or modify it
-- *  under the terms of the GNU General Public License version 2 as published
-- *  by the Free Software Foundation.
-- */
--
--#ifndef _ATH79_MACHTYPE_H
--#define _ATH79_MACHTYPE_H
--
--#include <asm/mips_machine.h>
--
--enum ath79_mach_type {
--	ATH79_MACH_GENERIC_OF = -1,	/* Device tree board */
--	ATH79_MACH_GENERIC = 0,
--	ATH79_MACH_AP121,		/* Atheros AP121 reference board */
--	ATH79_MACH_AP136_010,		/* Atheros AP136-010 reference board */
--	ATH79_MACH_AP81,		/* Atheros AP81 reference board */
--	ATH79_MACH_DB120,		/* Atheros DB120 reference board */
--	ATH79_MACH_PB44,		/* Atheros PB44 reference board */
--	ATH79_MACH_UBNT_XM,		/* Ubiquiti Networks XM board rev 1.0 */
--};
--
--#endif /* _ATH79_MACHTYPE_H */
---- a/arch/mips/ath79/setup.c
-+++ b/arch/mips/ath79/setup.c
-@@ -33,7 +33,6 @@
- #include <asm/mach-ath79/ar71xx_regs.h>
- #include "common.h"
- #include "dev-common.h"
--#include "machtypes.h"
- 
- #define ATH79_SYS_TYPE_LEN	64
- 
-@@ -230,25 +229,21 @@ void __init plat_mem_setup(void)
- 	else if (fw_passed_dtb)
- 		__dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb));
- 
--	if (mips_machtype != ATH79_MACH_GENERIC_OF) {
--		ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
--						   AR71XX_RESET_SIZE);
--		ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
--						 AR71XX_PLL_SIZE);
--		ath79_detect_sys_type();
--		ath79_ddr_ctrl_init();
-+	ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
-+					   AR71XX_RESET_SIZE);
-+	ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
-+					 AR71XX_PLL_SIZE);
-+	ath79_detect_sys_type();
-+	ath79_ddr_ctrl_init();
- 
--		detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
--
--		/* OF machines should use the reset driver */
--		_machine_restart = ath79_restart;
--	}
-+	detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
- 
-+	_machine_restart = ath79_restart;
- 	_machine_halt = ath79_halt;
- 	pm_power_off = ath79_halt;
- }
- 
--static void __init ath79_of_plat_time_init(void)
-+void __init plat_time_init(void)
- {
- 	struct device_node *np;
- 	struct clk *clk;
-@@ -278,66 +273,12 @@ static void __init ath79_of_plat_time_in
- 	clk_put(clk);
- }
- 
--void __init plat_time_init(void)
--{
--	unsigned long cpu_clk_rate;
--	unsigned long ahb_clk_rate;
--	unsigned long ddr_clk_rate;
--	unsigned long ref_clk_rate;
--
--	if (IS_ENABLED(CONFIG_OF) && mips_machtype == ATH79_MACH_GENERIC_OF) {
--		ath79_of_plat_time_init();
--		return;
--	}
--
--	ath79_clocks_init();
--
--	cpu_clk_rate = ath79_get_sys_clk_rate("cpu");
--	ahb_clk_rate = ath79_get_sys_clk_rate("ahb");
--	ddr_clk_rate = ath79_get_sys_clk_rate("ddr");
--	ref_clk_rate = ath79_get_sys_clk_rate("ref");
--
--	pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz\n",
--		cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000,
--		ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000,
--		ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000,
--		ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000);
--
--	mips_hpt_frequency = cpu_clk_rate / 2;
--}
--
- void __init arch_init_irq(void)
- {
- 	irqchip_init();
- }
- 
--static int __init ath79_setup(void)
--{
--	if  (mips_machtype == ATH79_MACH_GENERIC_OF)
--		return 0;
--
--	ath79_gpio_init();
--	ath79_register_uart();
--	ath79_register_wdt();
--
--	mips_machine_setup();
--
--	return 0;
--}
--
--arch_initcall(ath79_setup);
--
- void __init device_tree_init(void)
- {
- 	unflatten_and_copy_device_tree();
- }
--
--MIPS_MACHINE(ATH79_MACH_GENERIC,
--	     "Generic",
--	     "Generic AR71XX/AR724X/AR913X based board",
--	     NULL);
--
--MIPS_MACHINE(ATH79_MACH_GENERIC_OF,
--	     "DTB",
--	     "Generic AR71XX/AR724X/AR913X based board (DT)",
--	     NULL);

target/linux/ath79/patches-4.19/0029-MIPS-ath79-drop-legacy-pci-code.patch

@@ -1,379 +0,0 @@
-From d0f1420702ed47a82572aaf39e7407055518d14e Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Sat, 23 Jun 2018 15:05:19 +0200
-Subject: [PATCH 29/33] MIPS: ath79: drop legacy pci code
-
-With the target now being fully OF based, we can drop the legacy pci
-platform code. The only bits that we need to keep is the fixup code
-which we move to its own code file.
-
-Signed-off-by: John Crispin <[email protected]>
----
- arch/mips/ath79/Makefile    |   1 -
- arch/mips/ath79/pci.c       | 273 --------------------------------------------
- arch/mips/ath79/pci.h       |  35 ------
- arch/mips/pci/Makefile      |   1 +
- arch/mips/pci/fixup-ath79.c |  21 ++++
- 5 files changed, 22 insertions(+), 309 deletions(-)
- delete mode 100644 arch/mips/ath79/pci.c
- delete mode 100644 arch/mips/ath79/pci.h
- create mode 100644 arch/mips/pci/fixup-ath79.c
-
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -11,7 +11,6 @@
- obj-y	:= prom.o setup.o common.o clock.o
- 
- obj-$(CONFIG_EARLY_PRINTK)		+= early_printk.o
--obj-$(CONFIG_PCI)			+= pci.o
- 
- #
- # Devices
---- a/arch/mips/ath79/pci.c
-+++ /dev/null
-@@ -1,273 +0,0 @@
--/*
-- *  Atheros AR71XX/AR724X specific PCI setup code
-- *
-- *  Copyright (C) 2011 René Bolldorf <[email protected]>
-- *  Copyright (C) 2008-2011 Gabor Juhos <[email protected]>
-- *  Copyright (C) 2008 Imre Kaloz <[email protected]>
-- *
-- *  Parts of this file are based on Atheros' 2.6.15 BSP
-- *
-- *  This program is free software; you can redistribute it and/or modify it
-- *  under the terms of the GNU General Public License version 2 as published
-- *  by the Free Software Foundation.
-- */
--
--#include <linux/init.h>
--#include <linux/pci.h>
--#include <linux/resource.h>
--#include <linux/platform_device.h>
--#include <asm/mach-ath79/ar71xx_regs.h>
--#include <asm/mach-ath79/ath79.h>
--#include <asm/mach-ath79/irq.h>
--#include "pci.h"
--
--static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
--static const struct ath79_pci_irq *ath79_pci_irq_map;
--static unsigned ath79_pci_nr_irqs;
--
--static const struct ath79_pci_irq ar71xx_pci_irq_map[] = {
--	{
--		.slot	= 17,
--		.pin	= 1,
--		.irq	= ATH79_PCI_IRQ(0),
--	}, {
--		.slot	= 18,
--		.pin	= 1,
--		.irq	= ATH79_PCI_IRQ(1),
--	}, {
--		.slot	= 19,
--		.pin	= 1,
--		.irq	= ATH79_PCI_IRQ(2),
--	}
--};
--
--static const struct ath79_pci_irq ar724x_pci_irq_map[] = {
--	{
--		.slot	= 0,
--		.pin	= 1,
--		.irq	= ATH79_PCI_IRQ(0),
--	}
--};
--
--static const struct ath79_pci_irq qca955x_pci_irq_map[] = {
--	{
--		.bus	= 0,
--		.slot	= 0,
--		.pin	= 1,
--		.irq	= ATH79_PCI_IRQ(0),
--	},
--	{
--		.bus	= 1,
--		.slot	= 0,
--		.pin	= 1,
--		.irq	= ATH79_PCI_IRQ(1),
--	},
--};
--
--int pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
--{
--	int irq = -1;
--	int i;
--
--	if (ath79_pci_nr_irqs == 0 ||
--	    ath79_pci_irq_map == NULL) {
--		if (soc_is_ar71xx()) {
--			ath79_pci_irq_map = ar71xx_pci_irq_map;
--			ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map);
--		} else if (soc_is_ar724x() ||
--			   soc_is_ar9342() ||
--			   soc_is_ar9344()) {
--			ath79_pci_irq_map = ar724x_pci_irq_map;
--			ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
--		} else if (soc_is_qca955x()) {
--			ath79_pci_irq_map = qca955x_pci_irq_map;
--			ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
--		} else {
--			pr_crit("pci %s: invalid irq map\n",
--				pci_name((struct pci_dev *) dev));
--			return irq;
--		}
--	}
--
--	for (i = 0; i < ath79_pci_nr_irqs; i++) {
--		const struct ath79_pci_irq *entry;
--
--		entry = &ath79_pci_irq_map[i];
--		if (entry->bus == dev->bus->number &&
--		    entry->slot == slot &&
--		    entry->pin == pin) {
--			irq = entry->irq;
--			break;
--		}
--	}
--
--	if (irq < 0)
--		pr_crit("pci %s: no irq found for pin %u\n",
--			pci_name((struct pci_dev *) dev), pin);
--	else
--		pr_info("pci %s: using irq %d for pin %u\n",
--			pci_name((struct pci_dev *) dev), irq, pin);
--
--	return irq;
--}
--
--int pcibios_plat_dev_init(struct pci_dev *dev)
--{
--	if (ath79_pci_plat_dev_init)
--		return ath79_pci_plat_dev_init(dev);
--
--	return 0;
--}
--
--void __init ath79_pci_set_irq_map(unsigned nr_irqs,
--				  const struct ath79_pci_irq *map)
--{
--	ath79_pci_nr_irqs = nr_irqs;
--	ath79_pci_irq_map = map;
--}
--
--void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev))
--{
--	ath79_pci_plat_dev_init = func;
--}
--
--static struct platform_device *
--ath79_register_pci_ar71xx(void)
--{
--	struct platform_device *pdev;
--	struct resource res[4];
--
--	memset(res, 0, sizeof(res));
--
--	res[0].name = "cfg_base";
--	res[0].flags = IORESOURCE_MEM;
--	res[0].start = AR71XX_PCI_CFG_BASE;
--	res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1;
--
--	res[1].flags = IORESOURCE_IRQ;
--	res[1].start = ATH79_CPU_IRQ(2);
--	res[1].end = ATH79_CPU_IRQ(2);
--
--	res[2].name = "io_base";
--	res[2].flags = IORESOURCE_IO;
--	res[2].start = 0;
--	res[2].end = 0;
--
--	res[3].name = "mem_base";
--	res[3].flags = IORESOURCE_MEM;
--	res[3].start = AR71XX_PCI_MEM_BASE;
--	res[3].end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1;
--
--	pdev = platform_device_register_simple("ar71xx-pci", -1,
--					       res, ARRAY_SIZE(res));
--	return pdev;
--}
--
--static struct platform_device *
--ath79_register_pci_ar724x(int id,
--			  unsigned long cfg_base,
--			  unsigned long ctrl_base,
--			  unsigned long crp_base,
--			  unsigned long mem_base,
--			  unsigned long mem_size,
--			  unsigned long io_base,
--			  int irq)
--{
--	struct platform_device *pdev;
--	struct resource res[6];
--
--	memset(res, 0, sizeof(res));
--
--	res[0].name = "cfg_base";
--	res[0].flags = IORESOURCE_MEM;
--	res[0].start = cfg_base;
--	res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1;
--
--	res[1].name = "ctrl_base";
--	res[1].flags = IORESOURCE_MEM;
--	res[1].start = ctrl_base;
--	res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1;
--
--	res[2].flags = IORESOURCE_IRQ;
--	res[2].start = irq;
--	res[2].end = irq;
--
--	res[3].name = "mem_base";
--	res[3].flags = IORESOURCE_MEM;
--	res[3].start = mem_base;
--	res[3].end = mem_base + mem_size - 1;
--
--	res[4].name = "io_base";
--	res[4].flags = IORESOURCE_IO;
--	res[4].start = io_base;
--	res[4].end = io_base;
--
--	res[5].name = "crp_base";
--	res[5].flags = IORESOURCE_MEM;
--	res[5].start = crp_base;
--	res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1;
--
--	pdev = platform_device_register_simple("ar724x-pci", id,
--					       res, ARRAY_SIZE(res));
--	return pdev;
--}
--
--int __init ath79_register_pci(void)
--{
--	struct platform_device *pdev = NULL;
--
--	if (soc_is_ar71xx()) {
--		pdev = ath79_register_pci_ar71xx();
--	} else if (soc_is_ar724x()) {
--		pdev = ath79_register_pci_ar724x(-1,
--						 AR724X_PCI_CFG_BASE,
--						 AR724X_PCI_CTRL_BASE,
--						 AR724X_PCI_CRP_BASE,
--						 AR724X_PCI_MEM_BASE,
--						 AR724X_PCI_MEM_SIZE,
--						 0,
--						 ATH79_CPU_IRQ(2));
--	} else if (soc_is_ar9342() ||
--		   soc_is_ar9344()) {
--		u32 bootstrap;
--
--		bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
--		if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0)
--			return -ENODEV;
--
--		pdev = ath79_register_pci_ar724x(-1,
--						 AR724X_PCI_CFG_BASE,
--						 AR724X_PCI_CTRL_BASE,
--						 AR724X_PCI_CRP_BASE,
--						 AR724X_PCI_MEM_BASE,
--						 AR724X_PCI_MEM_SIZE,
--						 0,
--						 ATH79_IP2_IRQ(0));
--	} else if (soc_is_qca9558()) {
--		pdev = ath79_register_pci_ar724x(0,
--						 QCA955X_PCI_CFG_BASE0,
--						 QCA955X_PCI_CTRL_BASE0,
--						 QCA955X_PCI_CRP_BASE0,
--						 QCA955X_PCI_MEM_BASE0,
--						 QCA955X_PCI_MEM_SIZE,
--						 0,
--						 ATH79_IP2_IRQ(0));
--
--		pdev = ath79_register_pci_ar724x(1,
--						 QCA955X_PCI_CFG_BASE1,
--						 QCA955X_PCI_CTRL_BASE1,
--						 QCA955X_PCI_CRP_BASE1,
--						 QCA955X_PCI_MEM_BASE1,
--						 QCA955X_PCI_MEM_SIZE,
--						 1,
--						 ATH79_IP3_IRQ(2));
--	} else {
--		/* No PCI support */
--		return -ENODEV;
--	}
--
--	if (!pdev)
--		pr_err("unable to register PCI controller device\n");
--
--	return pdev ? 0 : -ENODEV;
--}
---- a/arch/mips/ath79/pci.h
-+++ /dev/null
-@@ -1,35 +0,0 @@
--/*
-- *  Atheros AR71XX/AR724X PCI support
-- *
-- *  Copyright (C) 2011 René Bolldorf <[email protected]>
-- *  Copyright (C) 2008-2011 Gabor Juhos <[email protected]>
-- *  Copyright (C) 2008 Imre Kaloz <[email protected]>
-- *
-- *  This program is free software; you can redistribute it and/or modify it
-- *  under the terms of the GNU General Public License version 2 as published
-- *  by the Free Software Foundation.
-- */
--
--#ifndef _ATH79_PCI_H
--#define _ATH79_PCI_H
--
--struct ath79_pci_irq {
--	int	bus;
--	u8	slot;
--	u8	pin;
--	int	irq;
--};
--
--#ifdef CONFIG_PCI
--void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map);
--void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev));
--int ath79_register_pci(void);
--#else
--static inline void
--ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map) {}
--static inline void
--ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {}
--static inline int ath79_register_pci(void) { return 0; }
--#endif
--
--#endif /* _ATH79_PCI_H */
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -29,6 +29,7 @@ obj-$(CONFIG_MIPS_PCI_VIRTIO)	+= pci-vir
- #
- # These are still pretty much in the old state, watch, go blind.
- #
-+obj-$(CONFIG_ATH79)		+= fixup-ath79.o
- obj-$(CONFIG_LASAT)		+= pci-lasat.o
- obj-$(CONFIG_MIPS_COBALT)	+= fixup-cobalt.o
- obj-$(CONFIG_LEMOTE_FULOONG2E)	+= fixup-fuloong2e.o ops-loongson2.o
---- /dev/null
-+++ b/arch/mips/pci/fixup-ath79.c
-@@ -0,0 +1,21 @@
-+/*
-+ *  Copyright (C) 2018 John Crispin <[email protected]>
-+ *
-+ *  This program is free software; you can redistribute it and/or modify it
-+ *  under the terms of the GNU General Public License version 2 as published
-+ *  by the Free Software Foundation.
-+ */
-+
-+#include <linux/pci.h>
-+//#include <linux/of_irq.h>
-+#include <linux/of_pci.h>
-+
-+int pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+	return PCIBIOS_SUCCESSFUL;
-+}
-+
-+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+	return of_irq_parse_and_map_pci(dev, slot, pin);
-+}

target/linux/ath79/patches-4.19/0030-MIPS-ath79-drop-platform-device-registration-code.patch

@@ -1,933 +0,0 @@
-From dce930fba8ad3a90ccd164f199e57c2d61937ccd Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Sat, 23 Jun 2018 15:12:38 +0200
-Subject: [PATCH 30/33] MIPS: ath79: drop platform device registration code
-
-With the target now being fully OF based, we can drop the legacy platform
-device registration code. All devices and their drivers are now probed
-via OF.
-
-Signed-off-by: John Crispin <[email protected]>
----
- arch/mips/ath79/Makefile           |  10 --
- arch/mips/ath79/common.h           |   2 -
- arch/mips/ath79/dev-common.c       | 159 ------------------------
- arch/mips/ath79/dev-common.h       |  18 ---
- arch/mips/ath79/dev-gpio-buttons.c |  56 ---------
- arch/mips/ath79/dev-gpio-buttons.h |  23 ----
- arch/mips/ath79/dev-leds-gpio.c    |  54 ---------
- arch/mips/ath79/dev-leds-gpio.h    |  21 ----
- arch/mips/ath79/dev-spi.c          |  38 ------
- arch/mips/ath79/dev-spi.h          |  22 ----
- arch/mips/ath79/dev-usb.c          | 242 -------------------------------------
- arch/mips/ath79/dev-usb.h          |  17 ---
- arch/mips/ath79/dev-wmac.c         | 155 ------------------------
- arch/mips/ath79/dev-wmac.h         |  17 ---
- arch/mips/ath79/setup.c            |   1 -
- 15 files changed, 835 deletions(-)
- delete mode 100644 arch/mips/ath79/dev-common.c
- delete mode 100644 arch/mips/ath79/dev-common.h
- delete mode 100644 arch/mips/ath79/dev-gpio-buttons.c
- delete mode 100644 arch/mips/ath79/dev-gpio-buttons.h
- delete mode 100644 arch/mips/ath79/dev-leds-gpio.c
- delete mode 100644 arch/mips/ath79/dev-leds-gpio.h
- delete mode 100644 arch/mips/ath79/dev-spi.c
- delete mode 100644 arch/mips/ath79/dev-spi.h
- delete mode 100644 arch/mips/ath79/dev-usb.c
- delete mode 100644 arch/mips/ath79/dev-usb.h
- delete mode 100644 arch/mips/ath79/dev-wmac.c
- delete mode 100644 arch/mips/ath79/dev-wmac.h
-
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -11,13 +11,3 @@
- obj-y	:= prom.o setup.o common.o clock.o
- 
- obj-$(CONFIG_EARLY_PRINTK)		+= early_printk.o
--
--#
--# Devices
--#
--obj-y					+= dev-common.o
--obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS)	+= dev-gpio-buttons.o
--obj-$(CONFIG_ATH79_DEV_LEDS_GPIO)	+= dev-leds-gpio.o
--obj-$(CONFIG_ATH79_DEV_SPI)		+= dev-spi.o
--obj-$(CONFIG_ATH79_DEV_USB)		+= dev-usb.o
--obj-$(CONFIG_ATH79_DEV_WMAC)		+= dev-wmac.o
---- a/arch/mips/ath79/common.h
-+++ b/arch/mips/ath79/common.h
-@@ -24,6 +24,4 @@ unsigned long ath79_get_sys_clk_rate(con
- 
- void ath79_ddr_ctrl_init(void);
- 
--void ath79_gpio_init(void);
--
- #endif /* __ATH79_COMMON_H */
---- a/arch/mips/ath79/dev-common.c
-+++ /dev/null
-@@ -1,159 +0,0 @@
--/*
-- *  Atheros AR71XX/AR724X/AR913X common devices
-- *
-- *  Copyright (C) 2008-2011 Gabor Juhos <[email protected]>
-- *  Copyright (C) 2008 Imre Kaloz <[email protected]>
-- *
-- *  Parts of this file are based on Atheros' 2.6.15 BSP
-- *
-- *  This program is free software; you can redistribute it and/or modify it
-- *  under the terms of the GNU General Public License version 2 as published
-- *  by the Free Software Foundation.
-- */
--
--#include <linux/kernel.h>
--#include <linux/init.h>
--#include <linux/platform_device.h>
--#include <linux/platform_data/gpio-ath79.h>
--#include <linux/serial_8250.h>
--#include <linux/clk.h>
--#include <linux/err.h>
--
--#include <asm/mach-ath79/ath79.h>
--#include <asm/mach-ath79/ar71xx_regs.h>
--#include "common.h"
--#include "dev-common.h"
--
--static struct resource ath79_uart_resources[] = {
--	{
--		.start	= AR71XX_UART_BASE,
--		.end	= AR71XX_UART_BASE + AR71XX_UART_SIZE - 1,
--		.flags	= IORESOURCE_MEM,
--	},
--};
--
--#define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
--static struct plat_serial8250_port ath79_uart_data[] = {
--	{
--		.mapbase	= AR71XX_UART_BASE,
--		.irq		= ATH79_MISC_IRQ(3),
--		.flags		= AR71XX_UART_FLAGS,
--		.iotype		= UPIO_MEM32,
--		.regshift	= 2,
--	}, {
--		/* terminating entry */
--	}
--};
--
--static struct platform_device ath79_uart_device = {
--	.name		= "serial8250",
--	.id		= PLAT8250_DEV_PLATFORM,
--	.resource	= ath79_uart_resources,
--	.num_resources	= ARRAY_SIZE(ath79_uart_resources),
--	.dev = {
--		.platform_data	= ath79_uart_data
--	},
--};
--
--static struct resource ar933x_uart_resources[] = {
--	{
--		.start	= AR933X_UART_BASE,
--		.end	= AR933X_UART_BASE + AR71XX_UART_SIZE - 1,
--		.flags	= IORESOURCE_MEM,
--	},
--	{
--		.start	= ATH79_MISC_IRQ(3),
--		.end	= ATH79_MISC_IRQ(3),
--		.flags	= IORESOURCE_IRQ,
--	},
--};
--
--static struct platform_device ar933x_uart_device = {
--	.name		= "ar933x-uart",
--	.id		= -1,
--	.resource	= ar933x_uart_resources,
--	.num_resources	= ARRAY_SIZE(ar933x_uart_resources),
--};
--
--void __init ath79_register_uart(void)
--{
--	unsigned long uart_clk_rate;
--
--	uart_clk_rate = ath79_get_sys_clk_rate("uart");
--
--	if (soc_is_ar71xx() ||
--	    soc_is_ar724x() ||
--	    soc_is_ar913x() ||
--	    soc_is_ar934x() ||
--	    soc_is_qca955x()) {
--		ath79_uart_data[0].uartclk = uart_clk_rate;
--		platform_device_register(&ath79_uart_device);
--	} else if (soc_is_ar933x()) {
--		platform_device_register(&ar933x_uart_device);
--	} else {
--		BUG();
--	}
--}
--
--void __init ath79_register_wdt(void)
--{
--	struct resource res;
--
--	memset(&res, 0, sizeof(res));
--
--	res.flags = IORESOURCE_MEM;
--	res.start = AR71XX_RESET_BASE + AR71XX_RESET_REG_WDOG_CTRL;
--	res.end = res.start + 0x8 - 1;
--
--	platform_device_register_simple("ath79-wdt", -1, &res, 1);
--}
--
--static struct ath79_gpio_platform_data ath79_gpio_pdata;
--
--static struct resource ath79_gpio_resources[] = {
--	{
--		.flags = IORESOURCE_MEM,
--		.start = AR71XX_GPIO_BASE,
--		.end = AR71XX_GPIO_BASE + AR71XX_GPIO_SIZE - 1,
--	},
--	{
--		.start	= ATH79_MISC_IRQ(2),
--		.end	= ATH79_MISC_IRQ(2),
--		.flags	= IORESOURCE_IRQ,
--	},
--};
--
--static struct platform_device ath79_gpio_device = {
--	.name		= "ath79-gpio",
--	.id		= -1,
--	.resource	= ath79_gpio_resources,
--	.num_resources	= ARRAY_SIZE(ath79_gpio_resources),
--	.dev = {
--		.platform_data	= &ath79_gpio_pdata
--	},
--};
--
--void __init ath79_gpio_init(void)
--{
--	if (soc_is_ar71xx()) {
--		ath79_gpio_pdata.ngpios = AR71XX_GPIO_COUNT;
--	} else if (soc_is_ar7240()) {
--		ath79_gpio_pdata.ngpios = AR7240_GPIO_COUNT;
--	} else if (soc_is_ar7241() || soc_is_ar7242()) {
--		ath79_gpio_pdata.ngpios = AR7241_GPIO_COUNT;
--	} else if (soc_is_ar913x()) {
--		ath79_gpio_pdata.ngpios = AR913X_GPIO_COUNT;
--	} else if (soc_is_ar933x()) {
--		ath79_gpio_pdata.ngpios = AR933X_GPIO_COUNT;
--	} else if (soc_is_ar934x()) {
--		ath79_gpio_pdata.ngpios = AR934X_GPIO_COUNT;
--		ath79_gpio_pdata.oe_inverted = 1;
--	} else if (soc_is_qca955x()) {
--		ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT;
--		ath79_gpio_pdata.oe_inverted = 1;
--	} else {
--		BUG();
--	}
--
--	platform_device_register(&ath79_gpio_device);
--}
---- a/arch/mips/ath79/dev-common.h
-+++ /dev/null
-@@ -1,18 +0,0 @@
--/*
-- *  Atheros AR71XX/AR724X/AR913X common devices
-- *
-- *  Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
-- *  Copyright (C) 2008 Imre Kaloz <[email protected]>
-- *
-- *  This program is free software; you can redistribute it and/or modify it
-- *  under the terms of the GNU General Public License version 2 as published
-- *  by the Free Software Foundation.
-- */
--
--#ifndef _ATH79_DEV_COMMON_H
--#define _ATH79_DEV_COMMON_H
--
--void ath79_register_uart(void);
--void ath79_register_wdt(void);
--
--#endif /* _ATH79_DEV_COMMON_H */
---- a/arch/mips/ath79/dev-gpio-buttons.c
-+++ /dev/null
-@@ -1,56 +0,0 @@
--/*
-- *  Atheros AR71XX/AR724X/AR913X GPIO button support
-- *
-- *  Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
-- *  Copyright (C) 2008 Imre Kaloz <[email protected]>
-- *
-- *  This program is free software; you can redistribute it and/or modify it
-- *  under the terms of the GNU General Public License version 2 as published
-- *  by the Free Software Foundation.
-- */
--
--#include "linux/init.h"
--#include "linux/slab.h"
--#include <linux/platform_device.h>
--
--#include "dev-gpio-buttons.h"
--
--void __init ath79_register_gpio_keys_polled(int id,
--					    unsigned poll_interval,
--					    unsigned nbuttons,
--					    struct gpio_keys_button *buttons)
--{
--	struct platform_device *pdev;
--	struct gpio_keys_platform_data pdata;
--	struct gpio_keys_button *p;
--	int err;
--
--	p = kmemdup(buttons, nbuttons * sizeof(*p), GFP_KERNEL);
--	if (!p)
--		return;
--
--	pdev = platform_device_alloc("gpio-keys-polled", id);
--	if (!pdev)
--		goto err_free_buttons;
--
--	memset(&pdata, 0, sizeof(pdata));
--	pdata.poll_interval = poll_interval;
--	pdata.nbuttons = nbuttons;
--	pdata.buttons = p;
--
--	err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
--	if (err)
--		goto err_put_pdev;
--
--	err = platform_device_add(pdev);
--	if (err)
--		goto err_put_pdev;
--
--	return;
--
--err_put_pdev:
--	platform_device_put(pdev);
--
--err_free_buttons:
--	kfree(p);
--}
---- a/arch/mips/ath79/dev-gpio-buttons.h
-+++ /dev/null
-@@ -1,23 +0,0 @@
--/*
-- *  Atheros AR71XX/AR724X/AR913X GPIO button support
-- *
-- *  Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
-- *  Copyright (C) 2008 Imre Kaloz <[email protected]>
-- *
-- *  This program is free software; you can redistribute it and/or modify it
-- *  under the terms of the GNU General Public License version 2 as published
-- *  by the Free Software Foundation.
-- */
--
--#ifndef _ATH79_DEV_GPIO_BUTTONS_H
--#define _ATH79_DEV_GPIO_BUTTONS_H
--
--#include <linux/input.h>
--#include <linux/gpio_keys.h>
--
--void ath79_register_gpio_keys_polled(int id,
--				     unsigned poll_interval,
--				     unsigned nbuttons,
--				     struct gpio_keys_button *buttons);
--
--#endif /* _ATH79_DEV_GPIO_BUTTONS_H */
---- a/arch/mips/ath79/dev-leds-gpio.c
-+++ /dev/null
-@@ -1,54 +0,0 @@
--/*
-- *  Atheros AR71XX/AR724X/AR913X common GPIO LEDs support
-- *
-- *  Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
-- *  Copyright (C) 2008 Imre Kaloz <[email protected]>
-- *
-- *  This program is free software; you can redistribute it and/or modify it
-- *  under the terms of the GNU General Public License version 2 as published
-- *  by the Free Software Foundation.
-- */
--
--#include <linux/init.h>
--#include <linux/slab.h>
--#include <linux/platform_device.h>
--
--#include "dev-leds-gpio.h"
--
--void __init ath79_register_leds_gpio(int id,
--				     unsigned num_leds,
--				     struct gpio_led *leds)
--{
--	struct platform_device *pdev;
--	struct gpio_led_platform_data pdata;
--	struct gpio_led *p;
--	int err;
--
--	p = kmemdup(leds, num_leds * sizeof(*p), GFP_KERNEL);
--	if (!p)
--		return;
--
--	pdev = platform_device_alloc("leds-gpio", id);
--	if (!pdev)
--		goto err_free_leds;
--
--	memset(&pdata, 0, sizeof(pdata));
--	pdata.num_leds = num_leds;
--	pdata.leds = p;
--
--	err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
--	if (err)
--		goto err_put_pdev;
--
--	err = platform_device_add(pdev);
--	if (err)
--		goto err_put_pdev;
--
--	return;
--
--err_put_pdev:
--	platform_device_put(pdev);
--
--err_free_leds:
--	kfree(p);
--}
---- a/arch/mips/ath79/dev-leds-gpio.h
-+++ /dev/null
-@@ -1,21 +0,0 @@
--/*
-- *  Atheros AR71XX/AR724X/AR913X common GPIO LEDs support
-- *
-- *  Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
-- *  Copyright (C) 2008 Imre Kaloz <[email protected]>
-- *
-- *  This program is free software; you can redistribute it and/or modify it
-- *  under the terms of the GNU General Public License version 2 as published
-- *  by the Free Software Foundation.
-- */
--
--#ifndef _ATH79_DEV_LEDS_GPIO_H
--#define _ATH79_DEV_LEDS_GPIO_H
--
--#include <linux/leds.h>
--
--void ath79_register_leds_gpio(int id,
--			      unsigned num_leds,
--			      struct gpio_led *leds);
--
--#endif /* _ATH79_DEV_LEDS_GPIO_H */
---- a/arch/mips/ath79/dev-spi.c
-+++ /dev/null
-@@ -1,38 +0,0 @@
--/*
-- *  Atheros AR71XX/AR724X/AR913X SPI controller device
-- *
-- *  Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
-- *  Copyright (C) 2008 Imre Kaloz <[email protected]>
-- *
-- *  This program is free software; you can redistribute it and/or modify it
-- *  under the terms of the GNU General Public License version 2 as published
-- *  by the Free Software Foundation.
-- */
--
--#include <linux/platform_device.h>
--#include <asm/mach-ath79/ar71xx_regs.h>
--#include "dev-spi.h"
--
--static struct resource ath79_spi_resources[] = {
--	{
--		.start	= AR71XX_SPI_BASE,
--		.end	= AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
--		.flags	= IORESOURCE_MEM,
--	},
--};
--
--static struct platform_device ath79_spi_device = {
--	.name		= "ath79-spi",
--	.id		= -1,
--	.resource	= ath79_spi_resources,
--	.num_resources	= ARRAY_SIZE(ath79_spi_resources),
--};
--
--void __init ath79_register_spi(struct ath79_spi_platform_data *pdata,
--			       struct spi_board_info const *info,
--			       unsigned n)
--{
--	spi_register_board_info(info, n);
--	ath79_spi_device.dev.platform_data = pdata;
--	platform_device_register(&ath79_spi_device);
--}
---- a/arch/mips/ath79/dev-spi.h
-+++ /dev/null
-@@ -1,22 +0,0 @@
--/*
-- *  Atheros AR71XX/AR724X/AR913X SPI controller device
-- *
-- *  Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
-- *  Copyright (C) 2008 Imre Kaloz <[email protected]>
-- *
-- *  This program is free software; you can redistribute it and/or modify it
-- *  under the terms of the GNU General Public License version 2 as published
-- *  by the Free Software Foundation.
-- */
--
--#ifndef _ATH79_DEV_SPI_H
--#define _ATH79_DEV_SPI_H
--
--#include <linux/spi/spi.h>
--#include <asm/mach-ath79/ath79_spi_platform.h>
--
--void ath79_register_spi(struct ath79_spi_platform_data *pdata,
--			 struct spi_board_info const *info,
--			 unsigned n);
--
--#endif /* _ATH79_DEV_SPI_H */
---- a/arch/mips/ath79/dev-usb.c
-+++ /dev/null
-@@ -1,242 +0,0 @@
--/*
-- *  Atheros AR7XXX/AR9XXX USB Host Controller device
-- *
-- *  Copyright (C) 2008-2011 Gabor Juhos <[email protected]>
-- *  Copyright (C) 2008 Imre Kaloz <[email protected]>
-- *
-- *  Parts of this file are based on Atheros' 2.6.15 BSP
-- *
-- *  This program is free software; you can redistribute it and/or modify it
-- *  under the terms of the GNU General Public License version 2 as published
-- *  by the Free Software Foundation.
-- */
--
--#include <linux/kernel.h>
--#include <linux/init.h>
--#include <linux/delay.h>
--#include <linux/irq.h>
--#include <linux/dma-mapping.h>
--#include <linux/platform_device.h>
--#include <linux/usb/ehci_pdriver.h>
--#include <linux/usb/ohci_pdriver.h>
--
--#include <asm/mach-ath79/ath79.h>
--#include <asm/mach-ath79/ar71xx_regs.h>
--#include "common.h"
--#include "dev-usb.h"
--
--static u64 ath79_usb_dmamask = DMA_BIT_MASK(32);
--
--static struct usb_ohci_pdata ath79_ohci_pdata = {
--};
--
--static struct usb_ehci_pdata ath79_ehci_pdata_v1 = {
--	.has_synopsys_hc_bug	= 1,
--};
--
--static struct usb_ehci_pdata ath79_ehci_pdata_v2 = {
--	.caps_offset		= 0x100,
--	.has_tt			= 1,
--};
--
--static void __init ath79_usb_register(const char *name, int id,
--				      unsigned long base, unsigned long size,
--				      int irq, const void *data,
--				      size_t data_size)
--{
--	struct resource res[2];
--	struct platform_device *pdev;
--
--	memset(res, 0, sizeof(res));
--
--	res[0].flags = IORESOURCE_MEM;
--	res[0].start = base;
--	res[0].end = base + size - 1;
--
--	res[1].flags = IORESOURCE_IRQ;
--	res[1].start = irq;
--	res[1].end = irq;
--
--	pdev = platform_device_register_resndata(NULL, name, id,
--						 res, ARRAY_SIZE(res),
--						 data, data_size);
--
--	if (IS_ERR(pdev)) {
--		pr_err("ath79: unable to register USB at %08lx, err=%d\n",
--		       base, (int) PTR_ERR(pdev));
--		return;
--	}
--
--	pdev->dev.dma_mask = &ath79_usb_dmamask;
--	pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
--}
--
--#define AR71XX_USB_RESET_MASK	(AR71XX_RESET_USB_HOST | \
--				 AR71XX_RESET_USB_PHY | \
--				 AR71XX_RESET_USB_OHCI_DLL)
--
--static void __init ath79_usb_setup(void)
--{
--	void __iomem *usb_ctrl_base;
--
--	ath79_device_reset_set(AR71XX_USB_RESET_MASK);
--	mdelay(1000);
--	ath79_device_reset_clear(AR71XX_USB_RESET_MASK);
--
--	usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE);
--
--	/* Turning on the Buff and Desc swap bits */
--	__raw_writel(0xf0000, usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG);
--
--	/* WAR for HW bug. Here it adjusts the duration between two SOFS */
--	__raw_writel(0x20c00, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
--
--	iounmap(usb_ctrl_base);
--
--	mdelay(900);
--
--	ath79_usb_register("ohci-platform", -1,
--			   AR71XX_OHCI_BASE, AR71XX_OHCI_SIZE,
--			   ATH79_MISC_IRQ(6),
--			   &ath79_ohci_pdata, sizeof(ath79_ohci_pdata));
--
--	ath79_usb_register("ehci-platform", -1,
--			   AR71XX_EHCI_BASE, AR71XX_EHCI_SIZE,
--			   ATH79_CPU_IRQ(3),
--			   &ath79_ehci_pdata_v1, sizeof(ath79_ehci_pdata_v1));
--}
--
--static void __init ar7240_usb_setup(void)
--{
--	void __iomem *usb_ctrl_base;
--
--	ath79_device_reset_clear(AR7240_RESET_OHCI_DLL);
--	ath79_device_reset_set(AR7240_RESET_USB_HOST);
--
--	mdelay(1000);
--
--	ath79_device_reset_set(AR7240_RESET_OHCI_DLL);
--	ath79_device_reset_clear(AR7240_RESET_USB_HOST);
--
--	usb_ctrl_base = ioremap(AR7240_USB_CTRL_BASE, AR7240_USB_CTRL_SIZE);
--
--	/* WAR for HW bug. Here it adjusts the duration between two SOFS */
--	__raw_writel(0x3, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
--
--	iounmap(usb_ctrl_base);
--
--	ath79_usb_register("ohci-platform", -1,
--			   AR7240_OHCI_BASE, AR7240_OHCI_SIZE,
--			   ATH79_CPU_IRQ(3),
--			   &ath79_ohci_pdata, sizeof(ath79_ohci_pdata));
--}
--
--static void __init ar724x_usb_setup(void)
--{
--	ath79_device_reset_set(AR724X_RESET_USBSUS_OVERRIDE);
--	mdelay(10);
--
--	ath79_device_reset_clear(AR724X_RESET_USB_HOST);
--	mdelay(10);
--
--	ath79_device_reset_clear(AR724X_RESET_USB_PHY);
--	mdelay(10);
--
--	ath79_usb_register("ehci-platform", -1,
--			   AR724X_EHCI_BASE, AR724X_EHCI_SIZE,
--			   ATH79_CPU_IRQ(3),
--			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
--}
--
--static void __init ar913x_usb_setup(void)
--{
--	ath79_device_reset_set(AR913X_RESET_USBSUS_OVERRIDE);
--	mdelay(10);
--
--	ath79_device_reset_clear(AR913X_RESET_USB_HOST);
--	mdelay(10);
--
--	ath79_device_reset_clear(AR913X_RESET_USB_PHY);
--	mdelay(10);
--
--	ath79_usb_register("ehci-platform", -1,
--			   AR913X_EHCI_BASE, AR913X_EHCI_SIZE,
--			   ATH79_CPU_IRQ(3),
--			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
--}
--
--static void __init ar933x_usb_setup(void)
--{
--	ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE);
--	mdelay(10);
--
--	ath79_device_reset_clear(AR933X_RESET_USB_HOST);
--	mdelay(10);
--
--	ath79_device_reset_clear(AR933X_RESET_USB_PHY);
--	mdelay(10);
--
--	ath79_usb_register("ehci-platform", -1,
--			   AR933X_EHCI_BASE, AR933X_EHCI_SIZE,
--			   ATH79_CPU_IRQ(3),
--			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
--}
--
--static void __init ar934x_usb_setup(void)
--{
--	u32 bootstrap;
--
--	bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
--	if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
--		return;
--
--	ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE);
--	udelay(1000);
--
--	ath79_device_reset_clear(AR934X_RESET_USB_PHY);
--	udelay(1000);
--
--	ath79_device_reset_clear(AR934X_RESET_USB_PHY_ANALOG);
--	udelay(1000);
--
--	ath79_device_reset_clear(AR934X_RESET_USB_HOST);
--	udelay(1000);
--
--	ath79_usb_register("ehci-platform", -1,
--			   AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
--			   ATH79_CPU_IRQ(3),
--			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
--}
--
--static void __init qca955x_usb_setup(void)
--{
--	ath79_usb_register("ehci-platform", 0,
--			   QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
--			   ATH79_IP3_IRQ(0),
--			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
--
--	ath79_usb_register("ehci-platform", 1,
--			   QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE,
--			   ATH79_IP3_IRQ(1),
--			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
--}
--
--void __init ath79_register_usb(void)
--{
--	if (soc_is_ar71xx())
--		ath79_usb_setup();
--	else if (soc_is_ar7240())
--		ar7240_usb_setup();
--	else if (soc_is_ar7241() || soc_is_ar7242())
--		ar724x_usb_setup();
--	else if (soc_is_ar913x())
--		ar913x_usb_setup();
--	else if (soc_is_ar933x())
--		ar933x_usb_setup();
--	else if (soc_is_ar934x())
--		ar934x_usb_setup();
--	else if (soc_is_qca955x())
--		qca955x_usb_setup();
--	else
--		BUG();
--}
---- a/arch/mips/ath79/dev-usb.h
-+++ /dev/null
-@@ -1,17 +0,0 @@
--/*
-- *  Atheros AR71XX/AR724X/AR913X USB Host Controller support
-- *
-- *  Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
-- *  Copyright (C) 2008 Imre Kaloz <[email protected]>
-- *
-- *  This program is free software; you can redistribute it and/or modify it
-- *  under the terms of the GNU General Public License version 2 as published
-- *  by the Free Software Foundation.
-- */
--
--#ifndef _ATH79_DEV_USB_H
--#define _ATH79_DEV_USB_H
--
--void ath79_register_usb(void);
--
--#endif /* _ATH79_DEV_USB_H */
---- a/arch/mips/ath79/dev-wmac.c
-+++ /dev/null
-@@ -1,155 +0,0 @@
--/*
-- *  Atheros AR913X/AR933X SoC built-in WMAC device support
-- *
-- *  Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]>
-- *  Copyright (C) 2008-2011 Gabor Juhos <[email protected]>
-- *  Copyright (C) 2008 Imre Kaloz <[email protected]>
-- *
-- *  Parts of this file are based on Atheros 2.6.15/2.6.31 BSP
-- *
-- *  This program is free software; you can redistribute it and/or modify it
-- *  under the terms of the GNU General Public License version 2 as published
-- *  by the Free Software Foundation.
-- */
--
--#include <linux/init.h>
--#include <linux/delay.h>
--#include <linux/irq.h>
--#include <linux/platform_device.h>
--#include <linux/ath9k_platform.h>
--
--#include <asm/mach-ath79/ath79.h>
--#include <asm/mach-ath79/ar71xx_regs.h>
--#include "dev-wmac.h"
--
--static struct ath9k_platform_data ath79_wmac_data;
--
--static struct resource ath79_wmac_resources[] = {
--	{
--		/* .start and .end fields are filled dynamically */
--		.flags	= IORESOURCE_MEM,
--	}, {
--		/* .start and .end fields are filled dynamically */
--		.flags	= IORESOURCE_IRQ,
--	},
--};
--
--static struct platform_device ath79_wmac_device = {
--	.name		= "ath9k",
--	.id		= -1,
--	.resource	= ath79_wmac_resources,
--	.num_resources	= ARRAY_SIZE(ath79_wmac_resources),
--	.dev = {
--		.platform_data = &ath79_wmac_data,
--	},
--};
--
--static void __init ar913x_wmac_setup(void)
--{
--	/* reset the WMAC */
--	ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
--	mdelay(10);
--
--	ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
--	mdelay(10);
--
--	ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
--	ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
--	ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
--	ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
--}
--
--
--static int ar933x_wmac_reset(void)
--{
--	ath79_device_reset_set(AR933X_RESET_WMAC);
--	ath79_device_reset_clear(AR933X_RESET_WMAC);
--
--	return 0;
--}
--
--static int ar933x_r1_get_wmac_revision(void)
--{
--	return ath79_soc_rev;
--}
--
--static void __init ar933x_wmac_setup(void)
--{
--	u32 t;
--
--	ar933x_wmac_reset();
--
--	ath79_wmac_device.name = "ar933x_wmac";
--
--	ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
--	ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
--	ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
--	ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
--
--	t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
--	if (t & AR933X_BOOTSTRAP_REF_CLK_40)
--		ath79_wmac_data.is_clk_25mhz = false;
--	else
--		ath79_wmac_data.is_clk_25mhz = true;
--
--	if (ath79_soc_rev == 1)
--		ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
--
--	ath79_wmac_data.external_reset = ar933x_wmac_reset;
--}
--
--static void ar934x_wmac_setup(void)
--{
--	u32 t;
--
--	ath79_wmac_device.name = "ar934x_wmac";
--
--	ath79_wmac_resources[0].start = AR934X_WMAC_BASE;
--	ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1;
--	ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
--	ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
--
--	t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
--	if (t & AR934X_BOOTSTRAP_REF_CLK_40)
--		ath79_wmac_data.is_clk_25mhz = false;
--	else
--		ath79_wmac_data.is_clk_25mhz = true;
--}
--
--static void qca955x_wmac_setup(void)
--{
--	u32 t;
--
--	ath79_wmac_device.name = "qca955x_wmac";
--
--	ath79_wmac_resources[0].start = QCA955X_WMAC_BASE;
--	ath79_wmac_resources[0].end = QCA955X_WMAC_BASE + QCA955X_WMAC_SIZE - 1;
--	ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
--	ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
--
--	t = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
--	if (t & QCA955X_BOOTSTRAP_REF_CLK_40)
--		ath79_wmac_data.is_clk_25mhz = false;
--	else
--		ath79_wmac_data.is_clk_25mhz = true;
--}
--
--void __init ath79_register_wmac(u8 *cal_data)
--{
--	if (soc_is_ar913x())
--		ar913x_wmac_setup();
--	else if (soc_is_ar933x())
--		ar933x_wmac_setup();
--	else if (soc_is_ar934x())
--		ar934x_wmac_setup();
--	else if (soc_is_qca955x())
--		qca955x_wmac_setup();
--	else
--		BUG();
--
--	if (cal_data)
--		memcpy(ath79_wmac_data.eeprom_data, cal_data,
--		       sizeof(ath79_wmac_data.eeprom_data));
--
--	platform_device_register(&ath79_wmac_device);
--}
---- a/arch/mips/ath79/dev-wmac.h
-+++ /dev/null
-@@ -1,17 +0,0 @@
--/*
-- *  Atheros AR913X/AR933X SoC built-in WMAC device support
-- *
-- *  Copyright (C) 2008-2011 Gabor Juhos <[email protected]>
-- *  Copyright (C) 2008 Imre Kaloz <[email protected]>
-- *
-- *  This program is free software; you can redistribute it and/or modify it
-- *  under the terms of the GNU General Public License version 2 as published
-- *  by the Free Software Foundation.
-- */
--
--#ifndef _ATH79_DEV_WMAC_H
--#define _ATH79_DEV_WMAC_H
--
--void ath79_register_wmac(u8 *cal_data);
--
--#endif /* _ATH79_DEV_WMAC_H */
---- a/arch/mips/ath79/setup.c
-+++ b/arch/mips/ath79/setup.c
-@@ -32,7 +32,6 @@
- #include <asm/mach-ath79/ath79.h>
- #include <asm/mach-ath79/ar71xx_regs.h>
- #include "common.h"
--#include "dev-common.h"
- 
- #define ATH79_SYS_TYPE_LEN	64
- 

target/linux/ath79/patches-4.19/0031-MIPS-ath79-drop-OF-clock-code.patch

@@ -1,95 +0,0 @@
-From 00e4313da4609074fff134e61dd9ffe3fd37474d Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Sun, 24 Jun 2018 09:39:41 +0200
-Subject: [PATCH 31/33] MIPS: ath79: drop !OF clock code
-
-With the target now being fully OF based, we can drop the legacy clock
-registration code. All clocks are now probed via devicetree.
-
-Signed-off-by: John Crispin <[email protected]>
----
- arch/mips/ath79/clock.c  | 56 ------------------------------------------------
- arch/mips/ath79/common.h |  3 ---
- 2 files changed, 59 deletions(-)
-
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -617,60 +617,6 @@ static void __init qca956x_clocks_init(v
- 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
- }
- 
--void __init ath79_clocks_init(void)
--{
--	const char *wdt;
--	const char *uart;
--
--	if (soc_is_ar71xx())
--		ar71xx_clocks_init(ath79_pll_base);
--	else if (soc_is_ar724x() || soc_is_ar913x())
--		ar724x_clocks_init(ath79_pll_base);
--	else if (soc_is_ar933x())
--		ar933x_clocks_init(ath79_pll_base);
--	else if (soc_is_ar934x())
--		ar934x_clocks_init(ath79_pll_base);
--	else if (soc_is_qca953x())
--		qca953x_clocks_init(ath79_pll_base);
--	else if (soc_is_qca955x())
--		qca955x_clocks_init(ath79_pll_base);
--	else if (soc_is_qca956x() || soc_is_tp9343())
--		qca956x_clocks_init(ath79_pll_base);
--	else
--		BUG();
--
--	if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) {
--		wdt = "ahb";
--		uart = "ahb";
--	} else if (soc_is_ar933x()) {
--		wdt = "ahb";
--		uart = "ref";
--	} else {
--		wdt = "ref";
--		uart = "ref";
--	}
--
--	clk_add_alias("wdt", NULL, wdt, NULL);
--	clk_add_alias("uart", NULL, uart, NULL);
--}
--
--unsigned long __init
--ath79_get_sys_clk_rate(const char *id)
--{
--	struct clk *clk;
--	unsigned long rate;
--
--	clk = clk_get(NULL, id);
--	if (IS_ERR(clk))
--		panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
--
--	rate = clk_get_rate(clk);
--	clk_put(clk);
--
--	return rate;
--}
--
--#ifdef CONFIG_OF
- static void __init ath79_clocks_init_dt(struct device_node *np)
- {
- 	struct clk *ref_clk;
-@@ -727,5 +673,3 @@ CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-p
- CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt);
- CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt);
- CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt);
--
--#endif
---- a/arch/mips/ath79/common.h
-+++ b/arch/mips/ath79/common.h
-@@ -19,9 +19,6 @@
- #define ATH79_MEM_SIZE_MIN	(2 * 1024 * 1024)
- #define ATH79_MEM_SIZE_MAX	(256 * 1024 * 1024)
- 
--void ath79_clocks_init(void);
--unsigned long ath79_get_sys_clk_rate(const char *id);
--
- void ath79_ddr_ctrl_init(void);
- 
- #endif /* __ATH79_COMMON_H */

target/linux/ath79/patches-4.19/0032-MIPS-ath79-sanitize-symbols.patch

@@ -1,93 +0,0 @@
-From 3fc8585cf76022dba7496627074d42af88c30718 Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Sat, 23 Jun 2018 15:16:55 +0200
-Subject: [PATCH 32/33] MIPS: ath79: sanitize symbols
-
-We no longer need to select which SoCs are supported as the whole arch
-code is always built. So lets drop all the SoC symbols
-
-Signed-off-by: John Crispin <[email protected]>
----
- arch/mips/Kconfig       |  2 ++
- arch/mips/ath79/Kconfig | 44 +++++---------------------------------------
- arch/mips/pci/Makefile  |  2 +-
- 3 files changed, 8 insertions(+), 40 deletions(-)
-
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -208,6 +208,8 @@ config ATH79
- 	select SYS_SUPPORTS_BIG_ENDIAN
- 	select SYS_SUPPORTS_MIPS16
- 	select SYS_SUPPORTS_ZBOOT_UART_PROM
-+	select HW_HAS_PCI
-+	select USB_ARCH_HAS_EHCI
- 	select USE_OF
- 	select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
- 	help
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -1,48 +1,14 @@
- # SPDX-License-Identifier: GPL-2.0
- if ATH79
- 
--config SOC_AR71XX
--	select HW_HAS_PCI
--	def_bool n
--
--config SOC_AR724X
--	select HW_HAS_PCI
--	select PCI_AR724X if PCI
--	def_bool n
--
--config SOC_AR913X
--	def_bool n
--
--config SOC_AR933X
--	def_bool n
--
--config SOC_AR934X
--	select HW_HAS_PCI
--	select PCI_AR724X if PCI
--	def_bool n
--
--config SOC_QCA955X
--	select HW_HAS_PCI
--	select PCI_AR724X if PCI
-+config PCI_AR71XX
-+	bool "PCI support for AR7100 type SoCs"
-+	depends on PCI
- 	def_bool n
- 
- config PCI_AR724X
--	def_bool n
--
--config ATH79_DEV_GPIO_BUTTONS
--	def_bool n
--
--config ATH79_DEV_LEDS_GPIO
--	def_bool n
--
--config ATH79_DEV_SPI
--	def_bool n
--
--config ATH79_DEV_USB
--	def_bool n
--
--config ATH79_DEV_WMAC
--	depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
-+	bool "PCI support for AR724x type SoCs"
-+	depends on PCI
- 	def_bool n
- 
- endif
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -23,7 +23,7 @@ obj-$(CONFIG_BCM63XX)		+= pci-bcm63xx.o
- 					ops-bcm63xx.o
- obj-$(CONFIG_MIPS_ALCHEMY)	+= pci-alchemy.o
- obj-$(CONFIG_PCI_AR2315)	+= pci-ar2315.o
--obj-$(CONFIG_SOC_AR71XX)	+= pci-ar71xx.o
-+obj-$(CONFIG_PCI_AR71XX)	+= pci-ar71xx.o
- obj-$(CONFIG_PCI_AR724X)	+= pci-ar724x.o
- obj-$(CONFIG_MIPS_PCI_VIRTIO)	+= pci-virtio-guest.o
- #

target/linux/ath79/patches-4.19/0033-spi-ath79-drop-pdata-support.patch

@@ -1,73 +0,0 @@
-From c4e197bbcecc7233aa9e553e7047fa50e4e1fe77 Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Mon, 25 Jun 2018 15:52:34 +0200
-Subject: [PATCH 33/33] spi: ath79: drop pdata support
-
-The target is being converted to pure OF. We can therefore drop all of the
-platform data code from the driver.
-
-Cc: [email protected]
-Acked-by: Mark Brown <[email protected]>
-Signed-off-by: John Crispin <[email protected]>
----
- arch/mips/include/asm/mach-ath79/ath79_spi_platform.h | 19 -------------------
- drivers/spi/spi-ath79.c                               |  8 --------
- 2 files changed, 27 deletions(-)
- delete mode 100644 arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
-
---- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
-+++ /dev/null
-@@ -1,19 +0,0 @@
--/*
-- *  Platform data definition for Atheros AR71XX/AR724X/AR913X SPI controller
-- *
-- *  Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
-- *
-- *  This program is free software; you can redistribute it and/or modify it
-- *  under the terms of the GNU General Public License version 2 as published
-- *  by the Free Software Foundation.
-- */
--
--#ifndef _ATH79_SPI_PLATFORM_H
--#define _ATH79_SPI_PLATFORM_H
--
--struct ath79_spi_platform_data {
--	unsigned	bus_num;
--	unsigned	num_chipselect;
--};
--
--#endif /* _ATH79_SPI_PLATFORM_H */
---- a/drivers/spi/spi-ath79.c
-+++ b/drivers/spi/spi-ath79.c
-@@ -26,7 +26,6 @@
- #include <linux/err.h>
- 
- #include <asm/mach-ath79/ar71xx_regs.h>
--#include <asm/mach-ath79/ath79_spi_platform.h>
- 
- #define DRV_NAME	"ath79-spi"
- 
-@@ -208,7 +207,6 @@ static int ath79_spi_probe(struct platfo
- {
- 	struct spi_master *master;
- 	struct ath79_spi *sp;
--	struct ath79_spi_platform_data *pdata;
- 	struct resource	*r;
- 	unsigned long rate;
- 	int ret;
-@@ -223,15 +221,9 @@ static int ath79_spi_probe(struct platfo
- 	master->dev.of_node = pdev->dev.of_node;
- 	platform_set_drvdata(pdev, sp);
- 
--	pdata = dev_get_platdata(&pdev->dev);
--
- 	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
- 	master->setup = ath79_spi_setup;
- 	master->cleanup = ath79_spi_cleanup;
--	if (pdata) {
--		master->bus_num = pdata->bus_num;
--		master->num_chipselect = pdata->num_chipselect;
--	}
- 
- 	sp->bitbang.master = master;
- 	sp->bitbang.chipselect = ath79_spi_chipselect;

target/linux/ath79/patches-4.19/0034-MIPS-ath79-ath9k-exports.patch

@@ -1,27 +0,0 @@
---- a/arch/mips/ath79/common.c
-+++ b/arch/mips/ath79/common.c
-@@ -34,11 +34,13 @@ EXPORT_SYMBOL_GPL(ath79_ddr_freq);
- 
- enum ath79_soc_type ath79_soc;
- unsigned int ath79_soc_rev;
-+EXPORT_SYMBOL_GPL(ath79_soc_rev);
- 
- void __iomem *ath79_pll_base;
- void __iomem *ath79_reset_base;
- EXPORT_SYMBOL_GPL(ath79_reset_base);
--static void __iomem *ath79_ddr_base;
-+void __iomem *ath79_ddr_base;
-+EXPORT_SYMBOL_GPL(ath79_ddr_base);
- static void __iomem *ath79_ddr_wb_flush_base;
- static void __iomem *ath79_ddr_pci_win_base;
- 
---- a/arch/mips/include/asm/mach-ath79/ath79.h
-+++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -152,6 +152,7 @@ void ath79_ddr_wb_flush(unsigned int reg
- void ath79_ddr_set_pci_windows(void);
- 
- extern void __iomem *ath79_pll_base;
-+extern void __iomem *ath79_ddr_base;
- extern void __iomem *ath79_reset_base;
- 
- static inline void ath79_pll_wr(unsigned reg, u32 val)

target/linux/ath79/patches-4.19/0036-GPIO-add-named-gpio-exports.patch

@@ -1,165 +0,0 @@
-From 4267880319bc1a2270d352e0ded6d6386242a7ef Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Tue, 12 Aug 2014 20:49:27 +0200
-Subject: [PATCH 24/53] GPIO: add named gpio exports
-
-Signed-off-by: John Crispin <[email protected]>
----
- drivers/gpio/gpiolib-of.c     |   68 +++++++++++++++++++++++++++++++++++++++++
- drivers/gpio/gpiolib-sysfs.c  |   10 +++++-
- include/asm-generic/gpio.h    |    6 ++++
- include/linux/gpio/consumer.h |    8 +++++
- 4 files changed, 91 insertions(+), 1 deletion(-)
-
---- a/drivers/gpio/gpiolib-of.c
-+++ b/drivers/gpio/gpiolib-of.c
-@@ -23,6 +23,8 @@
- #include <linux/pinctrl/pinctrl.h>
- #include <linux/slab.h>
- #include <linux/gpio/machine.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
- 
- #include "gpiolib.h"
- 
-@@ -660,3 +662,68 @@ void of_gpiochip_remove(struct gpio_chip
- 	gpiochip_remove_pin_ranges(chip);
- 	of_node_put(chip->of_node);
- }
-+
-+static struct of_device_id gpio_export_ids[] = {
-+	{ .compatible = "gpio-export" },
-+	{ /* sentinel */ }
-+};
-+
-+static int of_gpio_export_probe(struct platform_device *pdev)
-+{
-+	struct device_node *np = pdev->dev.of_node;
-+	struct device_node *cnp;
-+	u32 val;
-+	int nb = 0;
-+
-+	for_each_child_of_node(np, cnp) {
-+		const char *name = NULL;
-+		int gpio;
-+		bool dmc;
-+		int max_gpio = 1;
-+		int i;
-+
-+		of_property_read_string(cnp, "gpio-export,name", &name);
-+
-+		if (!name)
-+			max_gpio = of_gpio_count(cnp);
-+
-+		for (i = 0; i < max_gpio; i++) {
-+			unsigned flags = 0;
-+			enum of_gpio_flags of_flags;
-+
-+			gpio = of_get_gpio_flags(cnp, i, &of_flags);
-+			if (!gpio_is_valid(gpio))
-+				return gpio;
-+
-+			if (of_flags == OF_GPIO_ACTIVE_LOW)
-+				flags |= GPIOF_ACTIVE_LOW;
-+
-+			if (!of_property_read_u32(cnp, "gpio-export,output", &val))
-+				flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
-+			else
-+				flags |= GPIOF_IN;
-+
-+			if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np)))
-+				continue;
-+
-+			dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change");
-+			gpio_export_with_name(gpio, dmc, name);
-+			nb++;
-+		}
-+	}
-+
-+	dev_info(&pdev->dev, "%d gpio(s) exported\n", nb);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver gpio_export_driver = {
-+	.driver		= {
-+		.name		= "gpio-export",
-+		.owner	= THIS_MODULE,
-+		.of_match_table	= of_match_ptr(gpio_export_ids),
-+	},
-+	.probe		= of_gpio_export_probe,
-+};
-+
-+module_platform_driver(gpio_export_driver);
---- a/drivers/gpio/gpiolib-sysfs.c
-+++ b/drivers/gpio/gpiolib-sysfs.c
-@@ -568,7 +568,7 @@ static struct class gpio_class = {
-  *
-  * Returns zero on success, else an error.
-  */
--int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
-+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name)
- {
- 	struct gpio_chip	*chip;
- 	struct gpio_device	*gdev;
-@@ -630,6 +630,8 @@ int gpiod_export(struct gpio_desc *desc,
- 	offset = gpio_chip_hwgpio(desc);
- 	if (chip->names && chip->names[offset])
- 		ioname = chip->names[offset];
-+	if (name)
-+		ioname = name;
- 
- 	dev = device_create_with_groups(&gpio_class, &gdev->dev,
- 					MKDEV(0, 0), data, gpio_groups,
-@@ -651,6 +653,12 @@ err_unlock:
- 	gpiod_dbg(desc, "%s: status %d\n", __func__, status);
- 	return status;
- }
-+EXPORT_SYMBOL_GPL(__gpiod_export);
-+
-+int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
-+{
-+	return __gpiod_export(desc, direction_may_change, NULL);
-+}
- EXPORT_SYMBOL_GPL(gpiod_export);
- 
- static int match_export(struct device *dev, const void *desc)
---- a/include/asm-generic/gpio.h
-+++ b/include/asm-generic/gpio.h
-@@ -127,6 +127,12 @@ static inline int gpio_export(unsigned g
- 	return gpiod_export(gpio_to_desc(gpio), direction_may_change);
- }
- 
-+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
-+static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name)
-+{
-+	return __gpiod_export(gpio_to_desc(gpio), direction_may_change, name);
-+}
-+
- static inline int gpio_export_link(struct device *dev, const char *name,
- 				   unsigned gpio)
- {
---- a/include/linux/gpio/consumer.h
-+++ b/include/linux/gpio/consumer.h
-@@ -533,6 +533,7 @@ struct gpio_desc *devm_fwnode_get_gpiod_
- 
- #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS)
- 
-+int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
- int gpiod_export(struct gpio_desc *desc, bool direction_may_change);
- int gpiod_export_link(struct device *dev, const char *name,
- 		      struct gpio_desc *desc);
-@@ -540,6 +541,13 @@ void gpiod_unexport(struct gpio_desc *de
- 
- #else  /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */
- 
-+static inline int _gpiod_export(struct gpio_desc *desc,
-+			       bool direction_may_change,
-+			       const char *name)
-+{
-+	return -ENOSYS;
-+}
-+
- static inline int gpiod_export(struct gpio_desc *desc,
- 			       bool direction_may_change)
- {

target/linux/ath79/patches-4.19/0036-MIPS-ath79-remove-irq-code-from-pci.patch

@@ -1,139 +0,0 @@
---- a/arch/mips/pci/pci-ar71xx.c
-+++ b/arch/mips/pci/pci-ar71xx.c
-@@ -54,11 +54,9 @@
- struct ar71xx_pci_controller {
- 	struct device_node *np;
- 	void __iomem *cfg_base;
--	int irq;
- 	struct pci_controller pci_ctrl;
- 	struct resource io_res;
- 	struct resource mem_res;
--	struct irq_domain *domain;
- };
- 
- /* Byte lane enable bits */
-@@ -230,104 +228,6 @@ static struct pci_ops ar71xx_pci_ops = {
- 	.write	= ar71xx_pci_write_config,
- };
- 
--static void ar71xx_pci_irq_handler(struct irq_desc *desc)
--{
--	void __iomem *base = ath79_reset_base;
--	struct irq_chip *chip = irq_desc_get_chip(desc);
--	struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);
--	u32 pending;
--
--	chained_irq_enter(chip, desc);
--	pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
--		  __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
--
--	if (pending & AR71XX_PCI_INT_DEV0)
--		generic_handle_irq(irq_linear_revmap(apc->domain, 1));
--
--	else if (pending & AR71XX_PCI_INT_DEV1)
--		generic_handle_irq(irq_linear_revmap(apc->domain, 2));
--
--	else if (pending & AR71XX_PCI_INT_DEV2)
--		generic_handle_irq(irq_linear_revmap(apc->domain, 3));
--
--	else if (pending & AR71XX_PCI_INT_CORE)
--		generic_handle_irq(irq_linear_revmap(apc->domain, 4));
--
--	else
--		spurious_interrupt();
--	chained_irq_exit(chip, desc);
--}
--
--static void ar71xx_pci_irq_unmask(struct irq_data *d)
--{
--	struct ar71xx_pci_controller *apc;
--	unsigned int irq;
--	void __iomem *base = ath79_reset_base;
--	u32 t;
--
--	apc = irq_data_get_irq_chip_data(d);
--	irq = irq_linear_revmap(apc->domain, d->irq);
--
--	t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
--	__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
--
--	/* flush write */
--	__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
--}
--
--static void ar71xx_pci_irq_mask(struct irq_data *d)
--{
--	struct ar71xx_pci_controller *apc;
--	unsigned int irq;
--	void __iomem *base = ath79_reset_base;
--	u32 t;
--
--	apc = irq_data_get_irq_chip_data(d);
--	irq = irq_linear_revmap(apc->domain, d->irq);
--
--	t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
--	__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
--
--	/* flush write */
--	__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
--}
--
--static struct irq_chip ar71xx_pci_irq_chip = {
--	.name		= "AR71XX PCI",
--	.irq_mask	= ar71xx_pci_irq_mask,
--	.irq_unmask	= ar71xx_pci_irq_unmask,
--	.irq_mask_ack	= ar71xx_pci_irq_mask,
--};
--
--static int ar71xx_pci_irq_map(struct irq_domain *d,
--			      unsigned int irq, irq_hw_number_t hw)
--{
--	struct ar71xx_pci_controller *apc = d->host_data;
--
--	irq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq);
--	irq_set_chip_data(irq, apc);
--
--	return 0;
--}
--
--static const struct irq_domain_ops ar71xx_pci_domain_ops = {
--	.xlate = irq_domain_xlate_onecell,
--	.map = ar71xx_pci_irq_map,
--};
--
--static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
--{
--	void __iomem *base = ath79_reset_base;
--
--	__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
--	__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
--
--	apc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT,
--					    &ar71xx_pci_domain_ops, apc);
--	irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,
--					 apc);
--}
--
- static void ar71xx_pci_reset(void)
- {
- 	ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
-@@ -361,10 +261,6 @@ static int ar71xx_pci_probe(struct platf
- 	if (IS_ERR(apc->cfg_base))
- 		return PTR_ERR(apc->cfg_base);
- 
--	apc->irq = platform_get_irq(pdev, 0);
--	if (apc->irq < 0)
--		return -EINVAL;
--
- 	ar71xx_pci_reset();
- 
- 	/* setup COMMAND register */
-@@ -375,8 +271,6 @@ static int ar71xx_pci_probe(struct platf
- 	/* clear bus errors */
- 	ar71xx_pci_check_error(apc, 1);
- 
--	ar71xx_pci_irq_init(apc);
--
- 	apc->np = pdev->dev.of_node;
- 	apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
- 	apc->pci_ctrl.mem_resource = &apc->mem_res;

target/linux/ath79/patches-4.19/0037-missing-registers.patch

@@ -1,21 +0,0 @@
-commit f3ffac90bc7266b7d917616f3233f58e8c08a196
-Author: Christian Lamparter <[email protected]>
-Date:   Fri Aug 10 23:24:47 2018 +0200
-
-    ath79: gmac: add parsers for rxd(v)- and tx(d|en)-delay for AR9344
-
-    Signed-off-by: Christian Lamparter <[email protected]>
-
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -1229,6 +1229,10 @@
- #define AR934X_ETH_CFG_RDV_DELAY        BIT(16)
- #define AR934X_ETH_CFG_RDV_DELAY_MASK   0x3
- #define AR934X_ETH_CFG_RDV_DELAY_SHIFT  16
-+#define AR934X_ETH_CFG_TXD_DELAY_MASK   0x3
-+#define AR934X_ETH_CFG_TXD_DELAY_SHIFT  18
-+#define AR934X_ETH_CFG_TXE_DELAY_MASK   0x3
-+#define AR934X_ETH_CFG_TXE_DELAY_SHIFT  20
- 
- /*
-  * QCA953X GMAC Interface

target/linux/ath79/patches-4.19/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch

@@ -1,90 +0,0 @@
-From 60efe35257b063ce584968f9f80b437030ce6ba6 Mon Sep 17 00:00:00 2001
-From: David Bauer <[email protected]>
-Date: Mon, 18 Mar 2019 00:54:06 +0100
-Subject: [PATCH] MIPS: ath79: add missing QCA955x GMAC registers
-
-This adds missing GMAC register definitions for the Qualcomm Atheros
-QCA955X series MIPS SoCs.
-
-They originate from the platforms U-Boot code and the AVM FRITZ!WLAN
-Repeater 450E's GPL tarball.
-
-Signed-off-by: David Bauer <[email protected]>
----
- .../mips/include/asm/mach-ath79/ar71xx_regs.h | 54 +++++++++++++++++++
- 1 file changed, 54 insertions(+)
-
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -1249,7 +1249,12 @@
-  */
- 
- #define QCA955X_GMAC_REG_ETH_CFG	0x00
-+#define QCA955X_GMAC_REG_SGMII_RESET	0x14
- #define QCA955X_GMAC_REG_SGMII_SERDES	0x18
-+#define QCA955X_GMAC_REG_MR_AN_CONTROL	0x1c
-+#define QCA955X_GMAC_REG_MR_AN_STATUS	0x20
-+#define QCA955X_GMAC_REG_SGMII_CONFIG	0x34
-+#define QCA955X_GMAC_REG_SGMII_DEBUG	0x58
- 
- #define QCA955X_ETH_CFG_RGMII_EN	BIT(0)
- #define QCA955X_ETH_CFG_MII_GE0		BIT(1)
-@@ -1271,9 +1276,58 @@
- #define QCA955X_ETH_CFG_TXE_DELAY_MASK	0x3
- #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT	20
- 
-+#define QCA955X_SGMII_RESET_RX_CLK_N_RESET	0
-+#define QCA955X_SGMII_RESET_RX_CLK_N		BIT(0)
-+#define QCA955X_SGMII_RESET_TX_CLK_N		BIT(1)
-+#define QCA955X_SGMII_RESET_RX_125M_N		BIT(2)
-+#define QCA955X_SGMII_RESET_TX_125M_N		BIT(3)
-+#define QCA955X_SGMII_RESET_HW_RX_125M_N	BIT(4)
-+
- #define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS	BIT(15)
- #define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
- #define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
-+
-+#define QCA955X_MR_AN_CONTROL_SPEED_SEL1	BIT(6)
-+#define QCA955X_MR_AN_CONTROL_DUPLEX_MODE	BIT(8)
-+#define QCA955X_MR_AN_CONTROL_RESTART_AN	BIT(9)
-+#define QCA955X_MR_AN_CONTROL_POWER_DOWN	BIT(11)
-+#define QCA955X_MR_AN_CONTROL_AN_ENABLE		BIT(12)
-+#define QCA955X_MR_AN_CONTROL_SPEED_SEL0	BIT(13)
-+#define QCA955X_MR_AN_CONTROL_LOOPBACK		BIT(14)
-+#define QCA955X_MR_AN_CONTROL_PHY_RESET		BIT(15)
-+
-+#define QCA955X_MR_AN_STATUS_EXT_CAP		BIT(0)
-+#define QCA955X_MR_AN_STATUS_LINK_UP		BIT(2)
-+#define QCA955X_MR_AN_STATUS_AN_ABILITY		BIT(3)
-+#define QCA955X_MR_AN_STATUS_REMOTE_FAULT	BIT(4)
-+#define QCA955X_MR_AN_STATUS_AN_COMPLETE	BIT(5)
-+#define QCA955X_MR_AN_STATUS_NO_PREAMBLE	BIT(6)
-+#define QCA955X_MR_AN_STATUS_BASE_PAGE		BIT(7)
-+
-+#define QCA955X_SGMII_CONFIG_MODE_CTRL_SHIFT		0
-+#define QCA955X_SGMII_CONFIG_MODE_CTRL_MASK		0x7
-+#define QCA955X_SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE	BIT(3)
-+#define QCA955X_SGMII_CONFIG_MR_REG4_CHANGED		BIT(4)
-+#define QCA955X_SGMII_CONFIG_FORCE_SPEED		BIT(5)
-+#define QCA955X_SGMII_CONFIG_SPEED_SHIFT		6
-+#define QCA955X_SGMII_CONFIG_SPEED_MASK			0xc0
-+#define QCA955X_SGMII_CONFIG_REMOTE_PHY_LOOPBACK	BIT(8)
-+#define QCA955X_SGMII_CONFIG_NEXT_PAGE_LOADED		BIT(9)
-+#define QCA955X_SGMII_CONFIG_MDIO_ENABLE		BIT(10)
-+#define QCA955X_SGMII_CONFIG_MDIO_PULSE			BIT(11)
-+#define QCA955X_SGMII_CONFIG_MDIO_COMPLETE		BIT(12)
-+#define QCA955X_SGMII_CONFIG_PRBS_ENABLE		BIT(13)
-+#define QCA955X_SGMII_CONFIG_BERT_ENABLE		BIT(14)
-+
-+#define QCA955X_SGMII_DEBUG_TX_STATE_MASK	0xff
-+#define QCA955X_SGMII_DEBUG_TX_STATE_SHIFT	0
-+#define QCA955X_SGMII_DEBUG_RX_STATE_MASK	0xff00
-+#define QCA955X_SGMII_DEBUG_RX_STATE_SHIFT	8
-+#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_MASK	0xff0000
-+#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_SHIFT	16
-+#define QCA955X_SGMII_DEBUG_ARB_STATE_MASK	0xf000000
-+#define QCA955X_SGMII_DEBUG_ARB_STATE_SHIFT	24
-+
- /*
-  * QCA956X GMAC Interface
-  */

target/linux/ath79/patches-4.19/0038-at803x-disable-delays.patch

@@ -1,27 +0,0 @@
-Until upstream commit 6d4cd041f0af("net: phy: at803x: disable delay
-only for RGMII mode"), delays were not disabled on driver probe
-for the Atheros AR803x PHYs, although the RX delay is enabled on
-soft and hard reset.
-
-In addition, the TX delay setting is retained on soft-reset.
-
-This patch disables both delays on config init to align the behavior
-with kernel 5.1 and higher. It can be safely dropped with kernel 5.1.
-
---- a/drivers/net/phy/at803x.c
-+++ b/drivers/net/phy/at803x.c
-@@ -279,6 +279,14 @@ static int at803x_config_init(struct phy
- 	if (ret < 0)
- 		return ret;
- 
-+	/* Disable RX delay */
-+	at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
-+				AT803X_DEBUG_RX_CLK_DLY_EN, 0);
-+
-+	/* Disable TX delay */
-+	at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,
-+				AT803X_DEBUG_TX_CLK_DLY_EN, 0);
-+
- 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
- 			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
- 		ret = at803x_enable_rx_delay(phydev);

target/linux/ath79/patches-4.19/0039-MIPS-ath79-export-UART1-reference-clock.patch

@@ -1,52 +0,0 @@
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -42,6 +42,7 @@ static const char * const clk_names[ATH7
- 	[ATH79_CLK_AHB] = "ahb",
- 	[ATH79_CLK_REF] = "ref",
- 	[ATH79_CLK_MDIO] = "mdio",
-+	[ATH79_CLK_UART1] = "uart1",
- };
- 
- static const char * __init ath79_clk_name(int type)
-@@ -346,6 +347,9 @@ static void __init ar934x_clocks_init(vo
- 	if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
- 		ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
- 
-+	if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL)
-+		ath79_set_clk(ATH79_CLK_UART1, 100 * 1000 * 1000);
-+
- 	iounmap(dpll_base);
- }
- 
-@@ -651,6 +655,9 @@ static void __init ath79_clocks_init_dt(
- 	if (!clks[ATH79_CLK_MDIO])
- 		clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
- 
-+	if (!clks[ATH79_CLK_UART1])
-+		clks[ATH79_CLK_UART1] = clks[ATH79_CLK_REF];
-+
- 	if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
- 		pr_err("%pOF: could not register clk provider\n", np);
- 		goto err_iounmap;
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -351,6 +351,7 @@
- #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL	BIT(24)
- 
- #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL	BIT(6)
-+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL	BIT(7)
- 
- #define QCA953X_PLL_CPU_CONFIG_REG		0x00
- #define QCA953X_PLL_DDR_CONFIG_REG		0x04
---- a/include/dt-bindings/clock/ath79-clk.h
-+++ b/include/dt-bindings/clock/ath79-clk.h
-@@ -15,7 +15,8 @@
- #define ATH79_CLK_AHB		2
- #define ATH79_CLK_REF		3
- #define ATH79_CLK_MDIO		4
-+#define ATH79_CLK_UART1		5
- 
--#define ATH79_CLK_END		5
-+#define ATH79_CLK_END		6
- 
- #endif /* __DT_BINDINGS_ATH79_CLK_H */

target/linux/ath79/patches-4.19/004-register_gpio_driver_earlier.patch

@@ -1,18 +0,0 @@
-HACK: register the GPIO driver earlier to ensure that gpio_request calls
-from mach files succeed.
-
---- a/drivers/gpio/gpio-ath79.c
-+++ b/drivers/gpio/gpio-ath79.c
-@@ -325,7 +325,11 @@ static struct platform_driver ath79_gpio
- 	.remove = ath79_gpio_remove,
- };
- 
--module_platform_driver(ath79_gpio_driver);
-+static int __init ath79_gpio_init(void)
-+{
-+	return platform_driver_register(&ath79_gpio_driver);
-+}
-+postcore_initcall(ath79_gpio_init);
- 
- MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support");
- MODULE_LICENSE("GPL v2");

target/linux/ath79/patches-4.19/0050-v5.1-drivers-provide-devm_platform_ioremap_resource.patch

@@ -1,61 +0,0 @@
-From 7945f929f1a77a1c8887a97ca07f87626858ff42 Mon Sep 17 00:00:00 2001
-From: Bartosz Golaszewski <[email protected]>
-Date: Wed, 20 Feb 2019 11:12:39 +0000
-Subject: [PATCH] drivers: provide devm_platform_ioremap_resource()
-
-There are currently 1200+ instances of using platform_get_resource()
-and devm_ioremap_resource() together in the kernel tree.
-
-This patch wraps these two calls in a single helper. Thanks to that
-we don't have to declare a local variable for struct resource * and can
-omit the redundant argument for resource type. We also have one
-function call less.
-
-Signed-off-by: Bartosz Golaszewski <[email protected]>
-Acked-by: Greg Kroah-Hartman <[email protected]>
-Reviewed-by: Andy Shevchenko <[email protected]>
-Signed-off-by: Linus Walleij <[email protected]>
----
- drivers/base/platform.c         | 18 ++++++++++++++++++
- include/linux/platform_device.h |  3 +++
- 2 files changed, 21 insertions(+)
-
---- a/drivers/base/platform.c
-+++ b/drivers/base/platform.c
-@@ -81,6 +81,24 @@ struct resource *platform_get_resource(s
- EXPORT_SYMBOL_GPL(platform_get_resource);
- 
- /**
-+ * devm_platform_ioremap_resource - call devm_ioremap_resource() for a platform
-+ *				    device
-+ *
-+ * @pdev: platform device to use both for memory resource lookup as well as
-+ *        resource managemend
-+ * @index: resource index
-+ */
-+void __iomem *devm_platform_ioremap_resource(struct platform_device *pdev,
-+					     unsigned int index)
-+{
-+	struct resource *res;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, index);
-+	return devm_ioremap_resource(&pdev->dev, res);
-+}
-+EXPORT_SYMBOL_GPL(devm_platform_ioremap_resource);
-+
-+/**
-  * platform_get_irq - get an IRQ for a device
-  * @dev: platform device
-  * @num: IRQ number index
---- a/include/linux/platform_device.h
-+++ b/include/linux/platform_device.h
-@@ -51,6 +51,9 @@ extern struct device platform_bus;
- extern void arch_setup_pdev_archdata(struct platform_device *);
- extern struct resource *platform_get_resource(struct platform_device *,
- 					      unsigned int, unsigned int);
-+extern void __iomem *
-+devm_platform_ioremap_resource(struct platform_device *pdev,
-+			       unsigned int index);
- extern int platform_get_irq(struct platform_device *, unsigned int);
- extern int platform_irq_count(struct platform_device *);
- extern struct resource *platform_get_resource_byname(struct platform_device *,

target/linux/ath79/patches-4.19/0051-spi-add-driver-for-ar934x-spi-controller.patch

@@ -1,283 +0,0 @@
-From 7e161c423a232ef7ddf6c11b09ebe471dd5a23cf Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <[email protected]>
-Date: Wed, 5 Feb 2020 18:25:37 +0800
-Subject: [PATCH v4 1/2] spi: add driver for ar934x spi controller
-
-This patch adds driver for SPI controller found in Qualcomm Atheros
-AR934x/QCA95xx SoCs.
-This controller is a superset of the already supported qca,ar7100-spi.
-Besides the bit-bang mode in spi-ath79.c, this new controller added
-a new "shift register" mode, allowing faster spi operations.
-
-Signed-off-by: Chuanhong Guo <[email protected]>
----
- drivers/spi/Kconfig      |   7 ++
- drivers/spi/Makefile     |   1 +
- drivers/spi/spi-ar934x.c | 235 +++++++++++++++++++++++++++++++++++++++
- 3 files changed, 243 insertions(+)
- create mode 100644 drivers/spi/spi-ar934x.c
-
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -61,6 +61,13 @@ config SPI_ALTERA
- 	help
- 	  This is the driver for the Altera SPI Controller.
- 
-+config SPI_AR934X
-+	tristate "Qualcomm Atheros AR934X/QCA95XX SPI controller driver"
-+	depends on ATH79 || COMPILE_TEST
-+	help
-+	  This enables support for the SPI controller present on the
-+	  Qualcomm Atheros AR934X/QCA95XX SoCs.
-+
- config SPI_ATH79
- 	tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver"
- 	depends on ATH79 && GPIOLIB
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_LOOPBACK_TEST)		+= spi-
- 
- # SPI master controller drivers (bus)
- obj-$(CONFIG_SPI_ALTERA)		+= spi-altera.o
-+obj-$(CONFIG_SPI_AR934X)		+= spi-ar934x.o
- obj-$(CONFIG_SPI_ARMADA_3700)		+= spi-armada-3700.o
- obj-$(CONFIG_SPI_ATMEL)			+= spi-atmel.o
- obj-$(CONFIG_SPI_ATH79)			+= spi-ath79.o
---- /dev/null
-+++ b/drivers/spi/spi-ar934x.c
-@@ -0,0 +1,235 @@
-+// SPDX-License-Identifier: GPL-2.0
-+//
-+// SPI controller driver for Qualcomm Atheros AR934x/QCA95xx SoCs
-+//
-+// Copyright (C) 2020 Chuanhong Guo <[email protected]>
-+//
-+// Based on spi-mt7621.c:
-+// Copyright (C) 2011 Sergiy <[email protected]>
-+// Copyright (C) 2011-2013 Gabor Juhos <[email protected]>
-+// Copyright (C) 2014-2015 Felix Fietkau <[email protected]>
-+
-+#include <linux/clk.h>
-+#include <linux/io.h>
-+#include <linux/iopoll.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of_device.h>
-+#include <linux/spi/spi.h>
-+
-+#define DRIVER_NAME "spi-ar934x"
-+
-+#define AR934X_SPI_REG_FS		0x00
-+#define AR934X_SPI_ENABLE		BIT(0)
-+
-+#define AR934X_SPI_REG_IOC		0x08
-+#define AR934X_SPI_IOC_INITVAL		0x70000
-+
-+#define AR934X_SPI_REG_CTRL		0x04
-+#define AR934X_SPI_CLK_MASK		GENMASK(5, 0)
-+
-+#define AR934X_SPI_DATAOUT		0x10
-+
-+#define AR934X_SPI_REG_SHIFT_CTRL	0x14
-+#define AR934X_SPI_SHIFT_EN		BIT(31)
-+#define AR934X_SPI_SHIFT_CS(n)		BIT(28 + (n))
-+#define AR934X_SPI_SHIFT_TERM		26
-+#define AR934X_SPI_SHIFT_VAL(cs, term, count)			\
-+	(AR934X_SPI_SHIFT_EN | AR934X_SPI_SHIFT_CS(cs) |	\
-+	(term) << AR934X_SPI_SHIFT_TERM | (count))
-+
-+#define AR934X_SPI_DATAIN 0x18
-+
-+struct ar934x_spi {
-+	struct spi_controller *ctlr;
-+	void __iomem *base;
-+	struct clk *clk;
-+	unsigned int clk_freq;
-+};
-+
-+static inline int ar934x_spi_clk_div(struct ar934x_spi *sp, unsigned int freq)
-+{
-+	int div = DIV_ROUND_UP(sp->clk_freq, freq * 2) - 1;
-+
-+	if (div < 0)
-+		return 0;
-+	else if (div > AR934X_SPI_CLK_MASK)
-+		return -EINVAL;
-+	else
-+		return div;
-+}
-+
-+static int ar934x_spi_setup(struct spi_device *spi)
-+{
-+	struct ar934x_spi *sp = spi_controller_get_devdata(spi->master);
-+
-+	if ((spi->max_speed_hz == 0) ||
-+	    (spi->max_speed_hz > (sp->clk_freq / 2))) {
-+		spi->max_speed_hz = sp->clk_freq / 2;
-+	} else if (spi->max_speed_hz < (sp->clk_freq / 128)) {
-+		dev_err(&spi->dev, "spi clock is too low\n");
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static int ar934x_spi_transfer_one_message(struct spi_controller *master,
-+					   struct spi_message *m)
-+{
-+	struct ar934x_spi *sp = spi_controller_get_devdata(master);
-+	struct spi_transfer *t = NULL;
-+	struct spi_device *spi = m->spi;
-+	unsigned long trx_done, trx_cur;
-+	int stat = 0;
-+	u8 term = 0;
-+	int div, i;
-+	u32 reg;
-+	const u8 *tx_buf;
-+	u8 *buf;
-+
-+	m->actual_length = 0;
-+	list_for_each_entry(t, &m->transfers, transfer_list) {
-+		if (t->speed_hz)
-+			div = ar934x_spi_clk_div(sp, t->speed_hz);
-+		else
-+			div = ar934x_spi_clk_div(sp, spi->max_speed_hz);
-+		if (div < 0) {
-+			stat = -EIO;
-+			goto msg_done;
-+		}
-+
-+		reg = ioread32(sp->base + AR934X_SPI_REG_CTRL);
-+		reg &= ~AR934X_SPI_CLK_MASK;
-+		reg |= div;
-+		iowrite32(reg, sp->base + AR934X_SPI_REG_CTRL);
-+		iowrite32(0, sp->base + AR934X_SPI_DATAOUT);
-+
-+		for (trx_done = 0; trx_done < t->len; trx_done += 4) {
-+			trx_cur = t->len - trx_done;
-+			if (trx_cur > 4)
-+				trx_cur = 4;
-+			else if (list_is_last(&t->transfer_list, &m->transfers))
-+				term = 1;
-+
-+			if (t->tx_buf) {
-+				tx_buf = t->tx_buf + trx_done;
-+				reg = tx_buf[0];
-+				for (i = 1; i < trx_cur; i++)
-+					reg = reg << 8 | tx_buf[i];
-+				iowrite32(reg, sp->base + AR934X_SPI_DATAOUT);
-+			}
-+
-+			reg = AR934X_SPI_SHIFT_VAL(spi->chip_select, term,
-+						   trx_cur * 8);
-+			iowrite32(reg, sp->base + AR934X_SPI_REG_SHIFT_CTRL);
-+			stat = readl_poll_timeout(
-+				sp->base + AR934X_SPI_REG_SHIFT_CTRL, reg,
-+				!(reg & AR934X_SPI_SHIFT_EN), 0, 5);
-+			if (stat < 0)
-+				goto msg_done;
-+
-+			if (t->rx_buf) {
-+				reg = ioread32(sp->base + AR934X_SPI_DATAIN);
-+				buf = t->rx_buf + trx_done;
-+				for (i = 0; i < trx_cur; i++) {
-+					buf[trx_cur - i - 1] = reg & 0xff;
-+					reg >>= 8;
-+				}
-+			}
-+		}
-+		m->actual_length += t->len;
-+	}
-+
-+msg_done:
-+	m->status = stat;
-+	spi_finalize_current_message(master);
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id ar934x_spi_match[] = {
-+	{ .compatible = "qca,ar934x-spi" },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, ar934x_spi_match);
-+
-+static int ar934x_spi_probe(struct platform_device *pdev)
-+{
-+	struct spi_controller *ctlr;
-+	struct ar934x_spi *sp;
-+	void __iomem *base;
-+	struct clk *clk;
-+	int ret;
-+
-+	base = devm_platform_ioremap_resource(pdev, 0);
-+	if (IS_ERR(base))
-+		return PTR_ERR(base);
-+
-+	clk = devm_clk_get(&pdev->dev, NULL);
-+	if (IS_ERR(clk)) {
-+		dev_err(&pdev->dev, "failed to get clock\n");
-+		return PTR_ERR(clk);
-+	}
-+
-+	ret = clk_prepare_enable(clk);
-+	if (ret)
-+		return ret;
-+
-+	ctlr = spi_alloc_master(&pdev->dev, sizeof(*sp));
-+	if (!ctlr) {
-+		dev_info(&pdev->dev, "failed to allocate spi controller\n");
-+		return -ENOMEM;
-+	}
-+
-+	/* disable flash mapping and expose spi controller registers */
-+	iowrite32(AR934X_SPI_ENABLE, base + AR934X_SPI_REG_FS);
-+	/* restore pins to default state: CSn=1 DO=CLK=0 */
-+	iowrite32(AR934X_SPI_IOC_INITVAL, base + AR934X_SPI_REG_IOC);
-+
-+	ctlr->mode_bits = SPI_LSB_FIRST;
-+	ctlr->setup = ar934x_spi_setup;
-+	ctlr->transfer_one_message = ar934x_spi_transfer_one_message;
-+	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
-+	ctlr->dev.of_node = pdev->dev.of_node;
-+	ctlr->num_chipselect = 3;
-+
-+	dev_set_drvdata(&pdev->dev, ctlr);
-+
-+	sp = spi_controller_get_devdata(ctlr);
-+	sp->base = base;
-+	sp->clk = clk;
-+	sp->clk_freq = clk_get_rate(clk);
-+	sp->ctlr = ctlr;
-+
-+	return devm_spi_register_controller(&pdev->dev, ctlr);
-+}
-+
-+static int ar934x_spi_remove(struct platform_device *pdev)
-+{
-+	struct spi_controller *ctlr;
-+	struct ar934x_spi *sp;
-+
-+	ctlr = dev_get_drvdata(&pdev->dev);
-+	sp = spi_controller_get_devdata(ctlr);
-+
-+	clk_disable_unprepare(sp->clk);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver ar934x_spi_driver = {
-+	.driver = {
-+		.name = DRIVER_NAME,
-+		.of_match_table = ar934x_spi_match,
-+	},
-+	.probe = ar934x_spi_probe,
-+	.remove = ar934x_spi_remove,
-+};
-+
-+module_platform_driver(ar934x_spi_driver);
-+
-+MODULE_DESCRIPTION("SPI controller driver for Qualcomm Atheros AR934x/QCA95xx");
-+MODULE_AUTHOR("Chuanhong Guo <[email protected]>");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:" DRIVER_NAME);

target/linux/ath79/patches-4.19/0060-serial-ar933x_uart-set-UART_CS_-RX-TX-_READY_ORIDE.patch

@@ -1,64 +0,0 @@
-From patchwork Fri Feb  7 09:53:35 2020
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Daniel Golle <[email protected]>
-X-Patchwork-Id: 1190470
-Date: Fri, 7 Feb 2020 11:53:35 +0200
-From: Daniel Golle <[email protected]>
-To: [email protected], [email protected]
-Cc: Greg Kroah-Hartman <[email protected]>,
-        Jiri Slaby <[email protected]>,
-        Chuanhong Guo <[email protected]>,
-        Eitan Cohen <[email protected]>,
-        Ori Gofen <[email protected]>
-Subject: [PATCH] serial: ar933x_uart: set UART_CS_{RX,TX}_READY_ORIDE
-Message-ID: <[email protected]>
-MIME-Version: 1.0
-Content-Disposition: inline
-Sender: [email protected]
-Precedence: bulk
-List-ID: <linux-kernel.vger.kernel.org>
-X-Mailing-List: [email protected]
-
-On AR934x this UART is usually not initialized by the bootloader
-as it is only used as a secondary serial port while the primary
-UART is a newly introduced NS16550-compatible.
-In order to make use of the ar933x-uart on AR934x without RTS/CTS
-hardware flow control, one needs to set the
-UART_CS_{RX,TX}_READY_ORIDE bits as other than on AR933x where this
-UART is used as primary/console, the bootloader on AR934x typically
-doesn't set those bits.
-Setting them explicitely on AR933x should not do any harm, so just
-set them unconditionally.
-
-Tested-by: Chuanhong Guo <[email protected]>
-Signed-off-by: Daniel Golle <[email protected]>
----
- drivers/tty/serial/ar933x_uart.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/drivers/tty/serial/ar933x_uart.c
-+++ b/drivers/tty/serial/ar933x_uart.c
-@@ -290,6 +290,10 @@ static void ar933x_uart_set_termios(stru
- 	ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
- 		AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE);
- 
-+	/* enable RX and TX ready overide */
-+	ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
-+		AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE);
-+
- 	/* reenable the UART */
- 	ar933x_uart_rmw(up, AR933X_UART_CS_REG,
- 			AR933X_UART_CS_IF_MODE_M << AR933X_UART_CS_IF_MODE_S,
-@@ -424,6 +428,10 @@ static int ar933x_uart_startup(struct ua
- 
- 	/* enable RX and TX ready overide */
- 	ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
-+		AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE);
-+
-+	/* enable RX and TX ready overide */
-+	ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
- 		AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE);
- 
- 	/* Enable RX interrupts */

target/linux/ath79/patches-4.19/0061-tty-serial-ar933x-uart-rs485-gpio.patch

@@ -1,267 +0,0 @@
-From patchwork Fri Feb 21 21:23:31 2020
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Daniel Golle <[email protected]>
-X-Patchwork-Id: 1198835
-Date: Fri, 21 Feb 2020 22:23:31 +0100
-From: Daniel Golle <[email protected]>
-To: [email protected], [email protected]
-Cc: Greg Kroah-Hartman <[email protected]>,
- Jiri Slaby <[email protected]>, Petr =?utf-8?q?=C5=A0tetiar?= <[email protected]>,
- Chuanhong Guo <[email protected]>, Piotr Dymacz <[email protected]>
-Subject: [PATCH v2] serial: ar933x_uart: add RS485 support
-Message-ID: <[email protected]>
-MIME-Version: 1.0
-Content-Disposition: inline
-Sender: [email protected]
-Precedence: bulk
-List-ID: <linux-kernel.vger.kernel.org>
-X-Mailing-List: [email protected]
-
-Emulate half-duplex operation and use mctrl_gpio to add support for
-RS485 tranceiver with transmit/receive switch hooked to RTS GPIO line.
-This is needed to make use of the RS485 port found on Teltonika RUT955.
-
-Signed-off-by: Daniel Golle <[email protected]>
----
-v2: use bool to indicate ongoing half-duplex send, use it afterwards
-    to decide whether we've just been in a send operation.
-
- drivers/tty/serial/Kconfig       |   1 +
- drivers/tty/serial/ar933x_uart.c | 113 +++++++++++++++++++++++++++++--
- 2 files changed, 108 insertions(+), 6 deletions(-)
-
---- a/drivers/tty/serial/Kconfig
-+++ b/drivers/tty/serial/Kconfig
-@@ -1296,6 +1296,7 @@ config SERIAL_AR933X
- 	tristate "AR933X serial port support"
- 	depends on HAVE_CLK && ATH79
- 	select SERIAL_CORE
-+	select SERIAL_MCTRL_GPIO if GPIOLIB
- 	help
- 	  If you have an Atheros AR933X SOC based board and want to use the
- 	  built-in UART of the SoC, say Y to this option.
---- a/drivers/tty/serial/ar933x_uart.c
-+++ b/drivers/tty/serial/ar933x_uart.c
-@@ -13,6 +13,7 @@
- #include <linux/console.h>
- #include <linux/sysrq.h>
- #include <linux/delay.h>
-+#include <linux/gpio/consumer.h>
- #include <linux/platform_device.h>
- #include <linux/of.h>
- #include <linux/of_platform.h>
-@@ -29,6 +30,8 @@
- 
- #include <asm/mach-ath79/ar933x_uart.h>
- 
-+#include "serial_mctrl_gpio.h"
-+
- #define DRIVER_NAME "ar933x-uart"
- 
- #define AR933X_UART_MAX_SCALE	0xff
-@@ -47,6 +50,8 @@ struct ar933x_uart_port {
- 	unsigned int		min_baud;
- 	unsigned int		max_baud;
- 	struct clk		*clk;
-+	struct mctrl_gpios	*gpios;
-+	struct gpio_desc	*rts_gpiod;
- };
- 
- static inline unsigned int ar933x_uart_read(struct ar933x_uart_port *up,
-@@ -100,6 +105,18 @@ static inline void ar933x_uart_stop_tx_i
- 	ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
- }
- 
-+static inline void ar933x_uart_start_rx_interrupt(struct ar933x_uart_port *up)
-+{
-+	up->ier |= AR933X_UART_INT_RX_VALID;
-+	ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
-+}
-+
-+static inline void ar933x_uart_stop_rx_interrupt(struct ar933x_uart_port *up)
-+{
-+	up->ier &= ~AR933X_UART_INT_RX_VALID;
-+	ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
-+}
-+
- static inline void ar933x_uart_putc(struct ar933x_uart_port *up, int ch)
- {
- 	unsigned int rdata;
-@@ -125,11 +142,21 @@ static unsigned int ar933x_uart_tx_empty
- 
- static unsigned int ar933x_uart_get_mctrl(struct uart_port *port)
- {
--	return TIOCM_CAR;
-+	struct ar933x_uart_port *up =
-+		container_of(port, struct ar933x_uart_port, port);
-+	int ret = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
-+
-+	mctrl_gpio_get(up->gpios, &ret);
-+
-+	return ret;
- }
- 
- static void ar933x_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
- {
-+	struct ar933x_uart_port *up =
-+		container_of(port, struct ar933x_uart_port, port);
-+
-+	mctrl_gpio_set(up->gpios, mctrl);
- }
- 
- static void ar933x_uart_start_tx(struct uart_port *port)
-@@ -140,6 +167,37 @@ static void ar933x_uart_start_tx(struct
- 	ar933x_uart_start_tx_interrupt(up);
- }
- 
-+static void ar933x_uart_wait_tx_complete(struct ar933x_uart_port *up)
-+{
-+	unsigned int status;
-+	unsigned int timeout = 60000;
-+
-+	/* Wait up to 60ms for the character(s) to be sent. */
-+	do {
-+		status = ar933x_uart_read(up, AR933X_UART_CS_REG);
-+		if (--timeout == 0)
-+			break;
-+		udelay(1);
-+	} while (status & AR933X_UART_CS_TX_BUSY);
-+
-+	if (timeout == 0)
-+		dev_err(up->port.dev, "waiting for TX timed out\n");
-+}
-+
-+static void ar933x_uart_rx_flush(struct ar933x_uart_port *up)
-+{
-+	unsigned int status;
-+
-+	/* clear RX_VALID interrupt */
-+	ar933x_uart_write(up, AR933X_UART_INT_REG, AR933X_UART_INT_RX_VALID);
-+
-+	/* remove characters from the RX FIFO */
-+	do {
-+		ar933x_uart_write(up, AR933X_UART_DATA_REG, AR933X_UART_DATA_RX_CSR);
-+		status = ar933x_uart_read(up, AR933X_UART_DATA_REG);
-+	} while (status & AR933X_UART_DATA_RX_CSR);
-+}
-+
- static void ar933x_uart_stop_tx(struct uart_port *port)
- {
- 	struct ar933x_uart_port *up =
-@@ -153,8 +211,7 @@ static void ar933x_uart_stop_rx(struct u
- 	struct ar933x_uart_port *up =
- 		container_of(port, struct ar933x_uart_port, port);
- 
--	up->ier &= ~AR933X_UART_INT_RX_VALID;
--	ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
-+	ar933x_uart_stop_rx_interrupt(up);
- }
- 
- static void ar933x_uart_break_ctl(struct uart_port *port, int break_state)
-@@ -340,11 +397,20 @@ static void ar933x_uart_rx_chars(struct
- static void ar933x_uart_tx_chars(struct ar933x_uart_port *up)
- {
- 	struct circ_buf *xmit = &up->port.state->xmit;
-+	struct serial_rs485 *rs485conf = &up->port.rs485;
- 	int count;
-+	bool half_duplex_send = false;
- 
- 	if (uart_tx_stopped(&up->port))
- 		return;
- 
-+	if ((rs485conf->flags & SER_RS485_ENABLED) &&
-+	    (up->port.x_char || !uart_circ_empty(xmit))) {
-+		ar933x_uart_stop_rx_interrupt(up);
-+		gpiod_set_value(up->rts_gpiod, !!(rs485conf->flags & SER_RS485_RTS_ON_SEND));
-+		half_duplex_send = true;
-+	}
-+
- 	count = up->port.fifosize;
- 	do {
- 		unsigned int rdata;
-@@ -372,8 +438,14 @@ static void ar933x_uart_tx_chars(struct
- 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
- 		uart_write_wakeup(&up->port);
- 
--	if (!uart_circ_empty(xmit))
-+	if (!uart_circ_empty(xmit)) {
- 		ar933x_uart_start_tx_interrupt(up);
-+	} else if (half_duplex_send) {
-+		ar933x_uart_wait_tx_complete(up);
-+		ar933x_uart_rx_flush(up);
-+		ar933x_uart_start_rx_interrupt(up);
-+		gpiod_set_value(up->rts_gpiod, !!(rs485conf->flags & SER_RS485_RTS_AFTER_SEND));
-+	}
- }
- 
- static irqreturn_t ar933x_uart_interrupt(int irq, void *dev_id)
-@@ -435,8 +507,7 @@ static int ar933x_uart_startup(struct ua
- 		AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE);
- 
- 	/* Enable RX interrupts */
--	up->ier = AR933X_UART_INT_RX_VALID;
--	ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
-+	ar933x_uart_start_rx_interrupt(up);
- 
- 	spin_unlock_irqrestore(&up->port.lock, flags);
- 
-@@ -519,6 +590,21 @@ static const struct uart_ops ar933x_uart
- 	.verify_port	= ar933x_uart_verify_port,
- };
- 
-+static int ar933x_config_rs485(struct uart_port *port,
-+				struct serial_rs485 *rs485conf)
-+{
-+	struct ar933x_uart_port *up =
-+		container_of(port, struct ar933x_uart_port, port);
-+
-+	if ((rs485conf->flags & SER_RS485_ENABLED) &&
-+	    !up->rts_gpiod) {
-+		dev_err(port->dev, "RS485 needs rts-gpio\n");
-+		return 1;
-+	}
-+	port->rs485 = *rs485conf;
-+	return 0;
-+}
-+
- #ifdef CONFIG_SERIAL_AR933X_CONSOLE
- static struct ar933x_uart_port *
- ar933x_console_ports[CONFIG_SERIAL_AR933X_NR_UARTS];
-@@ -688,6 +774,8 @@ static int ar933x_uart_probe(struct plat
- 		goto err_disable_clk;
- 	}
- 
-+	uart_get_rs485_mode(&pdev->dev, &port->rs485);
-+
- 	port->mapbase = mem_res->start;
- 	port->line = id;
- 	port->irq = irq_res->start;
-@@ -698,6 +786,7 @@ static int ar933x_uart_probe(struct plat
- 	port->regshift = 2;
- 	port->fifosize = AR933X_UART_FIFO_SIZE;
- 	port->ops = &ar933x_uart_ops;
-+	port->rs485_config = ar933x_config_rs485;
- 
- 	baud = ar933x_uart_get_baud(port->uartclk, AR933X_UART_MAX_SCALE, 1);
- 	up->min_baud = max_t(unsigned int, baud, AR933X_UART_MIN_BAUD);
-@@ -705,6 +794,18 @@ static int ar933x_uart_probe(struct plat
- 	baud = ar933x_uart_get_baud(port->uartclk, 0, AR933X_UART_MAX_STEP);
- 	up->max_baud = min_t(unsigned int, baud, AR933X_UART_MAX_BAUD);
- 
-+	up->gpios = mctrl_gpio_init(port, 0);
-+	if (IS_ERR(up->gpios) && PTR_ERR(up->gpios) != -ENOSYS)
-+		return PTR_ERR(up->gpios);
-+
-+	up->rts_gpiod = mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS);
-+
-+	if ((port->rs485.flags & SER_RS485_ENABLED) &&
-+	    !up->rts_gpiod) {
-+		dev_err(&pdev->dev, "lacking rts-gpio, disabling RS485\n");
-+		port->rs485.flags &= ~SER_RS485_ENABLED;
-+	}
-+
- #ifdef CONFIG_SERIAL_AR933X_CONSOLE
- 	ar933x_console_ports[up->port.line] = up;
- #endif

target/linux/ath79/patches-4.19/0062-MIPS-pci-ar724x-add-QCA9550-reset-sequence.patch

@@ -1,130 +0,0 @@
-From: David Bauer <[email protected]>
-Date: Sat, 11 Apr 2020 14:03:12 +0200
-Subject: MIPS: pci-ar724x: add QCA9550 reset sequence
-
-The QCA9550 family of SoCs have a slightly different reset
-sequence compared to older chips.
-
-Normally the bootloader performs this sequence, however
-some bootloader implementation expect the operating system
-to clear the reset.
-
-Also get the resets from OF to support handling of the second
-PCIe root-complex on the QCA9558.
-
-Signed-off-by: David Bauer <[email protected]>
-
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -394,6 +394,7 @@
- #define QCA955X_PLL_CPU_CONFIG_REG		0x00
- #define QCA955X_PLL_DDR_CONFIG_REG		0x04
- #define QCA955X_PLL_CLK_CTRL_REG		0x08
-+#define QCA955X_PLL_PCIE_CONFIG_REG		0x0c
- #define QCA955X_PLL_ETH_XMII_CONTROL_REG	0x28
- #define QCA955X_PLL_ETH_SGMII_CONTROL_REG	0x48
- #define QCA955X_PLL_ETH_SGMII_SERDES_REG	0x4c
-@@ -479,6 +480,9 @@
- #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL	BIT(21)
- #define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)
- 
-+#define QCA955X_PLL_PCIE_CONFIG_PLL_PWD			BIT(30)
-+#define QCA955X_PLL_PCIE_CONFIG_PLL_BYPASS		BIT(16)
-+
- #define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB		BIT(5)
- #define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1		BIT(6)
- #define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL		BIT(7)
---- a/arch/mips/pci/pci-ar724x.c
-+++ b/arch/mips/pci/pci-ar724x.c
-@@ -11,6 +11,7 @@
- 
- #include <linux/irq.h>
- #include <linux/pci.h>
-+#include <linux/reset.h>
- #include <linux/init.h>
- #include <linux/delay.h>
- #include <linux/platform_device.h>
-@@ -58,6 +59,9 @@ struct ar724x_pci_controller {
- 	struct irq_domain *domain;
- 	struct resource io_res;
- 	struct resource mem_res;
-+
-+	struct reset_control *hc_reset;
-+	struct reset_control *phy_reset;
- };
- 
- static struct irq_chip ar724x_pci_irq_chip;
-@@ -343,18 +347,30 @@ static void ar724x_pci_hw_init(struct ar
- 	int wait = 0;
- 
- 	/* deassert PCIe host controller and PCIe PHY reset */
--	ath79_device_reset_clear(AR724X_RESET_PCIE);
--	ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
-+	reset_control_deassert(apc->hc_reset);
-+	reset_control_deassert(apc->phy_reset);
- 
--	/* remove the reset of the PCIE PLL */
--	ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
--	ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
--	ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
--
--	/* deassert bypass for the PCIE PLL */
--	ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
--	ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
--	ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
-+	if (of_device_is_compatible(apc->np, "qcom,qca9550-pci")) {
-+		/* remove the reset of the PCIE PLL */
-+		ppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG);
-+		ppl &= ~QCA955X_PLL_PCIE_CONFIG_PLL_PWD;
-+		ath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl);
-+
-+		/* deassert bypass for the PCIE PLL */
-+		ppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG);
-+		ppl &= ~QCA955X_PLL_PCIE_CONFIG_PLL_BYPASS;
-+		ath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl);
-+	} else {
-+		/* remove the reset of the PCIE PLL */
-+		ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
-+		ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
-+		ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
-+
-+		/* deassert bypass for the PCIE PLL */
-+		ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
-+		ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
-+		ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
-+	}
- 
- 	/* set PCIE Application Control to ready */
- 	app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
-@@ -402,6 +418,14 @@ static int ar724x_pci_probe(struct platf
- 	if (apc->irq < 0)
- 		return -EINVAL;
- 
-+	apc->hc_reset = devm_reset_control_get_exclusive(&pdev->dev, "hc");
-+	if (IS_ERR(apc->hc_reset))
-+		return PTR_ERR(apc->hc_reset);
-+
-+	apc->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, "phy");
-+	if (IS_ERR(apc->phy_reset))
-+		return PTR_ERR(apc->phy_reset);
-+
- 	apc->np = pdev->dev.of_node;
- 	apc->pci_controller.pci_ops = &ar724x_pci_ops;
- 	apc->pci_controller.io_resource = &apc->io_res;
-@@ -412,7 +436,7 @@ static int ar724x_pci_probe(struct platf
- 	 * Do the full PCIE Root Complex Initialization Sequence if the PCIe
- 	 * host controller is in reset.
- 	 */
--	if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
-+	if (reset_control_status(apc->hc_reset))
- 		ar724x_pci_hw_init(apc);
- 
- 	apc->link_up = ar724x_pci_check_link(apc);
-@@ -430,6 +454,7 @@ static int ar724x_pci_probe(struct platf
- 
- static const struct of_device_id ar724x_pci_ids[] = {
- 	{ .compatible = "qcom,ar7240-pci" },
-+	{ .compatible = "qcom,qca9550-pci" },
- 	{},
- };
- 

target/linux/ath79/patches-4.19/404-mtd-cybertan-trx-parser.patch

@@ -1,21 +0,0 @@
---- a/drivers/mtd/parsers/Makefile
-+++ b/drivers/mtd/parsers/Makefile
-@@ -1,3 +1,4 @@
-+obj-$(CONFIG_MTD_PARSER_CYBERTAN)	+= parser_cybertan.o
- obj-$(CONFIG_MTD_PARSER_TRX)		+= parser_trx.o
- obj-$(CONFIG_MTD_SHARPSL_PARTS)		+= sharpslpart.o
- obj-$(CONFIG_MTD_ROUTERBOOT_PARTS)		+= routerbootpart.o
---- a/drivers/mtd/parsers/Kconfig
-+++ b/drivers/mtd/parsers/Kconfig
-@@ -1,3 +1,11 @@
-+config MTD_PARSER_CYBERTAN
-+	tristate "Parser for Cybertan format partitions"
-+	depends on MTD && (ATH79 || COMPILE_TEST)
-+	help
-+	  Cybertan has a proprietory header than encompasses a Broadcom trx
-+	  header. This driver will parse the header and take care of the
-+	  special offsets that result in the extra headers.
-+
- config MTD_PARSER_TRX
- 	tristate "Parser for TRX format partitions"
- 	depends on MTD && (BCM47XX || ARCH_BCM_5301X || COMPILE_TEST)

target/linux/ath79/patches-4.19/408-mtd-redboot_partition_scan.patch

@@ -1,44 +0,0 @@
---- a/drivers/mtd/redboot.c
-+++ b/drivers/mtd/redboot.c
-@@ -76,12 +76,18 @@ static int parse_redboot_partitions(stru
- 	static char nullstring[] = "unallocated";
- #endif
- 
-+	buf = vmalloc(master->erasesize);
-+	if (!buf)
-+		return -ENOMEM;
-+
-+ restart:
- 	if ( directory < 0 ) {
- 		offset = master->size + directory * master->erasesize;
- 		while (mtd_block_isbad(master, offset)) {
- 			if (!offset) {
- 			nogood:
- 				printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n");
-+				vfree(buf);
- 				return -EIO;
- 			}
- 			offset -= master->erasesize;
-@@ -94,10 +100,6 @@ static int parse_redboot_partitions(stru
- 				goto nogood;
- 		}
- 	}
--	buf = vmalloc(master->erasesize);
--
--	if (!buf)
--		return -ENOMEM;
- 
- 	printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n",
- 	       master->name, offset);
-@@ -170,6 +172,11 @@ static int parse_redboot_partitions(stru
- 	}
- 	if (i == numslots) {
- 		/* Didn't find it */
-+		if (offset + master->erasesize < master->size) {
-+			/* not at the end of the flash yet, maybe next block :) */
-+			directory++;
-+			goto restart;
-+		}
- 		printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
- 		       master->name);
- 		ret = 0;

target/linux/ath79/patches-4.19/410-spi-ath79-Implement-the-spi_mem-interface.patch

@@ -1,68 +0,0 @@
-From 8d8cdb4a6ccee5b62cc0dc64651c3946364514dc Mon Sep 17 00:00:00 2001
-From: Luiz Angelo Daros de Luca <[email protected]>
-Date: Mon, 10 Feb 2020 16:11:27 -0300
-Subject: [PATCH] spi: ath79: Implement the spi_mem interface
-
-Signed-off-by: Luiz Angelo Daros de Luca <[email protected]>
----
- drivers/spi/spi-ath79.c | 35 +++++++++++++++++++++++++++++++++++
- 1 file changed, 35 insertions(+)
-
---- a/drivers/spi/spi-ath79.c
-+++ b/drivers/spi/spi-ath79.c
-@@ -19,6 +19,7 @@
- #include <linux/platform_device.h>
- #include <linux/io.h>
- #include <linux/spi/spi.h>
-+#include <linux/spi/spi-mem.h>
- #include <linux/spi/spi_bitbang.h>
- #include <linux/bitops.h>
- #include <linux/gpio.h>
-@@ -203,6 +204,39 @@ static u32 ath79_spi_txrx_mode0(struct s
- 	return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
- }
- 
-+static int ath79_exec_mem_op(struct spi_mem *mem,
-+                              const struct spi_mem_op *op)
-+{
-+	struct ath79_spi *sp = ath79_spidev_to_sp(mem->spi);
-+
-+	/* Ensures that reading is performed on device connected
-+	   to hardware cs0 */
-+	if (mem->spi->chip_select || gpio_is_valid(mem->spi->cs_gpio))
-+		return -ENOTSUPP;
-+
-+	/* Only use for fast-read op. */
-+	if (op->cmd.opcode != 0x0b || op->data.dir != SPI_MEM_DATA_IN ||
-+	    op->addr.nbytes != 3 || op->dummy.nbytes != 1)
-+		return -ENOTSUPP;
-+
-+	/* disable GPIO mode */
-+	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
-+
-+	memcpy_fromio(op->data.buf.in, sp->base + op->addr.val, op->data.nbytes);
-+
-+	/* enable GPIO mode */
-+	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
-+
-+	/* restore IOC register */
-+	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
-+
-+	return 0;
-+}
-+
-+static const struct spi_controller_mem_ops ath79_mem_ops = {
-+	.exec_op = ath79_exec_mem_op,
-+};
-+
- static int ath79_spi_probe(struct platform_device *pdev)
- {
- 	struct spi_master *master;
-@@ -237,6 +271,7 @@ static int ath79_spi_probe(struct platfo
- 		ret = PTR_ERR(sp->base);
- 		goto err_put_master;
- 	}
-+	master->mem_ops = &ath79_mem_ops;
- 
- 	sp->clk = devm_clk_get(&pdev->dev, "ahb");
- 	if (IS_ERR(sp->clk)) {

target/linux/ath79/patches-4.19/420-net-ar71xx_mac_driver.patch

@@ -1,28 +0,0 @@
---- a/drivers/net/ethernet/atheros/Kconfig
-+++ b/drivers/net/ethernet/atheros/Kconfig
-@@ -5,7 +5,7 @@
- config NET_VENDOR_ATHEROS
- 	bool "Atheros devices"
- 	default y
--	depends on PCI
-+	depends on (PCI || ATH79)
- 	---help---
- 	  If you have a network (Ethernet) card belonging to this class, say Y.
- 
-@@ -78,4 +78,6 @@ config ALX
- 	  To compile this driver as a module, choose M here.  The module
- 	  will be called alx.
- 
-+source drivers/net/ethernet/atheros/ag71xx/Kconfig
-+
- endif # NET_VENDOR_ATHEROS
---- a/drivers/net/ethernet/atheros/Makefile
-+++ b/drivers/net/ethernet/atheros/Makefile
-@@ -3,6 +3,7 @@
- # Makefile for the Atheros network device drivers.
- #
- 
-+obj-$(CONFIG_AG71XX) += ag71xx/
- obj-$(CONFIG_ATL1) += atlx/
- obj-$(CONFIG_ATL2) += atlx/
- obj-$(CONFIG_ATL1E) += atl1e/

target/linux/ath79/patches-4.19/425-at803x-allow-sgmii-aneg-override.patch

@@ -1,16 +0,0 @@
---- a/drivers/net/phy/at803x.c
-+++ b/drivers/net/phy/at803x.c
-@@ -391,6 +391,13 @@ static int at803x_aneg_done(struct phy_d
- 	if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) {
- 		pr_warn("803x_aneg_done: SGMII link is not ok\n");
- 		aneg_done = 0;
-+#ifdef CONFIG_OF_MDIO
-+		if (phydev->mdio.dev.of_node &&
-+				of_property_read_bool(phydev->mdio.dev.of_node,
-+				"at803x-override-sgmii-link-check")) {
-+			aneg_done = 1;
-+		}
-+#endif
- 	}
- 	/* switch back to copper page */
- 	phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL);

target/linux/ath79/patches-4.19/430-drivers-link-spi-before-mtd.patch

@@ -1,12 +0,0 @@
---- a/drivers/Makefile
-+++ b/drivers/Makefile
-@@ -80,8 +80,8 @@ obj-y				+= scsi/
- obj-y				+= nvme/
- obj-$(CONFIG_ATA)		+= ata/
- obj-$(CONFIG_TARGET_CORE)	+= target/
--obj-$(CONFIG_MTD)		+= mtd/
- obj-$(CONFIG_SPI)		+= spi/
-+obj-$(CONFIG_MTD)		+= mtd/
- obj-$(CONFIG_SPMI)		+= spmi/
- obj-$(CONFIG_HSI)		+= hsi/
- obj-$(CONFIG_SLIMBUS)		+= slimbus/

target/linux/ath79/patches-4.19/440-mtd-ar934x-nand-driver.patch

@@ -1,25 +0,0 @@
---- a/drivers/mtd/nand/raw/Kconfig
-+++ b/drivers/mtd/nand/raw/Kconfig
-@@ -561,4 +561,12 @@ config MTD_NAND_TEGRA
- 	  is supported. Extra OOB bytes when using HW ECC are currently
- 	  not supported.
- 
-+config MTD_NAND_AR934X
-+	tristate "Support for NAND controller on Qualcomm Atheros AR934x/QCA955x SoCs"
-+	depends on ATH79 || COMPILE_TEST
-+	depends on HAS_IOMEM
-+	help
-+	  Enables support for NAND controller on Qualcomm Atheros SoCs.
-+	  This controller is found on AR934x and QCA955x SoCs.
-+
- endif # MTD_NAND
---- a/drivers/mtd/nand/raw/Makefile
-+++ b/drivers/mtd/nand/raw/Makefile
-@@ -57,6 +57,7 @@ obj-$(CONFIG_MTD_NAND_BRCMNAND)		+= brcm
- obj-$(CONFIG_MTD_NAND_QCOM)		+= qcom_nandc.o
- obj-$(CONFIG_MTD_NAND_MTK)		+= mtk_ecc.o mtk_nand.o
- obj-$(CONFIG_MTD_NAND_TEGRA)		+= tegra_nand.o
-+obj-$(CONFIG_MTD_NAND_AR934X)		+= ar934x_nand.o
- 
- nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
- nand-objs += nand_amd.o

target/linux/ath79/patches-4.19/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch

@@ -1,98 +0,0 @@
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ath79/mangle-port.h
-@@ -0,0 +1,37 @@
-+/*
-+ *  Copyright (C) 2012 Gabor Juhos <[email protected]>
-+ *
-+ *  This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h
-+ *      Copyright (C) 2003, 2004 Ralf Baechle
-+ *
-+ *  This program is free software; you can redistribute it and/or modify it
-+ *  under the terms of the GNU General Public License version 2 as published
-+ *  by the Free Software Foundation.
-+ */
-+
-+#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H
-+#define __ASM_MACH_ATH79_MANGLE_PORT_H
-+
-+#ifdef CONFIG_PCI_AR71XX
-+extern unsigned long (ath79_pci_swizzle_b)(unsigned long port);
-+extern unsigned long (ath79_pci_swizzle_w)(unsigned long port);
-+#else
-+#define ath79_pci_swizzle_b(port) (port)
-+#define ath79_pci_swizzle_w(port) (port)
-+#endif
-+
-+#define __swizzle_addr_b(port)	ath79_pci_swizzle_b(port)
-+#define __swizzle_addr_w(port)	ath79_pci_swizzle_w(port)
-+#define __swizzle_addr_l(port)	(port)
-+#define __swizzle_addr_q(port)	(port)
-+
-+# define ioswabb(a, x)           (x)
-+# define __mem_ioswabb(a, x)     (x)
-+# define ioswabw(a, x)           (x)
-+# define __mem_ioswabw(a, x)     cpu_to_le16(x)
-+# define ioswabl(a, x)           (x)
-+# define __mem_ioswabl(a, x)     cpu_to_le32(x)
-+# define ioswabq(a, x)           (x)
-+# define __mem_ioswabq(a, x)     cpu_to_le64(x)
-+
-+#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */
---- a/arch/mips/pci/pci-ar71xx.c
-+++ b/arch/mips/pci/pci-ar71xx.c
-@@ -71,6 +71,45 @@ static const u32 ar71xx_pci_read_mask[8]
- 	0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0
- };
- 
-+static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port);
-+static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port);
-+
-+static inline bool ar71xx_is_pci_addr(unsigned long port)
-+{
-+	unsigned long phys = CPHYSADDR(port);
-+
-+	return (phys >= AR71XX_PCI_MEM_BASE &&
-+		phys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE);
-+}
-+
-+static unsigned long ar71xx_pci_swizzle_b(unsigned long port)
-+{
-+	return ar71xx_is_pci_addr(port) ? port ^ 3 : port;
-+}
-+
-+static unsigned long ar71xx_pci_swizzle_w(unsigned long port)
-+{
-+	return ar71xx_is_pci_addr(port) ? port ^ 2 : port;
-+}
-+
-+unsigned long ath79_pci_swizzle_b(unsigned long port)
-+{
-+	if (__ath79_pci_swizzle_b)
-+		return __ath79_pci_swizzle_b(port);
-+
-+	return port;
-+}
-+EXPORT_SYMBOL(ath79_pci_swizzle_b);
-+
-+unsigned long ath79_pci_swizzle_w(unsigned long port)
-+{
-+	if (__ath79_pci_swizzle_w)
-+		return __ath79_pci_swizzle_w(port);
-+
-+	return port;
-+}
-+EXPORT_SYMBOL(ath79_pci_swizzle_w);
-+
- static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
- {
- 	u32 t;
-@@ -279,6 +318,9 @@ static int ar71xx_pci_probe(struct platf
- 
- 	register_pci_controller(&apc->pci_ctrl);
- 
-+	__ath79_pci_swizzle_b = ar71xx_pci_swizzle_b;
-+	__ath79_pci_swizzle_w = ar71xx_pci_swizzle_w;
-+
- 	return 0;
- }
- 

target/linux/ath79/patches-4.19/700-net-phy-add-reset-controller-support.patch

@@ -1,107 +0,0 @@
-From 71dd6c0dff51b5f1fef2e9dfa6f6a948aac975f3 Mon Sep 17 00:00:00 2001
-From: David Bauer <[email protected]>
-Date: Wed, 17 Apr 2019 23:59:21 +0200
-Subject: [PATCH] net: phy: add support for reset-controller
-
-This commit adds support for PHY reset pins handled by a reset controller.
-
-Signed-off-by: David Bauer <[email protected]>
-Reviewed-by: Andrew Lunn <[email protected]>
-Signed-off-by: David S. Miller <[email protected]>
----
- drivers/net/phy/mdio_bus.c    | 27 +++++++++++++++++++++++++--
- drivers/net/phy/mdio_device.c | 13 +++++++++++--
- include/linux/mdio.h          |  1 +
- 3 files changed, 37 insertions(+), 4 deletions(-)
-
---- a/drivers/net/phy/mdio_bus.c
-+++ b/drivers/net/phy/mdio_bus.c
-@@ -29,6 +29,7 @@
- #include <linux/of_gpio.h>
- #include <linux/netdevice.h>
- #include <linux/etherdevice.h>
-+#include <linux/reset.h>
- #include <linux/skbuff.h>
- #include <linux/spinlock.h>
- #include <linux/mm.h>
-@@ -65,8 +66,23 @@ static int mdiobus_register_gpiod(struct
- 
- 	mdiodev->reset = gpiod;
- 
--	/* Assert the reset signal again */
--	mdio_device_reset(mdiodev, 1);
-+	return 0;
-+}
-+
-+static int mdiobus_register_reset(struct mdio_device *mdiodev)
-+{
-+	struct reset_control *reset = NULL;
-+
-+	if (mdiodev->dev.of_node)
-+		reset = devm_reset_control_get_exclusive(&mdiodev->dev,
-+							 "phy");
-+	if (PTR_ERR(reset) == -ENOENT ||
-+	    PTR_ERR(reset) == -ENOTSUPP)
-+		reset = NULL;
-+	else if (IS_ERR(reset))
-+		return PTR_ERR(reset);
-+
-+	mdiodev->reset_ctrl = reset;
- 
- 	return 0;
- }
-@@ -82,6 +98,13 @@ int mdiobus_register_device(struct mdio_
- 		err = mdiobus_register_gpiod(mdiodev);
- 		if (err)
- 			return err;
-+
-+		err = mdiobus_register_reset(mdiodev);
-+		if (err)
-+			return err;
-+
-+		/* Assert the reset signal */
-+		mdio_device_reset(mdiodev, 1);
- 	}
- 
- 	mdiodev->bus->mdio_map[mdiodev->addr] = mdiodev;
---- a/drivers/net/phy/mdio_device.c
-+++ b/drivers/net/phy/mdio_device.c
-@@ -21,6 +21,7 @@
- #include <linux/mii.h>
- #include <linux/module.h>
- #include <linux/phy.h>
-+#include <linux/reset.h>
- #include <linux/slab.h>
- #include <linux/string.h>
- #include <linux/unistd.h>
-@@ -121,10 +122,18 @@ void mdio_device_reset(struct mdio_devic
- {
- 	unsigned int d;
- 
--	if (!mdiodev->reset)
-+	if (!mdiodev->reset && !mdiodev->reset_ctrl)
- 		return;
- 
--	gpiod_set_value(mdiodev->reset, value);
-+	if (mdiodev->reset)
-+		gpiod_set_value(mdiodev->reset, value);
-+
-+	if (mdiodev->reset_ctrl) {
-+		if (value)
-+			reset_control_assert(mdiodev->reset_ctrl);
-+		else
-+			reset_control_deassert(mdiodev->reset_ctrl);
-+	}
- 
- 	d = value ? mdiodev->reset_assert_delay : mdiodev->reset_deassert_delay;
- 	if (d)
---- a/include/linux/mdio.h
-+++ b/include/linux/mdio.h
-@@ -40,6 +40,7 @@ struct mdio_device {
- 	int addr;
- 	int flags;
- 	struct gpio_desc *reset;
-+	struct reset_control *reset_ctrl;
- 	unsigned int reset_assert_delay;
- 	unsigned int reset_deassert_delay;
- };

target/linux/ath79/patches-4.19/701-mdio-bus-dont-use-managed-reset-controller.patch

@@ -1,44 +0,0 @@
-From 32085f25d7b68404055f3525c780142fc72e543f Mon Sep 17 00:00:00 2001
-From: David Bauer <[email protected]>
-Date: Fri, 22 Nov 2019 22:44:51 +0100
-Subject: [PATCH] mdio_bus: don't use managed reset-controller
-
-Geert Uytterhoeven reported that using devm_reset_controller_get leads
-to a WARNING when probing a reset-controlled PHY. This is because the
-device devm_reset_controller_get gets supplied is not actually the
-one being probed.
-
-Acquire an unmanaged reset-control as well as free the reset_control on
-unregister to fix this.
-
-Reported-by: Geert Uytterhoeven <[email protected]>
-CC: Andrew Lunn <[email protected]>
-Signed-off-by: David Bauer <[email protected]>
-Reviewed-by: Andrew Lunn <[email protected]>
-Signed-off-by: David S. Miller <[email protected]>
----
- drivers/net/phy/mdio_bus.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
---- a/drivers/net/phy/mdio_bus.c
-+++ b/drivers/net/phy/mdio_bus.c
-@@ -74,8 +74,8 @@ static int mdiobus_register_reset(struct
- 	struct reset_control *reset = NULL;
- 
- 	if (mdiodev->dev.of_node)
--		reset = devm_reset_control_get_exclusive(&mdiodev->dev,
--							 "phy");
-+		reset = of_reset_control_get_exclusive(mdiodev->dev.of_node,
-+						       "phy");
- 	if (PTR_ERR(reset) == -ENOENT ||
- 	    PTR_ERR(reset) == -ENOTSUPP)
- 		reset = NULL;
-@@ -118,6 +118,8 @@ int mdiobus_unregister_device(struct mdi
- 	if (mdiodev->bus->mdio_map[mdiodev->addr] != mdiodev)
- 		return -EINVAL;
- 
-+	reset_control_put(mdiodev->reset_ctrl);
-+
- 	mdiodev->bus->mdio_map[mdiodev->addr] = NULL;
- 
- 	return 0;

target/linux/ath79/patches-4.19/900-mdio_bitbang_ignore_ta_value.patch

@@ -1,32 +0,0 @@
---- a/drivers/net/phy/mdio-bitbang.c
-+++ b/drivers/net/phy/mdio-bitbang.c
-@@ -155,7 +155,7 @@ static int mdiobb_cmd_addr(struct mdiobb
- static int mdiobb_read(struct mii_bus *bus, int phy, int reg)
- {
- 	struct mdiobb_ctrl *ctrl = bus->priv;
--	int ret, i;
-+	int ret;
- 
- 	if (reg & MII_ADDR_C45) {
- 		reg = mdiobb_cmd_addr(ctrl, phy, reg);
-@@ -165,19 +165,7 @@ static int mdiobb_read(struct mii_bus *b
- 
- 	ctrl->ops->set_mdio_dir(ctrl, 0);
- 
--	/* check the turnaround bit: the PHY should be driving it to zero, if this
--	 * PHY is listed in phy_ignore_ta_mask as having broken TA, skip that
--	 */
--	if (mdiobb_get_bit(ctrl) != 0 &&
--	    !(bus->phy_ignore_ta_mask & (1 << phy))) {
--		/* PHY didn't drive TA low -- flush any bits it
--		 * may be trying to send.
--		 */
--		for (i = 0; i < 32; i++)
--			mdiobb_get_bit(ctrl);
--
--		return 0xffff;
--	}
-+	mdiobb_get_bit(ctrl);
- 
- 	ret = mdiobb_get_num(ctrl, 16);
- 	mdiobb_get_bit(ctrl);

target/linux/ath79/patches-4.19/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch

@@ -1,61 +0,0 @@
-From 66e584435ac0de6e0abeb6d7166fe4fe25d6bb73 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <[email protected]>
-Date: Tue, 16 Jun 2015 13:15:08 +0200
-Subject: [PATCH] phy/mdio-bitbang: prevent rescheduling during command
-
-It seems some phys have some maximum timings for accessing the MDIO line,
-resulting in bit errors under cpu stress. Prevent this from happening by
-disabling interrupts when sending commands.
-
-Signed-off-by: Jonas Gorski <[email protected]>
----
- drivers/net/phy/mdio-bitbang.c | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/drivers/net/phy/mdio-bitbang.c
-+++ b/drivers/net/phy/mdio-bitbang.c
-@@ -17,6 +17,7 @@
-  * kind, whether express or implied.
-  */
- 
-+#include <linux/irqflags.h>
- #include <linux/module.h>
- #include <linux/mdio-bitbang.h>
- #include <linux/types.h>
-@@ -156,7 +157,9 @@ static int mdiobb_read(struct mii_bus *b
- {
- 	struct mdiobb_ctrl *ctrl = bus->priv;
- 	int ret;
-+	unsigned long flags;
- 
-+	local_irq_save(flags);
- 	if (reg & MII_ADDR_C45) {
- 		reg = mdiobb_cmd_addr(ctrl, phy, reg);
- 		mdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg);
-@@ -169,13 +172,17 @@ static int mdiobb_read(struct mii_bus *b
- 
- 	ret = mdiobb_get_num(ctrl, 16);
- 	mdiobb_get_bit(ctrl);
-+	local_irq_restore(flags);
-+
- 	return ret;
- }
- 
- static int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val)
- {
- 	struct mdiobb_ctrl *ctrl = bus->priv;
-+	unsigned long flags;
- 
-+	local_irq_save(flags);
- 	if (reg & MII_ADDR_C45) {
- 		reg = mdiobb_cmd_addr(ctrl, phy, reg);
- 		mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, reg);
-@@ -190,6 +197,8 @@ static int mdiobb_write(struct mii_bus *
- 
- 	ctrl->ops->set_mdio_dir(ctrl, 0);
- 	mdiobb_get_bit(ctrl);
-+	local_irq_restore(flags);
-+
- 	return 0;
- }
- 

target/linux/ath79/patches-4.19/910-unaligned_access_hacks.patch

@@ -1,891 +0,0 @@
---- a/arch/mips/include/asm/checksum.h
-+++ b/arch/mips/include/asm/checksum.h
-@@ -134,26 +134,30 @@ static inline __sum16 ip_fast_csum(const
- 	const unsigned int *stop = word + ihl;
- 	unsigned int csum;
- 	int carry;
-+	unsigned int w;
- 
--	csum = word[0];
--	csum += word[1];
--	carry = (csum < word[1]);
-+	csum = net_hdr_word(word++);
-+
-+	w = net_hdr_word(word++);
-+	csum += w;
-+	carry = (csum < w);
- 	csum += carry;
- 
--	csum += word[2];
--	carry = (csum < word[2]);
-+	w = net_hdr_word(word++);
-+	csum += w;
-+	carry = (csum < w);
- 	csum += carry;
- 
--	csum += word[3];
--	carry = (csum < word[3]);
-+	w = net_hdr_word(word++);
-+	csum += w;
-+	carry = (csum < w);
- 	csum += carry;
- 
--	word += 4;
- 	do {
--		csum += *word;
--		carry = (csum < *word);
-+		w = net_hdr_word(word++);
-+		csum += w;
-+		carry = (csum < w);
- 		csum += carry;
--		word++;
- 	} while (word != stop);
- 
- 	return csum_fold(csum);
-@@ -214,73 +218,6 @@ static inline __sum16 ip_compute_csum(co
- 	return csum_fold(csum_partial(buff, len, 0));
- }
- 
--#define _HAVE_ARCH_IPV6_CSUM
--static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
--					  const struct in6_addr *daddr,
--					  __u32 len, __u8 proto,
--					  __wsum sum)
--{
--	__wsum tmp;
--
--	__asm__(
--	"	.set	push		# csum_ipv6_magic\n"
--	"	.set	noreorder	\n"
--	"	.set	noat		\n"
--	"	addu	%0, %5		# proto (long in network byte order)\n"
--	"	sltu	$1, %0, %5	\n"
--	"	addu	%0, $1		\n"
--
--	"	addu	%0, %6		# csum\n"
--	"	sltu	$1, %0, %6	\n"
--	"	lw	%1, 0(%2)	# four words source address\n"
--	"	addu	%0, $1		\n"
--	"	addu	%0, %1		\n"
--	"	sltu	$1, %0, %1	\n"
--
--	"	lw	%1, 4(%2)	\n"
--	"	addu	%0, $1		\n"
--	"	addu	%0, %1		\n"
--	"	sltu	$1, %0, %1	\n"
--
--	"	lw	%1, 8(%2)	\n"
--	"	addu	%0, $1		\n"
--	"	addu	%0, %1		\n"
--	"	sltu	$1, %0, %1	\n"
--
--	"	lw	%1, 12(%2)	\n"
--	"	addu	%0, $1		\n"
--	"	addu	%0, %1		\n"
--	"	sltu	$1, %0, %1	\n"
--
--	"	lw	%1, 0(%3)	\n"
--	"	addu	%0, $1		\n"
--	"	addu	%0, %1		\n"
--	"	sltu	$1, %0, %1	\n"
--
--	"	lw	%1, 4(%3)	\n"
--	"	addu	%0, $1		\n"
--	"	addu	%0, %1		\n"
--	"	sltu	$1, %0, %1	\n"
--
--	"	lw	%1, 8(%3)	\n"
--	"	addu	%0, $1		\n"
--	"	addu	%0, %1		\n"
--	"	sltu	$1, %0, %1	\n"
--
--	"	lw	%1, 12(%3)	\n"
--	"	addu	%0, $1		\n"
--	"	addu	%0, %1		\n"
--	"	sltu	$1, %0, %1	\n"
--
--	"	addu	%0, $1		# Add final carry\n"
--	"	.set	pop"
--	: "=&r" (sum), "=&r" (tmp)
--	: "r" (saddr), "r" (daddr),
--	  "0" (htonl(len)), "r" (htonl(proto)), "r" (sum));
--
--	return csum_fold(sum);
--}
--
- #include <asm-generic/checksum.h>
- #endif /* CONFIG_GENERIC_CSUM */
- 
---- a/include/uapi/linux/ip.h
-+++ b/include/uapi/linux/ip.h
-@@ -103,7 +103,7 @@ struct iphdr {
- 	__be32	saddr;
- 	__be32	daddr;
- 	/*The options start here. */
--};
-+} __attribute__((packed, aligned(2)));
- 
- 
- struct ip_auth_hdr {
---- a/include/uapi/linux/ipv6.h
-+++ b/include/uapi/linux/ipv6.h
-@@ -131,7 +131,7 @@ struct ipv6hdr {
- 
- 	struct	in6_addr	saddr;
- 	struct	in6_addr	daddr;
--};
-+} __attribute__((packed, aligned(2)));
- 
- 
- /* index values for the variables in ipv6_devconf */
---- a/include/uapi/linux/tcp.h
-+++ b/include/uapi/linux/tcp.h
-@@ -55,7 +55,7 @@ struct tcphdr {
- 	__be16	window;
- 	__sum16	check;
- 	__be16	urg_ptr;
--};
-+} __attribute__((packed, aligned(2)));
- 
- /*
-  *	The union cast uses a gcc extension to avoid aliasing problems
-@@ -65,7 +65,7 @@ struct tcphdr {
- union tcp_word_hdr { 
- 	struct tcphdr hdr;
- 	__be32 		  words[5];
--}; 
-+} __attribute__((packed, aligned(2)));
- 
- #define tcp_flag_word(tp) ( ((union tcp_word_hdr *)(tp))->words [3]) 
- 
---- a/include/uapi/linux/udp.h
-+++ b/include/uapi/linux/udp.h
-@@ -25,7 +25,7 @@ struct udphdr {
- 	__be16	dest;
- 	__be16	len;
- 	__sum16	check;
--};
-+} __attribute__((packed, aligned(2)));
- 
- /* UDP socket options */
- #define UDP_CORK	1	/* Never send partially complete segments */
---- a/net/netfilter/nf_conntrack_core.c
-+++ b/net/netfilter/nf_conntrack_core.c
-@@ -263,8 +263,8 @@ nf_ct_get_tuple(const struct sk_buff *sk
- 
- 	switch (l3num) {
- 	case NFPROTO_IPV4:
--		tuple->src.u3.ip = ap[0];
--		tuple->dst.u3.ip = ap[1];
-+		tuple->src.u3.ip = net_hdr_word(ap++);
-+		tuple->dst.u3.ip = net_hdr_word(ap);
- 		break;
- 	case NFPROTO_IPV6:
- 		memcpy(tuple->src.u3.ip6, ap, sizeof(tuple->src.u3.ip6));
---- a/include/uapi/linux/icmp.h
-+++ b/include/uapi/linux/icmp.h
-@@ -82,7 +82,7 @@ struct icmphdr {
- 	} frag;
- 	__u8	reserved[4];
-   } un;
--};
-+} __attribute__((packed, aligned(2)));
- 
- 
- /*
---- a/include/uapi/linux/in6.h
-+++ b/include/uapi/linux/in6.h
-@@ -43,7 +43,7 @@ struct in6_addr {
- #define s6_addr16		in6_u.u6_addr16
- #define s6_addr32		in6_u.u6_addr32
- #endif
--};
-+} __attribute__((packed, aligned(2)));
- #endif /* __UAPI_DEF_IN6_ADDR */
- 
- #if __UAPI_DEF_SOCKADDR_IN6
---- a/net/ipv6/tcp_ipv6.c
-+++ b/net/ipv6/tcp_ipv6.c
-@@ -39,6 +39,7 @@
- #include <linux/ipsec.h>
- #include <linux/times.h>
- #include <linux/slab.h>
-+#include <asm/unaligned.h>
- #include <linux/uaccess.h>
- #include <linux/ipv6.h>
- #include <linux/icmpv6.h>
-@@ -836,10 +837,10 @@ static void tcp_v6_send_response(const s
- 	topt = (__be32 *)(t1 + 1);
- 
- 	if (tsecr) {
--		*topt++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
--				(TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP);
--		*topt++ = htonl(tsval);
--		*topt++ = htonl(tsecr);
-+		put_unaligned_be32((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
-+				(TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP, topt++);
-+		put_unaligned_be32(tsval, topt++);
-+		put_unaligned_be32(tsecr, topt++);
- 	}
- 
- #ifdef CONFIG_TCP_MD5SIG
---- a/include/linux/ipv6.h
-+++ b/include/linux/ipv6.h
-@@ -6,6 +6,7 @@
- 
- #define ipv6_optlen(p)  (((p)->hdrlen+1) << 3)
- #define ipv6_authlen(p) (((p)->hdrlen+2) << 2)
-+
- /*
-  * This structure contains configuration options per IPv6 link.
-  */
---- a/net/ipv6/datagram.c
-+++ b/net/ipv6/datagram.c
-@@ -480,7 +480,7 @@ int ipv6_recv_error(struct sock *sk, str
- 				ipv6_iface_scope_id(&sin->sin6_addr,
- 						    IP6CB(skb)->iif);
- 		} else {
--			ipv6_addr_set_v4mapped(*(__be32 *)(nh + serr->addr_offset),
-+			ipv6_addr_set_v4mapped(net_hdr_word(nh + serr->addr_offset),
- 					       &sin->sin6_addr);
- 			sin->sin6_scope_id = 0;
- 		}
-@@ -830,12 +830,12 @@ int ip6_datagram_send_ctl(struct net *ne
- 			}
- 
- 			if (fl6->flowlabel&IPV6_FLOWINFO_MASK) {
--				if ((fl6->flowlabel^*(__be32 *)CMSG_DATA(cmsg))&~IPV6_FLOWINFO_MASK) {
-+				if ((fl6->flowlabel^net_hdr_word(CMSG_DATA(cmsg)))&~IPV6_FLOWINFO_MASK) {
- 					err = -EINVAL;
- 					goto exit_f;
- 				}
- 			}
--			fl6->flowlabel = IPV6_FLOWINFO_MASK & *(__be32 *)CMSG_DATA(cmsg);
-+			fl6->flowlabel = IPV6_FLOWINFO_MASK & net_hdr_word(CMSG_DATA(cmsg));
- 			break;
- 
- 		case IPV6_2292HOPOPTS:
---- a/net/ipv6/ip6_gre.c
-+++ b/net/ipv6/ip6_gre.c
-@@ -455,7 +455,7 @@ static void ip6gre_err(struct sk_buff *s
- 		return;
- 	ipv6h = (const struct ipv6hdr *)skb->data;
- 	greh = (const struct gre_base_hdr *)(skb->data + offset);
--	key = key_off ? *(__be32 *)(skb->data + key_off) : 0;
-+	key = key_off ? net_hdr_word((__be32 *)(skb->data + key_off)) : 0;
- 
- 	t = ip6gre_tunnel_lookup(skb->dev, &ipv6h->daddr, &ipv6h->saddr,
- 				 key, greh->protocol);
---- a/net/ipv6/exthdrs.c
-+++ b/net/ipv6/exthdrs.c
-@@ -756,7 +756,7 @@ static bool ipv6_hop_jumbo(struct sk_buf
- 		goto drop;
- 	}
- 
--	pkt_len = ntohl(*(__be32 *)(nh + optoff + 2));
-+	pkt_len = ntohl(net_hdr_word(nh + optoff + 2));
- 	if (pkt_len <= IPV6_MAXPLEN) {
- 		__IP6_INC_STATS(net, idev, IPSTATS_MIB_INHDRERRORS);
- 		icmpv6_param_prob(skb, ICMPV6_HDR_FIELD, optoff+2);
---- a/include/linux/types.h
-+++ b/include/linux/types.h
-@@ -230,5 +230,11 @@ struct callback_head {
- typedef void (*rcu_callback_t)(struct rcu_head *head);
- typedef void (*call_rcu_func_t)(struct rcu_head *head, rcu_callback_t func);
- 
-+struct net_hdr_word {
-+       u32 words[1];
-+} __attribute__((packed, aligned(2)));
-+
-+#define net_hdr_word(_p) (((struct net_hdr_word *) (_p))->words[0])
-+
- #endif /*  __ASSEMBLY__ */
- #endif /* _LINUX_TYPES_H */
---- a/net/ipv4/af_inet.c
-+++ b/net/ipv4/af_inet.c
-@@ -1422,8 +1422,8 @@ struct sk_buff *inet_gro_receive(struct
- 	if (unlikely(ip_fast_csum((u8 *)iph, 5)))
- 		goto out_unlock;
- 
--	id = ntohl(*(__be32 *)&iph->id);
--	flush = (u16)((ntohl(*(__be32 *)iph) ^ skb_gro_len(skb)) | (id & ~IP_DF));
-+	id = ntohl(net_hdr_word(&iph->id));
-+	flush = (u16)((ntohl(net_hdr_word(iph)) ^ skb_gro_len(skb)) | (id & ~IP_DF));
- 	id >>= 16;
- 
- 	list_for_each_entry(p, head, list) {
---- a/net/ipv4/route.c
-+++ b/net/ipv4/route.c
-@@ -449,7 +449,7 @@ static struct neighbour *ipv4_neigh_look
- 	else if (skb)
- 		pkey = &ip_hdr(skb)->daddr;
- 
--	n = __ipv4_neigh_lookup(dev, *(__force u32 *)pkey);
-+	n = __ipv4_neigh_lookup(dev, net_hdr_word(pkey));
- 	if (n)
- 		return n;
- 	return neigh_create(&arp_tbl, pkey, dev);
---- a/net/ipv4/tcp_output.c
-+++ b/net/ipv4/tcp_output.c
-@@ -447,48 +447,53 @@ static void tcp_options_write(__be32 *pt
- 	u16 options = opts->options;	/* mungable copy */
- 
- 	if (unlikely(OPTION_MD5 & options)) {
--		*ptr++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
--			       (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG);
-+		net_hdr_word(ptr++) =
-+			htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
-+			      (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG);
- 		/* overload cookie hash location */
- 		opts->hash_location = (__u8 *)ptr;
- 		ptr += 4;
- 	}
- 
- 	if (unlikely(opts->mss)) {
--		*ptr++ = htonl((TCPOPT_MSS << 24) |
--			       (TCPOLEN_MSS << 16) |
--			       opts->mss);
-+		net_hdr_word(ptr++) =
-+			htonl((TCPOPT_MSS << 24) | (TCPOLEN_MSS << 16) |
-+			      opts->mss);
- 	}
- 
- 	if (likely(OPTION_TS & options)) {
- 		if (unlikely(OPTION_SACK_ADVERTISE & options)) {
--			*ptr++ = htonl((TCPOPT_SACK_PERM << 24) |
--				       (TCPOLEN_SACK_PERM << 16) |
--				       (TCPOPT_TIMESTAMP << 8) |
--				       TCPOLEN_TIMESTAMP);
-+			net_hdr_word(ptr++) =
-+				htonl((TCPOPT_SACK_PERM << 24) |
-+				      (TCPOLEN_SACK_PERM << 16) |
-+				      (TCPOPT_TIMESTAMP << 8) |
-+				      TCPOLEN_TIMESTAMP);
- 			options &= ~OPTION_SACK_ADVERTISE;
- 		} else {
--			*ptr++ = htonl((TCPOPT_NOP << 24) |
--				       (TCPOPT_NOP << 16) |
--				       (TCPOPT_TIMESTAMP << 8) |
--				       TCPOLEN_TIMESTAMP);
-+			net_hdr_word(ptr++) =
-+				htonl((TCPOPT_NOP << 24) |
-+				      (TCPOPT_NOP << 16) |
-+				      (TCPOPT_TIMESTAMP << 8) |
-+				      TCPOLEN_TIMESTAMP);
- 		}
--		*ptr++ = htonl(opts->tsval);
--		*ptr++ = htonl(opts->tsecr);
-+		net_hdr_word(ptr++) = htonl(opts->tsval);
-+		net_hdr_word(ptr++) = htonl(opts->tsecr);
- 	}
- 
- 	if (unlikely(OPTION_SACK_ADVERTISE & options)) {
--		*ptr++ = htonl((TCPOPT_NOP << 24) |
--			       (TCPOPT_NOP << 16) |
--			       (TCPOPT_SACK_PERM << 8) |
--			       TCPOLEN_SACK_PERM);
-+		net_hdr_word(ptr++) =
-+			htonl((TCPOPT_NOP << 24) |
-+			      (TCPOPT_NOP << 16) |
-+			      (TCPOPT_SACK_PERM << 8) |
-+			      TCPOLEN_SACK_PERM);
- 	}
- 
- 	if (unlikely(OPTION_WSCALE & options)) {
--		*ptr++ = htonl((TCPOPT_NOP << 24) |
--			       (TCPOPT_WINDOW << 16) |
--			       (TCPOLEN_WINDOW << 8) |
--			       opts->ws);
-+		net_hdr_word(ptr++) =
-+			htonl((TCPOPT_NOP << 24) |
-+			      (TCPOPT_WINDOW << 16) |
-+			      (TCPOLEN_WINDOW << 8) |
-+			      opts->ws);
- 	}
- 
- 	if (unlikely(opts->num_sack_blocks)) {
-@@ -496,16 +501,17 @@ static void tcp_options_write(__be32 *pt
- 			tp->duplicate_sack : tp->selective_acks;
- 		int this_sack;
- 
--		*ptr++ = htonl((TCPOPT_NOP  << 24) |
--			       (TCPOPT_NOP  << 16) |
--			       (TCPOPT_SACK <<  8) |
--			       (TCPOLEN_SACK_BASE + (opts->num_sack_blocks *
-+		net_hdr_word(ptr++) =
-+			htonl((TCPOPT_NOP << 24) |
-+			      (TCPOPT_NOP << 16) |
-+			      (TCPOPT_SACK << 8) |
-+			      (TCPOLEN_SACK_BASE + (opts->num_sack_blocks *
- 						     TCPOLEN_SACK_PERBLOCK)));
- 
- 		for (this_sack = 0; this_sack < opts->num_sack_blocks;
- 		     ++this_sack) {
--			*ptr++ = htonl(sp[this_sack].start_seq);
--			*ptr++ = htonl(sp[this_sack].end_seq);
-+			net_hdr_word(ptr++) = htonl(sp[this_sack].start_seq);
-+			net_hdr_word(ptr++) = htonl(sp[this_sack].end_seq);
- 		}
- 
- 		tp->rx_opt.dsack = 0;
-@@ -518,13 +524,14 @@ static void tcp_options_write(__be32 *pt
- 
- 		if (foc->exp) {
- 			len = TCPOLEN_EXP_FASTOPEN_BASE + foc->len;
--			*ptr = htonl((TCPOPT_EXP << 24) | (len << 16) |
-+			net_hdr_word(ptr) =
-+				htonl((TCPOPT_EXP << 24) | (len << 16) |
- 				     TCPOPT_FASTOPEN_MAGIC);
- 			p += TCPOLEN_EXP_FASTOPEN_BASE;
- 		} else {
- 			len = TCPOLEN_FASTOPEN_BASE + foc->len;
--			*p++ = TCPOPT_FASTOPEN;
--			*p++ = len;
-+			net_hdr_word(p++) = TCPOPT_FASTOPEN;
-+			net_hdr_word(p++) = len;
- 		}
- 
- 		memcpy(p, foc->val, foc->len);
---- a/include/uapi/linux/igmp.h
-+++ b/include/uapi/linux/igmp.h
-@@ -33,7 +33,7 @@ struct igmphdr {
- 	__u8 code;		/* For newer IGMP */
- 	__sum16 csum;
- 	__be32 group;
--};
-+} __attribute__((packed, aligned(2)));
- 
- /* V3 group record types [grec_type] */
- #define IGMPV3_MODE_IS_INCLUDE		1
-@@ -49,7 +49,7 @@ struct igmpv3_grec {
- 	__be16	grec_nsrcs;
- 	__be32	grec_mca;
- 	__be32	grec_src[0];
--};
-+} __attribute__((packed, aligned(2)));
- 
- struct igmpv3_report {
- 	__u8 type;
-@@ -58,7 +58,7 @@ struct igmpv3_report {
- 	__be16 resv2;
- 	__be16 ngrec;
- 	struct igmpv3_grec grec[0];
--};
-+} __attribute__((packed, aligned(2)));
- 
- struct igmpv3_query {
- 	__u8 type;
-@@ -79,7 +79,7 @@ struct igmpv3_query {
- 	__u8 qqic;
- 	__be16 nsrcs;
- 	__be32 srcs[0];
--};
-+} __attribute__((packed, aligned(2)));
- 
- #define IGMP_HOST_MEMBERSHIP_QUERY	0x11	/* From RFC1112 */
- #define IGMP_HOST_MEMBERSHIP_REPORT	0x12	/* Ditto */
---- a/net/core/flow_dissector.c
-+++ b/net/core/flow_dissector.c
-@@ -111,7 +111,7 @@ __be32 __skb_flow_get_ports(const struct
- 		ports = __skb_header_pointer(skb, thoff + poff,
- 					     sizeof(_ports), data, hlen, &_ports);
- 		if (ports)
--			return *ports;
-+			return (__be32)net_hdr_word(ports);
- 	}
- 
- 	return 0;
---- a/include/uapi/linux/icmpv6.h
-+++ b/include/uapi/linux/icmpv6.h
-@@ -77,7 +77,7 @@ struct icmp6hdr {
- #define icmp6_addrconf_other	icmp6_dataun.u_nd_ra.other
- #define icmp6_rt_lifetime	icmp6_dataun.u_nd_ra.rt_lifetime
- #define icmp6_router_pref	icmp6_dataun.u_nd_ra.router_pref
--};
-+} __attribute__((packed, aligned(2)));
- 
- 
- #define ICMPV6_ROUTER_PREF_LOW		0x3
---- a/include/net/ndisc.h
-+++ b/include/net/ndisc.h
-@@ -89,7 +89,7 @@ struct ra_msg {
-         struct icmp6hdr		icmph;
- 	__be32			reachable_time;
- 	__be32			retrans_timer;
--};
-+} __attribute__((packed, aligned(2)));
- 
- struct rd_msg {
- 	struct icmp6hdr icmph;
-@@ -368,10 +368,10 @@ static inline u32 ndisc_hashfn(const voi
- {
- 	const u32 *p32 = pkey;
- 
--	return (((p32[0] ^ hash32_ptr(dev)) * hash_rnd[0]) +
--		(p32[1] * hash_rnd[1]) +
--		(p32[2] * hash_rnd[2]) +
--		(p32[3] * hash_rnd[3]));
-+	return (((net_hdr_word(&p32[0]) ^ hash32_ptr(dev)) * hash_rnd[0]) +
-+		(net_hdr_word(&p32[1]) * hash_rnd[1]) +
-+		(net_hdr_word(&p32[2]) * hash_rnd[2]) +
-+		(net_hdr_word(&p32[3]) * hash_rnd[3]));
- }
- 
- static inline struct neighbour *__ipv6_neigh_lookup_noref(struct net_device *dev, const void *pkey)
---- a/net/sched/cls_u32.c
-+++ b/net/sched/cls_u32.c
-@@ -165,7 +165,7 @@ next_knode:
- 			data = skb_header_pointer(skb, toff, 4, &hdata);
- 			if (!data)
- 				goto out;
--			if ((*data ^ key->val) & key->mask) {
-+			if ((net_hdr_word(data) ^ key->val) & key->mask) {
- 				n = rcu_dereference_bh(n->next);
- 				goto next_knode;
- 			}
-@@ -218,8 +218,8 @@ check_terminal:
- 						  &hdata);
- 			if (!data)
- 				goto out;
--			sel = ht->divisor & u32_hash_fold(*data, &n->sel,
--							  n->fshift);
-+			sel = ht->divisor & u32_hash_fold(net_hdr_word(data),
-+							  &n->sel, n->fshift);
- 		}
- 		if (!(n->sel.flags & (TC_U32_VAROFFSET | TC_U32_OFFSET | TC_U32_EAT)))
- 			goto next_ht;
---- a/net/ipv6/ip6_offload.c
-+++ b/net/ipv6/ip6_offload.c
-@@ -223,7 +223,7 @@ static struct sk_buff *ipv6_gro_receive(
- 			continue;
- 
- 		iph2 = (struct ipv6hdr *)(p->data + off);
--		first_word = *(__be32 *)iph ^ *(__be32 *)iph2;
-+		first_word = net_hdr_word(iph) ^ net_hdr_word(iph2);
- 
- 		/* All fields must match except length and Traffic Class.
- 		 * XXX skbs on the gro_list have all been parsed and pulled
---- a/include/net/addrconf.h
-+++ b/include/net/addrconf.h
-@@ -47,7 +47,7 @@ struct prefix_info {
- 	__be32			reserved2;
- 
- 	struct in6_addr		prefix;
--};
-+} __attribute__((packed, aligned(2)));
- 
- #include <linux/netdevice.h>
- #include <net/if_inet6.h>
---- a/include/net/inet_ecn.h
-+++ b/include/net/inet_ecn.h
-@@ -126,9 +126,9 @@ static inline int IP6_ECN_set_ce(struct
- 	if (INET_ECN_is_not_ect(ipv6_get_dsfield(iph)))
- 		return 0;
- 
--	from = *(__be32 *)iph;
-+	from = net_hdr_word(iph);
- 	to = from | htonl(INET_ECN_CE << 20);
--	*(__be32 *)iph = to;
-+	net_hdr_word(iph) = to;
- 	if (skb->ip_summed == CHECKSUM_COMPLETE)
- 		skb->csum = csum_add(csum_sub(skb->csum, (__force __wsum)from),
- 				     (__force __wsum)to);
---- a/include/net/ipv6.h
-+++ b/include/net/ipv6.h
-@@ -149,7 +149,7 @@ struct frag_hdr {
- 	__u8	reserved;
- 	__be16	frag_off;
- 	__be32	identification;
--};
-+} __attribute__((packed, aligned(2)));
- 
- #define	IP6_MF		0x0001
- #define	IP6_OFFSET	0xFFF8
-@@ -499,8 +499,8 @@ static inline void __ipv6_addr_set_half(
- 	}
- #endif
- #endif
--	addr[0] = wh;
--	addr[1] = wl;
-+	net_hdr_word(&addr[0]) = wh;
-+	net_hdr_word(&addr[1]) = wl;
- }
- 
- static inline void ipv6_addr_set(struct in6_addr *addr,
-@@ -559,6 +559,8 @@ static inline bool ipv6_prefix_equal(con
- 	const __be32 *a1 = addr1->s6_addr32;
- 	const __be32 *a2 = addr2->s6_addr32;
- 	unsigned int pdw, pbi;
-+	/* Used for last <32-bit fraction of prefix */
-+	u32 pbia1, pbia2;
- 
- 	/* check complete u32 in prefix */
- 	pdw = prefixlen >> 5;
-@@ -567,7 +569,9 @@ static inline bool ipv6_prefix_equal(con
- 
- 	/* check incomplete u32 in prefix */
- 	pbi = prefixlen & 0x1f;
--	if (pbi && ((a1[pdw] ^ a2[pdw]) & htonl((0xffffffff) << (32 - pbi))))
-+	pbia1 = net_hdr_word(&a1[pdw]);
-+	pbia2 = net_hdr_word(&a2[pdw]);
-+	if (pbi && ((pbia1 ^ pbia2) & htonl((0xffffffff) << (32 - pbi))))
- 		return false;
- 
- 	return true;
-@@ -683,13 +687,13 @@ static inline void ipv6_addr_set_v4mappe
-  */
- static inline int __ipv6_addr_diff32(const void *token1, const void *token2, int addrlen)
- {
--	const __be32 *a1 = token1, *a2 = token2;
-+	const struct in6_addr *a1 = token1, *a2 = token2;
- 	int i;
- 
- 	addrlen >>= 2;
- 
- 	for (i = 0; i < addrlen; i++) {
--		__be32 xb = a1[i] ^ a2[i];
-+		__be32 xb = a1->s6_addr32[i] ^ a2->s6_addr32[i];
- 		if (xb)
- 			return i * 32 + 31 - __fls(ntohl(xb));
- 	}
-@@ -876,17 +880,18 @@ static inline int ip6_multipath_hash_pol
- static inline void ip6_flow_hdr(struct ipv6hdr *hdr, unsigned int tclass,
- 				__be32 flowlabel)
- {
--	*(__be32 *)hdr = htonl(0x60000000 | (tclass << 20)) | flowlabel;
-+	net_hdr_word((__be32 *)hdr) =
-+		htonl(0x60000000 | (tclass << 20)) | flowlabel;
- }
- 
- static inline __be32 ip6_flowinfo(const struct ipv6hdr *hdr)
- {
--	return *(__be32 *)hdr & IPV6_FLOWINFO_MASK;
-+	return net_hdr_word((__be32 *)hdr) & IPV6_FLOWINFO_MASK;
- }
- 
- static inline __be32 ip6_flowlabel(const struct ipv6hdr *hdr)
- {
--	return *(__be32 *)hdr & IPV6_FLOWLABEL_MASK;
-+	return net_hdr_word((__be32 *)hdr) & IPV6_FLOWLABEL_MASK;
- }
- 
- static inline u8 ip6_tclass(__be32 flowinfo)
---- a/include/net/secure_seq.h
-+++ b/include/net/secure_seq.h
-@@ -3,6 +3,7 @@
- #define _NET_SECURE_SEQ
- 
- #include <linux/types.h>
-+#include <linux/in6.h>
- 
- u32 secure_ipv4_port_ephemeral(__be32 saddr, __be32 daddr, __be16 dport);
- u32 secure_ipv6_port_ephemeral(const __be32 *saddr, const __be32 *daddr,
---- a/include/uapi/linux/in.h
-+++ b/include/uapi/linux/in.h
-@@ -84,7 +84,7 @@ enum {
- /* Internet address. */
- struct in_addr {
- 	__be32	s_addr;
--};
-+} __attribute__((packed, aligned(2)));
- #endif
- 
- #define IP_TOS		1
---- a/net/ipv6/ip6_fib.c
-+++ b/net/ipv6/ip6_fib.c
-@@ -142,7 +142,7 @@ static __be32 addr_bit_set(const void *t
- 	 * See include/asm-generic/bitops/le.h.
- 	 */
- 	return (__force __be32)(1 << ((~fn_bit ^ BITOP_BE32_SWIZZLE) & 0x1f)) &
--	       addr[fn_bit >> 5];
-+	       net_hdr_word(&addr[fn_bit >> 5]);
- }
- 
- struct fib6_info *fib6_info_alloc(gfp_t gfp_flags)
---- a/net/netfilter/nf_conntrack_proto_tcp.c
-+++ b/net/netfilter/nf_conntrack_proto_tcp.c
-@@ -423,7 +423,7 @@ static void tcp_sack(const struct sk_buf
- 
- 	/* Fast path for timestamp-only option */
- 	if (length == TCPOLEN_TSTAMP_ALIGNED
--	    && *(__be32 *)ptr == htonl((TCPOPT_NOP << 24)
-+	    && net_hdr_word(ptr) == htonl((TCPOPT_NOP << 24)
- 				       | (TCPOPT_NOP << 16)
- 				       | (TCPOPT_TIMESTAMP << 8)
- 				       | TCPOLEN_TIMESTAMP))
---- a/net/xfrm/xfrm_input.c
-+++ b/net/xfrm/xfrm_input.c
-@@ -194,8 +194,8 @@ int xfrm_parse_spi(struct sk_buff *skb,
- 	if (!pskb_may_pull(skb, hlen))
- 		return -EINVAL;
- 
--	*spi = *(__be32 *)(skb_transport_header(skb) + offset);
--	*seq = *(__be32 *)(skb_transport_header(skb) + offset_seq);
-+	*spi = net_hdr_word(skb_transport_header(skb) + offset);
-+	*seq = net_hdr_word(skb_transport_header(skb) + offset_seq);
- 	return 0;
- }
- EXPORT_SYMBOL(xfrm_parse_spi);
---- a/net/ipv4/tcp_input.c
-+++ b/net/ipv4/tcp_input.c
-@@ -3907,14 +3907,16 @@ static bool tcp_parse_aligned_timestamp(
- {
- 	const __be32 *ptr = (const __be32 *)(th + 1);
- 
--	if (*ptr == htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16)
--			  | (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) {
-+	if (net_hdr_word(ptr) ==
-+	    htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
-+		  (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) {
- 		tp->rx_opt.saw_tstamp = 1;
- 		++ptr;
--		tp->rx_opt.rcv_tsval = ntohl(*ptr);
-+		tp->rx_opt.rcv_tsval = get_unaligned_be32(ptr);
- 		++ptr;
--		if (*ptr)
--			tp->rx_opt.rcv_tsecr = ntohl(*ptr) - tp->tsoffset;
-+		if (net_hdr_word(ptr))
-+			tp->rx_opt.rcv_tsecr = get_unaligned_be32(ptr) -
-+					       tp->tsoffset;
- 		else
- 			tp->rx_opt.rcv_tsecr = 0;
- 		return true;
---- a/include/uapi/linux/if_pppox.h
-+++ b/include/uapi/linux/if_pppox.h
-@@ -51,6 +51,7 @@ struct pppoe_addr {
-  */
- struct pptp_addr {
- 	__u16		call_id;
-+	__u16		pad;
- 	struct in_addr	sin_addr;
- };
- 
---- a/net/ipv6/netfilter/nf_log_ipv6.c
-+++ b/net/ipv6/netfilter/nf_log_ipv6.c
-@@ -66,9 +66,9 @@ static void dump_ipv6_packet(struct net
- 	/* Max length: 44 "LEN=65535 TC=255 HOPLIMIT=255 FLOWLBL=FFFFF " */
- 	nf_log_buf_add(m, "LEN=%zu TC=%u HOPLIMIT=%u FLOWLBL=%u ",
- 	       ntohs(ih->payload_len) + sizeof(struct ipv6hdr),
--	       (ntohl(*(__be32 *)ih) & 0x0ff00000) >> 20,
-+	       (ntohl(net_hdr_word(ih)) & 0x0ff00000) >> 20,
- 	       ih->hop_limit,
--	       (ntohl(*(__be32 *)ih) & 0x000fffff));
-+	       (ntohl(net_hdr_word(ih)) & 0x000fffff));
- 
- 	fragment = 0;
- 	ptr = ip6hoff + sizeof(struct ipv6hdr);
---- a/include/net/neighbour.h
-+++ b/include/net/neighbour.h
-@@ -266,8 +266,10 @@ static inline bool neigh_key_eq128(const
- 	const u32 *n32 = (const u32 *)n->primary_key;
- 	const u32 *p32 = pkey;
- 
--	return ((n32[0] ^ p32[0]) | (n32[1] ^ p32[1]) |
--		(n32[2] ^ p32[2]) | (n32[3] ^ p32[3])) == 0;
-+	return ((n32[0] ^ net_hdr_word(&p32[0])) |
-+		(n32[1] ^ net_hdr_word(&p32[1])) |
-+		(n32[2] ^ net_hdr_word(&p32[2])) |
-+		(n32[3] ^ net_hdr_word(&p32[3]))) == 0;
- }
- 
- static inline struct neighbour *___neigh_lookup_noref(
---- a/include/uapi/linux/netfilter_arp/arp_tables.h
-+++ b/include/uapi/linux/netfilter_arp/arp_tables.h
-@@ -70,7 +70,7 @@ struct arpt_arp {
- 	__u8 flags;
- 	/* Inverse flags */
- 	__u16 invflags;
--};
-+} __attribute__((aligned(4)));
- 
- /* Values for "flag" field in struct arpt_ip (general arp structure).
-  * No flags defined yet.
---- a/net/core/utils.c
-+++ b/net/core/utils.c
-@@ -464,8 +464,14 @@ void inet_proto_csum_replace16(__sum16 *
- 			       bool pseudohdr)
- {
- 	__be32 diff[] = {
--		~from[0], ~from[1], ~from[2], ~from[3],
--		to[0], to[1], to[2], to[3],
-+		~net_hdr_word(&from[0]),
-+		~net_hdr_word(&from[1]),
-+		~net_hdr_word(&from[2]),
-+		~net_hdr_word(&from[3]),
-+		net_hdr_word(&to[0]),
-+		net_hdr_word(&to[1]),
-+		net_hdr_word(&to[2]),
-+		net_hdr_word(&to[3]),
- 	};
- 	if (skb->ip_summed != CHECKSUM_PARTIAL) {
- 		*sum = csum_fold(csum_partial(diff, sizeof(diff),
---- a/include/linux/etherdevice.h
-+++ b/include/linux/etherdevice.h
-@@ -480,7 +480,7 @@ static inline bool is_etherdev_addr(cons
-  * @b: Pointer to Ethernet header
-  *
-  * Compare two Ethernet headers, returns 0 if equal.
-- * This assumes that the network header (i.e., IP header) is 4-byte
-+ * This assumes that the network header (i.e., IP header) is 2-byte
-  * aligned OR the platform can handle unaligned access.  This is the
-  * case for all packets coming into netif_receive_skb or similar
-  * entry points.
-@@ -503,11 +503,12 @@ static inline unsigned long compare_ethe
- 	fold |= *(unsigned long *)(a + 6) ^ *(unsigned long *)(b + 6);
- 	return fold;
- #else
--	u32 *a32 = (u32 *)((u8 *)a + 2);
--	u32 *b32 = (u32 *)((u8 *)b + 2);
-+	const u16 *a16 = a;
-+	const u16 *b16 = b;
- 
--	return (*(u16 *)a ^ *(u16 *)b) | (a32[0] ^ b32[0]) |
--	       (a32[1] ^ b32[1]) | (a32[2] ^ b32[2]);
-+	return (a16[0] ^ b16[0]) | (a16[1] ^ b16[1]) | (a16[2] ^ b16[2]) |
-+	       (a16[3] ^ b16[3]) | (a16[4] ^ b16[4]) | (a16[5] ^ b16[5]) |
-+	       (a16[6] ^ b16[6]);
- #endif
- }
- 
---- a/net/ipv4/tcp_offload.c
-+++ b/net/ipv4/tcp_offload.c
-@@ -226,7 +226,7 @@ struct sk_buff *tcp_gro_receive(struct l
- 
- 		th2 = tcp_hdr(p);
- 
--		if (*(u32 *)&th->source ^ *(u32 *)&th2->source) {
-+		if (net_hdr_word(&th->source) ^ net_hdr_word(&th2->source)) {
- 			NAPI_GRO_CB(p)->same_flow = 0;
- 			continue;
- 		}
-@@ -244,8 +244,8 @@ found:
- 		  ~(TCP_FLAG_CWR | TCP_FLAG_FIN | TCP_FLAG_PSH));
- 	flush |= (__force int)(th->ack_seq ^ th2->ack_seq);
- 	for (i = sizeof(*th); i < thlen; i += 4)
--		flush |= *(u32 *)((u8 *)th + i) ^
--			 *(u32 *)((u8 *)th2 + i);
-+		flush |= net_hdr_word((u8 *)th + i) ^
-+			 net_hdr_word((u8 *)th2 + i);
- 
- 	/* When we receive our second frame we can made a decision on if we
- 	 * continue this flow as an atomic flow with a fixed ID or if we use
---- a/net/ipv6/netfilter/ip6table_mangle.c
-+++ b/net/ipv6/netfilter/ip6table_mangle.c
-@@ -50,7 +50,7 @@ ip6t_mangle_out(struct sk_buff *skb, con
- 	hop_limit = ipv6_hdr(skb)->hop_limit;
- 
- 	/* flowlabel and prio (includes version, which shouldn't change either */
--	flowlabel = *((u_int32_t *)ipv6_hdr(skb));
-+	flowlabel = net_hdr_word(ipv6_hdr(skb));
- 
- 	ret = ip6t_do_table(skb, state, state->net->ipv6.ip6table_mangle);
- 
-@@ -59,7 +59,7 @@ ip6t_mangle_out(struct sk_buff *skb, con
- 	     !ipv6_addr_equal(&ipv6_hdr(skb)->daddr, &daddr) ||
- 	     skb->mark != mark ||
- 	     ipv6_hdr(skb)->hop_limit != hop_limit ||
--	     flowlabel != *((u_int32_t *)ipv6_hdr(skb)))) {
-+	     flowlabel != net_hdr_word(ipv6_hdr(skb)))) {
- 		err = ip6_route_me_harder(state->net, skb);
- 		if (err < 0)
- 			ret = NF_DROP_ERR(err);

target/linux/ath79/patches-4.19/920-mikrotik-rb4xx.patch

@@ -1,69 +0,0 @@
---- a/drivers/mfd/Kconfig
-+++ b/drivers/mfd/Kconfig
-@@ -1899,5 +1899,13 @@ config RAVE_SP_CORE
- 	  Select this to get support for the Supervisory Processor
- 	  device found on several devices in RAVE line of hardware.
- 
-+config MFD_RB4XX_CPLD
-+	tristate "CPLD driver for Mikrotik RB4xx series boards
-+	select MFD_CORE
-+	depends on ATH79 || COMPILE_TEST
-+	help
-+	  Enables support for the CPLD chip (NAND & GPIO) on Mikrotik
-+	  Routerboard RB4xx series.
-+
- endmenu
- endif
---- a/drivers/mfd/Makefile
-+++ b/drivers/mfd/Makefile
-@@ -241,3 +241,4 @@ obj-$(CONFIG_MFD_SC27XX_PMIC)	+= sprd-sc
- obj-$(CONFIG_RAVE_SP_CORE)	+= rave-sp.o
- obj-$(CONFIG_MFD_ROHM_BD718XX)	+= rohm-bd718x7.o
- 
-+obj-$(CONFIG_MFD_RB4XX_CPLD)	+= rb4xx-cpld.o
---- a/drivers/gpio/Kconfig
-+++ b/drivers/gpio/Kconfig
-@@ -1371,6 +1371,12 @@ config GPIO_XRA1403
- 	help
- 	  GPIO driver for EXAR XRA1403 16-bit SPI-based GPIO expander.
- 
-+config GPIO_RB4XX
-+	tristate "GPIO expander for Mikrotik RB4xx series boards"
-+	depends on MFD_RB4XX_CPLD
-+	help
-+	  GPIO driver for Mikrotik Routerboard RB4xx series.
-+
- endmenu
- 
- menu "USB GPIO expanders"
---- a/drivers/gpio/Makefile
-+++ b/drivers/gpio/Makefile
-@@ -159,3 +159,4 @@ obj-$(CONFIG_GPIO_ZEVIO)	+= gpio-zevio.o
- obj-$(CONFIG_GPIO_ZYNQ)		+= gpio-zynq.o
- obj-$(CONFIG_GPIO_ZX)		+= gpio-zx.o
- obj-$(CONFIG_GPIO_LOONGSON1)	+= gpio-loongson1.o
-+obj-$(CONFIG_GPIO_RB4XX)	+= gpio-rb4xx.o
---- a/drivers/mtd/nand/raw/Kconfig
-+++ b/drivers/mtd/nand/raw/Kconfig
-@@ -569,4 +569,11 @@ config MTD_NAND_AR934X
- 	  Enables support for NAND controller on Qualcomm Atheros SoCs.
- 	  This controller is found on AR934x and QCA955x SoCs.
- 
-+config MTD_NAND_RB4XX
-+	tristate "Support for NAND driver for Mikrotik RB4xx series boards"
-+	depends on MFD_RB4XX_CPLD
-+	help
-+	  Enables support for the NAND flash chip on Mikrotik Routerboard
-+	  RB4xx series.
-+
- endif # MTD_NAND
---- a/drivers/mtd/nand/raw/Makefile
-+++ b/drivers/mtd/nand/raw/Makefile
-@@ -58,6 +58,7 @@ obj-$(CONFIG_MTD_NAND_QCOM)		+= qcom_nan
- obj-$(CONFIG_MTD_NAND_MTK)		+= mtk_ecc.o mtk_nand.o
- obj-$(CONFIG_MTD_NAND_TEGRA)		+= tegra_nand.o
- obj-$(CONFIG_MTD_NAND_AR934X)		+= ar934x_nand.o
-+obj-$(CONFIG_MTD_NAND_RB4XX)		+= nand_rb4xx.o
- 
- nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
- nand-objs += nand_amd.o

target/linux/ath79/patches-4.19/921-serial-core-add-support-for-boot-console-with-arbitr.patch

@@ -1,54 +0,0 @@
-From 4d3c17975c7814884a721fe693b3adf5c426d759 Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <[email protected]>
-Date: Tue, 10 Nov 2015 22:18:39 +0100
-Subject: [RFC] serial: core: add support for boot console with arbitrary
- baud rates
-
-The Arduino Yun uses a baud rate of 250000 by default. The serial is
-going over the Atmel ATmega and is used to connect to this chip.
-Without this patch Linux wants to switch the console to 9600 Baud.
-
-With this patch Linux will use the configured baud rate and not a
-default one specified in uart_register_driver().
-
-Signed-off-by: Hauke Mehrtens <[email protected]>
-[rebased to 4.14, slightly reworded commit message]
-Signed-off-by: Sungbo Eo <[email protected]>
----
- drivers/tty/serial/serial_core.c | 6 +++++-
- include/linux/console.h          | 1 +
- 2 files changed, 6 insertions(+), 1 deletions(-)
-
---- a/drivers/tty/serial/serial_core.c
-+++ b/drivers/tty/serial/serial_core.c
-@@ -219,6 +219,8 @@ static int uart_port_startup(struct tty_
- 	if (retval == 0) {
- 		if (uart_console(uport) && uport->cons->cflag) {
- 			tty->termios.c_cflag = uport->cons->cflag;
-+			tty->termios.c_ospeed = uport->cons->baud;
-+			tty->termios.c_ispeed = uport->cons->baud;
- 			uport->cons->cflag = 0;
- 		}
- 		/*
-@@ -2058,8 +2060,10 @@ uart_set_options(struct uart_port *port,
- 	 * Allow the setting of the UART parameters with a NULL console
- 	 * too:
- 	 */
--	if (co)
-+	if (co) {
- 		co->cflag = termios.c_cflag;
-+		co->baud = baud;
-+	}
- 
- 	return 0;
- }
---- a/include/linux/console.h
-+++ b/include/linux/console.h
-@@ -153,6 +153,7 @@ struct console {
- 	short	flags;
- 	short	index;
- 	int	cflag;
-+	int	baud;
- 	void	*data;
- 	struct	 console *next;
- };

target/linux/bcm47xx/config-4.19

@@ -1,208 +0,0 @@
-CONFIG_ADM6996_PHY=y
-CONFIG_ARCH_BINFMT_ELF_STATE=y
-CONFIG_ARCH_CLOCKSOURCE_DATA=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
-CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_BCM47XX=y
-CONFIG_BCM47XX_BCMA=y
-CONFIG_BCM47XX_NVRAM=y
-CONFIG_BCM47XX_SPROM=y
-CONFIG_BCM47XX_SSB=y
-CONFIG_BCM47XX_WDT=y
-CONFIG_BCMA=y
-CONFIG_BCMA_BLOCKIO=y
-CONFIG_BCMA_DEBUG=y
-CONFIG_BCMA_DRIVER_GMAC_CMN=y
-CONFIG_BCMA_DRIVER_GPIO=y
-CONFIG_BCMA_DRIVER_MIPS=y
-CONFIG_BCMA_DRIVER_PCI=y
-CONFIG_BCMA_DRIVER_PCI_HOSTMODE=y
-CONFIG_BCMA_HOST_PCI=y
-CONFIG_BCMA_HOST_PCI_POSSIBLE=y
-CONFIG_BCMA_HOST_SOC=y
-CONFIG_BCMA_NFLASH=y
-CONFIG_BCMA_PFLASH=y
-CONFIG_BCMA_SFLASH=y
-# CONFIG_BGMAC_BCMA is not set
-CONFIG_BLK_MQ_PCI=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="noinitrd console=ttyS0,115200"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-# CONFIG_CPU_BMIPS is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-CONFIG_CPU_MIPS32_R1=y
-# CONFIG_CPU_MIPS32_R2 is not set
-CONFIG_CPU_MIPSR1=y
-CONFIG_CPU_MIPSR2_IRQ_VI=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_CSRC_R4K=y
-CONFIG_DMA_DIRECT_OPS=y
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y
-CONFIG_DMA_NONCOHERENT_MMAP=y
-CONFIG_DMA_NONCOHERENT_OPS=y
-# CONFIG_EARLY_PRINTK is not set
-CONFIG_FIXED_PHY=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_LIB_ASHLDI3=y
-CONFIG_GENERIC_LIB_ASHRDI3=y
-CONFIG_GENERIC_LIB_CMPDI2=y
-CONFIG_GENERIC_LIB_LSHRDI3=y
-CONFIG_GENERIC_LIB_UCMPDI2=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_WDT=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_ARCH_COMPILER_H=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_CBPF_JIT=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_COPY_THREAD_TLS=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_RSEQ=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_LEDS_GPIO_REGISTER=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MIGRATION=y
-CONFIG_MIPS=y
-CONFIG_MIPS_ASID_BITS=8
-CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_CLOCK_VSYSCALL=y
-# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
-CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_BCM47XXSFLASH=y
-CONFIG_MTD_BCM47XX_PARTS=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_BCM47XXNFLASH=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_PARSER_TRX=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NO_EXCEPT_FILL=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-# CONFIG_OF is not set
-CONFIG_PCI=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DRIVERS_LEGACY=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SRCU=y
-CONFIG_SSB=y
-CONFIG_SSB_B43_PCI_BRIDGE=y
-CONFIG_SSB_BLOCKIO=y
-CONFIG_SSB_DRIVER_EXTIF=y
-CONFIG_SSB_DRIVER_GIGE=y
-CONFIG_SSB_DRIVER_GPIO=y
-CONFIG_SSB_DRIVER_MIPS=y
-CONFIG_SSB_DRIVER_PCICORE=y
-CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
-CONFIG_SSB_EMBEDDED=y
-CONFIG_SSB_HOST_SOC=y
-CONFIG_SSB_PCICORE_HOSTMODE=y
-CONFIG_SSB_PCIHOST=y
-CONFIG_SSB_PCIHOST_POSSIBLE=y
-CONFIG_SSB_SERIAL=y
-CONFIG_SSB_SFLASH=y
-CONFIG_SSB_SPROM=y
-CONFIG_SWCONFIG=y
-CONFIG_SWCONFIG_B53=y
-# CONFIG_SWCONFIG_B53_MMAP_DRIVER is not set
-CONFIG_SWCONFIG_B53_PHY_DRIVER=y
-CONFIG_SWCONFIG_B53_PHY_FIXUP=y
-# CONFIG_SWCONFIG_B53_SRAB_DRIVER is not set
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_HAS_CPU_BMIPS=y
-CONFIG_SYS_HAS_CPU_BMIPS32_3300=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_HIGHMEM=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_SYS_SUPPORTS_ZBOOT=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TINY_SRCU=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y
-CONFIG_WATCHDOG_CORE=y

target/linux/bcm47xx/patches-4.19/031-v5.1-mips-bcm47xx-Enable-USB-power-on-Netgear-WNDR3400v2.patch

@@ -1,34 +0,0 @@
-From cdb8faa00e3fcdd0ad10add743516d616dc7d38e Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Petr=20=C5=A0tetiar?= <[email protected]>
-Date: Mon, 11 Mar 2019 22:08:22 +0100
-Subject: [PATCH] mips: bcm47xx: Enable USB power on Netgear WNDR3400v2
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Eric has reported on OpenWrt's bug tracking system[1], that he's not
-able to use USB devices on his WNDR3400v2 device after the boot, until
-he turns on GPIO #21 manually through sysfs.
-
-1. https://bugs.openwrt.org/index.php?do=details&task_id=2170
-
-Cc: Rafał Miłecki <[email protected]>
-Cc: Hauke Mehrtens <[email protected]>
-Reported-by: Eric Bohlman <[email protected]>
-Tested-by: Eric Bohlman <[email protected]>
-Signed-off-by: Petr Štetiar <[email protected]>
-Signed-off-by: Paul Burton <[email protected]>
----
- arch/mips/bcm47xx/workarounds.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/mips/bcm47xx/workarounds.c
-+++ b/arch/mips/bcm47xx/workarounds.c
-@@ -24,6 +24,7 @@ void __init bcm47xx_workarounds(void)
- 	case BCM47XX_BOARD_NETGEAR_WNR3500L:
- 		bcm47xx_workarounds_enable_usb_power(12);
- 		break;
-+	case BCM47XX_BOARD_NETGEAR_WNDR3400V2:
- 	case BCM47XX_BOARD_NETGEAR_WNDR3400_V3:
- 		bcm47xx_workarounds_enable_usb_power(21);
- 		break;

target/linux/bcm47xx/patches-4.19/032-v5.4-MIPS-BCM47XX-Add-support-for-Netgear-R6200v1.patch

@@ -1,46 +0,0 @@
---- a/arch/mips/bcm47xx/board.c
-+++ b/arch/mips/bcm47xx/board.c
-@@ -160,6 +160,7 @@ struct bcm47xx_board_type_list1 bcm47xx_
- 	{{BCM47XX_BOARD_LUXUL_XVW_P30_V1, "Luxul XVW-P30 V1"}, "luxul_xvwp30_v1"},
- 	{{BCM47XX_BOARD_LUXUL_XWR_600_V1, "Luxul XWR-600 V1"}, "luxul_xwr600_v1"},
- 	{{BCM47XX_BOARD_LUXUL_XWR_1750_V1, "Luxul XWR-1750 V1"}, "luxul_xwr1750_v1"},
-+	{{BCM47XX_BOARD_NETGEAR_R6200_V1, "Netgear R6200 V1"}, "U12H192T00_NETGEAR"},
- 	{{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"},
- 	{{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"},
- 	{{BCM47XX_BOARD_NETGEAR_WGR614_V10, "Netgear WGR614 V10"}, "U12H139T01_NETGEAR"},
---- a/arch/mips/bcm47xx/buttons.c
-+++ b/arch/mips/bcm47xx/buttons.c
-@@ -385,6 +385,13 @@ bcm47xx_buttons_motorola_wr850gv2v3[] __
- /* Netgear */
- 
- static const struct gpio_keys_button
-+bcm47xx_buttons_netgear_r6200_v1[] __initconst = {
-+	BCM47XX_GPIO_KEY(2, KEY_RFKILL),
-+	BCM47XX_GPIO_KEY(3, KEY_RESTART),
-+	BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
-+};
-+
-+static const struct gpio_keys_button
- bcm47xx_buttons_netgear_wndr3400v1[] __initconst = {
- 	BCM47XX_GPIO_KEY(4, KEY_RESTART),
- 	BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON),
-@@ -664,6 +671,9 @@ int __init bcm47xx_buttons_register(void
- 		err = bcm47xx_copy_bdata(bcm47xx_buttons_motorola_wr850gv2v3);
- 		break;
- 
-+	case BCM47XX_BOARD_NETGEAR_R6200_V1:
-+		err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_r6200_v1);
-+		break;
- 	case BCM47XX_BOARD_NETGEAR_WNDR3400V1:
- 		err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400v1);
- 		break;
---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-@@ -98,6 +98,7 @@ enum bcm47xx_board {
- 	BCM47XX_BOARD_MOTOROLA_WR850GP,
- 	BCM47XX_BOARD_MOTOROLA_WR850GV2V3,
- 
-+	BCM47XX_BOARD_NETGEAR_R6200_V1,
- 	BCM47XX_BOARD_NETGEAR_WGR614V8,
- 	BCM47XX_BOARD_NETGEAR_WGR614V9,
- 	BCM47XX_BOARD_NETGEAR_WGR614_V10,

target/linux/bcm47xx/patches-4.19/159-cpu_fixes.patch

@@ -1,510 +0,0 @@
---- a/arch/mips/include/asm/r4kcache.h
-+++ b/arch/mips/include/asm/r4kcache.h
-@@ -26,6 +26,38 @@
- extern void (*r4k_blast_dcache)(void);
- extern void (*r4k_blast_icache)(void);
- 
-+#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)
-+#include <asm/paccess.h>
-+#include <linux/ssb/ssb.h>
-+#define BCM4710_DUMMY_RREG() bcm4710_dummy_rreg()
-+
-+static inline unsigned long bcm4710_dummy_rreg(void)
-+{
-+      return *(volatile unsigned long *)(KSEG1ADDR(SSB_ENUM_BASE));
-+}
-+
-+#define BCM4710_FILL_TLB(addr) bcm4710_fill_tlb((void *)(addr))
-+
-+static inline unsigned long bcm4710_fill_tlb(void *addr)
-+{
-+      return *(unsigned long *)addr;
-+}
-+
-+#define BCM4710_PROTECTED_FILL_TLB(addr) bcm4710_protected_fill_tlb((void *)(addr))
-+
-+static inline void bcm4710_protected_fill_tlb(void *addr)
-+{
-+      unsigned long x;
-+      get_dbe(x, (unsigned long *)addr);;
-+}
-+
-+#else
-+#define BCM4710_DUMMY_RREG()
-+
-+#define BCM4710_FILL_TLB(addr)
-+#define BCM4710_PROTECTED_FILL_TLB(addr)
-+#endif
-+
- /*
-  * This macro return a properly sign-extended address suitable as base address
-  * for indexed cache operations.  Two issues here:
-@@ -99,6 +131,7 @@ static inline void flush_icache_line_ind
- static inline void flush_dcache_line_indexed(unsigned long addr)
- {
- 	__dflush_prologue
-+	BCM4710_DUMMY_RREG();
- 	cache_op(Index_Writeback_Inv_D, addr);
- 	__dflush_epilogue
- }
-@@ -126,6 +159,7 @@ static inline void flush_icache_line(uns
- static inline void flush_dcache_line(unsigned long addr)
- {
- 	__dflush_prologue
-+	BCM4710_DUMMY_RREG();
- 	cache_op(Hit_Writeback_Inv_D, addr);
- 	__dflush_epilogue
- }
-@@ -133,6 +167,7 @@ static inline void flush_dcache_line(uns
- static inline void invalidate_dcache_line(unsigned long addr)
- {
- 	__dflush_prologue
-+	BCM4710_DUMMY_RREG();
- 	cache_op(Hit_Invalidate_D, addr);
- 	__dflush_epilogue
- }
-@@ -206,6 +241,7 @@ static inline int protected_flush_icache
- #ifdef CONFIG_EVA
- 		return protected_cachee_op(Hit_Invalidate_I, addr);
- #else
-+		BCM4710_DUMMY_RREG();
- 		return protected_cache_op(Hit_Invalidate_I, addr);
- #endif
- 	}
-@@ -219,6 +255,7 @@ static inline int protected_flush_icache
-  */
- static inline int protected_writeback_dcache_line(unsigned long addr)
- {
-+	BCM4710_DUMMY_RREG();
- #ifdef CONFIG_EVA
- 	return protected_cachee_op(Hit_Writeback_Inv_D, addr);
- #else
-@@ -576,8 +613,51 @@ static inline void invalidate_tcache_pag
- 		: "r" (base),						\
- 		  "i" (op));
- 
-+static inline void blast_dcache(void)
-+{
-+	unsigned long start = KSEG0;
-+	unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
-+	unsigned long end = (start + dcache_size);
-+
-+	do {
-+		BCM4710_DUMMY_RREG();
-+		cache_op(Index_Writeback_Inv_D, start);
-+		start += current_cpu_data.dcache.linesz;
-+	} while(start < end);
-+}
-+
-+static inline void blast_dcache_page(unsigned long page)
-+{
-+	unsigned long start = page;
-+	unsigned long end = start + PAGE_SIZE;
-+
-+	BCM4710_FILL_TLB(start);
-+	do {
-+		BCM4710_DUMMY_RREG();
-+		cache_op(Hit_Writeback_Inv_D, start);
-+		start += current_cpu_data.dcache.linesz;
-+	} while(start < end);
-+}
-+
-+static inline void blast_dcache_page_indexed(unsigned long page)
-+{
-+	unsigned long start = page;
-+	unsigned long end = start + PAGE_SIZE;
-+	unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
-+	unsigned long ws_end = current_cpu_data.dcache.ways <<
-+	                       current_cpu_data.dcache.waybit;
-+	unsigned long ws, addr;
-+	for (ws = 0; ws < ws_end; ws += ws_inc) {
-+		start = page + ws;
-+		for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
-+			BCM4710_DUMMY_RREG();
-+			cache_op(Index_Writeback_Inv_D, addr);
-+		}
-+	}
-+}
-+
- /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
--#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra)	\
-+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra, war) \
- static inline void extra##blast_##pfx##cache##lsize(void)		\
- {									\
- 	unsigned long start = INDEX_BASE;				\
-@@ -589,6 +669,7 @@ static inline void extra##blast_##pfx##c
- 									\
- 	__##pfx##flush_prologue						\
- 									\
-+	war								\
- 	for (ws = 0; ws < ws_end; ws += ws_inc)				\
- 		for (addr = start; addr < end; addr += lsize * 32)	\
- 			cache##lsize##_unroll32(addr|ws, indexop);	\
-@@ -603,6 +684,7 @@ static inline void extra##blast_##pfx##c
- 									\
- 	__##pfx##flush_prologue						\
- 									\
-+	war								\
- 	do {								\
- 		cache##lsize##_unroll32(start, hitop);			\
- 		start += lsize * 32;					\
-@@ -621,6 +703,8 @@ static inline void extra##blast_##pfx##c
- 			       current_cpu_data.desc.waybit;		\
- 	unsigned long ws, addr;						\
- 									\
-+	war								\
-+									\
- 	__##pfx##flush_prologue						\
- 									\
- 	for (ws = 0; ws < ws_end; ws += ws_inc)				\
-@@ -630,26 +714,26 @@ static inline void extra##blast_##pfx##c
- 	__##pfx##flush_epilogue						\
- }
- 
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
--
--__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
--__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, , )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, , BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, , )
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, , )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, , BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_, BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, , )
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, , )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, , BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, , )
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, , )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, , )
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, , )
-+
-+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, , )
-+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, , )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, , )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, , )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, , )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, , )
- 
- #define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
- static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
-@@ -678,53 +762,23 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde
- __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
- 
- /* build blast_xxx_range, protected_blast_xxx_range */
--#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra)	\
-+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra, war, war2)	\
- static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
- 						    unsigned long end)	\
- {									\
- 	unsigned long lsize = cpu_##desc##_line_size();			\
--	unsigned long lsize_2 = lsize * 2;				\
--	unsigned long lsize_3 = lsize * 3;				\
--	unsigned long lsize_4 = lsize * 4;				\
--	unsigned long lsize_5 = lsize * 5;				\
--	unsigned long lsize_6 = lsize * 6;				\
--	unsigned long lsize_7 = lsize * 7;				\
--	unsigned long lsize_8 = lsize * 8;				\
- 	unsigned long addr = start & ~(lsize - 1);			\
--	unsigned long aend = (end + lsize - 1) & ~(lsize - 1);		\
--	int lines = (aend - addr) / lsize;				\
-+	unsigned long aend = (end - 1) & ~(lsize - 1);			\
-+	war								\
- 									\
- 	__##pfx##flush_prologue						\
- 									\
--	while (lines >= 8) {						\
--		prot##cache_op(hitop, addr);				\
--		prot##cache_op(hitop, addr + lsize);			\
--		prot##cache_op(hitop, addr + lsize_2);			\
--		prot##cache_op(hitop, addr + lsize_3);			\
--		prot##cache_op(hitop, addr + lsize_4);			\
--		prot##cache_op(hitop, addr + lsize_5);			\
--		prot##cache_op(hitop, addr + lsize_6);			\
--		prot##cache_op(hitop, addr + lsize_7);			\
--		addr += lsize_8;					\
--		lines -= 8;						\
--	}								\
--									\
--	if (lines & 0x4) {						\
--		prot##cache_op(hitop, addr);				\
--		prot##cache_op(hitop, addr + lsize);			\
--		prot##cache_op(hitop, addr + lsize_2);			\
--		prot##cache_op(hitop, addr + lsize_3);			\
--		addr += lsize_4;					\
--	}								\
--									\
--	if (lines & 0x2) {						\
--		prot##cache_op(hitop, addr);				\
--		prot##cache_op(hitop, addr + lsize);			\
--		addr += lsize_2;					\
--	}								\
--									\
--	if (lines & 0x1) {						\
-+	while (1) {							\
-+		war2							\
- 		prot##cache_op(hitop, addr);				\
-+		if (addr == aend)					\
-+			break;						\
-+		addr += lsize;						\
- 	}								\
- 									\
- 	__##pfx##flush_epilogue						\
-@@ -732,8 +786,8 @@ static inline void prot##extra##blast_##
- 
- #ifndef CONFIG_EVA
- 
--__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
--__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
-+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, , BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, , , )
- 
- #else
- 
-@@ -770,15 +824,15 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache
- __BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)
- 
- #endif
--__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
-+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, , , )
- __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
--	protected_, loongson2_)
--__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
--__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )
--__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
-+	protected_, loongson2_, , )
-+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , , BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , , , )
-+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , , , )
- /* blast_inv_dcache_range */
--__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
--__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
-+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , , , BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , , , )
- 
- /* Currently, this is very specific to Loongson-3 */
- #define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize)	\
---- a/arch/mips/include/asm/stackframe.h
-+++ b/arch/mips/include/asm/stackframe.h
-@@ -428,6 +428,10 @@
- 		eretnc
- #else
- 		.set	arch=r4000
-+#ifdef CONFIG_BCM47XX
-+		nop
-+		nop
-+#endif
- 		eret
- 		.set	mips0
- #endif
---- a/arch/mips/kernel/genex.S
-+++ b/arch/mips/kernel/genex.S
-@@ -21,6 +21,19 @@
- #include <asm/war.h>
- #include <asm/thread_info.h>
- 
-+#ifdef CONFIG_BCM47XX
-+# ifdef eret
-+#  undef eret
-+# endif
-+# define eret 					\
-+	.set push;				\
-+	.set noreorder;				\
-+	 nop; 					\
-+	 nop;					\
-+	 eret;					\
-+	.set pop;
-+#endif
-+
- 	__INIT
- 
- /*
-@@ -32,6 +45,9 @@
- NESTED(except_vec3_generic, 0, sp)
- 	.set	push
- 	.set	noat
-+#ifdef CONFIG_BCM47XX
-+	nop
-+#endif
- #if R5432_CP0_INTERRUPT_WAR
- 	mfc0	k0, CP0_INDEX
- #endif
-@@ -55,6 +71,9 @@ NESTED(except_vec3_r4000, 0, sp)
- 	.set	push
- 	.set	arch=r4000
- 	.set	noat
-+#ifdef CONFIG_BCM47XX
-+	nop
-+#endif
- 	mfc0	k1, CP0_CAUSE
- 	li	k0, 31<<2
- 	andi	k1, k1, 0x7c
---- a/arch/mips/mm/c-r4k.c
-+++ b/arch/mips/mm/c-r4k.c
-@@ -39,6 +39,9 @@
- #include <asm/dma-coherence.h>
- #include <asm/mips-cps.h>
- 
-+/* For enabling BCM4710 cache workarounds */
-+static int bcm4710 = 0;
-+
- /*
-  * Bits describing what cache ops an SMP callback function may perform.
-  *
-@@ -190,6 +193,9 @@ static void r4k_blast_dcache_user_page_s
- {
- 	unsigned long  dc_lsize = cpu_dcache_line_size();
- 
-+	if (bcm4710)
-+		r4k_blast_dcache_page = blast_dcache_page;
-+	else
- 	if (dc_lsize == 0)
- 		r4k_blast_dcache_user_page = (void *)cache_noop;
- 	else if (dc_lsize == 16)
-@@ -208,6 +214,9 @@ static void r4k_blast_dcache_page_indexe
- {
- 	unsigned long dc_lsize = cpu_dcache_line_size();
- 
-+	if (bcm4710)
-+		r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
-+	else
- 	if (dc_lsize == 0)
- 		r4k_blast_dcache_page_indexed = (void *)cache_noop;
- 	else if (dc_lsize == 16)
-@@ -227,6 +236,9 @@ static void r4k_blast_dcache_setup(void)
- {
- 	unsigned long dc_lsize = cpu_dcache_line_size();
- 
-+	if (bcm4710)
-+		r4k_blast_dcache = blast_dcache;
-+	else
- 	if (dc_lsize == 0)
- 		r4k_blast_dcache = (void *)cache_noop;
- 	else if (dc_lsize == 16)
-@@ -986,6 +998,8 @@ static void local_r4k_flush_cache_sigtra
- 	}
- 
- 	R4600_HIT_CACHEOP_WAR_IMPL;
-+	BCM4710_PROTECTED_FILL_TLB(addr);
-+	BCM4710_PROTECTED_FILL_TLB(addr + 4);
- 	if (!cpu_has_ic_fills_f_dc) {
- 		if (dc_lsize)
- 			vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1))
-@@ -1888,6 +1902,17 @@ static void coherency_setup(void)
- 	 * silly idea of putting something else there ...
- 	 */
- 	switch (current_cpu_type()) {
-+	case CPU_BMIPS3300:
-+		{
-+			u32 cm;
-+			cm = read_c0_diag();
-+			/* Enable icache */
-+			cm |= (1 << 31);
-+			/* Enable dcache */
-+			cm |= (1 << 30);
-+			write_c0_diag(cm);
-+		}
-+		break;
- 	case CPU_R4000PC:
- 	case CPU_R4000SC:
- 	case CPU_R4000MC:
-@@ -1934,6 +1959,15 @@ void r4k_cache_init(void)
- 	extern void build_copy_page(void);
- 	struct cpuinfo_mips *c = &current_cpu_data;
- 
-+	/* Check if special workarounds are required */
-+#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)
-+	if (current_cpu_data.cputype == CPU_BMIPS32 && (current_cpu_data.processor_id & 0xff) == 0) {
-+		printk("Enabling BCM4710A0 cache workarounds.\n");
-+		bcm4710 = 1;
-+	} else
-+#endif
-+		bcm4710 = 0;
-+
- 	probe_pcache();
- 	probe_vcache();
- 	setup_scache();
-@@ -2012,7 +2046,15 @@ void r4k_cache_init(void)
- 	 */
- 	local_r4k___flush_cache_all(NULL);
- 
-+#ifdef CONFIG_BCM47XX
-+	{
-+		static void (*_coherency_setup)(void);
-+		_coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
-+		_coherency_setup();
-+	}
-+#else
- 	coherency_setup();
-+#endif
- 	board_cache_error_setup = r4k_cache_error_setup;
- 
- 	/*
---- a/arch/mips/mm/tlbex.c
-+++ b/arch/mips/mm/tlbex.c
-@@ -979,6 +979,9 @@ void build_get_pgde32(u32 **p, unsigned
- 		uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
- 		uasm_i_addu(p, ptr, tmp, ptr);
- #else
-+#ifdef CONFIG_BCM47XX
-+		uasm_i_nop(p);
-+#endif
- 		UASM_i_LA_mostly(p, ptr, pgdc);
- #endif
- 		uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
-@@ -1340,6 +1343,9 @@ static void build_r4000_tlb_refill_handl
- #ifdef CONFIG_64BIT
- 		build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
- #else
-+# ifdef CONFIG_BCM47XX
-+		uasm_i_nop(&p);
-+# endif
- 		build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
- #endif
- 
-@@ -1351,6 +1357,9 @@ static void build_r4000_tlb_refill_handl
- 		build_update_entries(&p, K0, K1);
- 		build_tlb_write_entry(&p, &l, &r, tlb_random);
- 		uasm_l_leave(&l, p);
-+#ifdef CONFIG_BCM47XX
-+		uasm_i_nop(&p);
-+#endif
- 		uasm_i_eret(&p); /* return from trap */
- 	}
- #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
-@@ -2049,6 +2058,9 @@ build_r4000_tlbchange_handler_head(u32 *
- #ifdef CONFIG_64BIT
- 	build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
- #else
-+# ifdef CONFIG_BCM47XX
-+	uasm_i_nop(p);
-+# endif
- 	build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
- #endif
- 
-@@ -2095,6 +2107,9 @@ build_r4000_tlbchange_handler_tail(u32 *
- 	build_tlb_write_entry(p, l, r, tlb_indexed);
- 	uasm_l_leave(l, *p);
- 	build_restore_work_registers(p);
-+#ifdef CONFIG_BCM47XX
-+	uasm_i_nop(p);
-+#endif
- 	uasm_i_eret(p); /* return from trap */
- 
- #ifdef CONFIG_64BIT

target/linux/bcm47xx/patches-4.19/160-kmap_coherent.patch

@@ -1,78 +0,0 @@
-From: Jeff Hansen <[email protected]>
-Subject: [PATCH] kmap_coherent
-
-On ASUS WL-500gP there are some "Data bus error"s when executing simple
-commands liks "ps" or "cat /proc/1/cmdline".
-
-This fixes OpenWrt ticket #1485: https://dev.openwrt.org/ticket/1485
----
---- a/arch/mips/include/asm/cpu-features.h
-+++ b/arch/mips/include/asm/cpu-features.h
-@@ -226,6 +226,9 @@
- #ifndef cpu_has_local_ebase
- #define cpu_has_local_ebase	1
- #endif
-+#ifndef cpu_use_kmap_coherent
-+#define cpu_use_kmap_coherent 1
-+#endif
- 
- /*
-  * I-Cache snoops remote store.	 This only matters on SMP.  Some multiprocessors
---- a/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
-+++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
-@@ -80,4 +80,6 @@
- #define cpu_scache_line_size()		0
- #define cpu_has_vz			0
- 
-+#define cpu_use_kmap_coherent		0
-+
- #endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
---- a/arch/mips/mm/c-r4k.c
-+++ b/arch/mips/mm/c-r4k.c
-@@ -694,7 +694,7 @@ static inline void local_r4k_flush_cache
- 		map_coherent = (cpu_has_dc_aliases &&
- 				page_mapcount(page) &&
- 				!Page_dcache_dirty(page));
--		if (map_coherent)
-+		if (map_coherent && cpu_use_kmap_coherent)
- 			vaddr = kmap_coherent(page, addr);
- 		else
- 			vaddr = kmap_atomic(page);
-@@ -719,7 +719,7 @@ static inline void local_r4k_flush_cache
- 	}
- 
- 	if (vaddr) {
--		if (map_coherent)
-+		if (map_coherent && cpu_use_kmap_coherent)
- 			kunmap_coherent();
- 		else
- 			kunmap_atomic(vaddr);
---- a/arch/mips/mm/init.c
-+++ b/arch/mips/mm/init.c
-@@ -168,7 +168,7 @@ void copy_user_highpage(struct page *to,
- 	void *vfrom, *vto;
- 
- 	vto = kmap_atomic(to);
--	if (cpu_has_dc_aliases &&
-+	if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
- 	    page_mapcount(from) && !Page_dcache_dirty(from)) {
- 		vfrom = kmap_coherent(from, vaddr);
- 		copy_page(vto, vfrom);
-@@ -190,7 +190,7 @@ void copy_to_user_page(struct vm_area_st
- 	struct page *page, unsigned long vaddr, void *dst, const void *src,
- 	unsigned long len)
- {
--	if (cpu_has_dc_aliases &&
-+	if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
- 	    page_mapcount(page) && !Page_dcache_dirty(page)) {
- 		void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
- 		memcpy(vto, src, len);
-@@ -208,7 +208,7 @@ void copy_from_user_page(struct vm_area_
- 	struct page *page, unsigned long vaddr, void *dst, const void *src,
- 	unsigned long len)
- {
--	if (cpu_has_dc_aliases &&
-+	if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
- 	    page_mapcount(page) && !Page_dcache_dirty(page)) {
- 		void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
- 		memcpy(dst, vfrom, len);

target/linux/bcm47xx/patches-4.19/209-b44-register-adm-switch.patch

@@ -1,121 +0,0 @@
-From b36f694256f41bc71571f467646d015dda128d14 Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <[email protected]>
-Date: Sat, 9 Nov 2013 17:03:59 +0100
-Subject: [PATCH 210/210] b44: register adm switch
-
----
- drivers/net/ethernet/broadcom/b44.c |   57 +++++++++++++++++++++++++++++++++++
- drivers/net/ethernet/broadcom/b44.h |    3 ++
- 2 files changed, 60 insertions(+)
-
---- a/drivers/net/ethernet/broadcom/b44.c
-+++ b/drivers/net/ethernet/broadcom/b44.c
-@@ -31,6 +31,8 @@
- #include <linux/ssb/ssb.h>
- #include <linux/slab.h>
- #include <linux/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/platform_data/adm6996-gpio.h>
- 
- #include <linux/uaccess.h>
- #include <asm/io.h>
-@@ -2249,6 +2251,69 @@ static void b44_adjust_link(struct net_d
- 	}
- }
- 
-+#ifdef CONFIG_BCM47XX
-+static int b44_register_adm_switch(struct b44 *bp)
-+{
-+	int gpio;
-+	struct platform_device *pdev;
-+	struct adm6996_gpio_platform_data adm_data = {0};
-+	struct platform_device_info info = {0};
-+
-+	adm_data.model = ADM6996L;
-+	gpio = bcm47xx_nvram_gpio_pin("adm_eecs");
-+	if (gpio >= 0)
-+		adm_data.eecs = gpio;
-+	else
-+		adm_data.eecs = 2;
-+
-+	gpio = bcm47xx_nvram_gpio_pin("adm_eesk");
-+	if (gpio >= 0)
-+		adm_data.eesk = gpio;
-+	else
-+		adm_data.eesk = 3;
-+
-+	gpio = bcm47xx_nvram_gpio_pin("adm_eedi");
-+	if (gpio >= 0)
-+		adm_data.eedi = gpio;
-+	else
-+		adm_data.eedi = 4;
-+
-+	/*
-+	 * We ignore the "adm_rc" GPIO here. The driver does not use it,
-+	 * and it conflicts with the Reset button GPIO on the Linksys WRT54GSv1.
-+	 */
-+
-+	info.parent = bp->sdev->dev;
-+	info.name = "adm6996_gpio";
-+	info.id = -1;
-+	info.data = &adm_data;
-+	info.size_data = sizeof(adm_data);
-+
-+	if (!bp->adm_switch) {
-+		pdev = platform_device_register_full(&info);
-+		if (IS_ERR(pdev))
-+			return PTR_ERR(pdev);
-+
-+		bp->adm_switch = pdev;
-+	}
-+	return 0;
-+}
-+static void b44_unregister_adm_switch(struct b44 *bp)
-+{
-+	if (bp->adm_switch)
-+		platform_device_unregister(bp->adm_switch);
-+}
-+#else
-+static int b44_register_adm_switch(struct b44 *bp)
-+{
-+	return 0;
-+}
-+static void b44_unregister_adm_switch(struct b44 *bp)
-+{
-+
-+}
-+#endif /* CONFIG_BCM47XX */
-+
- static int b44_register_phy_one(struct b44 *bp)
- {
- 	struct mii_bus *mii_bus;
-@@ -2284,6 +2349,9 @@ static int b44_register_phy_one(struct b
- 	if (!mdiobus_is_registered_device(bp->mii_bus, bp->phy_addr) &&
- 	    (sprom->boardflags_lo & (B44_BOARDFLAG_ROBO | B44_BOARDFLAG_ADM))) {
- 
-+		if (sprom->boardflags_lo & B44_BOARDFLAG_ADM)
-+			b44_register_adm_switch(bp);
-+
- 		dev_info(sdev->dev,
- 			 "could not find PHY at %i, use fixed one\n",
- 			 bp->phy_addr);
-@@ -2478,6 +2546,7 @@ static void b44_remove_one(struct ssb_de
- 	unregister_netdev(dev);
- 	if (bp->flags & B44_FLAG_EXTERNAL_PHY)
- 		b44_unregister_phy_one(bp);
-+	b44_unregister_adm_switch(bp);
- 	ssb_device_disable(sdev, 0);
- 	ssb_bus_may_powerdown(sdev->bus);
- 	netif_napi_del(&bp->napi);
---- a/drivers/net/ethernet/broadcom/b44.h
-+++ b/drivers/net/ethernet/broadcom/b44.h
-@@ -408,6 +408,9 @@ struct b44 {
- 	struct mii_bus		*mii_bus;
- 	int			old_link;
- 	struct mii_if_info	mii_if;
-+
-+	/* platform device for associated switch */
-+	struct platform_device *adm_switch;
- };
- 
- #endif /* _B44_H */

target/linux/bcm47xx/patches-4.19/210-b44_phy_fix.patch

@@ -1,54 +0,0 @@
---- a/drivers/net/ethernet/broadcom/b44.c
-+++ b/drivers/net/ethernet/broadcom/b44.c
-@@ -431,10 +431,34 @@ static void b44_wap54g10_workaround(stru
- error:
- 	pr_warn("PHY: cannot reset MII transceiver isolate bit\n");
- }
-+
-+static void b44_bcm47xx_workarounds(struct b44 *bp)
-+{
-+	char buf[20];
-+	struct ssb_device *sdev = bp->sdev;
-+
-+	/* Toshiba WRC-1000, Siemens SE505 v1, Askey RT-210W, RT-220W */
-+	if (sdev->bus->sprom.board_num == 100) {
-+		bp->phy_addr = B44_PHY_ADDR_NO_LOCAL_PHY;
-+	} else {
-+		/* WL-HDD */
-+		if (bcm47xx_nvram_getenv("hardware_version", buf, sizeof(buf)) >= 0 &&
-+		    !strncmp(buf, "WL300-", strlen("WL300-"))) {
-+			if (sdev->bus->sprom.et0phyaddr == 0 &&
-+			    sdev->bus->sprom.et1phyaddr == 1)
-+				bp->phy_addr = B44_PHY_ADDR_NO_LOCAL_PHY;
-+		}
-+	}
-+	return;
-+}
- #else
- static inline void b44_wap54g10_workaround(struct b44 *bp)
- {
- }
-+
-+static inline void b44_bcm47xx_workarounds(struct b44 *bp)
-+{
-+}
- #endif
- 
- static int b44_setup_phy(struct b44 *bp)
-@@ -443,6 +467,7 @@ static int b44_setup_phy(struct b44 *bp)
- 	int err;
- 
- 	b44_wap54g10_workaround(bp);
-+	b44_bcm47xx_workarounds(bp);
- 
- 	if (bp->flags & B44_FLAG_EXTERNAL_PHY)
- 		return 0;
-@@ -2179,6 +2204,8 @@ static int b44_get_invariants(struct b44
- 	 * valid PHY address. */
- 	bp->phy_addr &= 0x1F;
- 
-+	b44_bcm47xx_workarounds(bp);
-+
- 	memcpy(bp->dev->dev_addr, addr, ETH_ALEN);
- 
- 	if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){

target/linux/bcm47xx/patches-4.19/280-activate_ssb_support_in_usb.patch

@@ -1,25 +0,0 @@
-This prevents the options from being delete with make kernel_oldconfig.
----
- drivers/ssb/Kconfig |    2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/bcma/Kconfig
-+++ b/drivers/bcma/Kconfig
-@@ -32,6 +32,7 @@ config BCMA_HOST_PCI
- config BCMA_HOST_SOC
- 	bool "Support for BCMA in a SoC"
- 	depends on HAS_IOMEM
-+	select USB_HCD_BCMA if USB_EHCI_HCD || USB_OHCI_HCD
- 	help
- 	  Host interface for a Broadcom AIX bus directly mapped into
- 	  the memory. This only works with the Broadcom SoCs from the
---- a/drivers/ssb/Kconfig
-+++ b/drivers/ssb/Kconfig
-@@ -135,6 +135,7 @@ config SSB_SFLASH
- config SSB_EMBEDDED
- 	bool
- 	depends on SSB_DRIVER_MIPS && SSB_PCICORE_HOSTMODE
-+	select USB_HCD_SSB if USB_EHCI_HCD || USB_OHCI_HCD
- 	default y
- 
- config SSB_DRIVER_EXTIF

target/linux/bcm47xx/patches-4.19/300-fork_cacheflush.patch

@@ -1,21 +0,0 @@
-From: Wolfram Joost <[email protected]>
-Subject: [PATCH] fork_cacheflush
-
-On ASUS WL-500gP there are many unexpected "Segmentation fault"s that
-seem to be caused by a kernel. They can be avoided by:
-1) Disabling highpage
-2) Using flush_cache_mm in flush_cache_dup_mm
-
-For details see OpenWrt ticket #2035 https://dev.openwrt.org/ticket/2035
----
---- a/arch/mips/include/asm/cacheflush.h
-+++ b/arch/mips/include/asm/cacheflush.h
-@@ -47,7 +47,7 @@
- extern void (*flush_cache_all)(void);
- extern void (*__flush_cache_all)(void);
- extern void (*flush_cache_mm)(struct mm_struct *mm);
--#define flush_cache_dup_mm(mm)	do { (void) (mm); } while (0)
-+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
- extern void (*flush_cache_range)(struct vm_area_struct *vma,
- 	unsigned long start, unsigned long end);
- extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);

target/linux/bcm47xx/patches-4.19/310-no_highpage.patch

@@ -1,74 +0,0 @@
-From: Jeff Hansen <[email protected]>
-Subject: [PATCH] no highpage
-
-On ASUS WL-500gP there are many unexpected "Segmentation fault"s that
-seem to be caused by a kernel. They can be avoided by:
-1) Disabling highpage
-2) Using flush_cache_mm in flush_cache_dup_mm
-
-For details see OpenWrt ticket #2035 https://dev.openwrt.org/ticket/2035
----
---- a/arch/mips/include/asm/page.h
-+++ b/arch/mips/include/asm/page.h
-@@ -71,6 +71,7 @@ static inline unsigned int page_size_ftl
- #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
- 
- #include <linux/pfn.h>
-+#include <asm/cpu-features.h>
- 
- extern void build_clear_page(void);
- extern void build_copy_page(void);
-@@ -110,11 +111,16 @@ static inline void clear_user_page(void
- 		flush_data_cache_page((unsigned long)addr);
- }
- 
--struct vm_area_struct;
--extern void copy_user_highpage(struct page *to, struct page *from,
--	unsigned long vaddr, struct vm_area_struct *vma);
-+static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
-+	struct page *to)
-+{
-+	extern void (*flush_data_cache_page)(unsigned long addr);
- 
--#define __HAVE_ARCH_COPY_USER_HIGHPAGE
-+	copy_page(vto, vfrom);
-+	if (!cpu_has_ic_fills_f_dc ||
-+	    pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
-+		flush_data_cache_page((unsigned long)vto);
-+}
- 
- /*
-  * These are used to make use of C type-checking..
---- a/arch/mips/mm/init.c
-+++ b/arch/mips/mm/init.c
-@@ -162,30 +162,6 @@ void kunmap_coherent(void)
- 	preempt_enable();
- }
- 
--void copy_user_highpage(struct page *to, struct page *from,
--	unsigned long vaddr, struct vm_area_struct *vma)
--{
--	void *vfrom, *vto;
--
--	vto = kmap_atomic(to);
--	if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
--	    page_mapcount(from) && !Page_dcache_dirty(from)) {
--		vfrom = kmap_coherent(from, vaddr);
--		copy_page(vto, vfrom);
--		kunmap_coherent();
--	} else {
--		vfrom = kmap_atomic(from);
--		copy_page(vto, vfrom);
--		kunmap_atomic(vfrom);
--	}
--	if ((!cpu_has_ic_fills_f_dc) ||
--	    pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
--		flush_data_cache_page((unsigned long)vto);
--	kunmap_atomic(vto);
--	/* Make sure this page is cleared on other CPU's too before using it */
--	smp_wmb();
--}
--
- void copy_to_user_page(struct vm_area_struct *vma,
- 	struct page *page, unsigned long vaddr, void *dst, const void *src,
- 	unsigned long len)

target/linux/bcm47xx/patches-4.19/320-MIPS-BCM47XX-Devices-database-update-for-4.x.patch

@@ -1,185 +0,0 @@
---- a/arch/mips/bcm47xx/board.c
-+++ b/arch/mips/bcm47xx/board.c
-@@ -141,6 +141,7 @@ struct bcm47xx_board_type_list2 bcm47xx_
- 	{{BCM47XX_BOARD_LINKSYS_WRT300NV11, "Linksys WRT300N V1.1"}, "WRT300N", "1.1"},
- 	{{BCM47XX_BOARD_LINKSYS_WRT310NV1, "Linksys WRT310N V1"}, "WRT310N", "1.0"},
- 	{{BCM47XX_BOARD_LINKSYS_WRT310NV2, "Linksys WRT310N V2"}, "WRT310N", "2.0"},
-+	{{BCM47XX_BOARD_LINKSYS_WRT320N_V1, "Linksys WRT320N V1"}, "WRT320N", "1.0"},
- 	{{BCM47XX_BOARD_LINKSYS_WRT54G3GV2, "Linksys WRT54G3GV2-VF"}, "WRT54G3GV2-VF", "1.0"},
- 	{{BCM47XX_BOARD_LINKSYS_WRT610NV1, "Linksys WRT610N V1"}, "WRT610N", "1.0"},
- 	{{BCM47XX_BOARD_LINKSYS_WRT610NV2, "Linksys WRT610N V2"}, "WRT610N", "2.0"},
-@@ -161,9 +162,12 @@ struct bcm47xx_board_type_list1 bcm47xx_
- 	{{BCM47XX_BOARD_LUXUL_XWR_600_V1, "Luxul XWR-600 V1"}, "luxul_xwr600_v1"},
- 	{{BCM47XX_BOARD_LUXUL_XWR_1750_V1, "Luxul XWR-1750 V1"}, "luxul_xwr1750_v1"},
- 	{{BCM47XX_BOARD_NETGEAR_R6200_V1, "Netgear R6200 V1"}, "U12H192T00_NETGEAR"},
-+	{{BCM47XX_BOARD_NETGEAR_R6300_V1, "Netgear R6300 V1"}, "U12H218T00_NETGEAR"},
- 	{{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"},
- 	{{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"},
- 	{{BCM47XX_BOARD_NETGEAR_WGR614_V10, "Netgear WGR614 V10"}, "U12H139T01_NETGEAR"},
-+	{{BCM47XX_BOARD_NETGEAR_WN2500RP_V1, "Netgear WN2500RP V1"}, "U12H197T00_NETGEAR"},
-+	{{BCM47XX_BOARD_NETGEAR_WN2500RP_V2, "Netgear WN2500RP V2"}, "U12H294T00_NETGEAR"},
- 	{{BCM47XX_BOARD_NETGEAR_WNDR3300, "Netgear WNDR3300"}, "U12H093T00_NETGEAR"},
- 	{{BCM47XX_BOARD_NETGEAR_WNDR3400V1, "Netgear WNDR3400 V1"}, "U12H155T00_NETGEAR"},
- 	{{BCM47XX_BOARD_NETGEAR_WNDR3400V2, "Netgear WNDR3400 V2"}, "U12H187T00_NETGEAR"},
---- a/arch/mips/bcm47xx/buttons.c
-+++ b/arch/mips/bcm47xx/buttons.c
-@@ -27,6 +27,12 @@
- /* Asus */
- 
- static const struct gpio_keys_button
-+bcm47xx_buttons_asus_rtn10u[] __initconst = {
-+	BCM47XX_GPIO_KEY(20, KEY_WPS_BUTTON),
-+	BCM47XX_GPIO_KEY(21, KEY_RESTART),
-+};
-+
-+static const struct gpio_keys_button
- bcm47xx_buttons_asus_rtn12[] __initconst = {
- 	BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
- 	BCM47XX_GPIO_KEY(1, KEY_RESTART),
-@@ -277,6 +283,18 @@ bcm47xx_buttons_linksys_wrt310nv1[] __in
- };
- 
- static const struct gpio_keys_button
-+bcm47xx_buttons_linksys_wrt310n_v2[] __initconst = {
-+	BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON),
-+	BCM47XX_GPIO_KEY(6, KEY_RESTART),
-+};
-+
-+static const struct gpio_keys_button
-+bcm47xx_buttons_linksys_wrt320n_v1[] __initconst = {
-+	BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON),
-+	BCM47XX_GPIO_KEY(8, KEY_RESTART),
-+};
-+
-+static const struct gpio_keys_button
- bcm47xx_buttons_linksys_wrt54g3gv2[] __initconst = {
- 	BCM47XX_GPIO_KEY(5, KEY_WIMAX),
- 	BCM47XX_GPIO_KEY(6, KEY_RESTART),
-@@ -392,6 +410,17 @@ bcm47xx_buttons_netgear_r6200_v1[] __ini
- };
- 
- static const struct gpio_keys_button
-+bcm47xx_buttons_netgear_r6300_v1[] __initconst = {
-+	BCM47XX_GPIO_KEY(6, KEY_RESTART),
-+};
-+
-+static const struct gpio_keys_button
-+bcm47xx_buttons_netgear_wn2500rp_v1[] __initconst = {
-+	BCM47XX_GPIO_KEY(12, KEY_RESTART),
-+	BCM47XX_GPIO_KEY(31, KEY_WPS_BUTTON),
-+};
-+
-+static const struct gpio_keys_button
- bcm47xx_buttons_netgear_wndr3400v1[] __initconst = {
- 	BCM47XX_GPIO_KEY(4, KEY_RESTART),
- 	BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON),
-@@ -478,6 +507,9 @@ int __init bcm47xx_buttons_register(void
- 	int err;
- 
- 	switch (board) {
-+	case BCM47XX_BOARD_ASUS_RTN10U:
-+		err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn10u);
-+		break;
- 	case BCM47XX_BOARD_ASUS_RTN12:
- 		err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn12);
- 		break;
-@@ -608,6 +640,12 @@ int __init bcm47xx_buttons_register(void
- 	case BCM47XX_BOARD_LINKSYS_WRT310NV1:
- 		err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310nv1);
- 		break;
-+	case BCM47XX_BOARD_LINKSYS_WRT310NV2:
-+		err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310n_v2);
-+		break;
-+	case BCM47XX_BOARD_LINKSYS_WRT320N_V1:
-+		err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt320n_v1);
-+		break;
- 	case BCM47XX_BOARD_LINKSYS_WRT54G3GV2:
- 		err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt54g3gv2);
- 		break;
-@@ -674,6 +712,12 @@ int __init bcm47xx_buttons_register(void
- 	case BCM47XX_BOARD_NETGEAR_R6200_V1:
- 		err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_r6200_v1);
- 		break;
-+	case BCM47XX_BOARD_NETGEAR_R6300_V1:
-+		err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_r6300_v1);
-+		break;
-+	case BCM47XX_BOARD_NETGEAR_WN2500RP_V1:
-+		err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wn2500rp_v1);
-+		break;
- 	case BCM47XX_BOARD_NETGEAR_WNDR3400V1:
- 		err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400v1);
- 		break;
---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-@@ -72,6 +72,7 @@ enum bcm47xx_board {
- 	BCM47XX_BOARD_LINKSYS_WRT300NV11,
- 	BCM47XX_BOARD_LINKSYS_WRT310NV1,
- 	BCM47XX_BOARD_LINKSYS_WRT310NV2,
-+	BCM47XX_BOARD_LINKSYS_WRT320N_V1,
- 	BCM47XX_BOARD_LINKSYS_WRT54G3GV2,
- 	BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101,
- 	BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467,
-@@ -99,9 +100,12 @@ enum bcm47xx_board {
- 	BCM47XX_BOARD_MOTOROLA_WR850GV2V3,
- 
- 	BCM47XX_BOARD_NETGEAR_R6200_V1,
-+	BCM47XX_BOARD_NETGEAR_R6300_V1,
- 	BCM47XX_BOARD_NETGEAR_WGR614V8,
- 	BCM47XX_BOARD_NETGEAR_WGR614V9,
- 	BCM47XX_BOARD_NETGEAR_WGR614_V10,
-+	BCM47XX_BOARD_NETGEAR_WN2500RP_V1,
-+	BCM47XX_BOARD_NETGEAR_WN2500RP_V2,
- 	BCM47XX_BOARD_NETGEAR_WNDR3300,
- 	BCM47XX_BOARD_NETGEAR_WNDR3400V1,
- 	BCM47XX_BOARD_NETGEAR_WNDR3400V2,
---- a/arch/mips/bcm47xx/leds.c
-+++ b/arch/mips/bcm47xx/leds.c
-@@ -30,6 +30,14 @@
- /* Asus */
- 
- static const struct gpio_led
-+bcm47xx_leds_asus_rtn10u[] __initconst = {
-+	BCM47XX_GPIO_LED(5, "green", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
-+	BCM47XX_GPIO_LED(6, "green", "power", 1, LEDS_GPIO_DEFSTATE_ON),
-+	BCM47XX_GPIO_LED(7, "green", "wps", 0, LEDS_GPIO_DEFSTATE_OFF),
-+	BCM47XX_GPIO_LED(8, "green", "usb", 0, LEDS_GPIO_DEFSTATE_OFF),
-+};
-+
-+static const struct gpio_led
- bcm47xx_leds_asus_rtn12[] __initconst = {
- 	BCM47XX_GPIO_LED(2, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
- 	BCM47XX_GPIO_LED(7, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
-@@ -314,6 +322,13 @@ bcm47xx_leds_linksys_wrt310nv1[] __initc
- };
- 
- static const struct gpio_led
-+bcm47xx_leds_linksys_wrt320n_v1[] __initconst = {
-+	BCM47XX_GPIO_LED(1, "blue", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
-+	BCM47XX_GPIO_LED(2, "blue", "power", 0, LEDS_GPIO_DEFSTATE_ON),
-+	BCM47XX_GPIO_LED(4, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
-+};
-+
-+static const struct gpio_led
- bcm47xx_leds_linksys_wrt54g_generic[] __initconst = {
- 	BCM47XX_GPIO_LED(0, "unk", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF),
- 	BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
-@@ -556,6 +571,9 @@ void __init bcm47xx_leds_register(void)
- 	enum bcm47xx_board board = bcm47xx_board_get();
- 
- 	switch (board) {
-+	case BCM47XX_BOARD_ASUS_RTN10U:
-+		bcm47xx_set_pdata(bcm47xx_leds_asus_rtn10u);
-+		break;
- 	case BCM47XX_BOARD_ASUS_RTN12:
- 		bcm47xx_set_pdata(bcm47xx_leds_asus_rtn12);
- 		break;
-@@ -689,6 +707,9 @@ void __init bcm47xx_leds_register(void)
- 	case BCM47XX_BOARD_LINKSYS_WRT310NV1:
- 		bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt310nv1);
- 		break;
-+	case BCM47XX_BOARD_LINKSYS_WRT320N_V1:
-+		bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt320n_v1);
-+		break;
- 	case BCM47XX_BOARD_LINKSYS_WRT54G3GV2:
- 		bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt54g3gv2);
- 		break;

target/linux/bcm47xx/patches-4.19/400-mtd-bcm47xxpart-get-nvram.patch

@@ -1,34 +0,0 @@
---- a/drivers/mtd/bcm47xxpart.c
-+++ b/drivers/mtd/bcm47xxpart.c
-@@ -102,6 +102,7 @@ static int bcm47xxpart_parse(struct mtd_
- 	int trx_num = 0; /* Number of found TRX partitions */
- 	int possible_nvram_sizes[] = { 0x8000, 0xF000, 0x10000, };
- 	int err;
-+	bool found_nvram = false;
- 
- 	/*
- 	 * Some really old flashes (like AT45DB*) had smaller erasesize-s, but
-@@ -283,12 +284,23 @@ static int bcm47xxpart_parse(struct mtd_
- 		if (buf[0] == NVRAM_HEADER) {
- 			bcm47xxpart_add_part(&parts[curr_part++], "nvram",
- 					     master->size - blocksize, 0);
-+			found_nvram = true;
- 			break;
- 		}
- 	}
- 
- 	kfree(buf);
- 
-+	if (!found_nvram) {
-+		pr_err("can not find a nvram partition reserve last block\n");
-+		bcm47xxpart_add_part(&parts[curr_part++], "nvram_guess",
-+				     master->size - blocksize * 2, MTD_WRITEABLE);
-+		for (i = 0; i < curr_part; i++) {
-+			if (parts[i].size + parts[i].offset == master->size)
-+				parts[i].offset -= blocksize * 2;
-+		}
-+	}
-+
- 	/*
- 	 * Assume that partitions end at the beginning of the one they are
- 	 * followed by.

target/linux/bcm47xx/patches-4.19/610-pci_ide_fix.patch

@@ -1,41 +0,0 @@
-From: b.sander
-Subject: [PATCH] pci: IDE fix
-
-These are standard probing messages when using pdc202xx_old:
-pdc202xx_old 0000:00:01.0: IDE controller (0x105a:0x0d30 rev 0x02)
-PCI: Enabling device 0000:00:01.0 (0004 -> 0007)
-PCI: Fixing up device 0000:00:01.0
-0000:00:01.0: (U)DMA Burst Bit DISABLED Primary PCI Mode Secondary PCI Mode.
-0000:00:01.0: FORCING BURST BIT 0x00->0x01 ACTIVE
-pdc202xx_old 0000:00:01.0: 100% native mode on irq 6
-
-With the default MAX_HWIFS value after above we get:
-    ide2: BM-DMA at 0x0400-0x0407
-    ide3: BM-DMA at 0x0408-0x040f
-Probing IDE interface ide2...
-hde: CF500, CFA DISK drive
-
-As you can see it's ide2 + ide3 and hde.
-
-With this patch applied we get:
-    ide0: BM-DMA at 0x0400-0x0407
-    ide1: BM-DMA at 0x0408-0x040f
-Probing IDE interface ide0...
-hda: CF500, CFA DISK drive
-
-This fixes OpenWrt ticket #7061: https://dev.openwrt.org/ticket/7061
----
---- a/include/linux/ide.h
-+++ b/include/linux/ide.h
-@@ -235,7 +235,11 @@ static inline void ide_std_init_ports(st
- 	hw->io_ports.ctl_addr = ctl_addr;
- }
- 
-+#if defined CONFIG_BCM47XX
-+# define MAX_HWIFS	2
-+#else
- #define MAX_HWIFS	10
-+#endif
- 
- /*
-  * Now for the data we need to maintain per-drive:  ide_drive_t

target/linux/bcm47xx/patches-4.19/791-tg3-no-pci-sleep.patch

@@ -1,17 +0,0 @@
-When the Ethernet controller is powered down and someone wants to 
-access the mdio bus like the witch driver (b53) the system crashed if 
-PCI_D3hot was set before. This patch deactivates this power sawing mode 
-when a switch driver is in use.
-
---- a/drivers/net/ethernet/broadcom/tg3.c
-+++ b/drivers/net/ethernet/broadcom/tg3.c
-@@ -4279,7 +4279,8 @@ static int tg3_power_down_prepare(struct
- static void tg3_power_down(struct tg3 *tp)
- {
- 	pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
--	pci_set_power_state(tp->pdev, PCI_D3hot);
-+	if (!tg3_flag(tp, ROBOSWITCH))
-+		pci_set_power_state(tp->pdev, PCI_D3hot);
- }
- 
- static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)

target/linux/bcm47xx/patches-4.19/800-bcma-add-table-of-serial-flashes-with-smaller-blocks.patch

@@ -1,73 +0,0 @@
-From 597715c61ae75a05ab3310a34ff3857a006f0f63 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <[email protected]>
-Date: Thu, 20 Nov 2014 21:32:42 +0100
-Subject: [PATCH] bcma: add table of serial flashes with smaller blocks
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Rafał Miłecki <[email protected]>
----
- drivers/bcma/driver_chipcommon_sflash.c | 29 +++++++++++++++++++++++++++++
- 1 file changed, 29 insertions(+)
-
---- a/drivers/bcma/driver_chipcommon_sflash.c
-+++ b/drivers/bcma/driver_chipcommon_sflash.c
-@@ -9,6 +9,7 @@
- 
- #include <linux/platform_device.h>
- #include <linux/bcma/bcma.h>
-+#include <bcm47xx_board.h>
- 
- static struct resource bcma_sflash_resource = {
- 	.name	= "bcma_sflash",
-@@ -42,6 +43,13 @@ static const struct bcma_sflash_tbl_e bc
- 	{ NULL },
- };
- 
-+/* Some devices use smaller blocks (and have more of them) */
-+static const struct bcma_sflash_tbl_e bcma_sflash_st_shrink_tbl[] = {
-+	{ "M25P16", 0x14, 0x1000, 512, },
-+	{ "M25P32", 0x15, 0x1000, 1024, },
-+	{ NULL },
-+};
-+
- static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
- 	{ "SST25WF512", 1, 0x1000, 16, },
- 	{ "SST25VF512", 0x48, 0x1000, 16, },
-@@ -85,6 +93,24 @@ static void bcma_sflash_cmd(struct bcma_
- 	bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n");
- }
- 
-+const struct bcma_sflash_tbl_e *bcma_sflash_shrink_flash(u32 id)
-+{
-+	enum bcm47xx_board board = bcm47xx_board_get();
-+	const struct bcma_sflash_tbl_e *e;
-+
-+	switch (board) {
-+	case BCM47XX_BOARD_NETGEAR_WGR614_V10:
-+	case BCM47XX_BOARD_NETGEAR_WNR1000_V3:
-+		for (e = bcma_sflash_st_shrink_tbl; e->name; e++) {
-+			if (e->id == id)
-+				return e;
-+		}
-+		return NULL;
-+	default:
-+		return NULL;
-+	}
-+}
-+
- /* Initialize serial flash access */
- int bcma_sflash_init(struct bcma_drv_cc *cc)
- {
-@@ -115,6 +141,10 @@ int bcma_sflash_init(struct bcma_drv_cc
- 		case 0x13:
- 			return -ENOTSUPP;
- 		default:
-+			e = bcma_sflash_shrink_flash(id);
-+			if (e)
-+				break;
-+
- 			for (e = bcma_sflash_st_tbl; e->name; e++) {
- 				if (e->id == id)
- 					break;

target/linux/bcm47xx/patches-4.19/820-wgt634u-nvram-fix.patch

@@ -1,304 +0,0 @@
-The Netgear wgt634u uses a different format for storing the 
-configuration. This patch is needed to read out the correct 
-configuration. The cfe_env.c file uses a different method way to read 
-out the configuration than the in kernel cfe config reader.
-
---- a/drivers/firmware/broadcom/Makefile
-+++ b/drivers/firmware/broadcom/Makefile
-@@ -1,2 +1,2 @@
--obj-$(CONFIG_BCM47XX_NVRAM)		+= bcm47xx_nvram.o
-+obj-$(CONFIG_BCM47XX_NVRAM)		+= bcm47xx_nvram.o cfe_env.o
- obj-$(CONFIG_BCM47XX_SPROM)		+= bcm47xx_sprom.o
---- /dev/null
-+++ b/drivers/firmware/broadcom/cfe_env.c
-@@ -0,0 +1,228 @@
-+/*
-+ * CFE environment variable access
-+ *
-+ * Copyright 2001-2003, Broadcom Corporation
-+ * Copyright 2006, Felix Fietkau <[email protected]>
-+ * 
-+ * This program is free software; you can redistribute  it and/or modify it
-+ * under  the terms of  the GNU General  Public License as published by the
-+ * Free Software Foundation;  either version 2 of the  License, or (at your
-+ * option) any later version.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/string.h>
-+#include <asm/io.h>
-+#include <linux/uaccess.h>
-+
-+#define NVRAM_SIZE       (0x1ff0)
-+static char _nvdata[NVRAM_SIZE];
-+static char _valuestr[256];
-+
-+/*
-+ * TLV types.  These codes are used in the "type-length-value"
-+ * encoding of the items stored in the NVRAM device (flash or EEPROM)
-+ *
-+ * The layout of the flash/nvram is as follows:
-+ *
-+ * <type> <length> <data ...> <type> <length> <data ...> <type_end>
-+ *
-+ * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
-+ * The "length" field marks the length of the data section, not
-+ * including the type and length fields.
-+ *
-+ * Environment variables are stored as follows:
-+ *
-+ * <type_env> <length> <flags> <name> = <value>
-+ *
-+ * If bit 0 (low bit) is set, the length is an 8-bit value.
-+ * If bit 0 (low bit) is clear, the length is a 16-bit value
-+ * 
-+ * Bit 7 set indicates "user" TLVs.  In this case, bit 0 still
-+ * indicates the size of the length field.  
-+ *
-+ * Flags are from the constants below:
-+ *
-+ */
-+#define ENV_LENGTH_16BITS	0x00	/* for low bit */
-+#define ENV_LENGTH_8BITS	0x01
-+
-+#define ENV_TYPE_USER		0x80
-+
-+#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
-+#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
-+
-+/*
-+ * The actual TLV types we support
-+ */
-+
-+#define ENV_TLV_TYPE_END	0x00	
-+#define ENV_TLV_TYPE_ENV	ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
-+
-+/*
-+ * Environment variable flags 
-+ */
-+
-+#define ENV_FLG_NORMAL		0x00	/* normal read/write */
-+#define ENV_FLG_BUILTIN		0x01	/* builtin - not stored in flash */
-+#define ENV_FLG_READONLY	0x02	/* read-only - cannot be changed */
-+
-+#define ENV_FLG_MASK		0xFF	/* mask of attributes we keep */
-+#define ENV_FLG_ADMIN		0x100	/* lets us internally override permissions */
-+
-+
-+/*  *********************************************************************
-+    *  _nvram_read(buffer,offset,length)
-+    *  
-+    *  Read data from the NVRAM device
-+    *  
-+    *  Input parameters: 
-+    *  	   buffer - destination buffer
-+    *  	   offset - offset of data to read
-+    *  	   length - number of bytes to read
-+    *  	   
-+    *  Return value:
-+    *  	   number of bytes read, or <0 if error occured
-+    ********************************************************************* */
-+static int
-+_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
-+{
-+    int i;
-+    if (offset > NVRAM_SIZE)
-+	return -1; 
-+
-+    for ( i = 0; i < length; i++) {
-+	buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
-+    }
-+    return length;
-+}
-+
-+
-+static char*
-+_strnchr(const char *dest,int c,size_t cnt)
-+{
-+	while (*dest && (cnt > 0)) {
-+	if (*dest == c) return (char *) dest;
-+	dest++;
-+	cnt--;
-+	}
-+	return NULL;
-+}
-+
-+
-+
-+/*
-+ * Core support API: Externally visible.
-+ */
-+
-+/*
-+ * Get the value of an NVRAM variable
-+ * @param	name	name of variable to get
-+ * @return	value of variable or NULL if undefined
-+ */
-+
-+char *cfe_env_get(unsigned char *nv_buf, const char *name)
-+{
-+    int size;
-+    unsigned char *buffer;
-+    unsigned char *ptr;
-+    unsigned char *envval;
-+    unsigned int reclen;
-+    unsigned int rectype;
-+    int offset;
-+    int flg;
-+    
-+	if (!strcmp(name, "nvram_type"))
-+		return "cfe";
-+	
-+    size = NVRAM_SIZE;
-+    buffer = &_nvdata[0];
-+
-+    ptr = buffer;
-+    offset = 0;
-+
-+    /* Read the record type and length */
-+    if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
-+	goto error;
-+    }
-+    
-+    while ((*ptr != ENV_TLV_TYPE_END)  && (size > 1)) {
-+
-+	/* Adjust pointer for TLV type */
-+	rectype = *(ptr);
-+	offset++;
-+	size--;
-+
-+	/* 
-+	 * Read the length.  It can be either 1 or 2 bytes
-+	 * depending on the code 
-+	 */
-+	if (rectype & ENV_LENGTH_8BITS) {
-+	    /* Read the record type and length - 8 bits */
-+	    if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
-+		goto error;
-+	    }
-+	    reclen = *(ptr);
-+	    size--;
-+	    offset++;
-+	}
-+	else {
-+	    /* Read the record type and length - 16 bits, MSB first */
-+	    if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
-+		goto error;
-+	    }
-+	    reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
-+	    size -= 2;
-+	    offset += 2;
-+	}
-+
-+	if (reclen > size)
-+	    break;	/* should not happen, bad NVRAM */
-+
-+	switch (rectype) {
-+	    case ENV_TLV_TYPE_ENV:
-+		/* Read the TLV data */
-+		if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
-+		    goto error;
-+		flg = *ptr++;
-+		envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
-+		if (envval) {
-+		    *envval++ = '\0';
-+		    memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
-+		    _valuestr[(reclen-1)-(envval-ptr)] = '\0';
-+#if 0			
-+		    printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
-+#endif
-+		    if(!strcmp(ptr, name)){
-+			return _valuestr;
-+		    }
-+		    if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
-+			return _valuestr;
-+		}
-+		break;
-+		
-+	    default: 
-+		/* Unknown TLV type, skip it. */
-+		break;
-+	    }
-+
-+	/*
-+	 * Advance to next TLV 
-+	 */
-+		
-+	size -= (int)reclen;
-+	offset += reclen;
-+
-+	/* Read the next record type */
-+	ptr = buffer;
-+	if (_nvram_read(nv_buf, ptr,offset,1) != 1)
-+	    goto error;
-+	}
-+
-+error:
-+    return NULL;
-+
-+}
-+
---- a/drivers/firmware/broadcom/bcm47xx_nvram.c
-+++ b/drivers/firmware/broadcom/bcm47xx_nvram.c
-@@ -37,6 +37,8 @@ struct nvram_header {
- static char nvram_buf[NVRAM_SPACE];
- static size_t nvram_len;
- static const u32 nvram_sizes[] = {0x6000, 0x8000, 0xF000, 0x10000};
-+static int cfe_env;
-+extern char *cfe_env_get(char *nv_buf, const char *name);
- 
- static u32 find_nvram_size(void __iomem *end)
- {
-@@ -56,7 +58,9 @@ static u32 find_nvram_size(void __iomem
- static int nvram_find_and_copy(void __iomem *iobase, u32 lim)
- {
- 	struct nvram_header __iomem *header;
-+	int i;
- 	u32 off;
-+	u32 *src, *dst;
- 	u32 size;
- 
- 	if (nvram_len) {
-@@ -64,6 +68,26 @@ static int nvram_find_and_copy(void __io
- 		return -EEXIST;
- 	}
- 
-+	cfe_env = 0;
-+
-+	/* XXX: hack for supporting the CFE environment stuff on WGT634U */
-+	if (lim >= 8 * 1024 * 1024) {
-+		src = (u32 *)(iobase + 8 * 1024 * 1024 - 0x2000);
-+		dst = (u32 *)nvram_buf;
-+
-+		if ((*src & 0xff00ff) == 0x000001) {
-+			printk("early_nvram_init: WGT634U NVRAM found.\n");
-+
-+			for (i = 0; i < 0x1ff0; i++) {
-+				if (*src == 0xFFFFFFFF)
-+					break;
-+				*dst++ = *src++;
-+			}
-+			cfe_env = 1;
-+			return 0;
-+		}
-+	}
-+
- 	/* TODO: when nvram is on nand flash check for bad blocks first. */
- 	off = FLASH_MIN;
- 	while (off <= lim) {
-@@ -174,6 +198,13 @@ int bcm47xx_nvram_getenv(const char *nam
- 	if (!name)
- 		return -EINVAL;
- 
-+	if (cfe_env) {
-+		value = cfe_env_get(nvram_buf, name);
-+		if (!value)
-+			return -ENOENT;
-+		return snprintf(val, val_len, "%s", value);
-+	}
-+
- 	if (!nvram_len) {
- 		err = nvram_init();
- 		if (err)

target/linux/bcm47xx/patches-4.19/830-huawei_e970_support.patch

@@ -1,101 +0,0 @@
---- a/arch/mips/bcm47xx/setup.c
-+++ b/arch/mips/bcm47xx/setup.c
-@@ -37,6 +37,7 @@
- #include <linux/ssb/ssb.h>
- #include <linux/ssb/ssb_embedded.h>
- #include <linux/bcma/bcma_soc.h>
-+#include <linux/old_gpio_wdt.h>
- #include <asm/bootinfo.h>
- #include <asm/idle.h>
- #include <asm/prom.h>
-@@ -254,6 +255,33 @@ static struct fixed_phy_status bcm47xx_f
- 	.duplex	= DUPLEX_FULL,
- };
- 
-+static struct gpio_wdt_platform_data gpio_wdt_data;
-+
-+static struct platform_device gpio_wdt_device = {
-+	.name			= "gpio-wdt",
-+	.id			= 0,
-+	.dev			= {
-+		.platform_data	= &gpio_wdt_data,
-+	},
-+};
-+
-+static int __init bcm47xx_register_gpio_watchdog(void)
-+{
-+	enum bcm47xx_board board = bcm47xx_board_get();
-+
-+	switch (board) {
-+	case BCM47XX_BOARD_HUAWEI_E970:
-+		pr_info("bcm47xx: detected Huawei E970 or similar, starting early gpio_wdt timer\n");
-+		gpio_wdt_data.gpio = 7;
-+		gpio_wdt_data.interval = HZ;
-+		gpio_wdt_data.first_interval = HZ / 5;
-+		return platform_device_register(&gpio_wdt_device);
-+	default:
-+		/* Nothing to do */
-+		return 0;
-+	}
-+}
-+
- static int __init bcm47xx_register_bus_complete(void)
- {
- 	switch (bcm47xx_bus_type) {
-@@ -275,6 +303,7 @@ static int __init bcm47xx_register_bus_c
- 	bcm47xx_workarounds();
- 
- 	fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status, -1);
-+	bcm47xx_register_gpio_watchdog();
- 	return 0;
- }
- device_initcall(bcm47xx_register_bus_complete);
---- a/arch/mips/configs/bcm47xx_defconfig
-+++ b/arch/mips/configs/bcm47xx_defconfig
-@@ -66,6 +66,7 @@ CONFIG_HW_RANDOM=y
- CONFIG_GPIO_SYSFS=y
- CONFIG_WATCHDOG=y
- CONFIG_BCM47XX_WDT=y
-+CONFIG_GPIO_WDT=y
- CONFIG_SSB_DRIVER_GIGE=y
- CONFIG_BCMA_DRIVER_GMAC_CMN=y
- CONFIG_USB=y
---- a/drivers/ssb/embedded.c
-+++ b/drivers/ssb/embedded.c
-@@ -34,11 +34,36 @@ int ssb_watchdog_timer_set(struct ssb_bu
- }
- EXPORT_SYMBOL(ssb_watchdog_timer_set);
- 
-+#ifdef CONFIG_BCM47XX
-+#include <bcm47xx_board.h>
-+
-+static bool ssb_watchdog_supported(void)
-+{
-+	enum bcm47xx_board board = bcm47xx_board_get();
-+
-+	/* The Huawei E970 has a hardware watchdog using a GPIO */
-+	switch (board) {
-+	case BCM47XX_BOARD_HUAWEI_E970:
-+		return false;
-+	default:
-+		return true;
-+	}
-+}
-+#else
-+static bool ssb_watchdog_supported(void)
-+{
-+	return true;
-+}
-+#endif
-+
- int ssb_watchdog_register(struct ssb_bus *bus)
- {
- 	struct bcm47xx_wdt wdt = {};
- 	struct platform_device *pdev;
- 
-+	if (!ssb_watchdog_supported())
-+		return 0;
-+
- 	if (ssb_chipco_available(&bus->chipco)) {
- 		wdt.driver_data = &bus->chipco;
- 		wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;

target/linux/bcm47xx/patches-4.19/831-old_gpio_wdt.patch

@@ -1,360 +0,0 @@
-This generic GPIO watchdog is used on Huawei E970 (bcm47xx)
-
-Signed-off-by: Mathias Adam <[email protected]>
-
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -1498,6 +1498,15 @@ config WDT_MTX1
- 	  Hardware driver for the MTX-1 boards. This is a watchdog timer that
- 	  will reboot the machine after a 100 seconds timer expired.
- 
-+config GPIO_WDT
-+	tristate "GPIO Hardware Watchdog"
-+ 	help
-+	  Hardware driver for GPIO-controlled watchdogs. GPIO pin and
-+	  toggle interval settings are platform-specific. The driver
-+	  will stop toggling the GPIO (i.e. machine reboots) after a
-+	  100 second timer expired and no process has written to
-+	  /dev/watchdog during that time.
-+
- config PNX833X_WDT
- 	tristate "PNX833x Hardware Watchdog"
- 	depends on SOC_PNX8335
---- a/drivers/watchdog/Makefile
-+++ b/drivers/watchdog/Makefile
-@@ -154,6 +154,7 @@ obj-$(CONFIG_RC32434_WDT) += rc32434_wdt
- obj-$(CONFIG_INDYDOG) += indydog.o
- obj-$(CONFIG_JZ4740_WDT) += jz4740_wdt.o
- obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o
-+obj-$(CONFIG_GPIO_WDT) += old_gpio_wdt.o
- obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o
- obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
- obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
---- /dev/null
-+++ b/drivers/watchdog/old_gpio_wdt.c
-@@ -0,0 +1,301 @@
-+/*
-+ *      Driver for GPIO-controlled Hardware Watchdogs.
-+ *
-+ *      Copyright (C) 2013 Mathias Adam <[email protected]>
-+ *
-+ *      Replaces mtx1_wdt (driver for the MTX-1 Watchdog):
-+ *
-+ *      (C) Copyright 2005 4G Systems <[email protected]>,
-+ *                              All Rights Reserved.
-+ *                              http://www.4g-systems.biz
-+ *
-+ *      (C) Copyright 2007 OpenWrt.org, Florian Fainelli <[email protected]>
-+ *
-+ *      This program is free software; you can redistribute it and/or
-+ *      modify it under the terms of the GNU General Public License
-+ *      as published by the Free Software Foundation; either version
-+ *      2 of the License, or (at your option) any later version.
-+ *
-+ *      Neither Michael Stickel nor 4G Systems admit liability nor provide
-+ *      warranty for any of this software. This material is provided
-+ *      "AS-IS" and at no charge.
-+ *
-+ *      (c) Copyright 2005    4G Systems <[email protected]>
-+ *
-+ *      Release 0.01.
-+ *      Author: Michael Stickel  [email protected]
-+ *
-+ *      Release 0.02.
-+ *      Author: Florian Fainelli [email protected]
-+ *              use the Linux watchdog/timer APIs
-+ *
-+ *      Release 0.03.
-+ *      Author: Mathias Adam <[email protected]>
-+ *              make it a generic gpio watchdog driver
-+ *
-+ *      The Watchdog is configured to reset the MTX-1
-+ *      if it is not triggered for 100 seconds.
-+ *      It should not be triggered more often than 1.6 seconds.
-+ *
-+ *      A timer triggers the watchdog every 5 seconds, until
-+ *      it is opened for the first time. After the first open
-+ *      it MUST be triggered every 2..95 seconds.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/types.h>
-+#include <linux/errno.h>
-+#include <linux/miscdevice.h>
-+#include <linux/fs.h>
-+#include <linux/init.h>
-+#include <linux/ioport.h>
-+#include <linux/timer.h>
-+#include <linux/completion.h>
-+#include <linux/jiffies.h>
-+#include <linux/watchdog.h>
-+#include <linux/platform_device.h>
-+#include <linux/io.h>
-+#include <linux/uaccess.h>
-+#include <linux/gpio.h>
-+#include <linux/old_gpio_wdt.h>
-+
-+static int ticks = 100 * HZ;
-+
-+static struct {
-+	struct completion stop;
-+	spinlock_t lock;
-+	int running;
-+	struct timer_list timer;
-+	int queue;
-+	int default_ticks;
-+	unsigned long inuse;
-+	unsigned gpio;
-+	unsigned int gstate;
-+	int interval;
-+	int first_interval;
-+} gpio_wdt_device;
-+
-+static void gpio_wdt_trigger(struct timer_list *unused)
-+{
-+	spin_lock(&gpio_wdt_device.lock);
-+	if (gpio_wdt_device.running && ticks > 0)
-+		ticks -= gpio_wdt_device.interval;
-+
-+	/* toggle wdt gpio */
-+	gpio_wdt_device.gstate = !gpio_wdt_device.gstate;
-+	gpio_set_value(gpio_wdt_device.gpio, gpio_wdt_device.gstate);
-+
-+	if (gpio_wdt_device.queue && ticks > 0)
-+		mod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.interval);
-+	else
-+		complete(&gpio_wdt_device.stop);
-+	spin_unlock(&gpio_wdt_device.lock);
-+}
-+
-+static void gpio_wdt_reset(void)
-+{
-+	ticks = gpio_wdt_device.default_ticks;
-+}
-+
-+
-+static void gpio_wdt_start(void)
-+{
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&gpio_wdt_device.lock, flags);
-+	if (!gpio_wdt_device.queue) {
-+		gpio_wdt_device.queue = 1;
-+		gpio_wdt_device.gstate = 1;
-+		gpio_set_value(gpio_wdt_device.gpio, 1);
-+		mod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.first_interval);
-+	}
-+	gpio_wdt_device.running++;
-+	spin_unlock_irqrestore(&gpio_wdt_device.lock, flags);
-+}
-+
-+static int gpio_wdt_stop(void)
-+{
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&gpio_wdt_device.lock, flags);
-+	if (gpio_wdt_device.queue) {
-+		gpio_wdt_device.queue = 0;
-+		gpio_wdt_device.gstate = 0;
-+		gpio_set_value(gpio_wdt_device.gpio, 0);
-+	}
-+	ticks = gpio_wdt_device.default_ticks;
-+	spin_unlock_irqrestore(&gpio_wdt_device.lock, flags);
-+	return 0;
-+}
-+
-+/* Filesystem functions */
-+
-+static int gpio_wdt_open(struct inode *inode, struct file *file)
-+{
-+	if (test_and_set_bit(0, &gpio_wdt_device.inuse))
-+		return -EBUSY;
-+	return nonseekable_open(inode, file);
-+}
-+
-+
-+static int gpio_wdt_release(struct inode *inode, struct file *file)
-+{
-+	clear_bit(0, &gpio_wdt_device.inuse);
-+	return 0;
-+}
-+
-+static long gpio_wdt_ioctl(struct file *file, unsigned int cmd,
-+							unsigned long arg)
-+{
-+	void __user *argp = (void __user *)arg;
-+	int __user *p = (int __user *)argp;
-+	unsigned int value;
-+	static const struct watchdog_info ident = {
-+		.options = WDIOF_CARDRESET,
-+		.identity = "GPIO WDT",
-+	};
-+
-+	switch (cmd) {
-+	case WDIOC_GETSUPPORT:
-+		if (copy_to_user(argp, &ident, sizeof(ident)))
-+			return -EFAULT;
-+		break;
-+	case WDIOC_GETSTATUS:
-+	case WDIOC_GETBOOTSTATUS:
-+		put_user(0, p);
-+		break;
-+	case WDIOC_SETOPTIONS:
-+		if (get_user(value, p))
-+			return -EFAULT;
-+		if (value & WDIOS_ENABLECARD)
-+			gpio_wdt_start();
-+		else if (value & WDIOS_DISABLECARD)
-+			gpio_wdt_stop();
-+		else
-+			return -EINVAL;
-+		return 0;
-+	case WDIOC_KEEPALIVE:
-+		gpio_wdt_reset();
-+		break;
-+	default:
-+		return -ENOTTY;
-+	}
-+	return 0;
-+}
-+
-+
-+static ssize_t gpio_wdt_write(struct file *file, const char *buf,
-+						size_t count, loff_t *ppos)
-+{
-+	if (!count)
-+		return -EIO;
-+	gpio_wdt_reset();
-+	return count;
-+}
-+
-+static const struct file_operations gpio_wdt_fops = {
-+	.owner		= THIS_MODULE,
-+	.llseek		= no_llseek,
-+	.unlocked_ioctl	= gpio_wdt_ioctl,
-+	.open		= gpio_wdt_open,
-+	.write		= gpio_wdt_write,
-+	.release	= gpio_wdt_release,
-+};
-+
-+
-+static struct miscdevice gpio_wdt_misc = {
-+	.minor	= WATCHDOG_MINOR,
-+	.name	= "watchdog",
-+	.fops	= &gpio_wdt_fops,
-+};
-+
-+
-+static int gpio_wdt_probe(struct platform_device *pdev)
-+{
-+	int ret;
-+	struct gpio_wdt_platform_data *gpio_wdt_data = pdev->dev.platform_data;
-+
-+	gpio_wdt_device.gpio = gpio_wdt_data->gpio;
-+	gpio_wdt_device.interval = gpio_wdt_data->interval;
-+	gpio_wdt_device.first_interval = gpio_wdt_data->first_interval;
-+	if (gpio_wdt_device.first_interval <= 0) {
-+		gpio_wdt_device.first_interval = gpio_wdt_device.interval;
-+	}
-+
-+	ret = gpio_request(gpio_wdt_device.gpio, "gpio-wdt");
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "failed to request gpio");
-+		return ret;
-+	}
-+
-+	spin_lock_init(&gpio_wdt_device.lock);
-+	init_completion(&gpio_wdt_device.stop);
-+	gpio_wdt_device.queue = 0;
-+	clear_bit(0, &gpio_wdt_device.inuse);
-+	timer_setup(&gpio_wdt_device.timer, gpio_wdt_trigger, 0L);
-+	gpio_wdt_device.default_ticks = ticks;
-+
-+	gpio_wdt_start();
-+	dev_info(&pdev->dev, "GPIO Hardware Watchdog driver (gpio=%i interval=%i/%i)\n",
-+		gpio_wdt_data->gpio, gpio_wdt_data->first_interval, gpio_wdt_data->interval);
-+	return 0;
-+}
-+
-+static int gpio_wdt_remove(struct platform_device *pdev)
-+{
-+	/* FIXME: do we need to lock this test ? */
-+	if (gpio_wdt_device.queue) {
-+		gpio_wdt_device.queue = 0;
-+		wait_for_completion(&gpio_wdt_device.stop);
-+	}
-+
-+	gpio_free(gpio_wdt_device.gpio);
-+	misc_deregister(&gpio_wdt_misc);
-+	return 0;
-+}
-+
-+static struct platform_driver gpio_wdt_driver = {
-+	.probe = gpio_wdt_probe,
-+	.remove = gpio_wdt_remove,
-+	.driver.name = "gpio-wdt",
-+	.driver.owner = THIS_MODULE,
-+};
-+
-+static int __init gpio_wdt_init(void)
-+{
-+	return platform_driver_register(&gpio_wdt_driver);
-+}
-+arch_initcall(gpio_wdt_init);
-+
-+/*
-+ * We do wdt initialization in two steps: arch_initcall probes the wdt
-+ * very early to start pinging the watchdog (misc devices are not yet
-+ * available), and later module_init() just registers the misc device.
-+ */
-+static int gpio_wdt_init_late(void)
-+{
-+	int ret;
-+
-+	ret = misc_register(&gpio_wdt_misc);
-+	if (ret < 0) {
-+		pr_err("GPIO_WDT: failed to register misc device\n");
-+		return ret;
-+	}
-+	return 0;
-+}
-+#ifndef MODULE
-+module_init(gpio_wdt_init_late);
-+#endif
-+
-+static void __exit gpio_wdt_exit(void)
-+{
-+	platform_driver_unregister(&gpio_wdt_driver);
-+}
-+module_exit(gpio_wdt_exit);
-+
-+MODULE_AUTHOR("Michael Stickel, Florian Fainelli, Mathias Adam");
-+MODULE_DESCRIPTION("Driver for GPIO hardware watchdogs");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
-+MODULE_ALIAS("platform:gpio-wdt");
---- /dev/null
-+++ b/include/linux/old_gpio_wdt.h
-@@ -0,0 +1,21 @@
-+/*
-+ *  Definitions for the GPIO watchdog driver
-+ *
-+ *  Copyright (C) 2013 Mathias Adam <[email protected]>
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License version 2 as
-+ *  published by the Free Software Foundation.
-+ *
-+ */
-+
-+#ifndef _GPIO_WDT_H_
-+#define _GPIO_WDT_H_
-+
-+struct gpio_wdt_platform_data {
-+	int	gpio;		/* GPIO line number */
-+	int	interval;	/* watchdog reset interval in system ticks */
-+	int	first_interval;	/* first wd reset interval in system ticks */
-+};
-+
-+#endif /* _GPIO_WDT_H_ */

target/linux/bcm47xx/patches-4.19/900-ssb-reject-PCI-writes-setting-CardBus-bridge-resourc.patch

@@ -1,30 +0,0 @@
-From 5c81397a0147ea59c778d1de14ef54e2268221f6 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <[email protected]>
-Date: Wed, 8 Apr 2015 06:58:11 +0200
-Subject: [PATCH] ssb: reject PCI writes setting CardBus bridge resources
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-If SoC has a CardBus we can set resources of device at slot 1 only. It's
-impossigle to set bridge resources as it simply overwrites device 1
-configuration and usually results in Data bus error-s.
-
-Signed-off-by: Rafał Miłecki <[email protected]>
----
- drivers/ssb/driver_pcicore.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/ssb/driver_pcicore.c
-+++ b/drivers/ssb/driver_pcicore.c
-@@ -164,6 +164,10 @@ static int ssb_extpci_write_config(struc
- 	WARN_ON(!pc->hostmode);
- 	if (unlikely(len != 1 && len != 2 && len != 4))
- 		goto out;
-+	/* CardBus SoCs allow configuring dev 1 resources only */
-+	if (extpci_core->cardbusmode && dev != 1 &&
-+	    off >= PCI_BASE_ADDRESS_0 && off <= PCI_BASE_ADDRESS_5)
-+		goto out;
- 	addr = get_cfgspace_addr(pc, bus, dev, func, off);
- 	if (unlikely(!addr))
- 		goto out;

target/linux/bcm47xx/patches-4.19/940-bcm47xx-yenta.patch

@@ -1,46 +0,0 @@
---- a/drivers/pcmcia/yenta_socket.c
-+++ b/drivers/pcmcia/yenta_socket.c
-@@ -920,6 +920,8 @@ static unsigned int yenta_probe_irq(stru
- 	 * Probe for usable interrupts using the force
- 	 * register to generate bogus card status events.
- 	 */
-+#ifndef CONFIG_BCM47XX
-+	/* WRT54G3G does not like this */
- 	cb_writel(socket, CB_SOCKET_EVENT, -1);
- 	cb_writel(socket, CB_SOCKET_MASK, CB_CSTSMASK);
- 	reg = exca_readb(socket, I365_CSCINT);
-@@ -935,6 +937,7 @@ static unsigned int yenta_probe_irq(stru
- 	}
- 	cb_writel(socket, CB_SOCKET_MASK, 0);
- 	exca_writeb(socket, I365_CSCINT, reg);
-+#endif
- 
- 	mask = probe_irq_mask(val) & 0xffff;
- 
-@@ -1019,6 +1022,10 @@ static void yenta_get_socket_capabilitie
- 	else
- 		socket->socket.irq_mask = 0;
- 
-+	/* irq mask probing is broken for the WRT54G3G */
-+	if (socket->socket.irq_mask == 0)
-+		socket->socket.irq_mask = 0x6f8;
-+
- 	dev_info(&socket->dev->dev, "ISA IRQ mask 0x%04x, PCI irq %d\n",
- 		 socket->socket.irq_mask, socket->cb_irq);
- }
-@@ -1250,6 +1257,15 @@ static int yenta_probe(struct pci_dev *d
- 	dev_info(&dev->dev, "Socket status: %08x\n",
- 		 cb_readl(socket, CB_SOCKET_STATE));
- 
-+	/* Generate an interrupt on card insert/remove */
-+	config_writew(socket, CB_SOCKET_MASK, CB_CSTSMASK | CB_CDMASK);
-+
-+	/* Set up Multifunction Routing Status Register */
-+	config_writew(socket, 0x8C, 0x1000 /* MFUNC3 to GPIO3 */ | 0x2 /* MFUNC0 to INTA */);
-+
-+	/* Switch interrupts to parallelized */
-+	config_writeb(socket, 0x92, 0x64);
-+
- 	yenta_fixup_parent_bridge(dev->subordinate);
- 
- 	/* Register it with the pcmcia layer.. */

target/linux/bcm47xx/patches-4.19/976-ssb_increase_pci_delay.patch

@@ -1,11 +0,0 @@
---- a/drivers/ssb/driver_pcicore.c
-+++ b/drivers/ssb/driver_pcicore.c
-@@ -390,7 +390,7 @@ static void ssb_pcicore_init_hostmode(st
- 	set_io_port_base(ssb_pcicore_controller.io_map_base);
- 	/* Give some time to the PCI controller to configure itself with the new
- 	 * values. Not waiting at this point causes crashes of the machine. */
--	mdelay(10);
-+	mdelay(300);
- 	register_pci_controller(&ssb_pcicore_controller);
- }
- 

target/linux/bcm47xx/patches-4.19/999-wl_exports.patch

@@ -1,22 +0,0 @@
---- a/drivers/firmware/broadcom/bcm47xx_nvram.c
-+++ b/drivers/firmware/broadcom/bcm47xx_nvram.c
-@@ -34,7 +34,8 @@ struct nvram_header {
- 	u32 config_ncdl;	/* ncdl values for memc */
- };
- 
--static char nvram_buf[NVRAM_SPACE];
-+char nvram_buf[NVRAM_SPACE];
-+EXPORT_SYMBOL(nvram_buf);
- static size_t nvram_len;
- static const u32 nvram_sizes[] = {0x6000, 0x8000, 0xF000, 0x10000};
- static int cfe_env;
---- a/arch/mips/mm/cache.c
-+++ b/arch/mips/mm/cache.c
-@@ -64,6 +64,7 @@ void (*_dma_cache_wback)(unsigned long s
- void (*_dma_cache_inv)(unsigned long start, unsigned long size);
- 
- EXPORT_SYMBOL(_dma_cache_wback_inv);
-+EXPORT_SYMBOL(_dma_cache_inv);
- 
- #endif /* CONFIG_DMA_NONCOHERENT */
- 

target/linux/bcm53xx/config-4.19

@@ -1,362 +0,0 @@
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_BCM=y
-CONFIG_ARCH_BCM_5301X=y
-CONFIG_ARCH_BCM_53573=y
-# CONFIG_ARCH_BCM_HR2 is not set
-CONFIG_ARCH_BCM_IPROC=y
-CONFIG_ARCH_CLOCKSOURCE_DATA=y
-CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
-CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
-CONFIG_ARCH_HAS_KCOV=y
-CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
-CONFIG_ARCH_HAS_PHYS_TO_DMA=y
-CONFIG_ARCH_HAS_SET_MEMORY=y
-CONFIG_ARCH_HAS_SG_CHAIN=y
-CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
-CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
-CONFIG_ARM_ERRATA_754322=y
-CONFIG_ARM_ERRATA_764369=y
-CONFIG_ARM_ERRATA_775420=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GLOBAL_TIMER=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-# CONFIG_ARM_LPAE is not set
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_SP805_WATCHDOG is not set
-CONFIG_ARM_THUMB=y
-# CONFIG_ARM_THUMBEE is not set
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BCM47XX_NVRAM=y
-CONFIG_BCM47XX_SPROM=y
-CONFIG_BCM47XX_WDT=y
-CONFIG_BCMA=y
-CONFIG_BCMA_BLOCKIO=y
-CONFIG_BCMA_DEBUG=y
-CONFIG_BCMA_DRIVER_GMAC_CMN=y
-CONFIG_BCMA_DRIVER_GPIO=y
-CONFIG_BCMA_DRIVER_PCI=y
-CONFIG_BCMA_HOST_PCI=y
-CONFIG_BCMA_HOST_PCI_POSSIBLE=y
-CONFIG_BCMA_HOST_SOC=y
-CONFIG_BCMA_SFLASH=y
-CONFIG_BCM_NET_PHYLIB=y
-CONFIG_BCM_NS_THERMAL=y
-CONFIG_BGMAC=y
-CONFIG_BGMAC_BCMA=y
-# CONFIG_BGMAC_PLATFORM is not set
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOUNCE=y
-CONFIG_BROADCOM_PHY=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
-CONFIG_CLKSRC_MMIO=y
-# CONFIG_CLK_BCM_NS2 is not set
-CONFIG_CLK_BCM_NSP=y
-# CONFIG_CLK_BCM_SR is not set
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_IPROC=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_ACOMP2=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_NULL2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_BCM_5301X=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
-CONFIG_DEBUG_UART_8250=y
-# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set
-CONFIG_DEBUG_UART_8250_SHIFT=0
-CONFIG_DEBUG_UART_PHYS=0x18000300
-CONFIG_DEBUG_UART_VIRT=0xf1000300
-CONFIG_DEBUG_UNCOMPRESS=y
-CONFIG_DEBUG_USER=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EXTCON=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_POINTER=y
-# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_74X164=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_ARCH_AUDITSYSCALL=y
-CONFIG_HAVE_ARCH_BITREVERSE=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ARM_ARCH_TIMER=y
-CONFIG_HAVE_ARM_SCU=y
-CONFIG_HAVE_ARM_SMCCC=y
-CONFIG_HAVE_ARM_TWD=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_HAVE_EBPF_JIT=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_OPTPROBES=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_RSEQ=y
-CONFIG_HAVE_SMP=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MDIO_BCM_IPROC=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_BUS_MUX=y
-# CONFIG_MDIO_BUS_MUX_BCM_IPROC is not set
-CONFIG_MDIO_BUS_MUX_MMIOREG=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_MIGRATION=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_BCM47XXSFLASH=y
-CONFIG_MTD_BCM47XX_PARTS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_BRCMNAND=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_PARSER_TRX=y
-# CONFIG_MTD_PHYSMAP_OF is not set
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_SEAMA_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-# CONFIG_MTD_UBI_FASTMAP is not set
-# CONFIG_MTD_UBI_GLUEBI is not set
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NO_BOOTMEM=y
-CONFIG_NR_CPUS=2
-CONFIG_NVMEM=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_NET=y
-CONFIG_OF_RESERVED_MEM=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PCI=y
-CONFIG_PCIE_IPROC=y
-CONFIG_PCIE_IPROC_BCMA=y
-# CONFIG_PCIE_IPROC_PLATFORM is not set
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-# CONFIG_PCI_V3_SEMI is not set
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-# CONFIG_PHY_BCM_NS_USB2 is not set
-# CONFIG_PHY_BCM_NS_USB3 is not set
-# CONFIG_PHY_BCM_SR_PCIE is not set
-# CONFIG_PHY_BRCM_SATA is not set
-# CONFIG_PHY_NS2_USB_DRD is not set
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_IPROC_GPIO is not set
-CONFIG_PINCTRL_NS=y
-# CONFIG_PINCTRL_NS2_MUX is not set
-# CONFIG_PL310_ERRATA_588369 is not set
-# CONFIG_PL310_ERRATA_727915 is not set
-# CONFIG_PL310_ERRATA_753970 is not set
-# CONFIG_PL310_ERRATA_769419 is not set
-CONFIG_RATIONAL=y
-CONFIG_RCU_NEED_SEGCBLIST=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_REFCOUNT_FULL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_SERIAL_8250_FSL=y
-# CONFIG_SERIAL_AMBA_PL011 is not set
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BCM_QSPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_GPIO=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SRCU=y
-CONFIG_SWCONFIG=y
-CONFIG_SWCONFIG_B53=y
-# CONFIG_SWCONFIG_B53_MMAP_DRIVER is not set
-CONFIG_SWCONFIG_B53_PHY_DRIVER=y
-CONFIG_SWCONFIG_B53_PHY_FIXUP=y
-CONFIG_SWCONFIG_B53_SRAB_DRIVER=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-CONFIG_UBIFS_FS_LZO=y
-CONFIG_UBIFS_FS_ZLIB=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-# CONFIG_VFP is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y

target/linux/bcm53xx/patches-4.19/030-v4.20-0001-ARM-dts-BCM5301X-Specify-flash-partitions.patch

@@ -1,167 +0,0 @@
-From b0465fdfdd7e7c1afe2fae1cb36b94e1ce89732e Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <[email protected]>
-Date: Sat, 28 Jul 2018 14:13:57 +0200
-Subject: [PATCH] ARM: dts: BCM5301X: Specify flash partitions
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Most devices use Broadcom standard partitions which allows them to be
-described with the "brcm,bcm947xx-cfe-partitions". Exceptions are:
-1) TP-LINK devices which use "os-image" partition with TRX containing
-   kernel only + separated rootfs partition.
-2) Asus RT-AC87U with custom "asus" partition.
-
-This commit also removes undocumented and unsupported linux,part-probe
-binding which got accidentally upstreamed while describing SPI
-controller.
-
-Signed-off-by: Rafał Miłecki <[email protected]>
-Signed-off-by: Florian Fainelli <[email protected]>
----
- arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts | 28 +++++++++++++++++++
- arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts        | 31 ++++++++++++++++++++++
- arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts  | 28 +++++++++++++++++++
- arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi           |  4 +++
- arch/arm/boot/dts/bcm5301x.dtsi                    |  5 +++-
- 5 files changed, 95 insertions(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
-+++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
-@@ -94,6 +94,34 @@
- 
- &spi_nor {
- 	status = "okay";
-+
-+	partitions {
-+		compatible = "fixed-partitions";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+
-+		boot@0 {
-+			label = "boot";
-+			reg = <0x000000 0x040000>;
-+			read-only;
-+		};
-+
-+		os-image@100000 {
-+			label = "os-image";
-+			reg = <0x040000 0x200000>;
-+			compatible = "brcm,trx";
-+		};
-+
-+		rootfs@240000 {
-+			label = "rootfs";
-+			reg = <0x240000 0xc00000>;
-+		};
-+
-+		nvram@ff0000 {
-+			label = "nvram";
-+			reg = <0xff0000 0x010000>;
-+		};
-+	};
- };
- 
- &usb2 {
---- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
-+++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
-@@ -66,3 +66,34 @@
- &usb3_phy {
- 	status = "okay";
- };
-+
-+&nandcs {
-+	partitions {
-+		compatible = "fixed-partitions";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+
-+		boot@0 {
-+			label = "boot";
-+			reg = <0x00000000 0x00080000>;
-+			read-only;
-+		};
-+
-+		nvram@80000 {
-+			label = "nvram";
-+			reg = <0x00080000 0x00180000>;
-+		};
-+
-+		firmware@200000 {
-+			label = "firmware";
-+			reg = <0x00200000 0x07cc0000>;
-+			compatible = "brcm,trx";
-+		};
-+
-+		asus@7ec0000 {
-+			label = "asus";
-+			reg = <0x07ec0000 0x00140000>;
-+			read-only;
-+		};
-+	};
-+};
---- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
-+++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
-@@ -103,6 +103,34 @@
- 
- &spi_nor {
- 	status = "okay";
-+
-+	partitions {
-+		compatible = "fixed-partitions";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+
-+		boot@0 {
-+			label = "boot";
-+			reg = <0x000000 0x040000>;
-+			read-only;
-+		};
-+
-+		os-image@100000 {
-+			label = "os-image";
-+			reg = <0x040000 0x200000>;
-+			compatible = "brcm,trx";
-+		};
-+
-+		rootfs@240000 {
-+			label = "rootfs";
-+			reg = <0x240000 0xc00000>;
-+		};
-+
-+		nvram@ff0000 {
-+			label = "nvram";
-+			reg = <0xff0000 0x010000>;
-+		};
-+	};
- };
- 
- &usb3_phy {
---- a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi
-+++ b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi
-@@ -12,6 +12,10 @@
- 			reg = <0>;
- 			#address-cells = <1>;
- 			#size-cells = <1>;
-+
-+			partitions {
-+				compatible = "brcm,bcm947xx-cfe-partitions";
-+			};
- 		};
- 	};
- };
---- a/arch/arm/boot/dts/bcm5301x.dtsi
-+++ b/arch/arm/boot/dts/bcm5301x.dtsi
-@@ -475,8 +475,11 @@
- 			compatible = "jedec,spi-nor";
- 			reg = <0>;
- 			spi-max-frequency = <20000000>;
--			linux,part-probe = "ofpart", "bcm47xxpart";
- 			status = "disabled";
-+
-+			partitions {
-+				compatible = "brcm,bcm947xx-cfe-partitions";
-+			};
- 		};
- 	};
- 

target/linux/bcm53xx/patches-4.19/031-v4.21-0001-ARM-dts-BCM5301X-Relicense-BCM47081-BCM4709-files-to.patch

@@ -1,58 +0,0 @@
-From 26ff86f7794b9466481ccf29ac79925d327f106d Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <[email protected]>
-Date: Thu, 20 Sep 2018 13:18:47 +0200
-Subject: [PATCH] ARM: dts: BCM5301X: Relicense BCM47081/BCM4709 files to the
- GPL 2.0+ / MIT
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This matches licensing used by other BCM5301X files and is preferred as:
-1) GPL 2.0+ makes it clearly compatible with Linux kernel
-2) MIT is also permissive but preferred over ISC
-
-Both files were fully developed by me. Commits touching them were signed
-by Florian and Hauke due to submitting process only.
-
-Signed-off-by: Rafał Miłecki <[email protected]>
-Signed-off-by: Florian Fainelli <[email protected]>
----
- arch/arm/boot/dts/bcm47081.dtsi | 13 +------------
- arch/arm/boot/dts/bcm4709.dtsi  |  3 +--
- 2 files changed, 2 insertions(+), 14 deletions(-)
-
---- a/arch/arm/boot/dts/bcm47081.dtsi
-+++ b/arch/arm/boot/dts/bcm47081.dtsi
-@@ -1,20 +1,9 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
- /*
-  * Broadcom BCM470X / BCM5301X ARM platform code.
-  * DTS for BCM47081 SoC.
-  *
-  * Copyright © 2014 Rafał Miłecki <[email protected]>
-- *
-- * Permission to use, copy, modify, and/or distribute this software for any
-- * purpose with or without fee is hereby granted, provided that the above
-- * copyright notice and this permission notice appear in all copies.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
-- * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
-- * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
-- * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
-- * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
-- * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
-- * PERFORMANCE OF THIS SOFTWARE.
-  */
- 
- #include "bcm5301x.dtsi"
---- a/arch/arm/boot/dts/bcm4709.dtsi
-+++ b/arch/arm/boot/dts/bcm4709.dtsi
-@@ -1,7 +1,6 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
- /*
-  * Copyright (C) 2016 Rafał Miłecki <[email protected]>
-- *
-- * Licensed under the ISC license.
-  */
- 
- #include "bcm4708.dtsi"

target/linux/bcm53xx/patches-4.19/031-v4.21-0002-ARM-dts-BCM5301X-Relicense-BCM47094-file-to-the-GPL-.patch

@@ -1,33 +0,0 @@
-From d10967344375026ca8762b6080dec2585d895906 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <[email protected]>
-Date: Thu, 20 Sep 2018 13:20:19 +0200
-Subject: [PATCH] ARM: dts: BCM5301X: Relicense BCM47094 file to the GPL 2.0+ /
- MIT
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This matches licensing used by other BCM5301X files and is preferred as:
-1) GPL 2.0+ makes it clearly compatible with Linux kernel
-2) MIT is also permissive but preferred over ISC
-
-This file has been developed by me & once modified by Vivek.
-
-Signed-off-by: Rafał Miłecki <[email protected]>
-Acked-by: Vivek Unune <[email protected]>
-Signed-off-by: Florian Fainelli <[email protected]>
----
- arch/arm/boot/dts/bcm47094.dtsi | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
---- a/arch/arm/boot/dts/bcm47094.dtsi
-+++ b/arch/arm/boot/dts/bcm47094.dtsi
-@@ -1,7 +1,6 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
- /*
-  * Copyright (C) 2016 Rafał Miłecki <[email protected]>
-- *
-- * Licensed under the ISC license.
-  */
- 
- #include "bcm4708.dtsi"

target/linux/bcm53xx/patches-4.19/031-v4.21-0003-ARM-dts-BCM53573-Relicense-Tenda-AC9-file-to-the-GPL.patch

@@ -1,32 +0,0 @@
-From 1c9001b4f69a37820862286b3bbcdde152a52dcf Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <[email protected]>
-Date: Thu, 20 Sep 2018 13:37:47 +0200
-Subject: [PATCH] ARM: dts: BCM53573: Relicense Tenda AC9 file to the GPL 2.0+
- / MIT
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This matches licensing used by most of BCM5301X files and is preferred as:
-1) GPL 2.0+ makes it clearly compatible with Linux kernel
-2) MIT is also permissive but preferred over ISC
-
-This file was fully developed by me.
-
-Signed-off-by: Rafał Miłecki <[email protected]>
-Signed-off-by: Florian Fainelli <[email protected]>
----
- arch/arm/boot/dts/bcm47189-tenda-ac9.dts | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
---- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
-+++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
-@@ -1,7 +1,6 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
- /*
-  * Copyright (C) 2016 Rafał Miłecki <[email protected]>
-- *
-- * Licensed under the ISC license.
-  */
- 
- /dts-v1/;