mediatek: adapt files and patches for Linux 6.1

With Linux 6.1 many of our downstream patches and out-of-tree files
can be removed or at least replaced by backported upstream commits.

Signed-off-by: Daniel Golle <[email protected]>
[fix CMDLINE_OVERRIDE for arm64]
Signed-off-by: Bjørn Mork <[email protected]>

target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso

@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
-	fragment@0 {
-		target-path = "/soc/mmc@11230000";
-		__overlay__ {
-			bus-width = <8>;
-			max-frequency = <200000000>;
-			cap-mmc-highspeed;
-			mmc-hs200-1_8v;
-			mmc-hs400-1_8v;
-			hs400-ds-delay = <0x14014>;
-			non-removable;
-			no-sd;
-			no-sdio;
-			status = "okay";
-		};
-	};
-};
-

target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso

@@ -1,55 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/*
- * Authors: Daniel Golle <[email protected]>
- *          Frank Wunderlich <[email protected]>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
-	fragment@0 {
-		target-path = "/soc/spi@1100a000";
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			spi_nand: spi_nand@0 {
-				compatible = "spi-nand";
-				reg = <0>;
-				spi-max-frequency = <10000000>;
-				spi-tx-buswidth = <4>;
-				spi-rx-buswidth = <4>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "bl2";
-						reg = <0x0 0x80000>;
-						read-only;
-					};
-
-					partition@80000 {
-						label = "reserved";
-						reg = <0x80000 0x300000>;
-					};
-
-					partition@380000 {
-						label = "fip";
-						reg = <0x380000 0x200000>;
-						read-only;
-					};
-
-					partition@580000 {
-						label = "ubi";
-						reg = <0x580000 0x7a80000>;
-					};
-				};
-			};
-		};
-	};
-};

target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso

@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/*
- * Authors: Daniel Golle <[email protected]>
- *          Frank Wunderlich <[email protected]>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
-	fragment@0 {
-		target-path = "/soc/spi@1100a000";
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			flash@0 {
-				compatible = "jedec,spi-nor";
-				reg = <0>;
-				spi-max-frequency = <10000000>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "bl2";
-						reg = <0x0 0x40000>;
-						read-only;
-					};
-
-					partition@40000 {
-						label = "u-boot-env";
-						reg = <0x40000 0x40000>;
-					};
-
-					partition@80000 {
-						label = "reserved2";
-						reg = <0x80000 0x80000>;
-					};
-
-					partition@100000 {
-						label = "fip";
-						reg = <0x100000 0x80000>;
-						read-only;
-					};
-
-					partition@180000 {
-						label = "recovery";
-						reg = <0x180000 0xa80000>;
-					};
-
-					partition@c00000 {
-						label = "fit";
-						reg = <0xc00000 0x1400000>;
-					};
-				};
-			};
-		};
-	};
-};

target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso

@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
-	fragment@0 {
-		target-path = "/soc/mmc@11230000";
-		__overlay__ {
-			bus-width = <4>;
-			max-frequency = <52000000>;
-			cap-sd-highspeed;
-			status = "okay";
-		};
-	};
-};
-

target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts

@@ -1,499 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Authors: Sam.Shih <[email protected]>
- *          Frank Wunderlich <[email protected]>
- *          Daniel Golle <[email protected]>
- */
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/mt65xx.h>
-
-#include "mt7986a.dtsi"
-
-/ {
-	model = "Bananapi BPI-R3";
-	chassis-type = "embedded";
-	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
-	aliases {
-		serial0 = &uart0;
-		ethernet0 = &gmac0;
-		ethernet1 = &gmac1;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	dcin: regulator-12vd {
-		compatible = "regulator-fixed";
-		regulator-name = "12vd";
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	fan: pwm-fan {
-		compatible = "pwm-fan";
-		#cooling-cells = <2>;
-		/* cooling level (0, 1, 2) - pwm inverted */
-		cooling-levels = <255 96 0>;
-		pwms = <&pwm 0 10000 0>;
-		status = "okay";
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-
-		reset-key {
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&pio 9 GPIO_ACTIVE_LOW>;
-		};
-
-		wps-key {
-			label = "wps";
-			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	/* i2c of the left SFP cage (wan) */
-	i2c_sfp1: i2c-gpio-0 {
-		compatible = "i2c-gpio";
-		sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		i2c-gpio,delay-us = <2>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	/* i2c of the right SFP cage (lan) */
-	i2c_sfp2: i2c-gpio-1 {
-		compatible = "i2c-gpio";
-		sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		i2c-gpio,delay-us = <2>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		green_led: led-0 {
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_POWER;
-			gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		blue_led: led-1 {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_STATUS;
-			gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-	};
-
-	reg_1p8v: regulator-1p8v {
-		compatible = "regulator-fixed";
-		regulator-name = "1.8vd";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-boot-on;
-		regulator-always-on;
-		vin-supply = <&dcin>;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "3.3vd";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-		vin-supply = <&dcin>;
-	};
-
-	/* left SFP cage (wan) */
-	sfp1: sfp-1 {
-		compatible = "sff,sfp";
-		i2c-bus = <&i2c_sfp1>;
-		los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
-		tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
-	};
-
-	/* right SFP cage (lan) */
-	sfp2: sfp-2 {
-		compatible = "sff,sfp";
-		i2c-bus = <&i2c_sfp2>;
-		los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
-		tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&cpu_thermal {
-	cooling-maps {
-		cpu-active-high {
-			/* active: set fan to cooling level 2 */
-			cooling-device = <&fan 2 2>;
-			trip = <&cpu_trip_active_high>;
-		};
-
-		cpu-active-low {
-			/* active: set fan to cooling level 1 */
-			cooling-device = <&fan 1 1>;
-			trip = <&cpu_trip_active_low>;
-		};
-
-		cpu-passive {
-			/* passive: set fan to cooling level 0 */
-			cooling-device = <&fan 0 0>;
-			trip = <&cpu_trip_passive>;
-		};
-	};
-};
-
-&crypto {
-	status = "okay";
-};
-
-&eth {
-	status = "okay";
-
-	gmac0: mac@0 {
-		compatible = "mediatek,eth-mac";
-		reg = <0>;
-		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	gmac1: mac@1 {
-		compatible = "mediatek,eth-mac";
-		reg = <1>;
-		phy-mode = "2500base-x";
-		sfp = <&sfp1>;
-		managed = "in-band-status";
-	};
-
-	mdio: mdio-bus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-};
-
-&mdio {
-	switch: switch@31 {
-		compatible = "mediatek,mt7531";
-		reg = <31>;
-		interrupt-controller;
-		#interrupt-cells = <1>;
-		interrupt-parent = <&pio>;
-		interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
-		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&mmc0 {
-	pinctrl-names = "default", "state_uhs";
-	pinctrl-0 = <&mmc0_pins_default>;
-	pinctrl-1 = <&mmc0_pins_uhs>;
-	vmmc-supply = <&reg_3p3v>;
-	vqmmc-supply = <&reg_1p8v>;
-};
-
-&i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c_pins>;
-	status = "okay";
-};
-
-&pcie {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie_pins>;
-	status = "okay";
-};
-
-&pcie_phy {
-	status = "okay";
-};
-
-&pio {
-	i2c_pins: i2c-pins {
-		mux {
-			function = "i2c";
-			groups = "i2c";
-		};
-	};
-
-	mmc0_pins_default: mmc0-pins {
-		mux {
-			function = "emmc";
-			groups = "emmc_51";
-		};
-		conf-cmd-dat {
-			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-			input-enable;
-			drive-strength = <4>;
-			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-		};
-		conf-clk {
-			pins = "EMMC_CK";
-			drive-strength = <6>;
-			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-		};
-		conf-ds {
-			pins = "EMMC_DSL";
-			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-		};
-		conf-rst {
-			pins = "EMMC_RSTB";
-			drive-strength = <4>;
-			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-		};
-	};
-
-	mmc0_pins_uhs: mmc0-uhs-pins {
-		mux {
-			function = "emmc";
-			groups = "emmc_51";
-		};
-		conf-cmd-dat {
-			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-			input-enable;
-			drive-strength = <4>;
-			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-		};
-		conf-clk {
-			pins = "EMMC_CK";
-			drive-strength = <6>;
-			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-		};
-		conf-ds {
-			pins = "EMMC_DSL";
-			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-		};
-		conf-rst {
-			pins = "EMMC_RSTB";
-			drive-strength = <4>;
-			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-		};
-	};
-
-	pcie_pins: pcie-pins {
-		mux {
-			function = "pcie";
-			groups = "pcie_clk", "pcie_pereset";
-		};
-	};
-
-	pwm_pins: pwm-pins {
-		mux {
-			function = "pwm";
-			groups = "pwm0", "pwm1_0";
-		};
-	};
-
-	spi_flash_pins: spi-flash-pins {
-		mux {
-			function = "spi";
-			groups = "spi0", "spi0_wp_hold";
-		};
-	};
-
-	spic_pins: spic-pins {
-		mux {
-			function = "spi";
-			groups = "spi1_0";
-		};
-	};
-
-	uart1_pins: uart1-pins {
-		mux {
-			function = "uart";
-			groups = "uart1_rx_tx";
-		};
-	};
-
-	uart2_pins: uart2-pins {
-		mux {
-			function = "uart";
-			groups = "uart2_0_rx_tx";
-		};
-	};
-
-	wf_2g_5g_pins: wf-2g-5g-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_2g", "wf_5g";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-
-	wf_dbdc_pins: wf-dbdc-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_dbdc";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-
-	wf_led_pins: wf-led-pins {
-		mux {
-			function = "led";
-			groups = "wifi_led";
-		};
-	};
-};
-
-&pwm {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pwm_pins>;
-	status = "okay";
-};
-
-&spi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi_flash_pins>;
-	status = "okay";
-};
-
-&spi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spic_pins>;
-	status = "okay";
-};
-
-&ssusb {
-	status = "okay";
-};
-
-&switch {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-			label = "wan";
-		};
-
-		port@1 {
-			reg = <1>;
-			label = "lan0";
-		};
-
-		port@2 {
-			reg = <2>;
-			label = "lan1";
-		};
-
-		port@3 {
-			reg = <3>;
-			label = "lan2";
-		};
-
-		port@4 {
-			reg = <4>;
-			label = "lan3";
-		};
-
-		port5: port@5 {
-			reg = <5>;
-			label = "lan4";
-			phy-mode = "2500base-x";
-			sfp = <&sfp2>;
-			managed = "in-band-status";
-		};
-
-		port@6 {
-			reg = <6>;
-			label = "cpu";
-			ethernet = <&gmac0>;
-			phy-mode = "2500base-x";
-
-			fixed-link {
-				speed = <2500>;
-				full-duplex;
-				pause;
-			};
-		};
-	};
-};
-
-&trng {
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_pins>;
-	status = "okay";
-};
-
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_pins>;
-	status = "okay";
-};
-
-&usb_phy {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&wifi {
-	status = "okay";
-	pinctrl-names = "default", "dbdc";
-	pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
-	pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
-
-	led {
-		led-active-low;
-	};
-};
-

target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a.dtsi

@@ -1,633 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/mt7986-clk.h>
-#include <dt-bindings/reset/mt7986-resets.h>
-#include <dt-bindings/phy/phy.h>
-
-/ {
-	compatible = "mediatek,mt7986a";
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	clk40m: oscillator-40m {
-		compatible = "fixed-clock";
-		clock-frequency = <40000000>;
-		#clock-cells = <0>;
-		clock-output-names = "clkxtal";
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		cpu0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			enable-method = "psci";
-			reg = <0x0>;
-			#cooling-cells = <2>;
-		};
-
-		cpu1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			enable-method = "psci";
-			reg = <0x1>;
-			#cooling-cells = <2>;
-		};
-
-		cpu2: cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			enable-method = "psci";
-			reg = <0x2>;
-			#cooling-cells = <2>;
-		};
-
-		cpu3: cpu@3 {
-			device_type = "cpu";
-			enable-method = "psci";
-			compatible = "arm,cortex-a53";
-			reg = <0x3>;
-			#cooling-cells = <2>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
-		secmon_reserved: secmon@43000000 {
-			reg = <0 0x43000000 0 0x30000>;
-			no-map;
-		};
-
-		wmcpu_emi: wmcpu-reserved@4fc00000 {
-			no-map;
-			reg = <0 0x4fc00000 0 0x00100000>;
-		};
-
-		wo_emi0: wo-emi@4fd00000 {
-			reg = <0 0x4fd00000 0 0x40000>;
-			no-map;
-		};
-
-		wo_emi1: wo-emi@4fd40000 {
-			reg = <0 0x4fd40000 0 0x40000>;
-			no-map;
-		};
-
-		wo_ilm0: wo-ilm@151e0000 {
-			reg = <0 0x151e0000 0 0x8000>;
-			no-map;
-		};
-
-		wo_ilm1: wo-ilm@151f0000 {
-			reg = <0 0x151f0000 0 0x8000>;
-			no-map;
-		};
-
-		wo_data: wo-data@4fd80000 {
-			reg = <0 0x4fd80000 0 0x240000>;
-			no-map;
-		};
-
-		wo_dlm0: wo-dlm@151e8000 {
-			reg = <0 0x151e8000 0 0x2000>;
-			no-map;
-		};
-
-		wo_dlm1: wo-dlm@151f8000 {
-			reg = <0 0x151f8000 0 0x2000>;
-			no-map;
-		};
-
-		wo_boot: wo-boot@15194000 {
-			reg = <0 0x15194000 0 0x1000>;
-			no-map;
-		};
-
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-	};
-
-	soc {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		compatible = "simple-bus";
-		ranges;
-
-		gic: interrupt-controller@c000000 {
-			compatible = "arm,gic-v3";
-			#interrupt-cells = <3>;
-			interrupt-parent = <&gic>;
-			interrupt-controller;
-			reg = <0 0x0c000000 0 0x10000>,  /* GICD */
-			      <0 0x0c080000 0 0x80000>,  /* GICR */
-			      <0 0x0c400000 0 0x2000>,   /* GICC */
-			      <0 0x0c410000 0 0x1000>,   /* GICH */
-			      <0 0x0c420000 0 0x2000>;   /* GICV */
-			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		infracfg: infracfg@10001000 {
-			compatible = "mediatek,mt7986-infracfg", "syscon";
-			reg = <0 0x10001000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		wed_pcie: wed-pcie@10003000 {
-			compatible = "mediatek,mt7986-wed-pcie",
-				     "syscon";
-			reg = <0 0x10003000 0 0x10>;
-		};
-
-		topckgen: topckgen@1001b000 {
-			compatible = "mediatek,mt7986-topckgen", "syscon";
-			reg = <0 0x1001B000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		watchdog: watchdog@1001c000 {
-			compatible = "mediatek,mt7986-wdt";
-			reg = <0 0x1001c000 0 0x1000>;
-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-			#reset-cells = <1>;
-			status = "disabled";
-		};
-
-		apmixedsys: apmixedsys@1001e000 {
-			compatible = "mediatek,mt7986-apmixedsys";
-			reg = <0 0x1001E000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		pio: pinctrl@1001f000 {
-			compatible = "mediatek,mt7986a-pinctrl";
-			reg = <0 0x1001f000 0 0x1000>,
-			      <0 0x11c30000 0 0x1000>,
-			      <0 0x11c40000 0 0x1000>,
-			      <0 0x11e20000 0 0x1000>,
-			      <0 0x11e30000 0 0x1000>,
-			      <0 0x11f00000 0 0x1000>,
-			      <0 0x11f10000 0 0x1000>,
-			      <0 0x1000b000 0 0x1000>;
-			reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
-				    "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pio 0 0 100>;
-			interrupt-controller;
-			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-parent = <&gic>;
-			#interrupt-cells = <2>;
-		};
-
-		sgmiisys0: syscon@10060000 {
-			compatible = "mediatek,mt7986-sgmiisys_0",
-				     "syscon";
-			reg = <0 0x10060000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		sgmiisys1: syscon@10070000 {
-			compatible = "mediatek,mt7986-sgmiisys_1",
-				     "syscon";
-			reg = <0 0x10070000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		trng: rng@1020f000 {
-			compatible = "mediatek,mt7986-rng",
-				     "mediatek,mt7623-rng";
-			reg = <0 0x1020f000 0 0x100>;
-			clocks = <&infracfg CLK_INFRA_TRNG_CK>;
-			clock-names = "rng";
-			status = "disabled";
-		};
-
-		crypto: crypto@10320000 {
-			compatible = "inside-secure,safexcel-eip97";
-			reg = <0 0x10320000 0 0x40000>;
-			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "ring0", "ring1", "ring2", "ring3";
-			clocks = <&infracfg CLK_INFRA_EIP97_CK>;
-			clock-names = "infra_eip97_ck";
-			assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
-			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
-			status = "disabled";
-		};
-
-		pwm: pwm@10048000 {
-			compatible = "mediatek,mt7986-pwm";
-			reg = <0 0x10048000 0 0x1000>;
-			#clock-cells = <1>;
-			#pwm-cells = <2>;
-			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_PWM_SEL>,
-				 <&infracfg CLK_INFRA_PWM_STA>,
-				 <&infracfg CLK_INFRA_PWM1_CK>,
-				 <&infracfg CLK_INFRA_PWM2_CK>;
-			clock-names = "top", "main", "pwm1", "pwm2";
-			status = "disabled";
-		};
-
-		uart0: serial@11002000 {
-			compatible = "mediatek,mt7986-uart",
-				     "mediatek,mt6577-uart";
-			reg = <0 0x11002000 0 0x400>;
-			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_UART0_SEL>,
-				 <&infracfg CLK_INFRA_UART0_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-					  <&infracfg CLK_INFRA_UART0_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
-						 <&topckgen CLK_TOP_UART_SEL>;
-			status = "disabled";
-		};
-
-		uart1: serial@11003000 {
-			compatible = "mediatek,mt7986-uart",
-				     "mediatek,mt6577-uart";
-			reg = <0 0x11003000 0 0x400>;
-			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_UART1_SEL>,
-				 <&infracfg CLK_INFRA_UART1_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
-			status = "disabled";
-		};
-
-		uart2: serial@11004000 {
-			compatible = "mediatek,mt7986-uart",
-				     "mediatek,mt6577-uart";
-			reg = <0 0x11004000 0 0x400>;
-			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_UART2_SEL>,
-				 <&infracfg CLK_INFRA_UART2_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
-			status = "disabled";
-		};
-
-		i2c0: i2c@11008000 {
-			compatible = "mediatek,mt7986-i2c";
-			reg = <0 0x11008000 0 0x90>,
-			      <0 0x10217080 0 0x80>;
-			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-			clock-div = <5>;
-			clocks = <&infracfg CLK_INFRA_I2C0_CK>,
-				 <&infracfg CLK_INFRA_AP_DMA_CK>;
-			clock-names = "main", "dma";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		spi0: spi@1100a000 {
-			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0 0x1100a000 0 0x100>;
-			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-				 <&topckgen CLK_TOP_SPI_SEL>,
-				 <&infracfg CLK_INFRA_SPI0_CK>,
-				 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-			status = "disabled";
-		};
-
-		spi1: spi@1100b000 {
-			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0 0x1100b000 0 0x100>;
-			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-				 <&topckgen CLK_TOP_SPIM_MST_SEL>,
-				 <&infracfg CLK_INFRA_SPI1_CK>,
-				 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-			status = "disabled";
-		};
-
-		auxadc: adc@1100d000 {
-			compatible = "mediatek,mt7986-auxadc";
-			reg = <0 0x1100d000 0 0x1000>;
-			clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
-			clock-names = "main";
-			#io-channel-cells = <1>;
-			status = "disabled";
-		};
-
-		ssusb: usb@11200000 {
-			compatible = "mediatek,mt7986-xhci",
-				     "mediatek,mtk-xhci";
-			reg = <0 0x11200000 0 0x2e00>,
-			      <0 0x11203e00 0 0x0100>;
-			reg-names = "mac", "ippc";
-			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
-				 <&infracfg CLK_INFRA_IUSB_CK>,
-				 <&infracfg CLK_INFRA_IUSB_133_CK>,
-				 <&infracfg CLK_INFRA_IUSB_66M_CK>,
-				 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
-			clock-names = "sys_ck",
-				      "ref_ck",
-				      "mcu_ck",
-				      "dma_ck",
-				      "xhci_ck";
-			phys = <&u2port0 PHY_TYPE_USB2>,
-			       <&u3port0 PHY_TYPE_USB3>,
-			       <&u2port1 PHY_TYPE_USB2>;
-			status = "disabled";
-		};
-
-		mmc0: mmc@11230000 {
-			compatible = "mediatek,mt7986-mmc";
-			reg = <0 0x11230000 0 0x1000>,
-			      <0 0x11c20000 0 0x1000>;
-			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
-				 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
-				 <&infracfg CLK_INFRA_MSDC_CK>,
-				 <&infracfg CLK_INFRA_MSDC_133M_CK>,
-				 <&infracfg CLK_INFRA_MSDC_66M_CK>;
-			clock-names = "source", "hclk", "source_cg", "bus_clk",
-				      "sys_cg";
-			status = "disabled";
-		};
-
-		thermal: thermal@1100c800 {
-			#thermal-sensor-cells = <1>;
-			compatible = "mediatek,mt7986-thermal";
-			reg = <0 0x1100c800 0 0x800>;
-			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_THERM_CK>,
-				 <&infracfg CLK_INFRA_ADC_26M_CK>,
-				 <&infracfg CLK_INFRA_ADC_FRC_CK>;
-			clock-names = "therm", "auxadc", "adc_32k";
-			mediatek,auxadc = <&auxadc>;
-			mediatek,apmixedsys = <&apmixedsys>;
-			nvmem-cells = <&thermal_calibration>;
-			nvmem-cell-names = "calibration-data";
-		};
-
-		pcie: pcie@11280000 {
-			compatible = "mediatek,mt7986-pcie",
-				     "mediatek,mt8192-pcie";
-			device_type = "pci";
-			#address-cells = <3>;
-			#size-cells = <2>;
-			reg = <0x00 0x11280000 0x00 0x4000>;
-			reg-names = "pcie-mac";
-			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
-			ranges = <0x82000000 0x00 0x20000000 0x00
-				  0x20000000 0x00 0x10000000>;
-			clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
-				 <&infracfg CLK_INFRA_IPCIE_CK>,
-				 <&infracfg CLK_INFRA_IPCIER_CK>,
-				 <&infracfg CLK_INFRA_IPCIEB_CK>;
-			clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
-			status = "disabled";
-
-			phys = <&pcie_port PHY_TYPE_PCIE>;
-			phy-names = "pcie-phy";
-
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0x7>;
-			interrupt-map = <0 0 0 1 &pcie_intc 0>,
-					<0 0 0 2 &pcie_intc 1>,
-					<0 0 0 3 &pcie_intc 2>,
-					<0 0 0 4 &pcie_intc 3>;
-			pcie_intc: interrupt-controller {
-				#address-cells = <0>;
-				#interrupt-cells = <1>;
-				interrupt-controller;
-			};
-		};
-
-		pcie_phy: t-phy@11c00000 {
-			compatible = "mediatek,mt7986-tphy",
-				     "mediatek,generic-tphy-v2";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges;
-			status = "disabled";
-
-			pcie_port: pcie-phy@11c00000 {
-				reg = <0 0x11c00000 0 0x20000>;
-				clocks = <&clk40m>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-			};
-		};
-
-		efuse: efuse@11d00000 {
-			compatible = "mediatek,mt7986-efuse", "mediatek,efuse";
-			reg = <0 0x11d00000 0 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			thermal_calibration: calib@274 {
-				reg = <0x274 0xc>;
-			};
-		};
-
-		usb_phy: t-phy@11e10000 {
-			compatible = "mediatek,mt7986-tphy",
-				     "mediatek,generic-tphy-v2";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0 0x11e10000 0x1700>;
-			status = "disabled";
-
-			u2port0: usb-phy@0 {
-				reg = <0x0 0x700>;
-				clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
-					 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
-				clock-names = "ref", "da_ref";
-				#phy-cells = <1>;
-			};
-
-			u3port0: usb-phy@700 {
-				reg = <0x700 0x900>;
-				clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-			};
-
-			u2port1: usb-phy@1000 {
-				reg = <0x1000 0x700>;
-				clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
-					 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
-				clock-names = "ref", "da_ref";
-				#phy-cells = <1>;
-			};
-		};
-
-		ethsys: syscon@15000000 {
-			 #address-cells = <1>;
-			 #size-cells = <1>;
-			 compatible = "mediatek,mt7986-ethsys",
-				      "syscon";
-			 reg = <0 0x15000000 0 0x1000>;
-			 #clock-cells = <1>;
-			 #reset-cells = <1>;
-		};
-
-		wed0: wed@15010000 {
-			compatible = "mediatek,mt7986-wed",
-				     "syscon";
-			reg = <0 0x15010000 0 0x1000>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
-			memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
-					<&wo_data>, <&wo_boot>;
-			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
-					      "wo-data", "wo-boot";
-			mediatek,wo-ccif = <&wo_ccif0>;
-		};
-
-		wed1: wed@15011000 {
-			compatible = "mediatek,mt7986-wed",
-				     "syscon";
-			reg = <0 0x15011000 0 0x1000>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
-			memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
-					<&wo_data>, <&wo_boot>;
-			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
-					      "wo-data", "wo-boot";
-			mediatek,wo-ccif = <&wo_ccif1>;
-		};
-
-		wo_ccif0: syscon@151a5000 {
-			compatible = "mediatek,mt7986-wo-ccif", "syscon";
-			reg = <0 0x151a5000 0 0x1000>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		wo_ccif1: syscon@151ad000 {
-			compatible = "mediatek,mt7986-wo-ccif", "syscon";
-			reg = <0 0x151ad000 0 0x1000>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		eth: ethernet@15100000 {
-			compatible = "mediatek,mt7986-eth";
-			reg = <0 0x15100000 0 0x80000>;
-			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ethsys CLK_ETH_FE_EN>,
-				 <&ethsys CLK_ETH_GP2_EN>,
-				 <&ethsys CLK_ETH_GP1_EN>,
-				 <&ethsys CLK_ETH_WOCPU1_EN>,
-				 <&ethsys CLK_ETH_WOCPU0_EN>,
-				 <&sgmiisys0 CLK_SGMII0_TX250M_EN>,
-				 <&sgmiisys0 CLK_SGMII0_RX250M_EN>,
-				 <&sgmiisys0 CLK_SGMII0_CDR_REF>,
-				 <&sgmiisys0 CLK_SGMII0_CDR_FB>,
-				 <&sgmiisys1 CLK_SGMII1_TX250M_EN>,
-				 <&sgmiisys1 CLK_SGMII1_RX250M_EN>,
-				 <&sgmiisys1 CLK_SGMII1_CDR_REF>,
-				 <&sgmiisys1 CLK_SGMII1_CDR_FB>,
-				 <&topckgen CLK_TOP_NETSYS_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
-			clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
-				      "sgmii_tx250m", "sgmii_rx250m",
-				      "sgmii_cdr_ref", "sgmii_cdr_fb",
-				      "sgmii2_tx250m", "sgmii2_rx250m",
-				      "sgmii2_cdr_ref", "sgmii2_cdr_fb",
-				      "netsys0", "netsys1";
-			assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
-					  <&topckgen CLK_TOP_SGM_325M_SEL>;
-			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
-						 <&apmixedsys CLK_APMIXED_SGMPLL>;
-			mediatek,ethsys = <&ethsys>;
-			mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
-			mediatek,wed-pcie = <&wed_pcie>;
-			mediatek,wed = <&wed0>, <&wed1>;
-			#reset-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		wifi: wifi@18000000 {
-			compatible = "mediatek,mt7986-wmac";
-			resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
-			reset-names = "consys";
-			clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
-				 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
-			clock-names = "mcu", "ap2conn";
-			reg = <0 0x18000000 0 0x1000000>,
-			      <0 0x10003000 0 0x1000>,
-			      <0 0x11d10000 0 0x1000>;
-			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
-			memory-region = <&wmcpu_emi>;
-		};
-	};
-
-	thermal-zones {
-		cpu_thermal: cpu-thermal {
-			polling-delay-passive = <1000>;
-			polling-delay = <1000>;
-			thermal-sensors = <&thermal 0>;
-
-			trips {
-				cpu_trip_active_high: active-high {
-					temperature = <115000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_low: active-low {
-					temperature = <85000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_passive: passive {
-					temperature = <40000>;
-					hysteresis = <2000>;
-					type = "passive";
-				};
-			};
-		};
-	};
-};

target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts

@@ -1,194 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-/dts-v1/;
-#include "mt7986b.dtsi"
-
-/ {
-	model = "MediaTek MT7986b RFB";
-	compatible = "mediatek,mt7986b-rfb";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory {
-		reg = <0 0x40000000 0 0x40000000>;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_5v: regulator-5v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-5V";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-};
-
-&ssusb {
-	vusb33-supply = <&reg_3p3v>;
-	vbus-supply = <&reg_5v>;
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&usb_phy {
-	status = "okay";
-};
-
-&wifi {
-	status = "okay";
-	pinctrl-names = "default", "dbdc";
-	pinctrl-0 = <&wf_2g_5g_pins>;
-	pinctrl-1 = <&wf_dbdc_pins>;
-};
-
-&eth {
-	status = "okay";
-
-	gmac0: mac@0 {
-		compatible = "mediatek,eth-mac";
-		reg = <0>;
-		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	gmac1: mac@1 {
-		compatible = "mediatek,eth-mac";
-		reg = <1>;
-		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	mdio: mdio-bus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		phy5: phy@5 {
-			compatible = "ethernet-phy-id67c9.de0a";
-			reg = <5>;
-			reset-gpios = <&pio 6 1>;
-			reset-deassert-us = <20000>;
-			phy-mode = "2500base-x";
-		};
-
-		phy6: phy@6 {
-			compatible = "ethernet-phy-id67c9.de0a";
-			reg = <6>;
-			phy-mode = "2500base-x";
-		};
-
-		switch@0 {
-			compatible = "mediatek,mt7531";
-			reg = <31>;
-			reset-gpios = <&pio 5 0>;
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@0 {
-					reg = <0>;
-					label = "lan0";
-				};
-
-				port@1 {
-					reg = <1>;
-					label = "lan1";
-				};
-
-				port@2 {
-					reg = <2>;
-					label = "lan2";
-				};
-
-				port@3 {
-					reg = <3>;
-					label = "lan3";
-				};
-
-				port@6 {
-					reg = <6>;
-					ethernet = <&gmac0>;
-					phy-mode = "2500base-x";
-
-					fixed-link {
-						speed = <2500>;
-						full-duplex;
-						pause;
-					};
-				};
-			};
-		};
-	};
-};
-
-&crypto {
-	status = "okay";
-};
-
-&pio {
-	wf_2g_5g_pins: wf_2g_5g-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_2g", "wf_5g";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-
-	wf_dbdc_pins: wf_dbdc-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_dbdc";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-};

target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986b.dtsi

@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <[email protected]>
- */
-
-#include "mt7986a.dtsi"
-/ {
-	compatible = "mediatek,mt7986b";
-};
-
-&pio {
-	compatible = "mediatek,mt7986b-pinctrl";
-	gpio-ranges = <&pio 0 0 41>, <&pio 66 66 35>;
-};

target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-apmixed.c

@@ -1,102 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- * Author: Wenzhen Yu <[email protected]>
- * Author: Jianhui Zhao <[email protected]>
- * Author: Daniel Golle <[email protected]>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-#include <linux/clk.h>
-
-#define MT7981_PLL_FMAX (2500UL * MHZ)
-#define CON0_MT7981_RST_BAR BIT(27)
-
-#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \
-		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift,         \
-		 _div_table, _parent_name)                                     \
-	{                                                                      \
-		.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg,    \
-		.en_mask = _en_mask, .flags = _flags,                          \
-		.rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX,  \
-		.pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
-		.tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg,                  \
-		.pcw_shift = _pcw_shift, .div_table = _div_table,              \
-		.parent_name = _parent_name,                                   \
-	}
-
-#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,   \
-	    _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift)                       \
-	PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \
-		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL,   \
-		 "clkxtal")
-
-static const struct mtk_pll_data plls[] = {
-	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO,
-	    32, 0x0200, 4, 0, 0x0204, 0),
-	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
-	    0x0210, 4, 0, 0x0214, 0),
-	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
-	    0x0220, 4, 0, 0x0224, 0),
-	PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32,
-	    0x0230, 4, 0, 0x0234, 0),
-	PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32,
-	    0x0240, 4, 0, 0x0244, 0),
-	PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32,
-	    0x0250, 4, 0, 0x0254, 0),
-	PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32,
-	    0x0260, 4, 0, 0x0264, 0),
-	PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
-	    0x0278, 4, 0, 0x027C, 0),
-};
-
-static const struct of_device_id of_match_clk_mt7981_apmixed[] = {
-	{ .compatible = "mediatek,mt7981-apmixedsys", },
-	{}
-};
-
-static int clk_mt7981_apmixed_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-
-	clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_apmixed_data;
-	}
-	return r;
-
-free_apmixed_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static struct platform_driver clk_mt7981_apmixed_drv = {
-	.probe = clk_mt7981_apmixed_probe,
-	.driver = {
-		.name = "clk-mt7981-apmixed",
-		.of_match_table = of_match_clk_mt7981_apmixed,
-	},
-};
-builtin_platform_driver(clk_mt7981_apmixed_drv);

target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-eth.c

@@ -1,139 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- * Author: Wenzhen Yu <[email protected]>
- * Author: Jianhui Zhao <[email protected]>
- * Author: Daniel Golle <[email protected]>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-
-#include "clk-mtk.h"
-#include "clk-gate.h"
-
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-
-static const struct mtk_gate_regs sgmii0_cg_regs = {
-	.set_ofs = 0xE4,
-	.clr_ofs = 0xE4,
-	.sta_ofs = 0xE4,
-};
-
-#define GATE_SGMII0(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &sgmii0_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
-	}
-
-static const struct mtk_gate sgmii0_clks[] __initconst = {
-	GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2),
-	GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3),
-	GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4),
-	GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5),
-};
-
-static const struct mtk_gate_regs sgmii1_cg_regs = {
-	.set_ofs = 0xE4,
-	.clr_ofs = 0xE4,
-	.sta_ofs = 0xE4,
-};
-
-#define GATE_SGMII1(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &sgmii1_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
-	}
-
-static const struct mtk_gate sgmii1_clks[] __initconst = {
-	GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2),
-	GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3),
-	GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4),
-	GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5),
-};
-
-static const struct mtk_gate_regs eth_cg_regs = {
-	.set_ofs = 0x30,
-	.clr_ofs = 0x30,
-	.sta_ofs = 0x30,
-};
-
-#define GATE_ETH(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &eth_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
-	}
-
-static const struct mtk_gate eth_clks[] __initconst = {
-	GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6),
-	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7),
-	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8),
-	GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15),
-};
-
-static void __init mtk_sgmiisys_0_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
-
-	mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7981-sgmiisys_0",
-	       mtk_sgmiisys_0_init);
-
-static void __init mtk_sgmiisys_1_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
-
-	mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7981-sgmiisys_1",
-	       mtk_sgmiisys_1_init);
-
-static void __init mtk_ethsys_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
-
-	mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7981-ethsys", mtk_ethsys_init);

target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-infracfg.c

@@ -1,235 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- * Author: Wenzhen Yu <[email protected]>
- * Author: Jianhui Zhao <[email protected]>
- * Author: Daniel Golle <[email protected]>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-#include <linux/clk.h>
-
-static DEFINE_SPINLOCK(mt7981_clk_lock);
-
-static const struct mtk_fixed_factor infra_divs[] = {
-	FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2),
-};
-
-static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
-								"uart_sel" };
-
-static const char *const infra_spi0_parents[] __initconst = { "i2c_sel",
-							      "spi_sel" };
-
-static const char *const infra_spi1_parents[] __initconst = { "i2c_sel",
-							      "spim_mst_sel" };
-
-static const char *const infra_pwm1_parents[] __initconst = { "pwm_sel" };
-
-static const char *const infra_pwm_bsel_parents[] __initconst = {
-	"cb_rtc_32p7k", "csw_f26m_sel", "infra_66m_mck", "pwm_sel"
-};
-
-static const char *const infra_pcie_parents[] __initconst = {
-	"cb_rtc_32p7k", "csw_f26m_sel", "cb_cksq_40m", "pextp_tl_ck_sel"
-};
-
-static const struct mtk_mux infra_muxes[] = {
-	/* MODULE_CLK_SEL_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
-			     infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
-			     infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel",
-			     infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
-			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
-			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel",
-			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
-			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
-			     2, -1, -1, -1),
-	/* MODULE_CLK_SEL_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
-			     infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
-			     -1, -1, -1),
-};
-
-static const struct mtk_gate_regs infra0_cg_regs = {
-	.set_ofs = 0x40,
-	.clr_ofs = 0x44,
-	.sta_ofs = 0x48,
-};
-
-static const struct mtk_gate_regs infra1_cg_regs = {
-	.set_ofs = 0x50,
-	.clr_ofs = 0x54,
-	.sta_ofs = 0x58,
-};
-
-static const struct mtk_gate_regs infra2_cg_regs = {
-	.set_ofs = 0x60,
-	.clr_ofs = 0x64,
-	.sta_ofs = 0x68,
-};
-
-#define GATE_INFRA0(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra0_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-#define GATE_INFRA1(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra1_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-#define GATE_INFRA2(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra2_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-static const struct mtk_gate infra_clks[] = {
-	/* INFRA0 */
-	GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0),
-	GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1),
-	GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
-	GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
-	GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
-	GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi", 6),
-
-	GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi", 8),
-	GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
-	GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l", 10),
-	GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys", 11),
-	GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner", 13),
-	GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
-		    14),
-	GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15),
-	GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16),
-	GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24),
-	GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
-	GATE_INFRA0(CLK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27),
-	/* INFRA1 */
-	GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
-	GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_bck", 1),
-	GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
-	GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
-	GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
-	GATE_INFRA1(CLK_INFRA_SPI2_CK, "infra_spi2", "infra_spi2_sel", 6),
-	GATE_INFRA1(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7),
-	GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x", 8),
-	GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_bck", 9),
-	GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10),
-	GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
-	GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
-	GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck",
-		    13),
-	GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck",
-		    14),
-	GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "cb_rtc_32k", 15),
-	GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_400m", 16),
-	GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_208m", 17),
-	GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi", 18),
-	GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "sysaxi", 19),
-	GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
-	GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21),
-	GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x", 23),
-	GATE_INFRA1(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "sysaxi", 25),
-	GATE_INFRA1(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26),
-	/* INFRA2 */
-	GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi", 0),
-	GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "sysaxi", 1),
-	GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys", 2),
-	GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_ref", 3),
-	GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl", 12),
-	GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m",
-		    13),
-	GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m", 14),
-	GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi", 15),
-};
-
-static int clk_mt7981_infracfg_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) +
-		 ARRAY_SIZE(infra_clks);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
-	mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
-			       &mt7981_clk_lock, clk_data);
-	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_infracfg_data;
-	}
-	return r;
-
-free_infracfg_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct of_device_id of_match_clk_mt7981_infracfg[] = {
-	{ .compatible = "mediatek,mt7981-infracfg", },
-	{}
-};
-
-static struct platform_driver clk_mt7981_infracfg_drv = {
-	.probe = clk_mt7981_infracfg_probe,
-	.driver = {
-		.name = "clk-mt7981-infracfg",
-		.of_match_table = of_match_clk_mt7981_infracfg,
-	},
-};
-builtin_platform_driver(clk_mt7981_infracfg_drv);

target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7981-topckgen.c

@@ -1,450 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- * Author: Wenzhen Yu <[email protected]>
- * Author: Jianhui Zhao <[email protected]>
- */
-
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-#include <linux/clk.h>
-
-static DEFINE_SPINLOCK(mt7981_clk_lock);
-
-static const struct mtk_fixed_factor top_divs[] = {
-	FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1),
-	FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1),
-	FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2),
-	FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3),
-	FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2),
-	FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4),
-	FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8),
-	FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16),
-	FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1),
-	FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2),
-	FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3),
-	FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15),
-	FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4),
-	FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6),
-	FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12),
-	FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8),
-	FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1),
-	FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
-	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
-	FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1),
-	FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4),
-	FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5),
-	FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10),
-	FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20),
-	FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8),
-	FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16),
-	FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32),
-	FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1),
-	FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2),
-	FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4),
-	FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8),
-	FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16),
-	FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6),
-	FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1),
-	FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1),
-	FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2),
-	FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250),
-	FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220),
-	FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1),
-	FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1),
-	FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1),
-	FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1),
-	FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1),
-	FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1),
-	FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1),
-	FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1),
-	FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1),
-	FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1),
-	FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1),
-	FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1),
-	FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1),
-	FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1),
-	FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1),
-	FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1),
-	FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1),
-	FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1),
-	FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1),
-	FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1),
-	FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1),
-	FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1),
-	FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1),
-	FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1),
-	FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1),
-	FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1),
-	FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1),
-	FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1),
-	FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1),
-	FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1),
-	FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1),
-	FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1),
-	FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1),
-	FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1),
-	FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1),
-	FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1),
-	FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1),
-	FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1),
-};
-
-static const char * const nfi1x_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_mm_d4",
-	"net1_d8_d2",
-	"cb_net2_d6",
-	"cb_m_d4",
-	"cb_mm_d8",
-	"net1_d8_d4",
-	"cb_m_d8"
-};
-
-static const char * const spinfi_parents[] __initconst = {
-	"cksq_40m_d2",
-	"cb_cksq_40m",
-	"net1_d5_d4",
-	"cb_m_d4",
-	"cb_mm_d8",
-	"net1_d8_d4",
-	"mm_d6_d2",
-	"cb_m_d8"
-};
-
-static const char * const spi_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_m_d2",
-	"cb_mm_d4",
-	"net1_d8_d2",
-	"cb_net2_d6",
-	"net1_d5_d4",
-	"cb_m_d4",
-	"net1_d8_d4"
-};
-
-static const char * const uart_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_m_d8",
-	"m_d8_d2"
-};
-
-static const char * const pwm_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d8_d2",
-	"net1_d5_d4",
-	"cb_m_d4",
-	"m_d8_d2",
-	"cb_rtc_32k"
-};
-
-static const char * const i2c_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d5_d4",
-	"cb_m_d4",
-	"net1_d8_d4"
-};
-
-static const char * const pextp_tl_ck_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d5_d4",
-	"cb_m_d4",
-	"cb_rtc_32k"
-};
-
-static const char * const emmc_208m_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_m_d2",
-	"cb_net2_d4",
-	"cb_apll2_196m",
-	"cb_mm_d4",
-	"net1_d8_d2",
-	"cb_mm_d6"
-};
-
-static const char * const emmc_400m_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net2_d2",
-	"cb_mm_d2",
-	"cb_net2_d2"
-};
-
-static const char * const csw_f26m_parents[] __initconst = {
-	"cksq_40m_d2",
-	"m_d8_d2"
-};
-
-static const char * const dramc_md32_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_m_d2",
-	"cb_wedmcu_208m"
-};
-
-static const char * const sysaxi_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d8_d2"
-};
-
-static const char * const sysapb_parents[] __initconst = {
-	"cb_cksq_40m",
-	"m_d3_d2"
-};
-
-static const char * const arm_db_main_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net2_d6"
-};
-
-static const char * const ap2cnn_host_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d8_d4"
-};
-
-static const char * const netsys_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_mm_d2"
-};
-
-static const char * const netsys_500m_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net1_d5"
-};
-
-static const char * const netsys_mcu_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_mm_720m",
-	"cb_net1_d4",
-	"cb_net1_d5",
-	"cb_m_416m"
-};
-
-static const char * const netsys_2x_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net2_800m",
-	"cb_mm_720m"
-};
-
-static const char * const sgm_325m_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_sgm_325m"
-};
-
-static const char * const sgm_reg_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net2_d4"
-};
-
-static const char * const eip97b_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net1_d5",
-	"cb_m_416m",
-	"cb_mm_d2",
-	"net1_d5_d2"
-};
-
-static const char * const aud_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_apll2_196m"
-};
-
-static const char * const a1sys_parents[] __initconst = {
-	"cb_cksq_40m",
-	"apll2_d4"
-};
-
-static const char * const aud_l_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_apll2_196m",
-	"m_d8_d2"
-};
-
-static const char * const a_tuner_parents[] __initconst = {
-	"cb_cksq_40m",
-	"apll2_d4",
-	"m_d8_d2"
-};
-
-static const char * const u2u3_parents[] __initconst = {
-	"cb_cksq_40m",
-	"m_d8_d2"
-};
-
-static const char * const u2u3_sys_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d5_d4"
-};
-
-static const char * const usb_frmcnt_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_mm_d3_d5"
-};
-
-static const struct mtk_mux top_muxes[] = {
-	/* CLK_CFG_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
-			     0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
-			     0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
-			     0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
-			     0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
-	/* CLK_CFG_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
-			     0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
-			     0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
-			     0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
-			     pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31,
-			     0x1C0, 7),
-	/* CLK_CFG_2 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel",
-			     emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7,
-			     0x1C0, 8),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
-			     emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15,
-			     0x1C0, 9),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
-				   csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23,
-				   0x1C0, 10,
-				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
-				   csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1,
-				   31, 0x1C0, 11,
-				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-	/* CLK_CFG_3 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
-				   dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2,
-				   7, 0x1C0, 12,
-				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
-				   sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15,
-				   0x1C0, 13,
-				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
-				   sysapb_parents, 0x030, 0x034, 0x038, 16, 1,
-				   23, 0x1C0, 14,
-				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
-			     arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31,
-			     0x1C0, 15),
-	/* CLK_CFG_4 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
-			     ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7,
-			     0x1C0, 16),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
-			     0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
-			     netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23,
-			     0x1C0, 18),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
-			     netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
-			     0x1C0, 19),
-	/* CLK_CFG_5 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
-			     netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
-			     0x1C0, 20),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
-			     sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
-			     0x1C0, 21),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
-			     0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents,
-			     0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
-	/* CLK_CFG_6 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
-			     csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1,
-			     7, 0x1C0, 24),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x060,
-			     0x064, 0x068, 8, 1, 15, 0x1C0, 25),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
-			     0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
-			     0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27),
-	/* CLK_CFG_7 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
-			     a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7,
-			     0x1C0, 28),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x070,
-			     0x074, 0x078, 8, 1, 15, 0x1C0, 29),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
-			     u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23,
-			     0x1C0, 30),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
-			     u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31,
-			     0x1C4, 0),
-	/* CLK_CFG_8 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
-			     usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7,
-			     0x1C4, 1),
-};
-
-static struct mtk_composite top_aud_divs[] = {
-	DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud",
-		0x0420, 0, 0x0420, 8, 8),
-};
-
-static int clk_mt7981_topckgen_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(top_divs) + ARRAY_SIZE(top_muxes) +
-		 ARRAY_SIZE(top_aud_divs);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
-	mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
-			       &mt7981_clk_lock, clk_data);
-	mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), base,
-                        &mt7981_clk_lock, clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_topckgen_data;
-	}
-	return r;
-
-free_topckgen_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct of_device_id of_match_clk_mt7981_topckgen[] = {
-	{ .compatible = "mediatek,mt7981-topckgen", },
-	{}
-};
-
-static struct platform_driver clk_mt7981_topckgen_drv = {
-	.probe = clk_mt7981_topckgen_probe,
-	.driver = {
-		.name = "clk-mt7981-topckgen",
-		.of_match_table = of_match_clk_mt7981_topckgen,
-	},
-};
-builtin_platform_driver(clk_mt7981_topckgen_drv);

target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-apmixed.c

@@ -1,100 +0,0 @@
-// SPDX-License-Identifier: GPL-1.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- * Author: Wenzhen Yu <[email protected]>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mt7986-clk.h>
-#include <linux/clk.h>
-
-#define MT7986_PLL_FMAX (2500UL * MHZ)
-#define CON0_MT7986_RST_BAR BIT(27)
-
-#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \
-		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift,         \
-		 _div_table, _parent_name)                                     \
-	{                                                                      \
-		.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg,    \
-		.en_mask = _en_mask, .flags = _flags,                          \
-		.rst_bar_mask = CON0_MT7986_RST_BAR, .fmax = MT7986_PLL_FMAX,  \
-		.pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
-		.tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg,                  \
-		.pcw_shift = _pcw_shift, .div_table = _div_table,              \
-		.parent_name = _parent_name,                                   \
-	}
-
-#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,   \
-	    _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift)                       \
-	PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \
-		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL,   \
-		 "clkxtal")
-
-static const struct mtk_pll_data plls[] = {
-	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, 0, 32,
-	    0x0200, 4, 0, 0x0204, 0),
-	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
-	    0x0210, 4, 0, 0x0214, 0),
-	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
-	    0x0220, 4, 0, 0x0224, 0),
-	PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x00000001, 0, 32,
-	    0x0230, 4, 0, 0x0234, 0),
-	PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x00000001, 0,
-	    32, 0x0240, 4, 0, 0x0244, 0),
-	PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025c, 0x00000001, 0, 32,
-	    0x0250, 4, 0, 0x0254, 0),
-	PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, 0x0260,
-	    4, 0, 0x0264, 0),
-	PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
-	    0x0278, 4, 0, 0x027c, 0),
-};
-
-static const struct of_device_id of_match_clk_mt7986_apmixed[] = {
-	{ .compatible = "mediatek,mt7986-apmixedsys", },
-	{}
-};
-
-static int clk_mt7986_apmixed_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-
-	clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_apmixed_data;
-	}
-	return r;
-
-free_apmixed_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static struct platform_driver clk_mt7986_apmixed_drv = {
-	.probe = clk_mt7986_apmixed_probe,
-	.driver = {
-		.name = "clk-mt7986-apmixed",
-		.of_match_table = of_match_clk_mt7986_apmixed,
-	},
-};
-builtin_platform_driver(clk_mt7986_apmixed_drv);

target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-eth.c

@@ -1,132 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- * Author: Wenzhen Yu <[email protected]>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-
-#include "clk-mtk.h"
-#include "clk-gate.h"
-
-#include <dt-bindings/clock/mt7986-clk.h>
-
-static const struct mtk_gate_regs sgmii0_cg_regs = {
-	.set_ofs = 0xe4,
-	.clr_ofs = 0xe4,
-	.sta_ofs = 0xe4,
-};
-
-#define GATE_SGMII0(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &sgmii0_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                        \
-	}
-
-static const struct mtk_gate sgmii0_clks[] __initconst = {
-	GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en", "top_xtal", 2),
-	GATE_SGMII0(CLK_SGMII0_RX250M_EN, "sgmii0_rx250m_en", "top_xtal", 3),
-	GATE_SGMII0(CLK_SGMII0_CDR_REF, "sgmii0_cdr_ref", "top_xtal", 4),
-	GATE_SGMII0(CLK_SGMII0_CDR_FB, "sgmii0_cdr_fb", "top_xtal", 5),
-};
-
-static const struct mtk_gate_regs sgmii1_cg_regs = {
-	.set_ofs = 0xe4,
-	.clr_ofs = 0xe4,
-	.sta_ofs = 0xe4,
-};
-
-#define GATE_SGMII1(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &sgmii1_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                        \
-	}
-
-static const struct mtk_gate sgmii1_clks[] __initconst = {
-	GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en", "top_xtal", 2),
-	GATE_SGMII1(CLK_SGMII1_RX250M_EN, "sgmii1_rx250m_en", "top_xtal", 3),
-	GATE_SGMII1(CLK_SGMII1_CDR_REF, "sgmii1_cdr_ref", "top_xtal", 4),
-	GATE_SGMII1(CLK_SGMII1_CDR_FB, "sgmii1_cdr_fb", "top_xtal", 5),
-};
-
-static const struct mtk_gate_regs eth_cg_regs = {
-	.set_ofs = 0x30,
-	.clr_ofs = 0x30,
-	.sta_ofs = 0x30,
-};
-
-#define GATE_ETH(_id, _name, _parent, _shift)                                  \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &eth_cg_regs, .shift = _shift,                         \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                        \
-	}
-
-static const struct mtk_gate eth_clks[] __initconst = {
-	GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x_sel", 6),
-	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m_sel", 7),
-	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m_sel", 8),
-	GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en", "netsys_mcu_sel", 14),
-	GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_mcu_sel", 15),
-};
-
-static void __init mtk_sgmiisys_0_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
-
-	mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7986-sgmiisys_0",
-	       mtk_sgmiisys_0_init);
-
-static void __init mtk_sgmiisys_1_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
-
-	mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7986-sgmiisys_1",
-	       mtk_sgmiisys_1_init);
-
-static void __init mtk_ethsys_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
-
-	mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7986-ethsys", mtk_ethsys_init);

target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-infracfg.c

@@ -1,224 +0,0 @@
-// SPDX-License-Identifier: GPL-1.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- * Author: Wenzhen Yu <[email protected]>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mt7986-clk.h>
-#include <linux/clk.h>
-
-static DEFINE_SPINLOCK(mt7986_clk_lock);
-
-static const struct mtk_fixed_factor infra_divs[] = {
-	FACTOR(CLK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", "sysaxi_sel", 1, 2),
-};
-
-static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
-							     "uart_sel" };
-
-static const char *const infra_spi_parents[] __initconst = { "i2c_sel",
-							     "spi_sel" };
-
-static const char *const infra_pwm_bsel_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_f26m_sel", "infra_sysaxi_d2", "pwm_sel"
-};
-
-static const char *const infra_pcie_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_f26m_sel", "top_xtal", "pextp_tl_ck_sel"
-};
-
-static const struct mtk_mux infra_muxes[] = {
-	/* MODULE_CLK_SEL_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
-			     infra_spi_parents, 0x0018, 0x0010, 0x0014, 4, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
-			     infra_spi_parents, 0x0018, 0x0010, 0x0014, 5, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
-			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 9,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
-			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 11,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
-			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
-			     2, -1, -1, -1),
-	/* MODULE_CLK_SEL_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
-			     infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
-			     -1, -1, -1),
-};
-
-static const struct mtk_gate_regs infra0_cg_regs = {
-	.set_ofs = 0x40,
-	.clr_ofs = 0x44,
-	.sta_ofs = 0x48,
-};
-
-static const struct mtk_gate_regs infra1_cg_regs = {
-	.set_ofs = 0x50,
-	.clr_ofs = 0x54,
-	.sta_ofs = 0x58,
-};
-
-static const struct mtk_gate_regs infra2_cg_regs = {
-	.set_ofs = 0x60,
-	.clr_ofs = 0x64,
-	.sta_ofs = 0x68,
-};
-
-#define GATE_INFRA0(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra0_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-#define GATE_INFRA1(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra1_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-#define GATE_INFRA2(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra2_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-static const struct mtk_gate infra_clks[] = {
-	/* INFRA0 */
-	GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_sysaxi_d2", 0),
-	GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_sysaxi_d2", 1),
-	GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
-	GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
-	GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
-	GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi_sel", 6),
-	GATE_INFRA0(CLK_INFRA_EIP97_CK, "infra_eip97", "eip_b_sel", 7),
-	GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi_sel", 8),
-	GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
-	GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l_sel", 10),
-	GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys_sel", 11),
-	GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner_sel", 13),
-	GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
-		    14),
-	GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_sysaxi_d2", 15),
-	GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_sysaxi_d2", 16),
-	GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_sysaxi_d2", 24),
-	GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
-	GATE_INFRA0(CLK_INFRA_TRNG_CK, "infra_trng", "sysaxi_sel", 26),
-	/* INFRA1 */
-	GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
-	GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_sel", 1),
-	GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
-	GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
-	GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
-	GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x_sel", 8),
-	GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_sel", 9),
-	GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_sysaxi_d2",
-		    10),
-	GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
-	GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
-	GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_sysaxi_d2",
-		    13),
-	GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_sysaxi_d2",
-		    14),
-	GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "top_rtc_32k", 15),
-	GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_416m_sel", 16),
-	GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_250m_sel",
-		    17),
-	GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi_sel",
-		    18),
-	GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "infra_sysaxi_d2",
-		    19),
-	GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
-	GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m_sel", 21),
-	GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x_sel", 23),
-	/* INFRA2 */
-	GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi_sel", 0),
-	GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "infra_sysaxi_d2",
-		    1),
-	GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys_sel", 2),
-	GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_sel", 3),
-	GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl_ck_sel", 12),
-	GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "top_xtal",
-		    13),
-	GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m_sel", 14),
-	GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi_sel", 15),
-};
-
-static int clk_mt7986_infracfg_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) +
-		 ARRAY_SIZE(infra_clks);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
-	mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
-			       &mt7986_clk_lock, clk_data);
-	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_infracfg_data;
-	}
-	return r;
-
-free_infracfg_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-
-}
-
-static const struct of_device_id of_match_clk_mt7986_infracfg[] = {
-	{ .compatible = "mediatek,mt7986-infracfg", },
-	{}
-};
-
-static struct platform_driver clk_mt7986_infracfg_drv = {
-	.probe = clk_mt7986_infracfg_probe,
-	.driver = {
-		.name = "clk-mt7986-infracfg",
-		.of_match_table = of_match_clk_mt7986_infracfg,
-	},
-};
-builtin_platform_driver(clk_mt7986_infracfg_drv);

target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7986-topckgen.c

@@ -1,342 +0,0 @@
-// SPDX-License-Identifier: GPL-1.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- * Author: Wenzhen Yu <[email protected]>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mt7986-clk.h>
-#include <linux/clk.h>
-
-static DEFINE_SPINLOCK(mt7986_clk_lock);
-
-static const struct mtk_fixed_clk top_fixed_clks[] = {
-	FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
-	FIXED_CLK(CLK_TOP_JTAG, "top_jtag", "clkxtal", 50000000),
-};
-
-static const struct mtk_fixed_factor top_divs[] = {
-	/* XTAL */
-	FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
-	FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
-	FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
-	/* MPLL */
-	FACTOR(CLK_TOP_MPLL_D2, "top_mpll_d2", "mpll", 1, 2),
-	FACTOR(CLK_TOP_MPLL_D4, "top_mpll_d4", "mpll", 1, 4),
-	FACTOR(CLK_TOP_MPLL_D8, "top_mpll_d8", "mpll", 1, 8),
-	FACTOR(CLK_TOP_MPLL_D8_D2, "top_mpll_d8_d2", "mpll", 1, 16),
-	FACTOR(CLK_TOP_MPLL_D3_D2, "top_mpll_d3_d2", "mpll", 1, 6),
-	/* MMPLL */
-	FACTOR(CLK_TOP_MMPLL_D2, "top_mmpll_d2", "mmpll", 1, 2),
-	FACTOR(CLK_TOP_MMPLL_D4, "top_mmpll_d4", "mmpll", 1, 4),
-	FACTOR(CLK_TOP_MMPLL_D8, "top_mmpll_d8", "mmpll", 1, 8),
-	FACTOR(CLK_TOP_MMPLL_D8_D2, "top_mmpll_d8_d2", "mmpll", 1, 16),
-	FACTOR(CLK_TOP_MMPLL_D3_D8, "top_mmpll_d3_d8", "mmpll", 1, 24),
-	FACTOR(CLK_TOP_MMPLL_U2PHY, "top_mmpll_u2phy", "mmpll", 1, 30),
-	/* APLL2 */
-	FACTOR(CLK_TOP_APLL2_D4, "top_apll2_d4", "apll2", 1, 4),
-	/* NET1PLL */
-	FACTOR(CLK_TOP_NET1PLL_D4, "top_net1pll_d4", "net1pll", 1, 4),
-	FACTOR(CLK_TOP_NET1PLL_D5, "top_net1pll_d5", "net1pll", 1, 5),
-	FACTOR(CLK_TOP_NET1PLL_D5_D2, "top_net1pll_d5_d2", "net1pll", 1, 10),
-	FACTOR(CLK_TOP_NET1PLL_D5_D4, "top_net1pll_d5_d4", "net1pll", 1, 20),
-	FACTOR(CLK_TOP_NET1PLL_D8_D2, "top_net1pll_d8_d2", "net1pll", 1, 16),
-	FACTOR(CLK_TOP_NET1PLL_D8_D4, "top_net1pll_d8_d4", "net1pll", 1, 32),
-	/* NET2PLL */
-	FACTOR(CLK_TOP_NET2PLL_D4, "top_net2pll_d4", "net2pll", 1, 4),
-	FACTOR(CLK_TOP_NET2PLL_D4_D2, "top_net2pll_d4_d2", "net2pll", 1, 8),
-	FACTOR(CLK_TOP_NET2PLL_D3_D2, "top_net2pll_d3_d2", "net2pll", 1, 2),
-	/* WEDMCUPLL */
-	FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "top_wedmcupll_d5_d2", "wedmcupll", 1,
-	       10),
-};
-
-static const char *const nfi1x_parents[] __initconst = { "top_xtal",
-							 "top_mmpll_d8",
-							 "top_net1pll_d8_d2",
-							 "top_net2pll_d3_d2",
-							 "top_mpll_d4",
-							 "top_mmpll_d8_d2",
-							 "top_wedmcupll_d5_d2",
-							 "top_mpll_d8" };
-
-static const char *const spinfi_parents[] __initconst = {
-	"top_xtal_d2",     "top_xtal",	"top_net1pll_d5_d4",
-	"top_mpll_d4",     "top_mmpll_d8_d2", "top_wedmcupll_d5_d2",
-	"top_mmpll_d3_d8", "top_mpll_d8"
-};
-
-static const char *const spi_parents[] __initconst = {
-	"top_xtal",	  "top_mpll_d2",	"top_mmpll_d8",
-	"top_net1pll_d8_d2", "top_net2pll_d3_d2",  "top_net1pll_d5_d4",
-	"top_mpll_d4",       "top_wedmcupll_d5_d2"
-};
-
-static const char *const uart_parents[] __initconst = { "top_xtal",
-							"top_mpll_d8",
-							"top_mpll_d8_d2" };
-
-static const char *const pwm_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d8_d2", "top_net1pll_d5_d4", "top_mpll_d4"
-};
-
-static const char *const i2c_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d5_d4", "top_mpll_d4", "top_net1pll_d8_d4"
-};
-
-static const char *const pextp_tl_ck_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d5_d4", "top_net2pll_d4_d2", "top_rtc_32k"
-};
-
-static const char *const emmc_250m_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d5_d2"
-};
-
-static const char *const emmc_416m_parents[] __initconst = { "top_xtal",
-							     "mpll" };
-
-static const char *const f_26m_adc_parents[] __initconst = { "top_xtal",
-							     "top_mpll_d8_d2" };
-
-static const char *const dramc_md32_parents[] __initconst = { "top_xtal",
-							      "top_mpll_d2" };
-
-static const char *const sysaxi_parents[] __initconst = { "top_xtal",
-							  "top_net1pll_d8_d2",
-							  "top_net2pll_d4" };
-
-static const char *const sysapb_parents[] __initconst = { "top_xtal",
-							  "top_mpll_d3_d2",
-							  "top_net2pll_d4_d2" };
-
-static const char *const arm_db_main_parents[] __initconst = {
-	"top_xtal", "top_net2pll_d3_d2"
-};
-
-static const char *const arm_db_jtsel_parents[] __initconst = { "top_jtag",
-								"top_xtal" };
-
-static const char *const netsys_parents[] __initconst = { "top_xtal",
-							  "top_mmpll_d4" };
-
-static const char *const netsys_500m_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d5"
-};
-
-static const char *const netsys_mcu_parents[] __initconst = {
-	"top_xtal", "wedmcupll", "top_mmpll_d2", "top_net1pll_d4",
-	"top_net1pll_d5"
-};
-
-static const char *const netsys_2x_parents[] __initconst = {
-	"top_xtal", "net2pll", "wedmcupll", "top_mmpll_d2"
-};
-
-static const char *const sgm_325m_parents[] __initconst = { "top_xtal",
-							    "sgmpll" };
-
-static const char *const sgm_reg_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d8_d4"
-};
-
-static const char *const a1sys_parents[] __initconst = { "top_xtal",
-							 "top_apll2_d4" };
-
-static const char *const conn_mcusys_parents[] __initconst = { "top_xtal",
-							       "top_mmpll_d2" };
-
-static const char *const eip_b_parents[] __initconst = { "top_xtal",
-							 "net2pll" };
-
-static const char *const aud_l_parents[] __initconst = { "top_xtal", "apll2",
-							 "top_mpll_d8_d2" };
-
-static const char *const a_tuner_parents[] __initconst = { "top_xtal",
-							   "top_apll2_d4",
-							   "top_mpll_d8_d2" };
-
-static const char *const u2u3_sys_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d5_d4"
-};
-
-static const char *const da_u2_refsel_parents[] __initconst = {
-	"top_xtal", "top_mmpll_u2phy"
-};
-
-static const struct mtk_mux top_muxes[] = {
-	/* CLK_CFG_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
-			     0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
-			     0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
-			     0x004, 0x008, 16, 3, 23, 0x1C0, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
-			     0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
-	/* CLK_CFG_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
-			     0x014, 0x018, 0, 2, 7, 0x1C0, 4),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
-			     0x014, 0x018, 8, 2, 15, 0x1C0, 5),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
-			     0x014, 0x018, 16, 2, 23, 0x1C0, 6),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
-			     pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2,
-			     31, 0x1C0, 7),
-	/* CLK_CFG_2 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
-			     emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7,
-			     0x1C0, 8),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel",
-			     emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15,
-			     0x1C0, 9),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",
-			     f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23,
-			     0x1C0, 10),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents,
-			     0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11),
-	/* CLK_CFG_3 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
-			     dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7,
-			     0x1C0, 12),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents,
-			     0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents,
-			     0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
-			     arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1,
-			     31, 0x1C0, 15),
-	/* CLK_CFG_4 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel",
-			     arm_db_jtsel_parents, 0x040, 0x044, 0x048, 0, 1, 7,
-			     0x1C0, 16),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
-			     0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
-			     netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1,
-			     23, 0x1C0, 18),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
-			     netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
-			     0x1C0, 19),
-	/* CLK_CFG_5 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
-			     netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
-			     0x1C0, 20),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
-			     sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
-			     0x1C0, 21),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
-			     sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23,
-			     0x1C0, 22),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
-			     0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23),
-	/* CLK_CFG_6 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel",
-			     conn_mcusys_parents, 0x060, 0x064, 0x068, 0, 1, 7,
-			     0x1C0, 24),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents,
-			     0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel",
-			     f_26m_adc_parents, 0x060, 0x064, 0x068, 16, 1, 23,
-			     0x1C0, 26),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
-			     f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31,
-			     0x1C0, 27),
-	/* CLK_CFG_7 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel",
-			     f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7,
-			     0x1C0, 28),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
-			     0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
-			     a_tuner_parents, 0x070, 0x074, 0x078, 16, 2, 23,
-			     0x1C0, 30),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents,
-			     0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0),
-	/* CLK_CFG_8 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
-			     u2u3_sys_parents, 0x080, 0x084, 0x088, 0, 1, 7,
-			     0x1C4, 1),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
-			     u2u3_sys_parents, 0x080, 0x084, 0x088, 8, 1, 15,
-			     0x1C4, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel",
-			     da_u2_refsel_parents, 0x080, 0x084, 0x088, 16, 1,
-			     23, 0x1C4, 3),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel",
-			     da_u2_refsel_parents, 0x080, 0x084, 0x088, 24, 1,
-			     31, 0x1C4, 4),
-	/* CLK_CFG_9 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
-			     sgm_reg_parents, 0x090, 0x094, 0x098, 0, 1, 7,
-			     0x1C4, 5),
-};
-
-static int clk_mt7986_topckgen_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) +
-		 ARRAY_SIZE(top_muxes);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
-				    clk_data);
-	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
-	mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
-			       &mt7986_clk_lock, clk_data);
-
-	clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAXI_SEL]);
-	clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAPB_SEL]);
-	clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_SEL]);
-	clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_MD32_SEL]);
-	clk_prepare_enable(clk_data->clks[CLK_TOP_F26M_SEL]);
-	clk_prepare_enable(clk_data->clks[CLK_TOP_SGM_REG_SEL]);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_topckgen_data;
-	}
-	return r;
-
-free_topckgen_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct of_device_id of_match_clk_mt7986_topckgen[] = {
-	{ .compatible = "mediatek,mt7986-topckgen", },
-	{}
-};
-
-static struct platform_driver clk_mt7986_topckgen_drv = {
-	.probe = clk_mt7986_topckgen_probe,
-	.driver = {
-		.name = "clk-mt7986-topckgen",
-		.of_match_table = of_match_clk_mt7986_topckgen,
-	},
-};
-builtin_platform_driver(clk_mt7986_topckgen_drv);

target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c

@@ -13,6 +13,7 @@
 #include "clk-mtk.h"
 #include "clk-gate.h"
 #include "clk-mux.h"
+#include "clk-pll.h"
 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
 
 #define MT7988_PLL_FMAX (2500UL * MHZ)
@@ -72,15 +73,13 @@ static const struct mtk_pll_data plls[] = {
 };
 
 static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
-	{
-		.compatible = "mediatek,mt7988-apmixedsys",
-	},
-	{}
+	{ .compatible = "mediatek,mt7988-apmixedsys", },
+	{ /* sentinel */ }
 };
 
 static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
 {
-	struct clk_onecell_data *clk_data;
+	struct clk_hw_onecell_data *clk_data;
 	struct device_node *node = pdev->dev.of_node;
 	int r;
 
@@ -90,7 +89,7 @@ static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
 
 	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
 
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 	if (r) {
 		pr_err("%s(): could not register clock provider: %d\n",
 		       __func__, r);
@@ -111,3 +110,4 @@ static struct platform_driver clk_mt7988_apmixed_drv = {
 	},
 };
 builtin_platform_driver(clk_mt7988_apmixed_drv);
+MODULE_LICENSE("GPL");

target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c

@@ -40,39 +40,10 @@ static const struct mtk_gate ethdma_clks[] = {
 		    29),
 };
 
-static int clk_mt7988_ethsys_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(ethdma_clks));
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_gates(node, ethdma_clks, ARRAY_SIZE(ethdma_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_data;
-	}
-	return r;
-
-free_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
+static const struct mtk_clk_desc ethdma_desc = {
+	.clks = ethdma_clks,
+	.num_clks = ARRAY_SIZE(ethdma_clks),
+};
 
 static const struct mtk_gate_regs sgmii0_cg_regs = {
 	.set_ofs = 0xe4,
@@ -92,39 +63,10 @@ static const struct mtk_gate sgmii0_clks[] = {
 	GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3),
 };
 
-static int clk_mt7988_sgmii0_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_data;
-	}
-	return r;
-
-free_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
+static const struct mtk_clk_desc sgmii0_desc = {
+	.clks = sgmii0_clks,
+	.num_clks = ARRAY_SIZE(sgmii0_clks),
+};
 
 static const struct mtk_gate_regs sgmii1_cg_regs = {
 	.set_ofs = 0xe4,
@@ -144,39 +86,10 @@ static const struct mtk_gate sgmii1_clks[] = {
 	GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3),
 };
 
-static int clk_mt7988_sgmii1_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_data;
-	}
-	return r;
-
-free_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
+static const struct mtk_clk_desc sgmii1_desc = {
+	.clks = sgmii1_clks,
+	.num_clks = ARRAY_SIZE(sgmii1_clks),
+};
 
 static const struct mtk_gate_regs ethwarp_cg_regs = {
 	.set_ofs = 0x14,
@@ -200,100 +113,29 @@ static const struct mtk_gate ethwarp_clks[] = {
 		     "netsys_mcu_sel", 15),
 };
 
-static int clk_mt7988_ethwarp_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(ethwarp_clks));
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_gates(node, ethwarp_clks, ARRAY_SIZE(ethwarp_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_data;
-	}
-	return r;
-
-free_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct of_device_id of_match_clk_mt7988_ethsys[] = {
-	{
-		.compatible = "mediatek,mt7988-ethsys",
-	},
-	{}
+static const struct mtk_clk_desc ethwarp_desc = {
+	.clks = ethwarp_clks,
+	.num_clks = ARRAY_SIZE(ethwarp_clks),
 };
 
-static struct platform_driver clk_mt7988_ethsys_drv = {
-	.probe = clk_mt7988_ethsys_probe,
-	.driver = {
-		.name = "clk-mt7988-ethsys",
-		.of_match_table = of_match_clk_mt7988_ethsys,
-	},
-};
-builtin_platform_driver(clk_mt7988_ethsys_drv);
-
-static const struct of_device_id of_match_clk_mt7988_sgmii0[] = {
-	{
-		.compatible = "mediatek,mt7988-sgmiisys_0",
-	},
-	{}
+static const struct of_device_id of_match_clk_mt7986_eth[] = {
+	{ .compatible = "mediatek,mt7988-ethsys", .data = &ethdma_desc },
+	{ .compatible = "mediatek,mt7988-sgmiisys_0", .data = &sgmii0_desc },
+	{ .compatible = "mediatek,mt7988-sgmiisys_1", .data = &sgmii1_desc },
+	{ .compatible = "mediatek,mt7988-ethwarp", .data = &ethwarp_desc },
+	{ /* sentinel */ }
 };
+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth);
 
-static struct platform_driver clk_mt7988_sgmii0_drv = {
-	.probe = clk_mt7988_sgmii0_probe,
+static struct platform_driver clk_mt7988_eth_drv = {
 	.driver = {
-		.name = "clk-mt7988-sgmiisys_0",
-		.of_match_table = of_match_clk_mt7988_sgmii0,
+		.name = "clk-mt7988-eth",
+		.of_match_table = of_match_clk_mt7986_eth,
 	},
+	.probe = mtk_clk_simple_probe,
+	.remove = mtk_clk_simple_remove,
 };
-builtin_platform_driver(clk_mt7988_sgmii0_drv);
+module_platform_driver(clk_mt7988_eth_drv);
 
-static const struct of_device_id of_match_clk_mt7988_sgmii1[] = {
-	{
-		.compatible = "mediatek,mt7988-sgmiisys_1",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_sgmii1_drv = {
-	.probe = clk_mt7988_sgmii1_probe,
-	.driver = {
-		.name = "clk-mt7988-sgmiisys_1",
-		.of_match_table = of_match_clk_mt7988_sgmii1,
-	},
-};
-builtin_platform_driver(clk_mt7988_sgmii1_drv);
-
-static const struct of_device_id of_match_clk_mt7988_ethwarp[] = {
-	{
-		.compatible = "mediatek,mt7988-ethwarp",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_ethwarp_drv = {
-	.probe = clk_mt7988_ethwarp_probe,
-	.driver = {
-		.name = "clk-mt7988-ethwarp",
-		.of_match_table = of_match_clk_mt7988_ethwarp,
-	},
-};
-builtin_platform_driver(clk_mt7988_ethwarp_drv);
+MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver");
+MODULE_LICENSE("GPL");

target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c

@@ -344,56 +344,26 @@ static const struct mtk_gate infra_clks[] = {
 		    "sysaxi_sel", 31),
 };
 
-static int clk_mt7988_infracfg_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(infra_muxes) + ARRAY_SIZE(infra_clks);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
-			       &mt7988_clk_lock, clk_data);
-
-	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_infracfg_data;
-	}
-	return r;
-
-free_infracfg_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
+static const struct mtk_clk_desc infra_desc = {
+	.clks = infra_clks,
+	.num_clks = ARRAY_SIZE(infra_clks),
+	.mux_clks = infra_muxes,
+	.num_mux_clks = ARRAY_SIZE(infra_muxes),
+	.clk_lock = &mt7988_clk_lock,
+};
 
 static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
-	{
-		.compatible = "mediatek,mt7988-infracfg",
-	},
-	{}
+	{ .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc },
+	{ /* sentinel */ }
 };
+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg);
 
 static struct platform_driver clk_mt7988_infracfg_drv = {
-	.probe = clk_mt7988_infracfg_probe,
 	.driver = {
 		.name = "clk-mt7988-infracfg",
 		.of_match_table = of_match_clk_mt7988_infracfg,
 	},
+	.probe = mtk_clk_simple_probe,
+	.remove = mtk_clk_simple_remove,
 };
-builtin_platform_driver(clk_mt7988_infracfg_drv);
+module_platform_driver(clk_mt7988_infracfg_drv);

target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c

@@ -395,49 +395,17 @@ static const struct mtk_composite top_aud_divs[] = {
 		 8, 8),
 };
 
-static int clk_mt7988_topckgen_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) +
-		 ARRAY_SIZE(top_muxes) + ARRAY_SIZE(top_aud_divs);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
-				    clk_data);
-
-	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
-
-	mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
-			       &mt7988_clk_lock, clk_data);
-
-	mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
-				    base, &mt7988_clk_lock, clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_topckgen_data;
-	}
-	return r;
-
-free_topckgen_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
+static const struct mtk_clk_desc topck_desc = {
+	.fixed_clks = top_fixed_clks,
+	.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
+	.factor_clks = top_divs,
+	.num_factor_clks = ARRAY_SIZE(top_divs),
+	.mux_clks = top_muxes,
+	.num_mux_clks = ARRAY_SIZE(top_muxes),
+	.composite_clks = top_aud_divs,
+	.num_composite_clks = ARRAY_SIZE(top_aud_divs),
+	.clk_lock = &mt7988_clk_lock,
+};
 
 static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b",
 						   "net1pll_d4" };
@@ -454,69 +422,25 @@ static struct mtk_composite mcu_muxes[] = {
 		       mcu_arm_div_parents, 0x7A8, 9, 2, -1, CLK_IS_CRITICAL),
 };
 
-static int clk_mt7988_mcusys_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(mcu_muxes);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
-				    &mt7988_clk_lock, clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_mcusys_data;
-	}
-	return r;
-
-free_mcusys_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
+static const struct mtk_clk_desc mcusys_desc = {
+	.composite_clks = mcu_muxes,
+	.num_composite_clks = ARRAY_SIZE(mcu_muxes),
+};
 
 static const struct of_device_id of_match_clk_mt7988_topckgen[] = {
-	{
-		.compatible = "mediatek,mt7988-topckgen",
-	},
-	{}
+	{ .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc },
+	{ .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc },
+	{ /* sentinel */ }
 };
+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen);
 
 static struct platform_driver clk_mt7988_topckgen_drv = {
-	.probe = clk_mt7988_topckgen_probe,
+	.probe = mtk_clk_simple_probe,
+	.remove = mtk_clk_simple_remove,
 	.driver = {
 		.name = "clk-mt7988-topckgen",
 		.of_match_table = of_match_clk_mt7988_topckgen,
 	},
 };
-builtin_platform_driver(clk_mt7988_topckgen_drv);
-
-static const struct of_device_id of_match_clk_mt7988_mcusys[] = {
-	{
-		.compatible = "mediatek,mt7988-mcusys",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_mcusys_drv = {
-	.probe = clk_mt7988_mcusys_probe,
-	.driver = {
-		.name = "clk-mt7988-mcusys",
-		.of_match_table = of_match_clk_mt7988_mcusys,
-	},
-};
-builtin_platform_driver(clk_mt7988_mcusys_drv);
+module_platform_driver(clk_mt7988_topckgen_drv);
+MODULE_LICENSE("GPL");

target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-ge-soc.c

@@ -1,1263 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-#include <linux/bitfield.h>
-#include <linux/module.h>
-#include <linux/nvmem-consumer.h>
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/phy.h>
-
-#define MTK_GPHY_ID_MT7981			0x03a29461
-#define MTK_GPHY_ID_MT7988			0x03a29481
-
-#define MTK_EXT_PAGE_ACCESS			0x1f
-#define MTK_PHY_PAGE_STANDARD			0x0000
-#define MTK_PHY_PAGE_EXTENDED_3			0x0003
-
-#define MTK_PHY_LPI_REG_14			0x14
-#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK	GENMASK(8, 0)
-
-#define MTK_PHY_LPI_REG_1c			0x1c
-#define MTK_PHY_SMI_DET_ON_THRESH_MASK		GENMASK(13, 8)
-
-#define MTK_PHY_PAGE_EXTENDED_2A30		0x2a30
-#define MTK_PHY_PAGE_EXTENDED_52B5		0x52b5
-
-#define ANALOG_INTERNAL_OPERATION_MAX_US	20
-#define TXRESERVE_MIN				0
-#define TXRESERVE_MAX				7
-
-#define MTK_PHY_ANARG_RG			0x10
-#define   MTK_PHY_TCLKOFFSET_MASK		GENMASK(12, 8)
-
-/* Registers on MDIO_MMD_VEND1 */
-#define MTK_PHY_TXVLD_DA_RG			0x12
-#define   MTK_PHY_DA_TX_I2MPB_A_GBE_MASK	GENMASK(15, 10)
-#define   MTK_PHY_DA_TX_I2MPB_A_TBT_MASK	GENMASK(5, 0)
-
-#define MTK_PHY_TX_I2MPB_TEST_MODE_A2		0x16
-#define   MTK_PHY_DA_TX_I2MPB_A_HBT_MASK	GENMASK(15, 10)
-#define   MTK_PHY_DA_TX_I2MPB_A_TST_MASK	GENMASK(5, 0)
-
-#define MTK_PHY_TX_I2MPB_TEST_MODE_B1		0x17
-#define   MTK_PHY_DA_TX_I2MPB_B_GBE_MASK	GENMASK(13, 8)
-#define   MTK_PHY_DA_TX_I2MPB_B_TBT_MASK	GENMASK(5, 0)
-
-#define MTK_PHY_TX_I2MPB_TEST_MODE_B2		0x18
-#define   MTK_PHY_DA_TX_I2MPB_B_HBT_MASK	GENMASK(13, 8)
-#define   MTK_PHY_DA_TX_I2MPB_B_TST_MASK	GENMASK(5, 0)
-
-#define MTK_PHY_TX_I2MPB_TEST_MODE_C1		0x19
-#define   MTK_PHY_DA_TX_I2MPB_C_GBE_MASK	GENMASK(13, 8)
-#define   MTK_PHY_DA_TX_I2MPB_C_TBT_MASK	GENMASK(5, 0)
-
-#define MTK_PHY_TX_I2MPB_TEST_MODE_C2		0x20
-#define   MTK_PHY_DA_TX_I2MPB_C_HBT_MASK	GENMASK(13, 8)
-#define   MTK_PHY_DA_TX_I2MPB_C_TST_MASK	GENMASK(5, 0)
-
-#define MTK_PHY_TX_I2MPB_TEST_MODE_D1		0x21
-#define   MTK_PHY_DA_TX_I2MPB_D_GBE_MASK	GENMASK(13, 8)
-#define   MTK_PHY_DA_TX_I2MPB_D_TBT_MASK	GENMASK(5, 0)
-
-#define MTK_PHY_TX_I2MPB_TEST_MODE_D2		0x22
-#define   MTK_PHY_DA_TX_I2MPB_D_HBT_MASK	GENMASK(13, 8)
-#define   MTK_PHY_DA_TX_I2MPB_D_TST_MASK	GENMASK(5, 0)
-
-#define MTK_PHY_RXADC_CTRL_RG7			0xc6
-#define   MTK_PHY_DA_AD_BUF_BIAS_LP_MASK	GENMASK(9, 8)
-
-#define MTK_PHY_RXADC_CTRL_RG9			0xc8
-#define   MTK_PHY_DA_RX_PSBN_TBT_MASK		GENMASK(14, 12)
-#define   MTK_PHY_DA_RX_PSBN_HBT_MASK		GENMASK(10, 8)
-#define   MTK_PHY_DA_RX_PSBN_GBE_MASK		GENMASK(6, 4)
-#define   MTK_PHY_DA_RX_PSBN_LP_MASK		GENMASK(2, 0)
-
-#define MTK_PHY_LDO_OUTPUT_V			0xd7
-
-#define MTK_PHY_RG_ANA_CAL_RG0			0xdb
-#define   MTK_PHY_RG_CAL_CKINV			BIT(12)
-#define   MTK_PHY_RG_ANA_CALEN			BIT(8)
-#define   MTK_PHY_RG_ZCALEN_A			BIT(0)
-
-#define MTK_PHY_RG_ANA_CAL_RG1			0xdc
-#define   MTK_PHY_RG_ZCALEN_B			BIT(12)
-#define   MTK_PHY_RG_ZCALEN_C			BIT(8)
-#define   MTK_PHY_RG_ZCALEN_D			BIT(4)
-#define   MTK_PHY_RG_TXVOS_CALEN		BIT(0)
-
-#define MTK_PHY_RG_ANA_CAL_RG5			0xe0
-#define   MTK_PHY_RG_REXT_TRIM_MASK		GENMASK(13, 8)
-
-#define MTK_PHY_RG_TX_FILTER			0xfe
-
-#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120	0x120
-#define   MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK	GENMASK(12, 8)
-#define   MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK	GENMASK(4, 0)
-
-#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122	0x122
-#define   MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK	GENMASK(7, 0)
-
-#define MTK_PHY_RG_TESTMUX_ADC_CTRL		0x144
-#define   MTK_PHY_RG_TXEN_DIG_MASK		GENMASK(5, 5)
-
-#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B		0x172
-#define   MTK_PHY_CR_TX_AMP_OFFSET_A_MASK	GENMASK(13, 8)
-#define   MTK_PHY_CR_TX_AMP_OFFSET_B_MASK	GENMASK(6, 0)
-
-#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D		0x173
-#define   MTK_PHY_CR_TX_AMP_OFFSET_C_MASK	GENMASK(13, 8)
-#define   MTK_PHY_CR_TX_AMP_OFFSET_D_MASK	GENMASK(6, 0)
-
-#define MTK_PHY_RG_AD_CAL_COMP			0x17a
-#define   MTK_PHY_AD_CAL_COMP_OUT_SHIFT		(8)
-
-#define MTK_PHY_RG_AD_CAL_CLK			0x17b
-#define   MTK_PHY_DA_CAL_CLK			BIT(0)
-
-#define MTK_PHY_RG_AD_CALIN			0x17c
-#define   MTK_PHY_DA_CALIN_FLAG			BIT(0)
-
-#define MTK_PHY_RG_DASN_DAC_IN0_A		0x17d
-#define   MTK_PHY_DASN_DAC_IN0_A_MASK		GENMASK(9, 0)
-
-#define MTK_PHY_RG_DASN_DAC_IN0_B		0x17e
-#define   MTK_PHY_DASN_DAC_IN0_B_MASK		GENMASK(9, 0)
-
-#define MTK_PHY_RG_DASN_DAC_IN0_C		0x17f
-#define   MTK_PHY_DASN_DAC_IN0_C_MASK		GENMASK(9, 0)
-
-#define MTK_PHY_RG_DASN_DAC_IN0_D		0x180
-#define   MTK_PHY_DASN_DAC_IN0_D_MASK		GENMASK(9, 0)
-
-#define MTK_PHY_RG_DASN_DAC_IN1_A		0x181
-#define   MTK_PHY_DASN_DAC_IN1_A_MASK		GENMASK(9, 0)
-
-#define MTK_PHY_RG_DASN_DAC_IN1_B		0x182
-#define   MTK_PHY_DASN_DAC_IN1_B_MASK		GENMASK(9, 0)
-
-#define MTK_PHY_RG_DASN_DAC_IN1_C		0x183
-#define   MTK_PHY_DASN_DAC_IN1_C_MASK		GENMASK(9, 0)
-
-#define MTK_PHY_RG_DASN_DAC_IN1_D		0x184
-#define   MTK_PHY_DASN_DAC_IN1_D_MASK		GENMASK(9, 0)
-
-#define MTK_PHY_RG_DEV1E_REG19b			0x19b
-#define   MTK_PHY_BYPASS_DSP_LPI_READY		BIT(8)
-
-#define MTK_PHY_RG_LP_IIR2_K1_L			0x22a
-#define MTK_PHY_RG_LP_IIR2_K1_U			0x22b
-#define MTK_PHY_RG_LP_IIR2_K2_L			0x22c
-#define MTK_PHY_RG_LP_IIR2_K2_U			0x22d
-#define MTK_PHY_RG_LP_IIR2_K3_L			0x22e
-#define MTK_PHY_RG_LP_IIR2_K3_U			0x22f
-#define MTK_PHY_RG_LP_IIR2_K4_L			0x230
-#define MTK_PHY_RG_LP_IIR2_K4_U			0x231
-#define MTK_PHY_RG_LP_IIR2_K5_L			0x232
-#define MTK_PHY_RG_LP_IIR2_K5_U			0x233
-
-#define MTK_PHY_RG_DEV1E_REG234			0x234
-#define   MTK_PHY_TR_OPEN_LOOP_EN_MASK		GENMASK(0, 0)
-#define   MTK_PHY_LPF_X_AVERAGE_MASK		GENMASK(7, 4)
-#define   MTK_PHY_TR_LP_IIR_EEE_EN		BIT(12)
-
-#define MTK_PHY_RG_LPF_CNT_VAL			0x235
-
-#define MTK_PHY_RG_DEV1E_REG238			0x238
-#define   MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK	GENMASK(8, 0)
-#define   MTK_PHY_LPI_SLV_SEND_TX_EN		BIT(12)
-
-#define MTK_PHY_RG_DEV1E_REG239			0x239
-#define   MTK_PHY_LPI_SEND_LOC_TIMER_MASK	GENMASK(8, 0)
-#define   MTK_PHY_LPI_TXPCS_LOC_RCV		BIT(12)
-
-#define MTK_PHY_RG_DEV1E_REG27C			0x27c
-#define   MTK_PHY_VGASTATE_FFE_THR_ST1_MASK	GENMASK(12, 8)
-#define MTK_PHY_RG_DEV1E_REG27D			0x27d
-#define   MTK_PHY_VGASTATE_FFE_THR_ST2_MASK	GENMASK(4, 0)
-
-#define MTK_PHY_RG_DEV1E_REG2C7			0x2c7
-#define   MTK_PHY_MAX_GAIN_MASK			GENMASK(4, 0)
-#define   MTK_PHY_MIN_GAIN_MASK			GENMASK(12, 8)
-
-#define MTK_PHY_RG_DEV1E_REG2D1			0x2d1
-#define   MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK	GENMASK(7, 0)
-#define   MTK_PHY_LPI_SKIP_SD_SLV_TR		BIT(8)
-#define   MTK_PHY_LPI_TR_READY			BIT(9)
-#define   MTK_PHY_LPI_VCO_EEE_STG0_EN		BIT(10)
-
-#define MTK_PHY_RG_DEV1E_REG323			0x323
-#define   MTK_PHY_EEE_WAKE_MAS_INT_DC		BIT(0)
-#define   MTK_PHY_EEE_WAKE_SLV_INT_DC		BIT(4)
-
-#define MTK_PHY_RG_DEV1E_REG324			0x324
-#define   MTK_PHY_SMI_DETCNT_MAX_MASK		GENMASK(5, 0)
-#define   MTK_PHY_SMI_DET_MAX_EN		BIT(8)
-
-#define MTK_PHY_RG_DEV1E_REG326			0x326
-#define   MTK_PHY_LPI_MODE_SD_ON		BIT(0)
-#define   MTK_PHY_RESET_RANDUPD_CNT		BIT(1)
-#define   MTK_PHY_TREC_UPDATE_ENAB_CLR		BIT(2)
-#define   MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF	BIT(4)
-#define   MTK_PHY_TR_READY_SKIP_AFE_WAKEUP	BIT(5)
-
-#define MTK_PHY_LDO_PUMP_EN_PAIRAB		0x502
-#define MTK_PHY_LDO_PUMP_EN_PAIRCD		0x503
-
-#define MTK_PHY_DA_TX_R50_PAIR_A		0x53d
-#define MTK_PHY_DA_TX_R50_PAIR_B		0x53e
-#define MTK_PHY_DA_TX_R50_PAIR_C		0x53f
-#define MTK_PHY_DA_TX_R50_PAIR_D		0x540
-
-/* Registers on MDIO_MMD_VEND2 */
-#define MTK_PHY_LED0_ON_CTRL			0x24
-#define   MTK_PHY_LED0_ON_MASK			GENMASK(6, 0)
-#define   MTK_PHY_LED0_ON_LINK1000		BIT(0)
-#define   MTK_PHY_LED0_ON_LINK100		BIT(1)
-#define   MTK_PHY_LED0_ON_LINK10		BIT(2)
-#define   MTK_PHY_LED0_ON_LINKDOWN		BIT(3)
-#define   MTK_PHY_LED0_ON_FDX			BIT(4) /* Full duplex */
-#define   MTK_PHY_LED0_ON_HDX			BIT(5) /* Half duplex */
-#define   MTK_PHY_LED0_FORCE_ON			BIT(6)
-#define   MTK_PHY_LED0_POLARITY			BIT(14)
-#define   MTK_PHY_LED0_ENABLE			BIT(15)
-
-#define MTK_PHY_LED0_BLINK_CTRL			0x25
-#define   MTK_PHY_LED0_1000TX			BIT(0)
-#define   MTK_PHY_LED0_1000RX			BIT(1)
-#define   MTK_PHY_LED0_100TX			BIT(2)
-#define   MTK_PHY_LED0_100RX			BIT(3)
-#define   MTK_PHY_LED0_10TX			BIT(4)
-#define   MTK_PHY_LED0_10RX			BIT(5)
-#define   MTK_PHY_LED0_COLLISION		BIT(6)
-#define   MTK_PHY_LED0_RX_CRC_ERR		BIT(7)
-#define   MTK_PHY_LED0_RX_IDLE_ERR		BIT(8)
-#define   MTK_PHY_LED0_FORCE_BLINK		BIT(9)
-
-#define MTK_PHY_LED1_ON_CTRL			0x26
-#define   MTK_PHY_LED1_ON_MASK			GENMASK(6, 0)
-#define   MTK_PHY_LED1_ON_LINK1000		BIT(0)
-#define   MTK_PHY_LED1_ON_LINK100		BIT(1)
-#define   MTK_PHY_LED1_ON_LINK10		BIT(2)
-#define   MTK_PHY_LED1_ON_LINKDOWN		BIT(3)
-#define   MTK_PHY_LED1_ON_FDX			BIT(4) /* Full duplex */
-#define   MTK_PHY_LED1_ON_HDX			BIT(5) /* Half duplex */
-#define   MTK_PHY_LED1_FORCE_ON			BIT(6)
-#define   MTK_PHY_LED1_POLARITY			BIT(14)
-#define   MTK_PHY_LED1_ENABLE			BIT(15)
-
-#define MTK_PHY_LED1_BLINK_CTRL			0x27
-#define   MTK_PHY_LED1_1000TX			BIT(0)
-#define   MTK_PHY_LED1_1000RX			BIT(1)
-#define   MTK_PHY_LED1_100TX			BIT(2)
-#define   MTK_PHY_LED1_100RX			BIT(3)
-#define   MTK_PHY_LED1_10TX			BIT(4)
-#define   MTK_PHY_LED1_10RX			BIT(5)
-#define   MTK_PHY_LED1_COLLISION		BIT(6)
-#define   MTK_PHY_LED1_RX_CRC_ERR		BIT(7)
-#define   MTK_PHY_LED1_RX_IDLE_ERR		BIT(8)
-#define   MTK_PHY_LED1_FORCE_BLINK		BIT(9)
-
-#define MTK_PHY_RG_BG_RASEL			0x115
-#define   MTK_PHY_RG_BG_RASEL_MASK		GENMASK(2, 0)
-
-/* These macro privides efuse parsing for internal phy. */
-#define EFS_DA_TX_I2MPB_A(x)			(((x) >> 0) & GENMASK(5, 0))
-#define EFS_DA_TX_I2MPB_B(x)			(((x) >> 6) & GENMASK(5, 0))
-#define EFS_DA_TX_I2MPB_C(x)			(((x) >> 12) & GENMASK(5, 0))
-#define EFS_DA_TX_I2MPB_D(x)			(((x) >> 18) & GENMASK(5, 0))
-#define EFS_DA_TX_AMP_OFFSET_A(x)		(((x) >> 24) & GENMASK(5, 0))
-
-#define EFS_DA_TX_AMP_OFFSET_B(x)		(((x) >> 0) & GENMASK(5, 0))
-#define EFS_DA_TX_AMP_OFFSET_C(x)		(((x) >> 6) & GENMASK(5, 0))
-#define EFS_DA_TX_AMP_OFFSET_D(x)		(((x) >> 12) & GENMASK(5, 0))
-#define EFS_DA_TX_R50_A(x)			(((x) >> 18) & GENMASK(5, 0))
-#define EFS_DA_TX_R50_B(x)			(((x) >> 24) & GENMASK(5, 0))
-
-#define EFS_DA_TX_R50_C(x)			(((x) >> 0) & GENMASK(5, 0))
-#define EFS_DA_TX_R50_D(x)			(((x) >> 6) & GENMASK(5, 0))
-
-#define EFS_RG_BG_RASEL(x)			(((x) >> 4) & GENMASK(2, 0))
-#define EFS_RG_REXT_TRIM(x)			(((x) >> 7) & GENMASK(5, 0))
-
-enum {
-	NO_PAIR,
-	PAIR_A,
-	PAIR_B,
-	PAIR_C,
-	PAIR_D,
-};
-
-enum {
-	GPHY_PORT0,
-	GPHY_PORT1,
-	GPHY_PORT2,
-	GPHY_PORT3,
-};
-
-enum calibration_mode {
-	EFUSE_K,
-	SW_K
-};
-
-enum CAL_ITEM {
-	REXT,
-	TX_OFFSET,
-	TX_AMP,
-	TX_R50,
-	TX_VCM
-};
-
-enum CAL_MODE {
-	EFUSE_M,
-	SW_M
-};
-
-struct mtk_socphy_shared_priv {
-	u32			boottrap;
-};
-
-static int mtk_socphy_read_page(struct phy_device *phydev)
-{
-	return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
-}
-
-static int mtk_socphy_write_page(struct phy_device *phydev, int page)
-{
-	return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
-}
-
-/* One calibration cycle consists of:
- * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
- *   until AD_CAL_COMP is ready to output calibration result.
- * 2.Wait until DA_CAL_CLK is available.
- * 3.Fetch AD_CAL_COMP_OUT.
- */
-static int cal_cycle(struct phy_device *phydev, int devad,
-		     u32 regnum, u16 mask, u16 cal_val)
-{
-	int reg_val;
-	int ret;
-
-	phy_modify_mmd(phydev, devad, regnum,
-		       mask, cal_val);
-	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
-			 MTK_PHY_DA_CALIN_FLAG);
-
-	ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
-					MTK_PHY_RG_AD_CAL_CLK, reg_val,
-					reg_val & MTK_PHY_DA_CAL_CLK, 500,
-					ANALOG_INTERNAL_OPERATION_MAX_US, false);
-	if (ret) {
-		phydev_err(phydev, "Calibration cycle timeout\n");
-		return ret;
-	}
-
-	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
-			   MTK_PHY_DA_CALIN_FLAG);
-	ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >>
-			   MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
-	phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
-
-	return ret;
-}
-
-static int rext_fill_result(struct phy_device *phydev, u16 *buf)
-{
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
-		       MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8);
-	phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL,
-		       MTK_PHY_RG_BG_RASEL_MASK, buf[1]);
-
-	return 0;
-}
-
-static int rext_cal_efuse(struct phy_device *phydev, u32 *buf)
-{
-	u16 rext_cal_val[2];
-
-	rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]);
-	rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]);
-	rext_fill_result(phydev, rext_cal_val);
-
-	return 0;
-}
-
-static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf)
-{
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
-		       MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8);
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
-		       MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]);
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
-		       MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8);
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
-		       MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]);
-
-	return 0;
-}
-
-static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf)
-{
-	u16 tx_offset_cal_val[4];
-
-	tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]);
-	tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]);
-	tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]);
-	tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]);
-
-	tx_offset_fill_result(phydev, tx_offset_cal_val);
-
-	return 0;
-}
-
-static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
-{
-	int i;
-	int bias[16] = {};
-	const int vals_9461[16] = { 7, 1, 4, 7,
-				    7, 1, 4, 7,
-				    7, 1, 4, 7,
-				    7, 1, 4, 7 };
-	const int vals_9481[16] = { 10, 6, 6, 10,
-				    10, 6, 6, 10,
-				    10, 6, 6, 10,
-				    10, 6, 6, 10 };
-	switch (phydev->drv->phy_id) {
-	case MTK_GPHY_ID_MT7981:
-		/* We add some calibration to efuse values
-		 * due to board level influence.
-		 * GBE: +7, TBT: +1, HBT: +4, TST: +7
-		 */
-		memcpy(bias, (const void *)vals_9461, sizeof(bias));
-		break;
-	case MTK_GPHY_ID_MT7988:
-		memcpy(bias, (const void *)vals_9481, sizeof(bias));
-		break;
-	}
-
-	/* Prevent overflow */
-	for (i = 0; i < 12; i++) {
-		if (buf[i >> 2] + bias[i] > 63) {
-			buf[i >> 2] = 63;
-			bias[i] = 0;
-		}
-	}
-
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
-		       MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10);
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
-		       MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]);
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
-		       MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10);
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
-		       MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]);
-
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
-		       MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8);
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
-		       MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]);
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
-		       MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8);
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
-		       MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]);
-
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
-		       MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8);
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
-		       MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]);
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
-		       MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8);
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
-		       MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]);
-
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
-		       MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8);
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
-		       MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]);
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
-		       MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8);
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
-		       MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]);
-
-	return 0;
-}
-
-static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf)
-{
-	u16 tx_amp_cal_val[4];
-
-	tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]);
-	tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]);
-	tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]);
-	tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]);
-	tx_amp_fill_result(phydev, tx_amp_cal_val);
-
-	return 0;
-}
-
-static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val,
-			      u8 txg_calen_x)
-{
-	int bias = 0;
-	u16 reg, val;
-
-	if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
-		bias = -2;
-
-	val = clamp_val(bias + tx_r50_cal_val, 0, 63);
-
-	switch (txg_calen_x) {
-	case PAIR_A:
-		reg = MTK_PHY_DA_TX_R50_PAIR_A;
-		break;
-	case PAIR_B:
-		reg = MTK_PHY_DA_TX_R50_PAIR_B;
-		break;
-	case PAIR_C:
-		reg = MTK_PHY_DA_TX_R50_PAIR_C;
-		break;
-	case PAIR_D:
-		reg = MTK_PHY_DA_TX_R50_PAIR_D;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8);
-
-	return 0;
-}
-
-static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf,
-			    u8 txg_calen_x)
-{
-	u16 tx_r50_cal_val;
-
-	switch (txg_calen_x) {
-	case PAIR_A:
-		tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]);
-		break;
-	case PAIR_B:
-		tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]);
-		break;
-	case PAIR_C:
-		tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]);
-		break;
-	case PAIR_D:
-		tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]);
-		break;
-	default:
-		return -EINVAL;
-	}
-	tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x);
-
-	return 0;
-}
-
-static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
-{
-	u8 lower_idx, upper_idx, txreserve_val;
-	u8 lower_ret, upper_ret;
-	int ret;
-
-	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
-			 MTK_PHY_RG_ANA_CALEN);
-	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
-			   MTK_PHY_RG_CAL_CKINV);
-	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
-			 MTK_PHY_RG_TXVOS_CALEN);
-
-	switch (rg_txreserve_x) {
-	case PAIR_A:
-		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-				   MTK_PHY_RG_DASN_DAC_IN0_A,
-				   MTK_PHY_DASN_DAC_IN0_A_MASK);
-		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-				   MTK_PHY_RG_DASN_DAC_IN1_A,
-				   MTK_PHY_DASN_DAC_IN1_A_MASK);
-		phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-				 MTK_PHY_RG_ANA_CAL_RG0,
-				 MTK_PHY_RG_ZCALEN_A);
-		break;
-	case PAIR_B:
-		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-				   MTK_PHY_RG_DASN_DAC_IN0_B,
-				   MTK_PHY_DASN_DAC_IN0_B_MASK);
-		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-				   MTK_PHY_RG_DASN_DAC_IN1_B,
-				   MTK_PHY_DASN_DAC_IN1_B_MASK);
-		phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-				 MTK_PHY_RG_ANA_CAL_RG1,
-				 MTK_PHY_RG_ZCALEN_B);
-		break;
-	case PAIR_C:
-		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-				   MTK_PHY_RG_DASN_DAC_IN0_C,
-				   MTK_PHY_DASN_DAC_IN0_C_MASK);
-		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-				   MTK_PHY_RG_DASN_DAC_IN1_C,
-				   MTK_PHY_DASN_DAC_IN1_C_MASK);
-		phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-				 MTK_PHY_RG_ANA_CAL_RG1,
-				 MTK_PHY_RG_ZCALEN_C);
-		break;
-	case PAIR_D:
-		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-				   MTK_PHY_RG_DASN_DAC_IN0_D,
-				   MTK_PHY_DASN_DAC_IN0_D_MASK);
-		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-				   MTK_PHY_RG_DASN_DAC_IN1_D,
-				   MTK_PHY_DASN_DAC_IN1_D_MASK);
-		phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-				 MTK_PHY_RG_ANA_CAL_RG1,
-				 MTK_PHY_RG_ZCALEN_D);
-		break;
-	default:
-		ret = -EINVAL;
-		goto restore;
-	}
-
-	lower_idx = TXRESERVE_MIN;
-	upper_idx = TXRESERVE_MAX;
-
-	phydev_dbg(phydev, "Start TX-VCM SW cal.\n");
-	while ((upper_idx - lower_idx) > 1) {
-		txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2);
-		ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
-				MTK_PHY_DA_RX_PSBN_TBT_MASK |
-				MTK_PHY_DA_RX_PSBN_HBT_MASK |
-				MTK_PHY_DA_RX_PSBN_GBE_MASK |
-				MTK_PHY_DA_RX_PSBN_LP_MASK,
-				txreserve_val << 12 | txreserve_val << 8 |
-				txreserve_val << 4 | txreserve_val);
-		if (ret == 1) {
-			upper_idx = txreserve_val;
-			upper_ret = ret;
-		} else if (ret == 0) {
-			lower_idx = txreserve_val;
-			lower_ret = ret;
-		} else {
-			goto restore;
-		}
-	}
-
-	if (lower_idx == TXRESERVE_MIN) {
-		lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
-				      MTK_PHY_RXADC_CTRL_RG9,
-				      MTK_PHY_DA_RX_PSBN_TBT_MASK |
-				      MTK_PHY_DA_RX_PSBN_HBT_MASK |
-				      MTK_PHY_DA_RX_PSBN_GBE_MASK |
-				      MTK_PHY_DA_RX_PSBN_LP_MASK,
-				      lower_idx << 12 | lower_idx << 8 |
-				      lower_idx << 4 | lower_idx);
-		ret = lower_ret;
-	} else if (upper_idx == TXRESERVE_MAX) {
-		upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
-				      MTK_PHY_RXADC_CTRL_RG9,
-				      MTK_PHY_DA_RX_PSBN_TBT_MASK |
-				      MTK_PHY_DA_RX_PSBN_HBT_MASK |
-				      MTK_PHY_DA_RX_PSBN_GBE_MASK |
-				      MTK_PHY_DA_RX_PSBN_LP_MASK,
-				      upper_idx << 12 | upper_idx << 8 |
-				      upper_idx << 4 | upper_idx);
-		ret = upper_ret;
-	}
-	if (ret < 0)
-		goto restore;
-
-	/* We calibrate TX-VCM in different logic. Check upper index and then
-	 * lower index. If this calibration is valid, apply lower index's result.
-	 */
-	ret = upper_ret - lower_ret;
-	if (ret == 1) {
-		ret = 0;
-		/* Make sure we use upper_idx in our calibration system */
-		cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
-			  MTK_PHY_DA_RX_PSBN_TBT_MASK |
-			  MTK_PHY_DA_RX_PSBN_HBT_MASK |
-			  MTK_PHY_DA_RX_PSBN_GBE_MASK |
-			  MTK_PHY_DA_RX_PSBN_LP_MASK,
-			  upper_idx << 12 | upper_idx << 8 |
-			  upper_idx << 4 | upper_idx);
-		phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx);
-	} else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 &&
-		   lower_ret == 1) {
-		ret = 0;
-		cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
-			  MTK_PHY_DA_RX_PSBN_TBT_MASK |
-			  MTK_PHY_DA_RX_PSBN_HBT_MASK |
-			  MTK_PHY_DA_RX_PSBN_GBE_MASK |
-			  MTK_PHY_DA_RX_PSBN_LP_MASK,
-			  lower_idx << 12 | lower_idx << 8 |
-			  lower_idx << 4 | lower_idx);
-		phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n",
-			    lower_idx);
-	} else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 &&
-		   lower_ret == 0) {
-		ret = 0;
-		phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n",
-			    upper_idx);
-	} else {
-		ret = -EINVAL;
-	}
-
-restore:
-	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
-			   MTK_PHY_RG_ANA_CALEN);
-	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
-			   MTK_PHY_RG_TXVOS_CALEN);
-	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
-			   MTK_PHY_RG_ZCALEN_A);
-	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
-			   MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C |
-			   MTK_PHY_RG_ZCALEN_D);
-
-	return ret;
-}
-
-static void mt798x_phy_common_finetune(struct phy_device *phydev)
-{
-	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-	/* EnabRandUpdTrig = 1 */
-	__phy_write(phydev, 0x11, 0x2f00);
-	__phy_write(phydev, 0x12, 0xe);
-	__phy_write(phydev, 0x10, 0x8fb0);
-
-	/* NormMseLoThresh = 85 */
-	__phy_write(phydev, 0x11, 0x55a0);
-	__phy_write(phydev, 0x12, 0x0);
-	__phy_write(phydev, 0x10, 0x83aa);
-
-	/* TrFreeze = 0 */
-	__phy_write(phydev, 0x11, 0x0);
-	__phy_write(phydev, 0x12, 0x0);
-	__phy_write(phydev, 0x10, 0x9686);
-
-	/* SSTrKp1000Slv = 5 */
-	__phy_write(phydev, 0x11, 0xbaef);
-	__phy_write(phydev, 0x12, 0x2e);
-	__phy_write(phydev, 0x10, 0x968c);
-
-	/* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
-	 * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
-	 */
-	__phy_write(phydev, 0x11, 0xd10a);
-	__phy_write(phydev, 0x12, 0x34);
-	__phy_write(phydev, 0x10, 0x8f82);
-
-	/* VcoSlicerThreshBitsHigh */
-	__phy_write(phydev, 0x11, 0x5555);
-	__phy_write(phydev, 0x12, 0x55);
-	__phy_write(phydev, 0x10, 0x8ec0);
-	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-
-	/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
-		       MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
-		       BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
-
-	/* rg_tr_lpf_cnt_val = 512 */
-	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
-
-	/* IIR2 related */
-	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
-	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
-	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
-	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
-	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
-	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
-	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
-	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
-	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
-	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
-
-	/* FFE peaking */
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
-		       MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8);
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
-		       MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e);
-
-	/* Disable LDO pump */
-	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
-	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
-	/* Adjust LDO output voltage */
-	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
-}
-
-static void mt7981_phy_finetune(struct phy_device *phydev)
-{
-	u16 val[8] = { 0x01ce, 0x01c1,
-		       0x020f, 0x0202,
-		       0x03d0, 0x03c0,
-		       0x0013, 0x0005 };
-	int i, k;
-
-	/* 100M eye finetune:
-	 * Keep middle level of TX MLT3 shapper as default.
-	 * Only change TX MLT3 overshoot level here.
-	 */
-	for (k = 0, i = 1; i < 12; i++) {
-		if (i % 3 == 0)
-			continue;
-		phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
-	}
-
-	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-	/* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
-	__phy_write(phydev, 0x11, 0xc71);
-	__phy_write(phydev, 0x12, 0xc);
-	__phy_write(phydev, 0x10, 0x8fae);
-
-	/* ResetSyncOffset = 6 */
-	__phy_write(phydev, 0x11, 0x600);
-	__phy_write(phydev, 0x12, 0x0);
-	__phy_write(phydev, 0x10, 0x8fc0);
-
-	/* VgaDecRate = 1 */
-	__phy_write(phydev, 0x11, 0x4c2a);
-	__phy_write(phydev, 0x12, 0x3e);
-	__phy_write(phydev, 0x10, 0x8fa4);
-
-	/* FfeUpdGainForce = 4 */
-	__phy_write(phydev, 0x11, 0x240);
-	__phy_write(phydev, 0x12, 0x0);
-	__phy_write(phydev, 0x10, 0x9680);
-
-	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-}
-
-static void mt7988_phy_finetune(struct phy_device *phydev)
-{
-	u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
-			0x020d, 0x0206, 0x0384, 0x03d0,
-			0x03c6, 0x030a, 0x0011, 0x0005 };
-	int i;
-
-	/* Set default MLT3 shaper first */
-	for (i = 0; i < 12; i++)
-		phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]);
-
-	/* TCT finetune */
-	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
-
-	/* Disable TX power saving */
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
-		       MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
-
-	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-
-	/* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
-	__phy_write(phydev, 0x11, 0x671);
-	__phy_write(phydev, 0x12, 0xc);
-	__phy_write(phydev, 0x10, 0x8fae);
-
-	/* ResetSyncOffset = 5 */
-	__phy_write(phydev, 0x11, 0x500);
-	__phy_write(phydev, 0x12, 0x0);
-	__phy_write(phydev, 0x10, 0x8fc0);
-
-	/* VgaDecRate is 1 at default on mt7988 */
-
-	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-
-	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
-	/* TxClkOffset = 2 */
-	__phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
-		     FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
-	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-}
-
-static void mt798x_phy_eee(struct phy_device *phydev)
-{
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1,
-		       MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120,
-		       MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK |
-		       MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK,
-		       FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) |
-		       FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14));
-
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1,
-		       MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
-		       MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
-		       FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
-				  0xff));
-
-	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-			   MTK_PHY_RG_TESTMUX_ADC_CTRL,
-			   MTK_PHY_RG_TXEN_DIG_MASK);
-
-	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-			 MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY);
-
-	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-			   MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN);
-
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238,
-		       MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK |
-		       MTK_PHY_LPI_SLV_SEND_TX_EN,
-		       FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
-
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
-		       MTK_PHY_LPI_SEND_LOC_TIMER_MASK |
-		       MTK_PHY_LPI_TXPCS_LOC_RCV,
-		       FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117));
-
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
-		       MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
-		       FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
-		       FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13));
-
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1,
-		       MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
-		       FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
-				  0x33) |
-		       MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY |
-		       MTK_PHY_LPI_VCO_EEE_STG0_EN);
-
-	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323,
-			 MTK_PHY_EEE_WAKE_MAS_INT_DC |
-			 MTK_PHY_EEE_WAKE_SLV_INT_DC);
-
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324,
-		       MTK_PHY_SMI_DETCNT_MAX_MASK,
-		       FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) |
-		       MTK_PHY_SMI_DET_MAX_EN);
-
-	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326,
-			 MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT |
-			 MTK_PHY_TREC_UPDATE_ENAB_CLR |
-			 MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF |
-			 MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
-
-	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-	/* Regsigdet_sel_1000 = 0 */
-	__phy_write(phydev, 0x11, 0xb);
-	__phy_write(phydev, 0x12, 0x0);
-	__phy_write(phydev, 0x10, 0x9690);
-
-	/* REG_EEE_st2TrKf1000 = 3 */
-	__phy_write(phydev, 0x11, 0x114f);
-	__phy_write(phydev, 0x12, 0x2);
-	__phy_write(phydev, 0x10, 0x969a);
-
-	/* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
-	__phy_write(phydev, 0x11, 0x3028);
-	__phy_write(phydev, 0x12, 0x0);
-	__phy_write(phydev, 0x10, 0x969e);
-
-	/* RegEEE_slv_wake_int_timer_tar = 8 */
-	__phy_write(phydev, 0x11, 0x5010);
-	__phy_write(phydev, 0x12, 0x0);
-	__phy_write(phydev, 0x10, 0x96a0);
-
-	/* RegEEE_trfreeze_timer2 = 586 */
-	__phy_write(phydev, 0x11, 0x24a);
-	__phy_write(phydev, 0x12, 0x0);
-	__phy_write(phydev, 0x10, 0x96a8);
-
-	/* RegEEE100Stg1_tar = 16 */
-	__phy_write(phydev, 0x11, 0x3210);
-	__phy_write(phydev, 0x12, 0x0);
-	__phy_write(phydev, 0x10, 0x96b8);
-
-	/* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */
-	__phy_write(phydev, 0x11, 0x1463);
-	__phy_write(phydev, 0x12, 0x0);
-	__phy_write(phydev, 0x10, 0x96ca);
-
-	/* DfeTailEnableVgaThresh1000 = 27 */
-	__phy_write(phydev, 0x11, 0x36);
-	__phy_write(phydev, 0x12, 0x0);
-	__phy_write(phydev, 0x10, 0x8f80);
-	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-
-	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
-	__phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
-		     FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c));
-
-	__phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK,
-		     FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc));
-	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1,
-		       MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
-		       MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
-		       FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff));
-}
-
-static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
-		  u8 start_pair, u8 end_pair)
-{
-	u8 pair_n;
-	int ret;
-
-	for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
-		/* TX_OFFSET & TX_AMP have no SW calibration. */
-		switch (cal_item) {
-		case TX_VCM:
-			ret = tx_vcm_cal_sw(phydev, pair_n);
-			break;
-		default:
-			return -EINVAL;
-		}
-		if (ret)
-			return ret;
-	}
-	return 0;
-}
-
-static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item,
-		     u8 start_pair, u8 end_pair, u32 *buf)
-{
-	u8 pair_n;
-	int ret;
-
-	for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
-		/* TX_VCM has no efuse calibration. */
-		switch (cal_item) {
-		case REXT:
-			ret = rext_cal_efuse(phydev, buf);
-			break;
-		case TX_OFFSET:
-			ret = tx_offset_cal_efuse(phydev, buf);
-			break;
-		case TX_AMP:
-			ret = tx_amp_cal_efuse(phydev, buf);
-			break;
-		case TX_R50:
-			ret = tx_r50_cal_efuse(phydev, buf, pair_n);
-			break;
-		default:
-			return -EINVAL;
-		}
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-
-static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item,
-		     enum CAL_MODE cal_mode, u8 start_pair,
-		     u8 end_pair, u32 *buf)
-{
-	int ret;
-
-	switch (cal_mode) {
-	case EFUSE_M:
-		ret = cal_efuse(phydev, cal_item, start_pair,
-				end_pair, buf);
-		break;
-	case SW_M:
-		ret = cal_sw(phydev, cal_item, start_pair, end_pair);
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	if (ret) {
-		phydev_err(phydev, "cal %d failed\n", cal_item);
-		return -EIO;
-	}
-
-	return 0;
-}
-
-static int mt798x_phy_calibration(struct phy_device *phydev)
-{
-	int ret = 0;
-	u32 *buf;
-	size_t len;
-	struct nvmem_cell *cell;
-
-	cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
-	if (IS_ERR(cell)) {
-		if (PTR_ERR(cell) == -EPROBE_DEFER)
-			return PTR_ERR(cell);
-		return 0;
-	}
-
-	buf = (u32 *)nvmem_cell_read(cell, &len);
-	if (IS_ERR(buf))
-		return PTR_ERR(buf);
-	nvmem_cell_put(cell);
-
-	if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) {
-		phydev_err(phydev, "invalid efuse data\n");
-		ret = -EINVAL;
-		goto out;
-	}
-
-	ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf);
-	if (ret)
-		goto out;
-	ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf);
-	if (ret)
-		goto out;
-	ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf);
-	if (ret)
-		goto out;
-	ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf);
-	if (ret)
-		goto out;
-	ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf);
-	if (ret)
-		goto out;
-
-out:
-	kfree(buf);
-	return ret;
-}
-
-static int mt798x_phy_config_init(struct phy_device *phydev)
-{
-	switch (phydev->drv->phy_id) {
-	case MTK_GPHY_ID_MT7981:
-		mt7981_phy_finetune(phydev);
-		break;
-	case MTK_GPHY_ID_MT7988:
-		mt7988_phy_finetune(phydev);
-		break;
-	}
-
-	mt798x_phy_common_finetune(phydev);
-	mt798x_phy_eee(phydev);
-
-	return mt798x_phy_calibration(phydev);
-}
-
-static int mt7988_phy_setup_led(struct phy_device *phydev)
-{
-	struct mtk_socphy_shared_priv *priv = phydev->shared->priv;
-	int port = phydev->mdio.addr;
-	u32 reg = priv->boottrap;
-	struct pinctrl *pinctrl;
-
-	phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
-		      MTK_PHY_LED0_ENABLE | MTK_PHY_LED0_POLARITY |
-		      MTK_PHY_LED0_ON_LINK10 |
-		      MTK_PHY_LED0_ON_LINK100 |
-		      MTK_PHY_LED0_ON_LINK1000);
-	phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
-		      MTK_PHY_LED1_ENABLE | MTK_PHY_LED1_POLARITY |
-		      MTK_PHY_LED1_ON_LINK10 |
-		      MTK_PHY_LED1_ON_LINK100 |
-		      MTK_PHY_LED1_ON_LINK1000);
-
-	if ((port == GPHY_PORT0 && reg & BIT(8)) ||
-	    (port == GPHY_PORT1 && reg & BIT(9)) ||
-	    (port == GPHY_PORT2 && reg & BIT(10)) ||
-	    (port == GPHY_PORT3 && reg & BIT(11))) {
-		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
-				   MTK_PHY_LED0_POLARITY);
-		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
-				   MTK_PHY_LED1_POLARITY);
-	}
-
-	phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL,
-		      MTK_PHY_LED0_1000TX | MTK_PHY_LED0_1000RX |
-		      MTK_PHY_LED0_100TX  | MTK_PHY_LED0_100RX  |
-		      MTK_PHY_LED0_10TX   | MTK_PHY_LED0_10RX);
-	phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL,
-		      MTK_PHY_LED1_1000TX | MTK_PHY_LED1_1000RX |
-		      MTK_PHY_LED1_100TX  | MTK_PHY_LED1_100RX  |
-		      MTK_PHY_LED1_10TX   | MTK_PHY_LED1_10RX);
-
-	pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
-	if (IS_ERR(pinctrl)) {
-		dev_err(&phydev->mdio.bus->dev, "Failed to setup LED pins\n");
-		return PTR_ERR(pinctrl);
-	}
-
-	return 0;
-}
-
-static int mt7988_phy_probe_shared(struct phy_device *phydev)
-{
-	struct mtk_socphy_shared_priv *priv = phydev->shared->priv;
-	void __iomem *boottrap;
-	struct device_node *np;
-	u32 reg;
-
-	np = of_find_compatible_node(NULL, NULL, "mediatek,boottrap");
-	if (!np)
-		return -ENOENT;
-
-	boottrap = of_iomap(np, 0);
-	if (!boottrap)
-		return -ENOMEM;
-
-	reg = readl(boottrap);
-	iounmap(boottrap);
-
-	priv->boottrap = reg;
-
-	return 0;
-}
-
-static int mt7981_phy_probe(struct phy_device *phydev)
-{
-	return mt798x_phy_calibration(phydev);
-}
-
-static int mt7988_phy_probe(struct phy_device *phydev)
-{
-	int err;
-
-	err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0,
-				    sizeof(struct mtk_socphy_shared_priv));
-	if (err)
-		return err;
-
-	if (phy_package_probe_once(phydev)) {
-		err = mt7988_phy_probe_shared(phydev);
-		if (err)
-			return err;
-	}
-
-	mt7988_phy_setup_led(phydev);
-
-	return mt798x_phy_calibration(phydev);
-}
-
-static struct phy_driver mtk_socphy_driver[] = {
-	{
-		PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
-		.name		= "MediaTek MT7981 PHY",
-		.config_init	= mt798x_phy_config_init,
-		.config_intr	= genphy_no_config_intr,
-		.handle_interrupt = genphy_handle_interrupt_no_ack,
-		.probe		= mt7981_phy_probe,
-		.suspend	= genphy_suspend,
-		.resume		= genphy_resume,
-		.read_page	= mtk_socphy_read_page,
-		.write_page	= mtk_socphy_write_page,
-	},
-	{
-		PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988),
-		.name		= "MediaTek MT7988 PHY",
-		.config_init	= mt798x_phy_config_init,
-		.config_intr	= genphy_no_config_intr,
-		.handle_interrupt = genphy_handle_interrupt_no_ack,
-		.probe		= mt7988_phy_probe,
-		.suspend	= genphy_suspend,
-		.resume		= genphy_resume,
-		.read_page	= mtk_socphy_read_page,
-		.write_page	= mtk_socphy_write_page,
-	},
-};
-
-module_phy_driver(mtk_socphy_driver);
-
-static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = {
-	{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) },
-	{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) },
-	{ }
-};
-
-MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver");
-MODULE_AUTHOR("Daniel Golle <[email protected]>");
-MODULE_AUTHOR("SkyLake Huang <[email protected]>");
-MODULE_LICENSE("GPL");
-
-MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl);

target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7981.c

@@ -1,1048 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * The MT7981 driver based on Linux generic pinctrl binding.
- *
- * Copyright (C) 2020 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- */
-
-#include "pinctrl-moore.h"
-
-#define MT7981_PIN(_number, _name)				\
-	MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
-
-#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits)	\
-	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
-		       _x_bits, 32, 0)
-
-#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits)	\
-	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
-		      _x_bits, 32, 1)
-
-static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = {
-	PIN_FIELD(0, 56, 0x300, 0x10, 0, 4),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = {
-	PIN_FIELD(0, 56, 0x0, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_di_range[] = {
-	PIN_FIELD(0, 56, 0x200, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_do_range[] = {
-	PIN_FIELD(0, 56, 0x100, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1),
-	PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1),
-	PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1),
-	PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1),
-	PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1),
-	PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1),
-	PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1),
-	PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1),
-	PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1),
-	PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1),
-	PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1),
-	PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1),
-	PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1),
-	PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1),
-	PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1),
-	PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1),
-	PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1),
-	PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1),
-	PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1),
-	PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1),
-	PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1),
-	PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1),
-	PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1),
-	PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1),
-	PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1),
-	PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1),
-	PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1),
-	PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1),
-	PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1),
-	PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x90, 0x10, 9, 1),
-	PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1),
-	PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1),
-	PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1),
-	PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1),
-	PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1),
-	PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1),
-	PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
-	PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1),
-	PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1),
-	PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1),
-	PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1),
-	PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1),
-	PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1),
-	PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1),
-	PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1),
-	PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1),
-	PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1),
-	PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1),
-	PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1),
-	PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1),
-	PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1),
-	PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1),
-	PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1),
-	PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = {
-	PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1),
-	PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = {
-	PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1),
-	PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1),
-	PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1),
-	PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1),
-	PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1),
-	PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3),
-
-	PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3),
-
-	PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3),
-
-	PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3),
-
-	PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1),
-	PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1),
-	PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
-	PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1),
-	PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1),
-	PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1),
-	PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1),
-	PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1),
-	PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1),
-};
-
-static const unsigned int mt7981_pull_type[] = {
-	MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
-	MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
-	MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
-	MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
-	MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
-	MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
-	MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
-	MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
-	MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
-	MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
-	MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
-	MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
-	MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
-	MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
-	MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
-	MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
-	MTK_PULL_PU_PD_TYPE,/*100*/
-};
-
-static const struct mtk_pin_reg_calc mt7981_reg_cals[] = {
-	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range),
-	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range),
-	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range),
-	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range),
-	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range),
-	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range),
-	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range),
-	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range),
-	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range),
-	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range),
-	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range),
-	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range),
-};
-
-static const struct mtk_pin_desc mt7981_pins[] = {
-	MT7981_PIN(0, "GPIO_WPS"),
-	MT7981_PIN(1, "GPIO_RESET"),
-	MT7981_PIN(2, "SYS_WATCHDOG"),
-	MT7981_PIN(3, "PCIE_PERESET_N"),
-	MT7981_PIN(4, "JTAG_JTDO"),
-	MT7981_PIN(5, "JTAG_JTDI"),
-	MT7981_PIN(6, "JTAG_JTMS"),
-	MT7981_PIN(7, "JTAG_JTCLK"),
-	MT7981_PIN(8, "JTAG_JTRST_N"),
-	MT7981_PIN(9, "WO_JTAG_JTDO"),
-	MT7981_PIN(10, "WO_JTAG_JTDI"),
-	MT7981_PIN(11, "WO_JTAG_JTMS"),
-	MT7981_PIN(12, "WO_JTAG_JTCLK"),
-	MT7981_PIN(13, "WO_JTAG_JTRST_N"),
-	MT7981_PIN(14, "USB_VBUS"),
-	MT7981_PIN(15, "PWM0"),
-	MT7981_PIN(16, "SPI0_CLK"),
-	MT7981_PIN(17, "SPI0_MOSI"),
-	MT7981_PIN(18, "SPI0_MISO"),
-	MT7981_PIN(19, "SPI0_CS"),
-	MT7981_PIN(20, "SPI0_HOLD"),
-	MT7981_PIN(21, "SPI0_WP"),
-	MT7981_PIN(22, "SPI1_CLK"),
-	MT7981_PIN(23, "SPI1_MOSI"),
-	MT7981_PIN(24, "SPI1_MISO"),
-	MT7981_PIN(25, "SPI1_CS"),
-	MT7981_PIN(26, "SPI2_CLK"),
-	MT7981_PIN(27, "SPI2_MOSI"),
-	MT7981_PIN(28, "SPI2_MISO"),
-	MT7981_PIN(29, "SPI2_CS"),
-	MT7981_PIN(30, "SPI2_HOLD"),
-	MT7981_PIN(31, "SPI2_WP"),
-	MT7981_PIN(32, "UART0_RXD"),
-	MT7981_PIN(33, "UART0_TXD"),
-	MT7981_PIN(34, "PCIE_CLK_REQ"),
-	MT7981_PIN(35, "PCIE_WAKE_N"),
-	MT7981_PIN(36, "SMI_MDC"),
-	MT7981_PIN(37, "SMI_MDIO"),
-	MT7981_PIN(38, "GBE_INT"),
-	MT7981_PIN(39, "GBE_RESET"),
-	MT7981_PIN(40, "WF_DIG_RESETB"),
-	MT7981_PIN(41, "WF_CBA_RESETB"),
-	MT7981_PIN(42, "WF_XO_REQ"),
-	MT7981_PIN(43, "WF_TOP_CLK"),
-	MT7981_PIN(44, "WF_TOP_DATA"),
-	MT7981_PIN(45, "WF_HB1"),
-	MT7981_PIN(46, "WF_HB2"),
-	MT7981_PIN(47, "WF_HB3"),
-	MT7981_PIN(48, "WF_HB4"),
-	MT7981_PIN(49, "WF_HB0"),
-	MT7981_PIN(50, "WF_HB0_B"),
-	MT7981_PIN(51, "WF_HB5"),
-	MT7981_PIN(52, "WF_HB6"),
-	MT7981_PIN(53, "WF_HB7"),
-	MT7981_PIN(54, "WF_HB8"),
-	MT7981_PIN(55, "WF_HB9"),
-	MT7981_PIN(56, "WF_HB10"),
-};
-
-/* List all groups consisting of these pins dedicated to the enablement of
- * certain hardware block and the corresponding mode for all of the pins.
- * The hardware probably has multiple combinations of these pinouts.
- */
-
-/* WA_AICE */
-static int mt7981_wa_aice1_pins[] = { 0, 1, };
-static int mt7981_wa_aice1_funcs[] = { 2, 2, };
-
-static int mt7981_wa_aice2_pins[] = { 0, 1, };
-static int mt7981_wa_aice2_funcs[] = { 3, 3, };
-
-static int mt7981_wa_aice3_pins[] = { 28, 29, };
-static int mt7981_wa_aice3_funcs[] = { 3, 3, };
-
-static int mt7981_wm_aice1_pins[] = { 9, 10, };
-static int mt7981_wm_aice1_funcs[] = { 2, 2, };
-
-static int mt7981_wm_aice2_pins[] = { 30, 31, };
-static int mt7981_wm_aice2_funcs[] = { 5, 5, };
-
-/* WM_UART */
-static int mt7981_wm_uart_0_pins[] = { 0, 1, };
-static int mt7981_wm_uart_0_funcs[] = { 5, 5, };
-
-static int mt7981_wm_uart_1_pins[] = { 20, 21, };
-static int mt7981_wm_uart_1_funcs[] = { 4, 4, };
-
-static int mt7981_wm_uart_2_pins[] = { 30, 31, };
-static int mt7981_wm_uart_2_funcs[] = { 3, 3, };
-
-/* DFD */
-static int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
-static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
-
-/* SYS_WATCHDOG */
-static int mt7981_watchdog_pins[] = { 2, };
-static int mt7981_watchdog_funcs[] = { 1, };
-
-static int mt7981_watchdog1_pins[] = { 13, };
-static int mt7981_watchdog1_funcs[] = { 5, };
-
-/* PCIE_PERESET_N */
-static int mt7981_pcie_pereset_pins[] = { 3, };
-static int mt7981_pcie_pereset_funcs[] = { 1, };
-
-/* JTAG */
-static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
-static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
-
-/* WM_JTAG */
-static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
-static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
-
-static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
-static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
-
-/* WO0_JTAG */
-static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
-static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
-
-static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
-static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
-
-/* UART2 */
-static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
-static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
-
-/* GBE_LED0 */
-static int mt7981_gbe_led0_pins[] = { 8, };
-static int mt7981_gbe_led0_funcs[] = { 3, };
-
-/* PTA_EXT */
-static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
-static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
-
-static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
-static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
-
-/* PWM2 */
-static int mt7981_pwm2_pins[] = { 7, };
-static int mt7981_pwm2_funcs[] = { 4, };
-
-/* NET_WO0_UART_TXD */
-static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
-static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
-
-static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
-static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
-
-static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
-static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
-
-/* SPI1 */
-static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
-static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
-
-/* I2C */
-static int mt7981_i2c0_0_pins[] = { 6, 7, };
-static int mt7981_i2c0_0_funcs[] = { 6, 6, };
-
-static int mt7981_i2c0_1_pins[] = { 30, 31, };
-static int mt7981_i2c0_1_funcs[] = { 4, 4, };
-
-static int mt7981_i2c0_2_pins[] = { 36, 37, };
-static int mt7981_i2c0_2_funcs[] = { 2, 2, };
-
-static int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
-static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
-
-static int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
-static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
-
-static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
-static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
-
-static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
-static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
-
-/* DFD_NTRST */
-static int mt7981_dfd_ntrst_pins[] = { 8, };
-static int mt7981_dfd_ntrst_funcs[] = { 6, };
-
-/* PWM0 */
-static int mt7981_pwm0_0_pins[] = { 13, };
-static int mt7981_pwm0_0_funcs[] = { 2, };
-
-static int mt7981_pwm0_1_pins[] = { 15, };
-static int mt7981_pwm0_1_funcs[] = { 1, };
-
-/* PWM1 */
-static int mt7981_pwm1_0_pins[] = { 14, };
-static int mt7981_pwm1_0_funcs[] = { 2, };
-
-static int mt7981_pwm1_1_pins[] = { 15, };
-static int mt7981_pwm1_1_funcs[] = { 3, };
-
-/* GBE_LED1 */
-static int mt7981_gbe_led1_pins[] = { 13, };
-static int mt7981_gbe_led1_funcs[] = { 3, };
-
-/* PCM */
-static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
-static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
-
-/* UDI */
-static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
-static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
-
-/* DRV_VBUS */
-static int mt7981_drv_vbus_pins[] = { 14, };
-static int mt7981_drv_vbus_funcs[] = { 1, };
-
-/* EMMC */
-static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
-static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-
-/* SNFI */
-static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
-static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
-
-/* SPI0 */
-static int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
-static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
-
-/* SPI0 */
-static int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
-static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
-
-/* SPI1 */
-static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
-static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
-
-/* SPI2 */
-static int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
-static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
-
-/* SPI2 */
-static int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
-static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
-
-/* UART1 */
-static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
-static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
-
-static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
-static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
-
-/* UART2 */
-static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
-static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
-
-/* UART0 */
-static int mt7981_uart0_pins[] = { 32, 33, };
-static int mt7981_uart0_funcs[] = { 1, 1, };
-
-/* PCIE_CLK_REQ */
-static int mt7981_pcie_clk_pins[] = { 34, };
-static int mt7981_pcie_clk_funcs[] = { 2, };
-
-/* PCIE_WAKE_N */
-static int mt7981_pcie_wake_pins[] = { 35, };
-static int mt7981_pcie_wake_funcs[] = { 2, };
-
-/* MDC_MDIO */
-static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
-static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
-
-static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
-static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
-
-/* WF0_MODE1 */
-static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 };
-static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
-
-/* WF0_MODE3 */
-static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
-static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
-
-/* WF2G_LED */
-static int mt7981_wf2g_led0_pins[] = { 30, };
-static int mt7981_wf2g_led0_funcs[] = { 2, };
-
-static int mt7981_wf2g_led1_pins[] = { 34, };
-static int mt7981_wf2g_led1_funcs[] = { 1, };
-
-/* WF5G_LED */
-static int mt7981_wf5g_led0_pins[] = { 31, };
-static int mt7981_wf5g_led0_funcs[] = { 2, };
-
-static int mt7981_wf5g_led1_pins[] = { 35, };
-static int mt7981_wf5g_led1_funcs[] = { 1, };
-
-/* MT7531_INT */
-static int mt7981_mt7531_int_pins[] = { 38, };
-static int mt7981_mt7531_int_funcs[] = { 1, };
-
-/* ANT_SEL */
-static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
-static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
-
-static const struct group_desc mt7981_groups[] = {
-	/* @GPIO(0,1): WA_AICE(2) */
-	PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1),
-	/* @GPIO(0,1): WA_AICE(3) */
-	PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2),
-	/* @GPIO(0,1): WM_UART(5) */
-	PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0),
-	/* @GPIO(0,1,4,5): DFD(6) */
-	PINCTRL_PIN_GROUP("dfd", mt7981_dfd),
-	/* @GPIO(2): SYS_WATCHDOG(1) */
-	PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog),
-	/* @GPIO(3): PCIE_PERESET_N(1) */
-	PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset),
-	/* @GPIO(4,8) JTAG(1) */
-	PINCTRL_PIN_GROUP("jtag", mt7981_jtag),
-	/* @GPIO(4,8) WM_JTAG(2) */
-	PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0),
-	/* @GPIO(9,13) WO0_JTAG(1) */
-	PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
-	/* @GPIO(4,7) WM_JTAG(3) */
-	PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
-	/* @GPIO(8) GBE_LED0(3) */
-	PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
-	/* @GPIO(4,6) PTA_EXT(4) */
-	PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0),
-	/* @GPIO(7) PWM2(4) */
-	PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2),
-	/* @GPIO(8) NET_WO0_UART_TXD(4) */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0),
-	/* @GPIO(4,7) SPI1(5) */
-	PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0),
-	/* @GPIO(6,7) I2C(5) */
-	PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0),
-	/* @GPIO(0,1,4,5): DFD_NTRST(6) */
-	PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst),
-	/* @GPIO(9,10): WM_AICE(2) */
-	PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1),
-	/* @GPIO(13): PWM0(2) */
-	PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0),
-	/* @GPIO(15): PWM0(1) */
-	PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1),
-	/* @GPIO(14): PWM1(2) */
-	PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0),
-	/* @GPIO(15): PWM1(3) */
-	PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1),
-	/* @GPIO(14) NET_WO0_UART_TXD(3) */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1),
-	/* @GPIO(15) NET_WO0_UART_TXD(4) */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2),
-	/* @GPIO(13) GBE_LED0(3) */
-	PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1),
-	/* @GPIO(9,13) PCM(4) */
-	PINCTRL_PIN_GROUP("pcm", mt7981_pcm),
-	/* @GPIO(13): SYS_WATCHDOG1(5) */
-	PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1),
-	/* @GPIO(9,13) UDI(4) */
-	PINCTRL_PIN_GROUP("udi", mt7981_udi),
-	/* @GPIO(14) DRV_VBUS(1) */
-	PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus),
-	/* @GPIO(15,25): EMMC(2) */
-	PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45),
-	/* @GPIO(16,21): SNFI(3) */
-	PINCTRL_PIN_GROUP("snfi", mt7981_snfi),
-	/* @GPIO(16,19): SPI0(1) */
-	PINCTRL_PIN_GROUP("spi0", mt7981_spi0),
-	/* @GPIO(20,21): SPI0(1) */
-	PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold),
-	/* @GPIO(22,25) SPI1(1) */
-	PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1),
-	/* @GPIO(26,29): SPI2(1) */
-	PINCTRL_PIN_GROUP("spi2", mt7981_spi2),
-	/* @GPIO(30,31): SPI0(1) */
-	PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold),
-	/* @GPIO(16,19): UART1(4) */
-	PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
-	/* @GPIO(26,29): UART1(2) */
-	PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
-	/* @GPIO(22,25): UART1(3) */
-	PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
-	/* @GPIO(22,24) PTA_EXT(4) */
-	PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1),
-	/* @GPIO(20,21): WM_UART(4) */
-	PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1),
-	/* @GPIO(30,31): WM_UART(3) */
-	PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2),
-	/* @GPIO(20,24) WM_JTAG(5) */
-	PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1),
-	/* @GPIO(25,29) WO0_JTAG(5) */
-	PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1),
-	/* @GPIO(28,29): WA_AICE(3) */
-	PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3),
-	/* @GPIO(30,31): WM_AICE(5) */
-	PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2),
-	/* @GPIO(30,31): I2C(4) */
-	PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1),
-	/* @GPIO(30,31): I2C(6) */
-	PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c),
-	/* @GPIO(32,33): I2C(1) */
-	PINCTRL_PIN_GROUP("uart0", mt7981_uart0),
-	/* @GPIO(32,33): I2C(2) */
-	PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c),
-	/* @GPIO(32,33): I2C(3) */
-	PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c),
-	/* @GPIO(32,33): I2C(5) */
-	PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c),
-	/* @GPIO(34): PCIE_CLK_REQ(2) */
-	PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk),
-	/* @GPIO(35): PCIE_WAKE_N(2) */
-	PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake),
-	/* @GPIO(36,37): I2C(2) */
-	PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2),
-	/* @GPIO(36,37): MDC_MDIO(1) */
-	PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio),
-	/* @GPIO(36,37): MDC_MDIO(3) */
-	PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio),
-	/* @GPIO(69,85): WF0_MODE1(1) */
-	PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1),
-	/* @GPIO(74,80): WF0_MODE3(3) */
-	PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3),
-	/* @GPIO(30): WF2G_LED(2) */
-	PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0),
-	/* @GPIO(34): WF2G_LED(1) */
-	PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1),
-	/* @GPIO(31): WF5G_LED(2) */
-	PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0),
-	/* @GPIO(35): WF5G_LED(1) */
-	PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1),
-	/* @GPIO(38): MT7531_INT(1) */
-	PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int),
-	/* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */
-	PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel),
-};
-
-/* Joint those groups owning the same capability in user point of view which
- * allows that people tend to use through the device tree.
- */
-static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
-	"wa_aice3", "wm_aice1_2", };
-static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
-	"net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
-	"uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", };
-static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
-static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
-static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", };
-static const char *mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", "wo0_jtag_0",
-	"wo0_jtag_1", "wm_jtag_1", };
-static const char *mt7981_led_groups[] = { "gbe_led0", "gbe_led1", "wf2g_led0",
-	"wf2g_led1", "wf5g_led0", "wf5g_led1", };
-static const char *mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", };
-static const char *mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1",
-	"pwm1_0", "pwm1_1", };
-static const char *mt7981_spi_groups[] = { "spi1_0", "spi0", "spi0_wp_hold", "spi1_1", "spi2",
-	"spi2_wp_hold", };
-static const char *mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", "u2_phy_i2c",
-	"sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", "i2c0_2", };
-static const char *mt7981_pcm_groups[] = { "pcm", };
-static const char *mt7981_udi_groups[] = { "udi", };
-static const char *mt7981_usb_groups[] = { "drv_vbus", };
-static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", };
-static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio",
-	"wf0_mode1", "wf0_mode3", "mt7531_int", };
-static const char *mt7981_ant_groups[] = { "ant_sel", };
-
-static const struct function_desc mt7981_functions[] = {
-	{"wa_aice",	mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)},
-	{"dfd",	mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)},
-	{"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)},
-	{"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)},
-	{"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)},
-	{"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)},
-	{"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)},
-	{"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)},
-	{"eth",	mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)},
-	{"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)},
-	{"led",	mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)},
-	{"pwm",	mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)},
-	{"spi",	mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)},
-	{"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)},
-	{"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)},
-	{"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)},
-	{"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)},
-};
-
-static const struct mtk_eint_hw mt7981_eint_hw = {
-	.port_mask = 7,
-	.ports     = 7,
-	.ap_num    = ARRAY_SIZE(mt7981_pins),
-	.db_cnt    = 16,
-};
-
-static const char * const mt7981_pinctrl_register_base_names[] = {
-	"gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb",
-	"iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl",
-};
-
-static struct mtk_pin_soc mt7981_data = {
-	.reg_cal = mt7981_reg_cals,
-	.pins = mt7981_pins,
-	.npins = ARRAY_SIZE(mt7981_pins),
-	.grps = mt7981_groups,
-	.ngrps = ARRAY_SIZE(mt7981_groups),
-	.funcs = mt7981_functions,
-	.nfuncs = ARRAY_SIZE(mt7981_functions),
-	.eint_hw = &mt7981_eint_hw,
-	.gpio_m = 0,
-	.ies_present = false,
-	.base_names = mt7981_pinctrl_register_base_names,
-	.nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names),
-	.pull_type = mt7981_pull_type,
-	.bias_set_combo = mtk_pinconf_bias_set_combo,
-	.bias_get_combo = mtk_pinconf_bias_get_combo,
-	.drive_set = mtk_pinconf_drive_set_rev1,
-	.drive_get = mtk_pinconf_drive_get_rev1,
-	.adv_pull_get = mtk_pinconf_adv_pull_get,
-	.adv_pull_set = mtk_pinconf_adv_pull_set,
-};
-
-static const struct of_device_id mt7981_pinctrl_of_match[] = {
-	{ .compatible = "mediatek,mt7981-pinctrl", },
-	{}
-};
-
-static int mt7981_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_moore_pinctrl_probe(pdev, &mt7981_data);
-}
-
-static struct platform_driver mt7981_pinctrl_driver = {
-	.driver = {
-		.name = "mt7981-pinctrl",
-		.of_match_table = mt7981_pinctrl_of_match,
-	},
-	.probe = mt7981_pinctrl_probe,
-};
-
-static int __init mt7981_pinctrl_init(void)
-{
-	return platform_driver_register(&mt7981_pinctrl_driver);
-}
-arch_initcall(mt7981_pinctrl_init);

target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7986.c

@@ -1,1003 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * The MT7986 driver based on Linux generic pinctrl binding.
- *
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- */
-
-#include "pinctrl-moore.h"
-
-#define MT7986_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
-#define MT7986_NOT_BALLOUT_PIN(_number) { .number = _number, .name = NULL }
-
-#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
-			_x_bits)	\
-		PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
-			_x_bits, 32, 0)
-
-/**
- * enum - Locking variants of the iocfg bases
- *
- * MT7986 have multiple bases to program pin configuration listed as the below:
- * iocfg_rt:0x11c30000, iocfg_rb:0x11c40000, iocfg_lt:0x11e20000,
- * iocfg_lb:0x11e30000, iocfg_tr:0x11f00000, iocfg_tl:0x11f10000,
- * _i_based could be used to indicate what base the pin should be mapped into.
- *
- * Each iocfg register base control different group of pads on the SoC
- *
- *
- *  chip carrier
- *
- *      A  B  C  D  E  F  G  H
- *    +------------------------+
- *  8 | o  o  o  o  o  o  o  o |
- *  7 | o  o  o  o  o  o  o  o |
- *  6 | o  o  o  o  o  o  o  o |
- *  5 | o  o  o  o  o  o  o  o |
- *  4 | o  o  o  o  o  o  o  o |
- *  3 | o  o  o  o  o  o  o  o |
- *  2 | o  o  o  o  o  o  o  o |
- *  1 | o  o  o  o  o  o  o  o |
- *    +------------------------+
- *
- *  inside Chip carrier
- *
- *      A  B  C  D  E  F  G  H
- *    +------------------------+
- *  8 |                        |
- *  7 |        TL  TR          |
- *  6 |      +---------+       |
- *  5 |   LT |         | RT    |
- *  4 |      |         |       |
- *  3 |   LB |         | RB    |
- *  2 |      +---------+       |
- *  1 |                        |
- *    +------------------------+
- *
- */
-
-enum {
-	GPIO_BASE,
-	IOCFG_RT_BASE,
-	IOCFG_RB_BASE,
-	IOCFG_LT_BASE,
-	IOCFG_LB_BASE,
-	IOCFG_TR_BASE,
-	IOCFG_TL_BASE,
-};
-
-static const char *const mt7986_pinctrl_register_base_names[] = {
-	"gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", "iocfg_lb", "iocfg_tr",
-	"iocfg_tl",
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_mode_range[] = {
-	PIN_FIELD(0, 100, 0x300, 0x10, 0, 4),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_dir_range[] = {
-	PIN_FIELD(0, 100, 0x0, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_di_range[] = {
-	PIN_FIELD(0, 100, 0x200, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_do_range[] = {
-	PIN_FIELD(0, 100, 0x100, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_ies_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x20, 0x10, 10, 1),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x40, 0x10, 8, 1),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x30, 0x10, 12, 1),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x30, 0x10, 18, 1),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x30, 0x10, 17, 1),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x30, 0x10, 15, 1),
-	PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x30, 0x10, 19, 1),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x30, 0x10, 23, 1),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x30, 0x10, 22, 1),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x30, 0x10, 21, 1),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x20, 0x10, 4, 1),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x20, 0x10, 8, 1),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x20, 0x10, 7, 1),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x20, 0x10, 5, 1),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x20, 0x10, 9, 1),
-	PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x40, 0x10, 18, 1),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x40, 0x10, 12, 1),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x40, 0x10, 22, 1),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x40, 0x10, 20, 1),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x40, 0x10, 26, 1),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x40, 0x10, 24, 1),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x30, 0x10, 10, 1),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x40, 0x10, 15, 1),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x40, 0x10, 14, 1),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x40, 0x10, 13, 1),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x40, 0x10, 16, 1),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x30, 0x10, 16, 1),
-	PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x30, 0x10, 14, 1),
-	PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x30, 0x10, 14, 1),
-	PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x30, 0x10, 12, 1),
-	PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x30, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_smt_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0xf0, 0x10, 17, 1),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x90, 0x10, 10, 1),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0xf0, 0x10, 0, 1),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0xf0, 0x10, 8, 1),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0xf0, 0x10, 2, 1),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0xc0, 0x10, 12, 1),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0xc0, 0x10, 18, 1),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0xc0, 0x10, 17, 1),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0xc0, 0x10, 15, 1),
-	PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0xc0, 0x10, 19, 1),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0xc0, 0x10, 23, 1),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0xc0, 0x10, 22, 1),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0xc0, 0x10, 21, 1),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x90, 0x10, 4, 1),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x90, 0x10, 8, 1),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x90, 0x10, 7, 1),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x90, 0x10, 5, 1),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x90, 0x10, 9, 1),
-	PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0xf0, 0x10, 18, 1),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xf0, 0x10, 12, 1),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0xf0, 0x10, 22, 1),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0xf0, 0x10, 20, 1),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0xf0, 0x10, 26, 1),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0xf0, 0x10, 24, 1),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0xc0, 0x10, 2, 1),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0xc0, 0x10, 1, 1),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0xc0, 0x10, 0, 1),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0xc0, 0x10, 10, 1),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0xf0, 0x10, 15, 1),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0xf0, 0x10, 14, 1),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0xf0, 0x10, 13, 1),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0xf0, 0x10, 16, 1),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x90, 0x10, 2, 1),
-	PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x80, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x80, 0x10, 0, 1),
-	PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x80, 0x10, 16, 1),
-	PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x80, 0x10, 14, 1),
-	PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x80, 0x10, 4, 1),
-	PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x80, 0x10, 6, 1),
-	PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x80, 0x10, 2, 1),
-	PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x80, 0x10, 9, 1),
-	PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x80, 0x10, 5, 1),
-	PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x70, 0x10, 1, 1),
-	PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x70, 0x10, 14, 1),
-	PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x70, 0x10, 12, 1),
-	PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x70, 0x10, 4, 1),
-	PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x70, 0x10, 2, 1),
-	PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x70, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_pu_range[] = {
-	PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x50, 0x10, 16, 1),
-	PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x50, 0x10, 14, 1),
-	PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x50, 0x10, 14, 1),
-	PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x50, 0x10, 12, 1),
-	PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x50, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_pd_range[] = {
-	PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x40, 0x10, 16, 1),
-	PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x40, 0x10, 14, 1),
-	PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x40, 0x10, 14, 1),
-	PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x40, 0x10, 12, 1),
-	PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x40, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_drv_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x10, 0x10, 21, 3),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x00, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(11, 12, IOCFG_RB_BASE, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(13, 14, IOCFG_RB_BASE, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x10, 0x10, 6, 3),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x10, 0x10, 24, 3),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x10, 0x10, 21, 3),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x10, 0x10, 15, 3),
-	PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x10, 0x10, 27, 3),
-	PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x20, 0x10, 0, 3),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x20, 0x10, 9, 3),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x20, 0x10, 6, 3),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x20, 0x10, 3, 3),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 27, 3),
-	PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x20, 0x10, 0, 3),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x10, 0x10, 6, 3),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x20, 0x10, 9, 3),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x20, 0x10, 3, 3),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x20, 0x10, 21, 3),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x20, 0x10, 15, 3),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x10, 0x10, 15, 3),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x10, 0x10, 12, 3),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x10, 0x10, 9, 3),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x10, 0x10, 18, 3),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x00, 0x10, 2, 3),
-	PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x10, 0x10, 18, 3),
-	PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x10, 0x10, 12, 3),
-	PIN_FIELD_BASE(74, 77, IOCFG_TR_BASE, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(81, 84, IOCFG_TR_BASE, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x10, 0x10, 12, 3),
-	PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x10, 0x10, 6, 3),
-	PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(97, 98, IOCFG_TL_BASE, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(99, 100, IOCFG_TL_BASE, 0x10, 0x10, 2, 3),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_pupd_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x60, 0x10, 17, 1),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x30, 0x10, 10, 1),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x60, 0x10, 8, 1),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x60, 0x10, 2, 1),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x40, 0x10, 12, 1),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x40, 0x10, 18, 1),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x40, 0x10, 17, 1),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x40, 0x10, 15, 1),
-	PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x40, 0x10, 19, 1),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x40, 0x10, 23, 1),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x40, 0x10, 22, 1),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x40, 0x10, 21, 1),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x60, 0x10, 18, 1),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x60, 0x10, 12, 1),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x60, 0x10, 23, 1),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x60, 0x10, 21, 1),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x60, 0x10, 27, 1),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x60, 0x10, 25, 1),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x60, 0x10, 15, 1),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x60, 0x10, 14, 1),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x60, 0x10, 13, 1),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x60, 0x10, 16, 1),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x40, 0x10, 2, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_r0_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x70, 0x10, 17, 1),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x70, 0x10, 8, 1),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x70, 0x10, 2, 1),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x50, 0x10, 12, 1),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x50, 0x10, 18, 1),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x50, 0x10, 17, 1),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x50, 0x10, 15, 1),
-	PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x50, 0x10, 19, 1),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x50, 0x10, 23, 1),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x50, 0x10, 22, 1),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x50, 0x10, 21, 1),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x40, 0x10, 8, 1),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x70, 0x10, 18, 1),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 12, 1),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x70, 0x10, 23, 1),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x70, 0x10, 21, 1),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x70, 0x10, 27, 1),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x70, 0x10, 25, 1),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x50, 0x10, 10, 1),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x70, 0x10, 15, 1),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x70, 0x10, 14, 1),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x70, 0x10, 13, 1),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x70, 0x10, 16, 1),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x50, 0x10, 2, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_r1_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x80, 0x10, 17, 1),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x50, 0x10, 10, 1),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x80, 0x10, 0, 1),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x80, 0x10, 8, 1),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x80, 0x10, 2, 1),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x60, 0x10, 12, 1),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x60, 0x10, 18, 1),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x60, 0x10, 17, 1),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x60, 0x10, 15, 1),
-	PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x60, 0x10, 19, 1),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x60, 0x10, 23, 1),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x60, 0x10, 22, 1),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x60, 0x10, 21, 1),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x50, 0x10, 8, 1),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x80, 0x10, 18, 1),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x80, 0x10, 12, 1),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x80, 0x10, 23, 1),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x80, 0x10, 21, 1),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x80, 0x10, 27, 1),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x80, 0x10, 25, 1),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x60, 0x10, 2, 1),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x60, 0x10, 10, 1),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x80, 0x10, 15, 1),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x80, 0x10, 14, 1),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x80, 0x10, 13, 1),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x80, 0x10, 16, 1),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
-};
-
-static const unsigned int mt7986_pull_type[] = {
-	MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
-	MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
-	MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
-	MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
-	MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
-	MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
-	MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
-	MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
-	MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
-	MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
-	MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
-	MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
-	MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
-	MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
-	MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
-	MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
-	MTK_PULL_PU_PD_TYPE,/*100*/
-};
-
-static const struct mtk_pin_reg_calc mt7986_reg_cals[] = {
-	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range),
-	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range),
-	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7986_pin_di_range),
-	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7986_pin_do_range),
-	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7986_pin_smt_range),
-	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7986_pin_ies_range),
-	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7986_pin_drv_range),
-	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7986_pin_pu_range),
-	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7986_pin_pd_range),
-	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7986_pin_pupd_range),
-	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7986_pin_r0_range),
-	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7986_pin_r1_range),
-};
-
-static const struct mtk_pin_desc mt7986a_pins[] = {
-	MT7986_PIN(0, "SYS_WATCHDOG"),
-	MT7986_PIN(1, "WF2G_LED"),
-	MT7986_PIN(2, "WF5G_LED"),
-	MT7986_PIN(3, "I2C_SCL"),
-	MT7986_PIN(4, "I2C_SDA"),
-	MT7986_PIN(5, "GPIO_0"),
-	MT7986_PIN(6, "GPIO_1"),
-	MT7986_PIN(7, "GPIO_2"),
-	MT7986_PIN(8, "GPIO_3"),
-	MT7986_PIN(9, "GPIO_4"),
-	MT7986_PIN(10, "GPIO_5"),
-	MT7986_PIN(11, "GPIO_6"),
-	MT7986_PIN(12, "GPIO_7"),
-	MT7986_PIN(13, "GPIO_8"),
-	MT7986_PIN(14, "GPIO_9"),
-	MT7986_PIN(15, "GPIO_10"),
-	MT7986_PIN(16, "GPIO_11"),
-	MT7986_PIN(17, "GPIO_12"),
-	MT7986_PIN(18, "GPIO_13"),
-	MT7986_PIN(19, "GPIO_14"),
-	MT7986_PIN(20, "GPIO_15"),
-	MT7986_PIN(21, "PWM0"),
-	MT7986_PIN(22, "PWM1"),
-	MT7986_PIN(23, "SPI0_CLK"),
-	MT7986_PIN(24, "SPI0_MOSI"),
-	MT7986_PIN(25, "SPI0_MISO"),
-	MT7986_PIN(26, "SPI0_CS"),
-	MT7986_PIN(27, "SPI0_HOLD"),
-	MT7986_PIN(28, "SPI0_WP"),
-	MT7986_PIN(29, "SPI1_CLK"),
-	MT7986_PIN(30, "SPI1_MOSI"),
-	MT7986_PIN(31, "SPI1_MISO"),
-	MT7986_PIN(32, "SPI1_CS"),
-	MT7986_PIN(33, "SPI2_CLK"),
-	MT7986_PIN(34, "SPI2_MOSI"),
-	MT7986_PIN(35, "SPI2_MISO"),
-	MT7986_PIN(36, "SPI2_CS"),
-	MT7986_PIN(37, "SPI2_HOLD"),
-	MT7986_PIN(38, "SPI2_WP"),
-	MT7986_PIN(39, "UART0_RXD"),
-	MT7986_PIN(40, "UART0_TXD"),
-	MT7986_PIN(41, "PCIE_PERESET_N"),
-	MT7986_PIN(42, "UART1_RXD"),
-	MT7986_PIN(43, "UART1_TXD"),
-	MT7986_PIN(44, "UART1_CTS"),
-	MT7986_PIN(45, "UART1_RTS"),
-	MT7986_PIN(46, "UART2_RXD"),
-	MT7986_PIN(47, "UART2_TXD"),
-	MT7986_PIN(48, "UART2_CTS"),
-	MT7986_PIN(49, "UART2_RTS"),
-	MT7986_PIN(50, "EMMC_DATA_0"),
-	MT7986_PIN(51, "EMMC_DATA_1"),
-	MT7986_PIN(52, "EMMC_DATA_2"),
-	MT7986_PIN(53, "EMMC_DATA_3"),
-	MT7986_PIN(54, "EMMC_DATA_4"),
-	MT7986_PIN(55, "EMMC_DATA_5"),
-	MT7986_PIN(56, "EMMC_DATA_6"),
-	MT7986_PIN(57, "EMMC_DATA_7"),
-	MT7986_PIN(58, "EMMC_CMD"),
-	MT7986_PIN(59, "EMMC_CK"),
-	MT7986_PIN(60, "EMMC_DSL"),
-	MT7986_PIN(61, "EMMC_RSTB"),
-	MT7986_PIN(62, "PCM_DTX"),
-	MT7986_PIN(63, "PCM_DRX"),
-	MT7986_PIN(64, "PCM_CLK"),
-	MT7986_PIN(65, "PCM_FS"),
-	MT7986_PIN(66, "MT7531_INT"),
-	MT7986_PIN(67, "SMI_MDC"),
-	MT7986_PIN(68, "SMI_MDIO"),
-	MT7986_PIN(69, "WF0_DIG_RESETB"),
-	MT7986_PIN(70, "WF0_CBA_RESETB"),
-	MT7986_PIN(71, "WF0_XO_REQ"),
-	MT7986_PIN(72, "WF0_TOP_CLK"),
-	MT7986_PIN(73, "WF0_TOP_DATA"),
-	MT7986_PIN(74, "WF0_HB1"),
-	MT7986_PIN(75, "WF0_HB2"),
-	MT7986_PIN(76, "WF0_HB3"),
-	MT7986_PIN(77, "WF0_HB4"),
-	MT7986_PIN(78, "WF0_HB0"),
-	MT7986_PIN(79, "WF0_HB0_B"),
-	MT7986_PIN(80, "WF0_HB5"),
-	MT7986_PIN(81, "WF0_HB6"),
-	MT7986_PIN(82, "WF0_HB7"),
-	MT7986_PIN(83, "WF0_HB8"),
-	MT7986_PIN(84, "WF0_HB9"),
-	MT7986_PIN(85, "WF0_HB10"),
-	MT7986_PIN(86, "WF1_DIG_RESETB"),
-	MT7986_PIN(87, "WF1_CBA_RESETB"),
-	MT7986_PIN(88, "WF1_XO_REQ"),
-	MT7986_PIN(89, "WF1_TOP_CLK"),
-	MT7986_PIN(90, "WF1_TOP_DATA"),
-	MT7986_PIN(91, "WF1_HB1"),
-	MT7986_PIN(92, "WF1_HB2"),
-	MT7986_PIN(93, "WF1_HB3"),
-	MT7986_PIN(94, "WF1_HB4"),
-	MT7986_PIN(95, "WF1_HB0"),
-	MT7986_PIN(96, "WF1_HB0_B"),
-	MT7986_PIN(97, "WF1_HB5"),
-	MT7986_PIN(98, "WF1_HB6"),
-	MT7986_PIN(99, "WF1_HB7"),
-	MT7986_PIN(100, "WF1_HB8"),
-};
-
-static const struct mtk_pin_desc mt7986b_pins[] = {
-	MT7986_PIN(0, "SYS_WATCHDOG"),
-	MT7986_PIN(1, "WF2G_LED"),
-	MT7986_PIN(2, "WF5G_LED"),
-	MT7986_PIN(3, "I2C_SCL"),
-	MT7986_PIN(4, "I2C_SDA"),
-	MT7986_PIN(5, "GPIO_0"),
-	MT7986_PIN(6, "GPIO_1"),
-	MT7986_PIN(7, "GPIO_2"),
-	MT7986_PIN(8, "GPIO_3"),
-	MT7986_PIN(9, "GPIO_4"),
-	MT7986_PIN(10, "GPIO_5"),
-	MT7986_PIN(11, "GPIO_6"),
-	MT7986_PIN(12, "GPIO_7"),
-	MT7986_PIN(13, "GPIO_8"),
-	MT7986_PIN(14, "GPIO_9"),
-	MT7986_PIN(15, "GPIO_10"),
-	MT7986_PIN(16, "GPIO_11"),
-	MT7986_PIN(17, "GPIO_12"),
-	MT7986_PIN(18, "GPIO_13"),
-	MT7986_PIN(19, "GPIO_14"),
-	MT7986_PIN(20, "GPIO_15"),
-	MT7986_PIN(21, "PWM0"),
-	MT7986_PIN(22, "PWM1"),
-	MT7986_PIN(23, "SPI0_CLK"),
-	MT7986_PIN(24, "SPI0_MOSI"),
-	MT7986_PIN(25, "SPI0_MISO"),
-	MT7986_PIN(26, "SPI0_CS"),
-	MT7986_PIN(27, "SPI0_HOLD"),
-	MT7986_PIN(28, "SPI0_WP"),
-	MT7986_PIN(29, "SPI1_CLK"),
-	MT7986_PIN(30, "SPI1_MOSI"),
-	MT7986_PIN(31, "SPI1_MISO"),
-	MT7986_PIN(32, "SPI1_CS"),
-	MT7986_PIN(33, "SPI2_CLK"),
-	MT7986_PIN(34, "SPI2_MOSI"),
-	MT7986_PIN(35, "SPI2_MISO"),
-	MT7986_PIN(36, "SPI2_CS"),
-	MT7986_PIN(37, "SPI2_HOLD"),
-	MT7986_PIN(38, "SPI2_WP"),
-	MT7986_PIN(39, "UART0_RXD"),
-	MT7986_PIN(40, "UART0_TXD"),
-	MT7986_NOT_BALLOUT_PIN(41),
-	MT7986_NOT_BALLOUT_PIN(42),
-	MT7986_NOT_BALLOUT_PIN(43),
-	MT7986_NOT_BALLOUT_PIN(44),
-	MT7986_NOT_BALLOUT_PIN(45),
-	MT7986_NOT_BALLOUT_PIN(46),
-	MT7986_NOT_BALLOUT_PIN(47),
-	MT7986_NOT_BALLOUT_PIN(48),
-	MT7986_NOT_BALLOUT_PIN(49),
-	MT7986_NOT_BALLOUT_PIN(50),
-	MT7986_NOT_BALLOUT_PIN(51),
-	MT7986_NOT_BALLOUT_PIN(52),
-	MT7986_NOT_BALLOUT_PIN(53),
-	MT7986_NOT_BALLOUT_PIN(54),
-	MT7986_NOT_BALLOUT_PIN(55),
-	MT7986_NOT_BALLOUT_PIN(56),
-	MT7986_NOT_BALLOUT_PIN(57),
-	MT7986_NOT_BALLOUT_PIN(58),
-	MT7986_NOT_BALLOUT_PIN(59),
-	MT7986_NOT_BALLOUT_PIN(60),
-	MT7986_NOT_BALLOUT_PIN(61),
-	MT7986_NOT_BALLOUT_PIN(62),
-	MT7986_NOT_BALLOUT_PIN(63),
-	MT7986_NOT_BALLOUT_PIN(64),
-	MT7986_NOT_BALLOUT_PIN(65),
-	MT7986_PIN(66, "MT7531_INT"),
-	MT7986_PIN(67, "SMI_MDC"),
-	MT7986_PIN(68, "SMI_MDIO"),
-	MT7986_PIN(69, "WF0_DIG_RESETB"),
-	MT7986_PIN(70, "WF0_CBA_RESETB"),
-	MT7986_PIN(71, "WF0_XO_REQ"),
-	MT7986_PIN(72, "WF0_TOP_CLK"),
-	MT7986_PIN(73, "WF0_TOP_DATA"),
-	MT7986_PIN(74, "WF0_HB1"),
-	MT7986_PIN(75, "WF0_HB2"),
-	MT7986_PIN(76, "WF0_HB3"),
-	MT7986_PIN(77, "WF0_HB4"),
-	MT7986_PIN(78, "WF0_HB0"),
-	MT7986_PIN(79, "WF0_HB0_B"),
-	MT7986_PIN(80, "WF0_HB5"),
-	MT7986_PIN(81, "WF0_HB6"),
-	MT7986_PIN(82, "WF0_HB7"),
-	MT7986_PIN(83, "WF0_HB8"),
-	MT7986_PIN(84, "WF0_HB9"),
-	MT7986_PIN(85, "WF0_HB10"),
-	MT7986_PIN(86, "WF1_DIG_RESETB"),
-	MT7986_PIN(87, "WF1_CBA_RESETB"),
-	MT7986_PIN(88, "WF1_XO_REQ"),
-	MT7986_PIN(89, "WF1_TOP_CLK"),
-	MT7986_PIN(90, "WF1_TOP_DATA"),
-	MT7986_PIN(91, "WF1_HB1"),
-	MT7986_PIN(92, "WF1_HB2"),
-	MT7986_PIN(93, "WF1_HB3"),
-	MT7986_PIN(94, "WF1_HB4"),
-	MT7986_PIN(95, "WF1_HB0"),
-	MT7986_PIN(96, "WF1_HB0_B"),
-	MT7986_PIN(97, "WF1_HB5"),
-	MT7986_PIN(98, "WF1_HB6"),
-	MT7986_PIN(99, "WF1_HB7"),
-	MT7986_PIN(100, "WF1_HB8"),
-};
-
-/* List all groups consisting of these pins dedicated to the enablement of
- * certain hardware block and the corresponding mode for all of the pins.
- * The hardware probably has multiple combinations of these pinouts.
- */
-
-static int mt7986_watchdog_pins[] = { 0, };
-static int mt7986_watchdog_funcs[] = { 1, };
-
-static int mt7986_wifi_led_pins[] = { 1, 2, };
-static int mt7986_wifi_led_funcs[] = { 1, 1, };
-
-static int mt7986_i2c_pins[] = { 3, 4, };
-static int mt7986_i2c_funcs[] = { 1, 1, };
-
-static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, };
-static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, };
-static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7986_pwm1_1_pins[] = { 20, };
-static int mt7986_pwm1_1_funcs[] = { 2, };
-
-static int mt7986_pwm0_pins[] = { 21, };
-static int mt7986_pwm0_funcs[] = { 1, };
-
-static int mt7986_pwm1_0_pins[] = { 22, };
-static int mt7986_pwm1_0_funcs[] = { 1, };
-
-static int mt7986_emmc_45_pins[] = {
-	22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, };
-static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-
-static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, };
-static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, };
-
-static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, };
-static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, };
-static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, };
-
-static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
-static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, };
-static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, };
-
-static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, };
-static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, };
-
-static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, };
-static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, };
-
-static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, };
-static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, };
-
-static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
-static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_spi0_wp_hold_pins[] = { 37, 38, };
-static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, };
-
-static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, };
-static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, };
-static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, };
-
-static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, };
-static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, };
-
-static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, };
-static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, };
-
-static int mt7986_uart0_pins[] = { 39, 40, };
-static int mt7986_uart0_funcs[] = { 1, 1, };
-
-static int mt7986_pcie_reset_pins[] = { 41, };
-static int mt7986_pcie_reset_funcs[] = { 1, };
-
-static int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
-static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_uart1_rx_tx_pins[] = { 42, 43, };
-static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, };
-
-static int mt7986_uart1_cts_rts_pins[] = { 44, 45, };
-static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, };
-
-static int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
-static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_emmc_51_pins[] = {
-	50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, };
-static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-
-static int mt7986_pcm_pins[] = { 62, 63, 64, 65, };
-static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_i2s_pins[] = { 62, 63, 64, 65, };
-static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_switch_int_pins[] = { 66, };
-static int mt7986_switch_int_funcs[] = { 1, };
-
-static int mt7986_mdc_mdio_pins[] = { 67, 68, };
-static int mt7986_mdc_mdio_funcs[] = { 1, 1, };
-
-static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, };
-static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-
-static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, };
-static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-
-static int mt7986_wf_dbdc_pins[] = {
-	74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, };
-static int mt7986_wf_dbdc_funcs[] = {
-	2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-
-static int mt7986_pcie_clk_pins[] = { 9, };
-static int mt7986_pcie_clk_funcs[] = { 1, };
-
-static int mt7986_pcie_wake_pins[] = { 10, };
-static int mt7986_pcie_wake_funcs[] = { 1, };
-
-static const struct group_desc mt7986_groups[] = {
-	PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog),
-	PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led),
-	PINCTRL_PIN_GROUP("i2c", mt7986_i2c),
-	PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0),
-	PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx),
-	PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts),
-	PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk),
-	PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake),
-	PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0),
-	PINCTRL_PIN_GROUP("pwm1_1", mt7986_pwm1_1),
-	PINCTRL_PIN_GROUP("pwm0", mt7986_pwm0),
-	PINCTRL_PIN_GROUP("pwm1_0", mt7986_pwm1_0),
-	PINCTRL_PIN_GROUP("emmc_45", mt7986_emmc_45),
-	PINCTRL_PIN_GROUP("snfi", mt7986_snfi),
-	PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1),
-	PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1),
-	PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2),
-	PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx),
-	PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts),
-	PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx),
-	PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts),
-	PINCTRL_PIN_GROUP("spi0", mt7986_spi0),
-	PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold),
-	PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1),
-	PINCTRL_PIN_GROUP("uart1_3_rx_tx", mt7986_uart1_3_rx_tx),
-	PINCTRL_PIN_GROUP("uart1_3_cts_rts", mt7986_uart1_3_cts_rts),
-	PINCTRL_PIN_GROUP("spi1_3", mt7986_spi1_3),
-	PINCTRL_PIN_GROUP("uart0", mt7986_uart0),
-	PINCTRL_PIN_GROUP("switch_int", mt7986_switch_int),
-	PINCTRL_PIN_GROUP("mdc_mdio", mt7986_mdc_mdio),
-	PINCTRL_PIN_GROUP("pcie_pereset", mt7986_pcie_reset),
-	PINCTRL_PIN_GROUP("uart1", mt7986_uart1),
-	PINCTRL_PIN_GROUP("uart2", mt7986_uart2),
-	PINCTRL_PIN_GROUP("emmc_51", mt7986_emmc_51),
-	PINCTRL_PIN_GROUP("pcm", mt7986_pcm),
-	PINCTRL_PIN_GROUP("i2s", mt7986_i2s),
-	PINCTRL_PIN_GROUP("wf_2g", mt7986_wf_2g),
-	PINCTRL_PIN_GROUP("wf_5g", mt7986_wf_5g),
-	PINCTRL_PIN_GROUP("wf_dbdc", mt7986_wf_dbdc),
-};
-
-/* Joint those groups owning the same capability in user point of view which
- * allows that people tend to use through the device tree.
- */
-
-static const char *mt7986_audio_groups[] = { "pcm", "i2s" };
-static const char *mt7986_emmc_groups[] = {
-	"emmc_45", "emmc_51", };
-static const char *mt7986_ethernet_groups[] = {
-	"switch_int", "mdc_mdio", };
-static const char *mt7986_i2c_groups[] = { "i2c", };
-static const char *mt7986_led_groups[] = { "wifi_led", };
-static const char *mt7986_flash_groups[] = { "snfi", };
-static const char *mt7986_pcie_groups[] = {
-	"pcie_clk", "pcie_wake", "pcie_pereset" };
-static const char *mt7986_pwm_groups[] = { "pwm0", "pwm1_0", "pwm1_1", };
-static const char *mt7986_spi_groups[] = {
-	"spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", };
-static const char *mt7986_uart_groups[] = {
-	"uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts",
-	"uart1_2_rx_tx", "uart1_2_cts_rts",
-	"uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts",
-	"uart2_0", "uart2_1", "uart0", "uart1", "uart2",
-};
-static const char *mt7986_wdt_groups[] = { "watchdog", };
-static const char *mt7986_wf_groups[] = { "wf_2g", "wf_5g", "wf_dbdc", };
-
-static const struct function_desc mt7986_functions[] = {
-	{"audio", mt7986_audio_groups, ARRAY_SIZE(mt7986_audio_groups)},
-	{"emmc", mt7986_emmc_groups, ARRAY_SIZE(mt7986_emmc_groups)},
-	{"eth", mt7986_ethernet_groups, ARRAY_SIZE(mt7986_ethernet_groups)},
-	{"i2c", mt7986_i2c_groups, ARRAY_SIZE(mt7986_i2c_groups)},
-	{"led", mt7986_led_groups, ARRAY_SIZE(mt7986_led_groups)},
-	{"flash", mt7986_flash_groups, ARRAY_SIZE(mt7986_flash_groups)},
-	{"pcie", mt7986_pcie_groups, ARRAY_SIZE(mt7986_pcie_groups)},
-	{"pwm", mt7986_pwm_groups, ARRAY_SIZE(mt7986_pwm_groups)},
-	{"spi", mt7986_spi_groups, ARRAY_SIZE(mt7986_spi_groups)},
-	{"uart", mt7986_uart_groups, ARRAY_SIZE(mt7986_uart_groups)},
-	{"watchdog", mt7986_wdt_groups, ARRAY_SIZE(mt7986_wdt_groups)},
-	{"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)},
-};
-
-static const struct mtk_eint_hw mt7986a_eint_hw = {
-	.port_mask = 7,
-	.ports = 7,
-	.ap_num = ARRAY_SIZE(mt7986a_pins),
-	.db_cnt = 16,
-	.db_time = debounce_time_mt6765,
-};
-
-static const struct mtk_eint_hw mt7986b_eint_hw = {
-	.port_mask = 7,
-	.ports = 7,
-	.ap_num = ARRAY_SIZE(mt7986b_pins),
-	.db_cnt = 16,
-	.db_time = debounce_time_mt6765,
-};
-
-static struct mtk_pin_soc mt7986a_data = {
-	.reg_cal = mt7986_reg_cals,
-	.pins = mt7986a_pins,
-	.npins = ARRAY_SIZE(mt7986a_pins),
-	.grps = mt7986_groups,
-	.ngrps = ARRAY_SIZE(mt7986_groups),
-	.funcs = mt7986_functions,
-	.nfuncs = ARRAY_SIZE(mt7986_functions),
-	.eint_hw = &mt7986a_eint_hw,
-	.gpio_m = 0,
-	.ies_present = false,
-	.base_names = mt7986_pinctrl_register_base_names,
-	.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
-	.pull_type = mt7986_pull_type,
-	.bias_set_combo = mtk_pinconf_bias_set_combo,
-	.bias_get_combo = mtk_pinconf_bias_get_combo,
-	.drive_set = mtk_pinconf_drive_set_rev1,
-	.drive_get = mtk_pinconf_drive_get_rev1,
-	.adv_pull_get = mtk_pinconf_adv_pull_get,
-	.adv_pull_set = mtk_pinconf_adv_pull_set,
-};
-
-static struct mtk_pin_soc mt7986b_data = {
-	.reg_cal = mt7986_reg_cals,
-	.pins = mt7986b_pins,
-	.npins = ARRAY_SIZE(mt7986b_pins),
-	.grps = mt7986_groups,
-	.ngrps = ARRAY_SIZE(mt7986_groups),
-	.funcs = mt7986_functions,
-	.nfuncs = ARRAY_SIZE(mt7986_functions),
-	.eint_hw = &mt7986b_eint_hw,
-	.gpio_m = 0,
-	.ies_present = false,
-	.base_names = mt7986_pinctrl_register_base_names,
-	.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
-	.pull_type = mt7986_pull_type,
-	.bias_set_combo = mtk_pinconf_bias_set_combo,
-	.bias_get_combo = mtk_pinconf_bias_get_combo,
-	.drive_set = mtk_pinconf_drive_set_rev1,
-	.drive_get = mtk_pinconf_drive_get_rev1,
-	.adv_pull_get = mtk_pinconf_adv_pull_get,
-	.adv_pull_set = mtk_pinconf_adv_pull_set,
-};
-
-static const struct of_device_id mt7986a_pinctrl_of_match[] = {
-	{.compatible = "mediatek,mt7986a-pinctrl",},
-	{}
-};
-
-static const struct of_device_id mt7986b_pinctrl_of_match[] = {
-	{.compatible = "mediatek,mt7986b-pinctrl",},
-	{}
-};
-
-static int mt7986a_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_moore_pinctrl_probe(pdev, &mt7986a_data);
-}
-
-static int mt7986b_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_moore_pinctrl_probe(pdev, &mt7986b_data);
-}
-
-static struct platform_driver mt7986a_pinctrl_driver = {
-	.driver = {
-		.name = "mt7986a-pinctrl",
-		.of_match_table = mt7986a_pinctrl_of_match,
-	},
-	.probe = mt7986a_pinctrl_probe,
-};
-
-static struct platform_driver mt7986b_pinctrl_driver = {
-	.driver = {
-		.name = "mt7986b-pinctrl",
-		.of_match_table = mt7986b_pinctrl_of_match,
-	},
-	.probe = mt7986b_pinctrl_probe,
-};
-
-static int __init mt7986a_pinctrl_init(void)
-{
-	return platform_driver_register(&mt7986a_pinctrl_driver);
-}
-
-static int __init mt7986b_pinctrl_init(void)
-{
-	return platform_driver_register(&mt7986b_pinctrl_driver);
-}
-
-arch_initcall(mt7986a_pinctrl_init);
-arch_initcall(mt7986b_pinctrl_init);

target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c

@@ -1096,20 +1096,20 @@ static const struct group_desc mt7988_groups[] = {
 /* Joint those groups owning the same capability in user point of view which
  * allows that people tend to use through the device tree.
  */
-static const char *mt7988_jtag_groups[] = {
+static const char * const mt7988_jtag_groups[] = {
 	"tops_jtag0_0", "wo0_jtag", "wo1_jtag",
 	"wo2_jtag",	"jtag",	    "tops_jtag0_1",
 };
-static const char *mt7988_int_usxgmii_groups[] = {
+static const char * const mt7988_int_usxgmii_groups[] = {
 	"int_usxgmii",
 };
-static const char *mt7988_pwm_groups[] = {
+static const char * const mt7988_pwm_groups[] = {
 	"pwm0", "pwm1", "pwm2", "pwm3", "pwm4",	"pwm5",	"pwm6", "pwm7"
 };
-static const char *mt7988_dfd_groups[] = {
+static const char * const mt7988_dfd_groups[] = {
 	"dfd",
 };
-static const char *mt7988_i2c_groups[] = {
+static const char * const mt7988_i2c_groups[] = {
 	"xfi_phy0_i2c0",
 	"xfi_phy1_i2c0",
 	"xfi_phy_pll_i2c0",
@@ -1134,13 +1134,13 @@ static const char *mt7988_i2c_groups[] = {
 	"i2c2_0",
 	"i2c2_1",
 };
-static const char *mt7988_ethernet_groups[] = {
+static const char * const mt7988_ethernet_groups[] = {
 	"mdc_mdio0",
 	"2p5g_ext_mdio",
 	"gbe_ext_mdio",
 	"mdc_mdio1",
 };
-static const char *mt7988_pcie_groups[] = {
+static const char * const mt7988_pcie_groups[] = {
 	"pcie_wake_n0_0",    "pcie_clk_req_n0_0", "pcie_wake_n3_0",
 	"pcie_clk_req_n3",   "pcie_p0_phy_i2c",	  "pcie_p1_phy_i2c",
 	"pcie_p3_phy_i2c",   "pcie_p2_phy_i2c",	  "ckm_phy_i2c",
@@ -1150,18 +1150,18 @@ static const char *mt7988_pcie_groups[] = {
 	"pcie_wake_n2_0",    "pcie_clk_req_n2_0", "pcie_wake_n2_1",
 	"pcie_clk_req_n0_1"
 };
-static const char *mt7988_pmic_groups[] = {
+static const char * const mt7988_pmic_groups[] = {
 	"pmic",
 };
-static const char *mt7988_wdt_groups[] = {
+static const char * const mt7988_wdt_groups[] = {
 	"watchdog",
 };
-static const char *mt7988_spi_groups[] = {
+static const char * const mt7988_spi_groups[] = {
 	"spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold",
 };
-static const char *mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi",
+static const char * const mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi",
 						    "emmc_51" };
-static const char *mt7988_uart_groups[] = {
+static const char * const mt7988_uart_groups[] = {
 	"uart2",
 	"tops_uart0_0",
 	"uart2_0",
@@ -1183,18 +1183,18 @@ static const char *mt7988_uart_groups[] = {
 	"net_wo1_uart_txd_1",
 	"net_wo2_uart_txd_1",
 };
-static const char *mt7988_udi_groups[] = {
+static const char * const mt7988_udi_groups[] = {
 	"udi",
 };
-static const char *mt7988_audio_groups[] = {
+static const char * const mt7988_audio_groups[] = {
 	"i2s", "pcm",
 };
-static const char *mt7988_led_groups[] = {
+static const char * const mt7988_led_groups[] = {
 	"gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1",
 	"gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0",
 	"wf5g_led0",   "wf5g_led1",
 };
-static const char *mt7988_usb_groups[] = {
+static const char * const mt7988_usb_groups[] = {
 	"drv_vbus",
 	"drv_vbus_p1",
 };
@@ -1226,7 +1226,7 @@ static const struct mtk_eint_hw mt7988_eint_hw = {
 	.db_cnt = 16,
 };
 
-static const char *mt7988_pinctrl_register_base_names[] = {
+static const char * const mt7988_pinctrl_register_base_names[] = {
 	"gpio_base",	 "iocfg_tr_base", "iocfg_br_base",
 	"iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
 };
@@ -1279,3 +1279,4 @@ static int __init mt7988_pinctrl_init(void)
 	return platform_driver_register(&mt7988_pinctrl_driver);
 }
 arch_initcall(mt7988_pinctrl_init);
+

target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7981-clk.h

@@ -1,215 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Wenzhen.Yu <[email protected]>
- * Author: Jianhui Zhao <[email protected]>
- * Author: Daniel Golle <[email protected]>
- */
-
-#ifndef _DT_BINDINGS_CLK_MT7981_H
-#define _DT_BINDINGS_CLK_MT7981_H
-
-/* TOPCKGEN */
-#define CLK_TOP_CB_CKSQ_40M		0
-#define CLK_TOP_CB_M_416M		1
-#define CLK_TOP_CB_M_D2			2
-#define CLK_TOP_CB_M_D3			3
-#define CLK_TOP_M_D3_D2			4
-#define CLK_TOP_CB_M_D4			5
-#define CLK_TOP_CB_M_D8			6
-#define CLK_TOP_M_D8_D2			7
-#define CLK_TOP_CB_MM_720M		8
-#define CLK_TOP_CB_MM_D2		9
-#define CLK_TOP_CB_MM_D3		10
-#define CLK_TOP_CB_MM_D3_D5		11
-#define CLK_TOP_CB_MM_D4		12
-#define CLK_TOP_CB_MM_D6		13
-#define CLK_TOP_MM_D6_D2		14
-#define CLK_TOP_CB_MM_D8		15
-#define CLK_TOP_CB_APLL2_196M		16
-#define CLK_TOP_APLL2_D2		17
-#define CLK_TOP_APLL2_D4		18
-#define CLK_TOP_NET1_2500M		19
-#define CLK_TOP_CB_NET1_D4		20
-#define CLK_TOP_CB_NET1_D5		21
-#define CLK_TOP_NET1_D5_D2		22
-#define CLK_TOP_NET1_D5_D4		23
-#define CLK_TOP_CB_NET1_D8		24
-#define CLK_TOP_NET1_D8_D2		25
-#define CLK_TOP_NET1_D8_D4		26
-#define CLK_TOP_CB_NET2_800M		27
-#define CLK_TOP_CB_NET2_D2		28
-#define CLK_TOP_CB_NET2_D4		29
-#define CLK_TOP_NET2_D4_D2		30
-#define CLK_TOP_NET2_D4_D4		31
-#define CLK_TOP_CB_NET2_D6		32
-#define CLK_TOP_CB_WEDMCU_208M		33
-#define CLK_TOP_CB_SGM_325M		34
-#define CLK_TOP_CKSQ_40M_D2		35
-#define CLK_TOP_CB_RTC_32K		36
-#define CLK_TOP_CB_RTC_32P7K		37
-#define CLK_TOP_USB_TX250M		38
-#define CLK_TOP_FAUD			39
-#define CLK_TOP_NFI1X			40
-#define CLK_TOP_USB_EQ_RX250M		41
-#define CLK_TOP_USB_CDR_CK		42
-#define CLK_TOP_USB_LN0_CK		43
-#define CLK_TOP_SPINFI_BCK		44
-#define CLK_TOP_SPI			45
-#define CLK_TOP_SPIM_MST		46
-#define CLK_TOP_UART_BCK		47
-#define CLK_TOP_PWM_BCK			48
-#define CLK_TOP_I2C_BCK			49
-#define CLK_TOP_PEXTP_TL		50
-#define CLK_TOP_EMMC_208M		51
-#define CLK_TOP_EMMC_400M		52
-#define CLK_TOP_DRAMC_REF		53
-#define CLK_TOP_DRAMC_MD32		54
-#define CLK_TOP_SYSAXI			55
-#define CLK_TOP_SYSAPB			56
-#define CLK_TOP_ARM_DB_MAIN		57
-#define CLK_TOP_AP2CNN_HOST		58
-#define CLK_TOP_NETSYS			59
-#define CLK_TOP_NETSYS_500M		60
-#define CLK_TOP_NETSYS_WED_MCU		61
-#define CLK_TOP_NETSYS_2X		62
-#define CLK_TOP_SGM_325M		63
-#define CLK_TOP_SGM_REG			64
-#define CLK_TOP_F26M			65
-#define CLK_TOP_EIP97B			66
-#define CLK_TOP_USB3_PHY		67
-#define CLK_TOP_AUD			68
-#define CLK_TOP_A1SYS			69
-#define CLK_TOP_AUD_L			70
-#define CLK_TOP_A_TUNER			71
-#define CLK_TOP_U2U3_REF		72
-#define CLK_TOP_U2U3_SYS		73
-#define CLK_TOP_U2U3_XHCI		74
-#define CLK_TOP_USB_FRMCNT		75
-#define CLK_TOP_NFI1X_SEL		76
-#define CLK_TOP_SPINFI_SEL		77
-#define CLK_TOP_SPI_SEL			78
-#define CLK_TOP_SPIM_MST_SEL		79
-#define CLK_TOP_UART_SEL		80
-#define CLK_TOP_PWM_SEL			81
-#define CLK_TOP_I2C_SEL			82
-#define CLK_TOP_PEXTP_TL_SEL		83
-#define CLK_TOP_EMMC_208M_SEL		84
-#define CLK_TOP_EMMC_400M_SEL		85
-#define CLK_TOP_F26M_SEL		86
-#define CLK_TOP_DRAMC_SEL		87
-#define CLK_TOP_DRAMC_MD32_SEL		88
-#define CLK_TOP_SYSAXI_SEL		89
-#define CLK_TOP_SYSAPB_SEL		90
-#define CLK_TOP_ARM_DB_MAIN_SEL		91
-#define CLK_TOP_AP2CNN_HOST_SEL		92
-#define CLK_TOP_NETSYS_SEL		93
-#define CLK_TOP_NETSYS_500M_SEL		94
-#define CLK_TOP_NETSYS_MCU_SEL		95
-#define CLK_TOP_NETSYS_2X_SEL		96
-#define CLK_TOP_SGM_325M_SEL		97
-#define CLK_TOP_SGM_REG_SEL		98
-#define CLK_TOP_EIP97B_SEL		99
-#define CLK_TOP_USB3_PHY_SEL		100
-#define CLK_TOP_AUD_SEL			101
-#define CLK_TOP_A1SYS_SEL		102
-#define CLK_TOP_AUD_L_SEL		103
-#define CLK_TOP_A_TUNER_SEL		104
-#define CLK_TOP_U2U3_SEL		105
-#define CLK_TOP_U2U3_SYS_SEL		106
-#define CLK_TOP_U2U3_XHCI_SEL		107
-#define CLK_TOP_USB_FRMCNT_SEL		108
-#define CLK_TOP_AUD_I2S_M		109
-
-/* INFRACFG */
-#define CLK_INFRA_66M_MCK		0
-#define CLK_INFRA_UART0_SEL		1
-#define CLK_INFRA_UART1_SEL		2
-#define CLK_INFRA_UART2_SEL		3
-#define CLK_INFRA_SPI0_SEL		4
-#define CLK_INFRA_SPI1_SEL		5
-#define CLK_INFRA_SPI2_SEL		6
-#define CLK_INFRA_PWM1_SEL		7
-#define CLK_INFRA_PWM2_SEL		8
-#define CLK_INFRA_PWM3_SEL		9
-#define CLK_INFRA_PWM_BSEL		10
-#define CLK_INFRA_PCIE_SEL		11
-#define CLK_INFRA_GPT_STA		12
-#define CLK_INFRA_PWM_HCK		13
-#define CLK_INFRA_PWM_STA		14
-#define CLK_INFRA_PWM1_CK		15
-#define CLK_INFRA_PWM2_CK		16
-#define CLK_INFRA_PWM3_CK		17
-#define CLK_INFRA_CQ_DMA_CK		18
-#define CLK_INFRA_AUD_BUS_CK		19
-#define CLK_INFRA_AUD_26M_CK		20
-#define CLK_INFRA_AUD_L_CK		21
-#define CLK_INFRA_AUD_AUD_CK		22
-#define CLK_INFRA_AUD_EG2_CK		23
-#define CLK_INFRA_DRAMC_26M_CK		24
-#define CLK_INFRA_DBG_CK		25
-#define CLK_INFRA_AP_DMA_CK		26
-#define CLK_INFRA_SEJ_CK		27
-#define CLK_INFRA_SEJ_13M_CK		28
-#define CLK_INFRA_THERM_CK		29
-#define CLK_INFRA_I2C0_CK		30
-#define CLK_INFRA_UART0_CK		31
-#define CLK_INFRA_UART1_CK		32
-#define CLK_INFRA_UART2_CK		33
-#define CLK_INFRA_SPI2_CK		34
-#define CLK_INFRA_SPI2_HCK_CK		35
-#define CLK_INFRA_NFI1_CK		36
-#define CLK_INFRA_SPINFI1_CK		37
-#define CLK_INFRA_NFI_HCK_CK		38
-#define CLK_INFRA_SPI0_CK		39
-#define CLK_INFRA_SPI1_CK		40
-#define CLK_INFRA_SPI0_HCK_CK		41
-#define CLK_INFRA_SPI1_HCK_CK		42
-#define CLK_INFRA_FRTC_CK		43
-#define CLK_INFRA_MSDC_CK		44
-#define CLK_INFRA_MSDC_HCK_CK		45
-#define CLK_INFRA_MSDC_133M_CK		46
-#define CLK_INFRA_MSDC_66M_CK		47
-#define CLK_INFRA_ADC_26M_CK		48
-#define CLK_INFRA_ADC_FRC_CK		49
-#define CLK_INFRA_FBIST2FPC_CK		50
-#define CLK_INFRA_I2C_MCK_CK		51
-#define CLK_INFRA_I2C_PCK_CK		52
-#define CLK_INFRA_IUSB_133_CK		53
-#define CLK_INFRA_IUSB_66M_CK		54
-#define CLK_INFRA_IUSB_SYS_CK		55
-#define CLK_INFRA_IUSB_CK		56
-#define CLK_INFRA_IPCIE_CK		57
-#define CLK_INFRA_IPCIE_PIPE_CK		58
-#define CLK_INFRA_IPCIER_CK		59
-#define CLK_INFRA_IPCIEB_CK		60
-
-/* APMIXEDSYS */
-#define CLK_APMIXED_ARMPLL		0
-#define CLK_APMIXED_NET2PLL		1
-#define CLK_APMIXED_MMPLL		2
-#define CLK_APMIXED_SGMPLL		3
-#define CLK_APMIXED_WEDMCUPLL		4
-#define CLK_APMIXED_NET1PLL		5
-#define CLK_APMIXED_MPLL		6
-#define CLK_APMIXED_APLL2		7
-
-/* SGMIISYS_0 */
-#define CLK_SGM0_TX_EN			0
-#define CLK_SGM0_RX_EN			1
-#define CLK_SGM0_CK0_EN			2
-#define CLK_SGM0_CDR_CK0_EN		3
-
-/* SGMIISYS_1 */
-#define CLK_SGM1_TX_EN			0
-#define CLK_SGM1_RX_EN			1
-#define CLK_SGM1_CK1_EN			2
-#define CLK_SGM1_CDR_CK1_EN		3
-
-/* ETHSYS */
-#define CLK_ETH_FE_EN			0
-#define CLK_ETH_GP2_EN			1
-#define CLK_ETH_GP1_EN			2
-#define CLK_ETH_WOCPU0_EN		3
-
-#endif /* _DT_BINDINGS_CLK_MT7981_H */

target/linux/mediatek/files-6.1/include/dt-bindings/clock/mt7986-clk.h

@@ -1,169 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- */
-
-#ifndef _DT_BINDINGS_CLK_MT7986_H
-#define _DT_BINDINGS_CLK_MT7986_H
-
-/* APMIXEDSYS */
-
-#define CLK_APMIXED_ARMPLL		0
-#define CLK_APMIXED_NET2PLL		1
-#define CLK_APMIXED_MMPLL		2
-#define CLK_APMIXED_SGMPLL		3
-#define CLK_APMIXED_WEDMCUPLL		4
-#define CLK_APMIXED_NET1PLL		5
-#define CLK_APMIXED_MPLL		6
-#define CLK_APMIXED_APLL2		7
-
-/* TOPCKGEN */
-
-#define CLK_TOP_XTAL			0
-#define CLK_TOP_XTAL_D2			1
-#define CLK_TOP_RTC_32K			2
-#define CLK_TOP_RTC_32P7K		3
-#define CLK_TOP_MPLL_D2			4
-#define CLK_TOP_MPLL_D4			5
-#define CLK_TOP_MPLL_D8			6
-#define CLK_TOP_MPLL_D8_D2		7
-#define CLK_TOP_MPLL_D3_D2		8
-#define CLK_TOP_MMPLL_D2		9
-#define CLK_TOP_MMPLL_D4		10
-#define CLK_TOP_MMPLL_D8		11
-#define CLK_TOP_MMPLL_D8_D2		12
-#define CLK_TOP_MMPLL_D3_D8		13
-#define CLK_TOP_MMPLL_U2PHY		14
-#define CLK_TOP_APLL2_D4		15
-#define CLK_TOP_NET1PLL_D4		16
-#define CLK_TOP_NET1PLL_D5		17
-#define CLK_TOP_NET1PLL_D5_D2		18
-#define CLK_TOP_NET1PLL_D5_D4		19
-#define CLK_TOP_NET1PLL_D8_D2		20
-#define CLK_TOP_NET1PLL_D8_D4		21
-#define CLK_TOP_NET2PLL_D4		22
-#define CLK_TOP_NET2PLL_D4_D2		23
-#define CLK_TOP_NET2PLL_D3_D2		24
-#define CLK_TOP_WEDMCUPLL_D5_D2		25
-#define CLK_TOP_NFI1X_SEL		26
-#define CLK_TOP_SPINFI_SEL		27
-#define CLK_TOP_SPI_SEL			28
-#define CLK_TOP_SPIM_MST_SEL		29
-#define CLK_TOP_UART_SEL		30
-#define CLK_TOP_PWM_SEL			31
-#define CLK_TOP_I2C_SEL			32
-#define CLK_TOP_PEXTP_TL_SEL		33
-#define CLK_TOP_EMMC_250M_SEL		34
-#define CLK_TOP_EMMC_416M_SEL		35
-#define CLK_TOP_F_26M_ADC_SEL		36
-#define CLK_TOP_DRAMC_SEL		37
-#define CLK_TOP_DRAMC_MD32_SEL		38
-#define CLK_TOP_SYSAXI_SEL		39
-#define CLK_TOP_SYSAPB_SEL		40
-#define CLK_TOP_ARM_DB_MAIN_SEL		41
-#define CLK_TOP_ARM_DB_JTSEL		42
-#define CLK_TOP_NETSYS_SEL		43
-#define CLK_TOP_NETSYS_500M_SEL		44
-#define CLK_TOP_NETSYS_MCU_SEL		45
-#define CLK_TOP_NETSYS_2X_SEL		46
-#define CLK_TOP_SGM_325M_SEL		47
-#define CLK_TOP_SGM_REG_SEL		48
-#define CLK_TOP_A1SYS_SEL		49
-#define CLK_TOP_CONN_MCUSYS_SEL		50
-#define CLK_TOP_EIP_B_SEL		51
-#define CLK_TOP_PCIE_PHY_SEL		52
-#define CLK_TOP_USB3_PHY_SEL		53
-#define CLK_TOP_F26M_SEL		54
-#define CLK_TOP_AUD_L_SEL		55
-#define CLK_TOP_A_TUNER_SEL		56
-#define CLK_TOP_U2U3_SEL		57
-#define CLK_TOP_U2U3_SYS_SEL		58
-#define CLK_TOP_U2U3_XHCI_SEL		59
-#define CLK_TOP_DA_U2_REFSEL		60
-#define CLK_TOP_DA_U2_CK_1P_SEL		61
-#define CLK_TOP_AP2CNN_HOST_SEL		62
-#define CLK_TOP_JTAG			63
-
-/* INFRACFG */
-
-#define CLK_INFRA_SYSAXI_D2		0
-#define CLK_INFRA_UART0_SEL		1
-#define CLK_INFRA_UART1_SEL		2
-#define CLK_INFRA_UART2_SEL		3
-#define CLK_INFRA_SPI0_SEL		4
-#define CLK_INFRA_SPI1_SEL		5
-#define CLK_INFRA_PWM1_SEL		6
-#define CLK_INFRA_PWM2_SEL		7
-#define CLK_INFRA_PWM_BSEL		8
-#define CLK_INFRA_PCIE_SEL		9
-#define CLK_INFRA_GPT_STA		10
-#define CLK_INFRA_PWM_HCK		11
-#define CLK_INFRA_PWM_STA		12
-#define CLK_INFRA_PWM1_CK		13
-#define CLK_INFRA_PWM2_CK		14
-#define CLK_INFRA_CQ_DMA_CK		15
-#define CLK_INFRA_EIP97_CK		16
-#define CLK_INFRA_AUD_BUS_CK		17
-#define CLK_INFRA_AUD_26M_CK		18
-#define CLK_INFRA_AUD_L_CK		19
-#define CLK_INFRA_AUD_AUD_CK		20
-#define CLK_INFRA_AUD_EG2_CK		21
-#define CLK_INFRA_DRAMC_26M_CK		22
-#define CLK_INFRA_DBG_CK		23
-#define CLK_INFRA_AP_DMA_CK		24
-#define CLK_INFRA_SEJ_CK		25
-#define CLK_INFRA_SEJ_13M_CK		26
-#define CLK_INFRA_THERM_CK		27
-#define CLK_INFRA_I2C0_CK		28
-#define CLK_INFRA_UART0_CK		29
-#define CLK_INFRA_UART1_CK		30
-#define CLK_INFRA_UART2_CK		31
-#define CLK_INFRA_NFI1_CK		32
-#define CLK_INFRA_SPINFI1_CK		33
-#define CLK_INFRA_NFI_HCK_CK		34
-#define CLK_INFRA_SPI0_CK		35
-#define CLK_INFRA_SPI1_CK		36
-#define CLK_INFRA_SPI0_HCK_CK		37
-#define CLK_INFRA_SPI1_HCK_CK		38
-#define CLK_INFRA_FRTC_CK		39
-#define CLK_INFRA_MSDC_CK		40
-#define CLK_INFRA_MSDC_HCK_CK		41
-#define CLK_INFRA_MSDC_133M_CK		42
-#define CLK_INFRA_MSDC_66M_CK		43
-#define CLK_INFRA_ADC_26M_CK		44
-#define CLK_INFRA_ADC_FRC_CK		45
-#define CLK_INFRA_FBIST2FPC_CK		46
-#define CLK_INFRA_IUSB_133_CK		47
-#define CLK_INFRA_IUSB_66M_CK		48
-#define CLK_INFRA_IUSB_SYS_CK		49
-#define CLK_INFRA_IUSB_CK		50
-#define CLK_INFRA_IPCIE_CK		51
-#define CLK_INFRA_IPCIE_PIPE_CK		52
-#define CLK_INFRA_IPCIER_CK		53
-#define CLK_INFRA_IPCIEB_CK		54
-#define CLK_INFRA_TRNG_CK		55
-
-/* SGMIISYS_0 */
-
-#define CLK_SGMII0_TX250M_EN		0
-#define CLK_SGMII0_RX250M_EN		1
-#define CLK_SGMII0_CDR_REF		2
-#define CLK_SGMII0_CDR_FB		3
-
-/* SGMIISYS_1 */
-
-#define CLK_SGMII1_TX250M_EN		0
-#define CLK_SGMII1_RX250M_EN		1
-#define CLK_SGMII1_CDR_REF		2
-#define CLK_SGMII1_CDR_FB		3
-
-/* ETHSYS */
-
-#define CLK_ETH_FE_EN			0
-#define CLK_ETH_GP2_EN			1
-#define CLK_ETH_GP1_EN			2
-#define CLK_ETH_WOCPU1_EN		3
-#define CLK_ETH_WOCPU0_EN		4
-
-#endif /* _DT_BINDINGS_CLK_MT7986_H */

target/linux/mediatek/files-6.1/include/dt-bindings/reset/mt7986-resets.h

@@ -1,55 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
-/*
- * Copyright (c) 2022 MediaTek Inc.
- * Author: Sam Shih <[email protected]>
- */
-
-#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7986
-#define _DT_BINDINGS_RESET_CONTROLLER_MT7986
-
-/* INFRACFG resets */
-#define MT7986_INFRACFG_PEXTP_MAC_SW_RST	6
-#define MT7986_INFRACFG_SSUSB_SW_RST		7
-#define MT7986_INFRACFG_EIP97_SW_RST		8
-#define MT7986_INFRACFG_AUDIO_SW_RST		13
-#define MT7986_INFRACFG_CQ_DMA_SW_RST		14
-
-#define MT7986_INFRACFG_TRNG_SW_RST		17
-#define MT7986_INFRACFG_AP_DMA_SW_RST		32
-#define MT7986_INFRACFG_I2C_SW_RST		33
-#define MT7986_INFRACFG_NFI_SW_RST		34
-#define MT7986_INFRACFG_SPI0_SW_RST		35
-#define MT7986_INFRACFG_SPI1_SW_RST		36
-#define MT7986_INFRACFG_UART0_SW_RST		37
-#define MT7986_INFRACFG_UART1_SW_RST		38
-#define MT7986_INFRACFG_UART2_SW_RST		39
-#define MT7986_INFRACFG_AUXADC_SW_RST		43
-
-#define MT7986_INFRACFG_APXGPT_SW_RST		66
-#define MT7986_INFRACFG_PWM_SW_RST		68
-
-#define MT7986_INFRACFG_SW_RST_NUM		69
-
-/* TOPRGU resets */
-#define MT7986_TOPRGU_APMIXEDSYS_SW_RST		0
-#define MT7986_TOPRGU_SGMII0_SW_RST		1
-#define MT7986_TOPRGU_SGMII1_SW_RST		2
-#define MT7986_TOPRGU_INFRA_SW_RST		3
-#define MT7986_TOPRGU_U2PHY_SW_RST		5
-#define MT7986_TOPRGU_PCIE_SW_RST		6
-#define MT7986_TOPRGU_SSUSB_SW_RST		7
-#define MT7986_TOPRGU_ETHDMA_SW_RST		20
-#define MT7986_TOPRGU_CONSYS_SW_RST		23
-
-#define MT7986_TOPRGU_SW_RST_NUM		24
-
-/* ETHSYS Subsystem resets */
-#define MT7986_ETHSYS_FE_SW_RST			6
-#define MT7986_ETHSYS_PMTR_SW_RST		8
-#define MT7986_ETHSYS_GMAC_SW_RST		23
-#define MT7986_ETHSYS_PPE0_SW_RST		30
-#define MT7986_ETHSYS_PPE1_SW_RST		31
-
-#define MT7986_ETHSYS_SW_RST_NUM		32
-
-#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */

target/linux/mediatek/patches-6.1/000-v6.2-kbuild-Allow-DTB-overlays-to-built-from-.dtso-named-.patch

@@ -0,0 +1,44 @@
+From 363547d2191cbc32ca954ba75d72908712398ff2 Mon Sep 17 00:00:00 2001
+From: Andrew Davis <[email protected]>
+Date: Mon, 24 Oct 2022 12:34:28 -0500
+Subject: [PATCH] kbuild: Allow DTB overlays to built from .dtso named source
+ files
+
+Currently DTB Overlays (.dtbo) are build from source files with the same
+extension (.dts) as the base DTs (.dtb). This may become confusing and
+even lead to wrong results. For example, a composite DTB (created from a
+base DTB and a set of overlays) might have the same name as one of the
+overlays that create it.
+
+Different files should be generated from differently named sources.
+ .dtb  <-> .dts
+ .dtbo <-> .dtso
+
+We do not remove the ability to compile DTBO files from .dts files here,
+only add a new rule allowing the .dtso file name. The current .dts named
+overlays can be renamed with time. After all have been renamed we can
+remove the other rule.
+
+Signed-off-by: Andrew Davis <[email protected]>
+Reviewed-by: Geert Uytterhoeven <[email protected]>
+Tested-by: Geert Uytterhoeven <[email protected]>
+Reviewed-by: Frank Rowand <[email protected]>
+Tested-by: Frank Rowand <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Rob Herring <[email protected]>
+---
+ scripts/Makefile.lib | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/scripts/Makefile.lib
++++ b/scripts/Makefile.lib
+@@ -408,6 +408,9 @@ $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_T
+ $(obj)/%.dtbo: $(src)/%.dts $(DTC) FORCE
+ 	$(call if_changed_dep,dtc)
+ 
++$(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE
++	$(call if_changed_dep,dtc)
++
+ dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
+ 
+ # Bzip2

target/linux/mediatek/patches-6.1/001-v6.2-arm64-dts-mediatek-mt7986-add-support-for-RX-Wireles.patch

@@ -0,0 +1,106 @@
+From 2c4daed9580164522859fa100128be408cc69be2 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <[email protected]>
+Date: Sat, 5 Nov 2022 23:36:16 +0100
+Subject: [PATCH 01/19] arm64: dts: mediatek: mt7986: add support for RX
+ Wireless Ethernet Dispatch
+
+Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet
+Dispatch to offload traffic received by the wlan interface to lan/wan
+one.
+
+Co-developed-by: Sujuan Chen <[email protected]>
+Signed-off-by: Sujuan Chen <[email protected]>
+Signed-off-by: Lorenzo Bianconi <[email protected]>
+Signed-off-by: David S. Miller <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 65 +++++++++++++++++++++++
+ 1 file changed, 65 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -76,6 +76,47 @@
+ 			no-map;
+ 			reg = <0 0x4fc00000 0 0x00100000>;
+ 		};
++
++		wo_emi0: wo-emi@4fd00000 {
++			reg = <0 0x4fd00000 0 0x40000>;
++			no-map;
++		};
++
++		wo_emi1: wo-emi@4fd40000 {
++			reg = <0 0x4fd40000 0 0x40000>;
++			no-map;
++		};
++
++		wo_ilm0: wo-ilm@151e0000 {
++			reg = <0 0x151e0000 0 0x8000>;
++			no-map;
++		};
++
++		wo_ilm1: wo-ilm@151f0000 {
++			reg = <0 0x151f0000 0 0x8000>;
++			no-map;
++		};
++
++		wo_data: wo-data@4fd80000 {
++			reg = <0 0x4fd80000 0 0x240000>;
++			no-map;
++		};
++
++		wo_dlm0: wo-dlm@151e8000 {
++			reg = <0 0x151e8000 0 0x2000>;
++			no-map;
++		};
++
++		wo_dlm1: wo-dlm@151f8000 {
++			reg = <0 0x151f8000 0 0x2000>;
++			no-map;
++		};
++
++		wo_boot: wo-boot@15194000 {
++			reg = <0 0x15194000 0 0x1000>;
++			no-map;
++		};
++
+ 	};
+ 
+ 	timer {
+@@ -239,6 +280,11 @@
+ 			reg = <0 0x15010000 0 0x1000>;
+ 			interrupt-parent = <&gic>;
+ 			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
++			memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
++					<&wo_data>, <&wo_boot>;
++			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
++					      "wo-data", "wo-boot";
++			mediatek,wo-ccif = <&wo_ccif0>;
+ 		};
+ 
+ 		wed1: wed@15011000 {
+@@ -247,6 +293,25 @@
+ 			reg = <0 0x15011000 0 0x1000>;
+ 			interrupt-parent = <&gic>;
+ 			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
++			memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
++					<&wo_data>, <&wo_boot>;
++			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
++					      "wo-data", "wo-boot";
++			mediatek,wo-ccif = <&wo_ccif1>;
++		};
++
++		wo_ccif0: syscon@151a5000 {
++			compatible = "mediatek,mt7986-wo-ccif", "syscon";
++			reg = <0 0x151a5000 0 0x1000>;
++			interrupt-parent = <&gic>;
++			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
++		};
++
++		wo_ccif1: syscon@151ad000 {
++			compatible = "mediatek,mt7986-wo-ccif", "syscon";
++			reg = <0 0x151ad000 0 0x1000>;
++			interrupt-parent = <&gic>;
++			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+ 		};
+ 
+ 		eth: ethernet@15100000 {

target/linux/mediatek/patches-6.1/002-v6.2-arm64-dts-mt7986-harmonize-device-node-order.patch

@@ -0,0 +1,166 @@
+From 438e53828c08cf0e8a65b61cf6ce1e4b6620551a Mon Sep 17 00:00:00 2001
+From: Sam Shih <[email protected]>
+Date: Sun, 6 Nov 2022 09:50:24 +0100
+Subject: [PATCH 02/19] arm64: dts: mt7986: harmonize device node order
+
+This arrange device tree nodes in alphabetical order.
+
+Signed-off-by: Sam Shih <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 94 ++++++++++----------
+ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 22 ++---
+ 2 files changed, 58 insertions(+), 58 deletions(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -54,6 +54,53 @@
+ 	};
+ };
+ 
++&pio {
++	uart1_pins: uart1-pins {
++		mux {
++			function = "uart";
++			groups = "uart1";
++		};
++	};
++
++	uart2_pins: uart2-pins {
++		mux {
++			function = "uart";
++			groups = "uart2";
++		};
++	};
++
++	wf_2g_5g_pins: wf-2g-5g-pins {
++		mux {
++			function = "wifi";
++			groups = "wf_2g", "wf_5g";
++		};
++		conf {
++			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
++			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
++			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
++			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
++			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
++			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
++			       "WF1_TOP_CLK", "WF1_TOP_DATA";
++			drive-strength = <4>;
++		};
++	};
++
++	wf_dbdc_pins: wf-dbdc-pins {
++		mux {
++			function = "wifi";
++			groups = "wf_dbdc";
++		};
++		conf {
++			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
++			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
++			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
++			       "WF0_TOP_CLK", "WF0_TOP_DATA";
++			drive-strength = <4>;
++		};
++	};
++};
++
+ &switch {
+ 	ports {
+ 		#address-cells = <1>;
+@@ -121,50 +168,3 @@
+ 	pinctrl-0 = <&wf_2g_5g_pins>;
+ 	pinctrl-1 = <&wf_dbdc_pins>;
+ };
+-
+-&pio {
+-	uart1_pins: uart1-pins {
+-		mux {
+-			function = "uart";
+-			groups = "uart1";
+-		};
+-	};
+-
+-	uart2_pins: uart2-pins {
+-		mux {
+-			function = "uart";
+-			groups = "uart2";
+-		};
+-	};
+-
+-	wf_2g_5g_pins: wf-2g-5g-pins {
+-		mux {
+-			function = "wifi";
+-			groups = "wf_2g", "wf_5g";
+-		};
+-		conf {
+-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
+-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
+-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
+-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
+-			drive-strength = <4>;
+-		};
+-	};
+-
+-	wf_dbdc_pins: wf-dbdc-pins {
+-		mux {
+-			function = "wifi";
+-			groups = "wf_dbdc";
+-		};
+-		conf {
+-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+-			       "WF0_TOP_CLK", "WF0_TOP_DATA";
+-			drive-strength = <4>;
+-		};
+-	};
+-};
+--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+@@ -25,10 +25,6 @@
+ 	};
+ };
+ 
+-&uart0 {
+-	status = "okay";
+-};
+-
+ &eth {
+ 	status = "okay";
+ 
+@@ -99,13 +95,6 @@
+ 	};
+ };
+ 
+-&wifi {
+-	status = "okay";
+-	pinctrl-names = "default", "dbdc";
+-	pinctrl-0 = <&wf_2g_5g_pins>;
+-	pinctrl-1 = <&wf_dbdc_pins>;
+-};
+-
+ &pio {
+ 	wf_2g_5g_pins: wf-2g-5g-pins {
+ 		mux {
+@@ -138,3 +127,14 @@
+ 		};
+ 	};
+ };
++
++&uart0 {
++	status = "okay";
++};
++
++&wifi {
++	status = "okay";
++	pinctrl-names = "default", "dbdc";
++	pinctrl-0 = <&wf_2g_5g_pins>;
++	pinctrl-1 = <&wf_dbdc_pins>;
++};

target/linux/mediatek/patches-6.1/003-v6.2-arm64-dts-mt7986-add-crypto-related-device-nodes.patch

@@ -0,0 +1,68 @@
+From ffb05357b47f06b2b4d1e14ba89169e28feb727b Mon Sep 17 00:00:00 2001
+From: Sam Shih <[email protected]>
+Date: Sun, 6 Nov 2022 09:50:27 +0100
+Subject: [PATCH 03/19] arm64: dts: mt7986: add crypto related device nodes
+
+This patch adds crypto engine support for MT7986.
+
+Signed-off-by: Vic Wu <[email protected]>
+Signed-off-by: Sam Shih <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts |  4 ++++
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi    | 15 +++++++++++++++
+ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts |  4 ++++
+ 3 files changed, 23 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -25,6 +25,10 @@
+ 	};
+ };
+ 
++&crypto {
++	status = "okay";
++};
++
+ &eth {
+ 	status = "okay";
+ 
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -223,6 +223,21 @@
+ 			status = "disabled";
+ 		};
+ 
++		crypto: crypto@10320000 {
++			compatible = "inside-secure,safexcel-eip97";
++			reg = <0 0x10320000 0 0x40000>;
++			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ring0", "ring1", "ring2", "ring3";
++			clocks = <&infracfg CLK_INFRA_EIP97_CK>;
++			clock-names = "infra_eip97_ck";
++			assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
++			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
++			status = "disabled";
++		};
++
+ 		uart0: serial@11002000 {
+ 			compatible = "mediatek,mt7986-uart",
+ 				     "mediatek,mt6577-uart";
+--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+@@ -25,6 +25,10 @@
+ 	};
+ };
+ 
++&crypto {
++	status = "okay";
++};
++
+ &eth {
+ 	status = "okay";
+ 

target/linux/mediatek/patches-6.1/004-v6.2-arm64-dts-mt7986-add-i2c-node.patch

@@ -0,0 +1,37 @@
+From b49b7dc404ded1d89cbc568d875009a5c1ed4ef6 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <[email protected]>
+Date: Sun, 6 Nov 2022 09:50:29 +0100
+Subject: [PATCH 04/19] arm64: dts: mt7986: add i2c node
+
+Add i2c Node to mt7986 devicetree.
+
+Signed-off-by: Frank Wunderlich <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -279,6 +279,20 @@
+ 			status = "disabled";
+ 		};
+ 
++		i2c0: i2c@11008000 {
++			compatible = "mediatek,mt7986-i2c";
++			reg = <0 0x11008000 0 0x90>,
++			      <0 0x10217080 0 0x80>;
++			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
++			clock-div = <5>;
++			clocks = <&infracfg CLK_INFRA_I2C0_CK>,
++				 <&infracfg CLK_INFRA_AP_DMA_CK>;
++			clock-names = "main", "dma";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
+ 		ethsys: syscon@15000000 {
+ 			 #address-cells = <1>;
+ 			 #size-cells = <1>;

target/linux/mediatek/patches-6.1/005-v6.2-arm64-dts-mediatek-mt7986-Add-SoC-compatible.patch

@@ -0,0 +1,61 @@
+From 2cd6022800d6da7822e169f3e6f7f790c1431445 Mon Sep 17 00:00:00 2001
+From: Matthias Brugger <[email protected]>
+Date: Mon, 14 Nov 2022 13:16:53 +0100
+Subject: [PATCH 05/19] arm64: dts: mediatek: mt7986: Add SoC compatible
+
+Missing SoC compatible in the board file causes dt bindings check.
+
+Signed-off-by: Matthias Brugger <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 2 +-
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi    | 1 +
+ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 2 +-
+ arch/arm64/boot/dts/mediatek/mt7986b.dtsi    | 3 +++
+ 4 files changed, 6 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -9,7 +9,7 @@
+ 
+ / {
+ 	model = "MediaTek MT7986a RFB";
+-	compatible = "mediatek,mt7986a-rfb";
++	compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
+ 
+ 	aliases {
+ 		serial0 = &uart0;
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -10,6 +10,7 @@
+ #include <dt-bindings/reset/mt7986-resets.h>
+ 
+ / {
++	compatible = "mediatek,mt7986a";
+ 	interrupt-parent = <&gic>;
+ 	#address-cells = <2>;
+ 	#size-cells = <2>;
+--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+@@ -9,7 +9,7 @@
+ 
+ / {
+ 	model = "MediaTek MT7986b RFB";
+-	compatible = "mediatek,mt7986b-rfb";
++	compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
+ 
+ 	aliases {
+ 		serial0 = &uart0;
+--- a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
+@@ -5,6 +5,9 @@
+  */
+ 
+ #include "mt7986a.dtsi"
++/ {
++	compatible = "mediatek,mt7986b";
++};
+ 
+ &pio {
+ 	compatible = "mediatek,mt7986b-pinctrl";

target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch

@@ -0,0 +1,157 @@
+From f4029538f063a845dc9aae46cce4cf386e6253a5 Mon Sep 17 00:00:00 2001
+From: Sam Shih <[email protected]>
+Date: Fri, 18 Nov 2022 20:01:21 +0100
+Subject: [PATCH 06/19] arm64: dts: mt7986: add spi related device nodes
+
+This patch adds spi support for MT7986.
+
+Signed-off-by: Sam Shih <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 35 ++++++++++++++++++++
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi    | 28 ++++++++++++++++
+ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 35 ++++++++++++++++++++
+ 3 files changed, 98 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -59,6 +59,20 @@
+ };
+ 
+ &pio {
++	spi_flash_pins: spi-flash-pins {
++		mux {
++			function = "spi";
++			groups = "spi0", "spi0_wp_hold";
++		};
++	};
++
++	spic_pins: spic-pins {
++		mux {
++			function = "spi";
++			groups = "spi1_2";
++		};
++	};
++
+ 	uart1_pins: uart1-pins {
+ 		mux {
+ 			function = "uart";
+@@ -105,6 +119,27 @@
+ 	};
+ };
+ 
++&spi0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi_flash_pins>;
++	cs-gpios = <0>, <0>;
++	status = "okay";
++	spi_nand: spi_nand@0 {
++		compatible = "spi-nand";
++		reg = <0>;
++		spi-max-frequency = <10000000>;
++		spi-tx-buswidth = <4>;
++		spi-rx-buswidth = <4>;
++	};
++};
++
++&spi1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&spic_pins>;
++	cs-gpios = <0>, <0>;
++	status = "okay";
++};
++
+ &switch {
+ 	ports {
+ 		#address-cells = <1>;
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -294,6 +294,34 @@
+ 			status = "disabled";
+ 		};
+ 
++		spi0: spi@1100a000 {
++			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0 0x1100a000 0 0x100>;
++			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&topckgen CLK_TOP_MPLL_D2>,
++				 <&topckgen CLK_TOP_SPI_SEL>,
++				 <&infracfg CLK_INFRA_SPI0_CK>,
++				 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
++			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
++			status = "disabled";
++		};
++
++		spi1: spi@1100b000 {
++			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0 0x1100b000 0 0x100>;
++			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&topckgen CLK_TOP_MPLL_D2>,
++				 <&topckgen CLK_TOP_SPIM_MST_SEL>,
++				 <&infracfg CLK_INFRA_SPI1_CK>,
++				 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
++			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
++			status = "disabled";
++		};
++
+ 		ethsys: syscon@15000000 {
+ 			 #address-cells = <1>;
+ 			 #size-cells = <1>;
+--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+@@ -100,6 +100,20 @@
+ };
+ 
+ &pio {
++	spi_flash_pins: spi-flash-pins {
++		mux {
++			function = "spi";
++			groups = "spi0", "spi0_wp_hold";
++		};
++	};
++
++	spic_pins: spic-pins {
++		mux {
++			function = "spi";
++			groups = "spi1_2";
++		};
++	};
++
+ 	wf_2g_5g_pins: wf-2g-5g-pins {
+ 		mux {
+ 			function = "wifi";
+@@ -132,6 +146,27 @@
+ 	};
+ };
+ 
++&spi0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi_flash_pins>;
++	cs-gpios = <0>, <0>;
++	status = "okay";
++	spi_nand: spi_nand@0 {
++		compatible = "spi-nand";
++		reg = <0>;
++		spi-max-frequency = <10000000>;
++		spi-tx-buswidth = <4>;
++		spi-rx-buswidth = <4>;
++	};
++};
++
++&spi1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&spic_pins>;
++	cs-gpios = <0>, <0>;
++	status = "okay";
++};
++
+ &uart0 {
+ 	status = "okay";
+ };

target/linux/mediatek/patches-6.1/007-v6.3-arm64-dts-mt7986-add-usb-related-device-nodes.patch

@@ -0,0 +1,127 @@
+From 9e8e24ab716098e617195ce29b88e84608bf2108 Mon Sep 17 00:00:00 2001
+From: Sam Shih <[email protected]>
+Date: Fri, 6 Jan 2023 16:28:42 +0100
+Subject: [PATCH 07/19] arm64: dts: mt7986: add usb related device nodes
+
+This patch adds USB support for MT7986.
+
+Signed-off-by: Sam Shih <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Reviewed-by: Chunfeng Yun <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts |  8 +++
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi    | 55 ++++++++++++++++++++
+ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts |  8 +++
+ 3 files changed, 71 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -140,6 +140,10 @@
+ 	status = "okay";
+ };
+ 
++&ssusb {
++	status = "okay";
++};
++
+ &switch {
+ 	ports {
+ 		#address-cells = <1>;
+@@ -201,6 +205,10 @@
+ 	status = "okay";
+ };
+ 
++&usb_phy {
++	status = "okay";
++};
++
+ &wifi {
+ 	status = "okay";
+ 	pinctrl-names = "default", "dbdc";
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -322,6 +322,61 @@
+ 			status = "disabled";
+ 		};
+ 
++		ssusb: usb@11200000 {
++			compatible = "mediatek,mt7986-xhci",
++				     "mediatek,mtk-xhci";
++			reg = <0 0x11200000 0 0x2e00>,
++			      <0 0x11203e00 0 0x0100>;
++			reg-names = "mac", "ippc";
++			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
++				 <&infracfg CLK_INFRA_IUSB_CK>,
++				 <&infracfg CLK_INFRA_IUSB_133_CK>,
++				 <&infracfg CLK_INFRA_IUSB_66M_CK>,
++				 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
++			clock-names = "sys_ck",
++				      "ref_ck",
++				      "mcu_ck",
++				      "dma_ck",
++				      "xhci_ck";
++			phys = <&u2port0 PHY_TYPE_USB2>,
++			       <&u3port0 PHY_TYPE_USB3>,
++			       <&u2port1 PHY_TYPE_USB2>;
++			status = "disabled";
++		};
++
++		usb_phy: t-phy@11e10000 {
++			compatible = "mediatek,mt7986-tphy",
++				     "mediatek,generic-tphy-v2";
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0 0 0x11e10000 0x1700>;
++			status = "disabled";
++
++			u2port0: usb-phy@0 {
++				reg = <0x0 0x700>;
++				clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
++					 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
++				clock-names = "ref", "da_ref";
++				#phy-cells = <1>;
++			};
++
++			u3port0: usb-phy@700 {
++				reg = <0x700 0x900>;
++				clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
++				clock-names = "ref";
++				#phy-cells = <1>;
++			};
++
++			u2port1: usb-phy@1000 {
++				reg = <0x1000 0x700>;
++				clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
++					 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
++				clock-names = "ref", "da_ref";
++				#phy-cells = <1>;
++			};
++		};
++
+ 		ethsys: syscon@15000000 {
+ 			 #address-cells = <1>;
+ 			 #size-cells = <1>;
+--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+@@ -167,10 +167,18 @@
+ 	status = "okay";
+ };
+ 
++&ssusb {
++	status = "okay";
++};
++
+ &uart0 {
+ 	status = "okay";
+ };
+ 
++&usb_phy {
++	status = "okay";
++};
++
+ &wifi {
+ 	status = "okay";
+ 	pinctrl-names = "default", "dbdc";

target/linux/mediatek/patches-6.1/008-v6.3-arm64-dts-mt7986-add-mmc-related-device-nodes.patch

@@ -0,0 +1,160 @@
+From c1744e9e75a6a8abc7c893f349bcbf725b9c0d74 Mon Sep 17 00:00:00 2001
+From: Sam Shih <[email protected]>
+Date: Fri, 6 Jan 2023 16:28:43 +0100
+Subject: [PATCH 08/19] arm64: dts: mt7986: add mmc related device nodes
+
+This patch adds mmc support for MT7986.
+
+Signed-off-by: Sam Shih <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 96 ++++++++++++++++++++
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi    | 15 +++
+ 2 files changed, 111 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -5,6 +5,8 @@
+  */
+ 
+ /dts-v1/;
++#include <dt-bindings/pinctrl/mt65xx.h>
++
+ #include "mt7986a.dtsi"
+ 
+ / {
+@@ -23,6 +25,24 @@
+ 		device_type = "memory";
+ 		reg = <0 0x40000000 0 0x40000000>;
+ 	};
++
++	reg_1p8v: regulator-1p8v {
++		compatible = "regulator-fixed";
++		regulator-name = "fixed-1.8V";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	reg_3p3v: regulator-3p3v {
++		compatible = "regulator-fixed";
++		regulator-name = "fixed-3.3V";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
+ };
+ 
+ &crypto {
+@@ -58,7 +78,83 @@
+ 	};
+ };
+ 
++&mmc0 {
++	pinctrl-names = "default", "state_uhs";
++	pinctrl-0 = <&mmc0_pins_default>;
++	pinctrl-1 = <&mmc0_pins_uhs>;
++	bus-width = <8>;
++	max-frequency = <200000000>;
++	cap-mmc-highspeed;
++	mmc-hs200-1_8v;
++	mmc-hs400-1_8v;
++	hs400-ds-delay = <0x14014>;
++	vmmc-supply = <&reg_3p3v>;
++	vqmmc-supply = <&reg_1p8v>;
++	non-removable;
++	no-sd;
++	no-sdio;
++	status = "okay";
++};
++
+ &pio {
++	mmc0_pins_default: mmc0-pins {
++		mux {
++			function = "emmc";
++			groups = "emmc_51";
++		};
++		conf-cmd-dat {
++			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
++			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
++			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
++			input-enable;
++			drive-strength = <4>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++		};
++		conf-clk {
++			pins = "EMMC_CK";
++			drive-strength = <6>;
++			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++		};
++		conf-ds {
++			pins = "EMMC_DSL";
++			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++		};
++		conf-rst {
++			pins = "EMMC_RSTB";
++			drive-strength = <4>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++		};
++	};
++
++	mmc0_pins_uhs: mmc0-uhs-pins {
++		mux {
++			function = "emmc";
++			groups = "emmc_51";
++		};
++		conf-cmd-dat {
++			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
++			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
++			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
++			input-enable;
++			drive-strength = <4>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++		};
++		conf-clk {
++			pins = "EMMC_CK";
++			drive-strength = <6>;
++			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++		};
++		conf-ds {
++			pins = "EMMC_DSL";
++			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++		};
++		conf-rst {
++			pins = "EMMC_RSTB";
++			drive-strength = <4>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++		};
++	};
++
+ 	spi_flash_pins: spi-flash-pins {
+ 		mux {
+ 			function = "spi";
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -345,6 +345,21 @@
+ 			status = "disabled";
+ 		};
+ 
++		mmc0: mmc@11230000 {
++			compatible = "mediatek,mt7986-mmc";
++			reg = <0 0x11230000 0 0x1000>,
++			      <0 0x11c20000 0 0x1000>;
++			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
++				 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
++				 <&infracfg CLK_INFRA_MSDC_CK>,
++				 <&infracfg CLK_INFRA_MSDC_133M_CK>,
++				 <&infracfg CLK_INFRA_MSDC_66M_CK>;
++			clock-names = "source", "hclk", "source_cg", "bus_clk",
++				      "sys_cg";
++			status = "disabled";
++		};
++
+ 		usb_phy: t-phy@11e10000 {
+ 			compatible = "mediatek,mt7986-tphy",
+ 				     "mediatek,generic-tphy-v2";

target/linux/mediatek/patches-6.1/009-v6.3-arm64-dts-mt7986-add-pcie-related-device-nodes.patch

@@ -0,0 +1,118 @@
+From 87a42ef1d6cf602e4aa40555b4404cad6149a90f Mon Sep 17 00:00:00 2001
+From: Sam Shih <[email protected]>
+Date: Fri, 6 Jan 2023 16:28:44 +0100
+Subject: [PATCH 09/19] arm64: dts: mt7986: add pcie related device nodes
+
+This patch adds PCIe support for MT7986.
+
+Signed-off-by: Jieyy Yang <[email protected]>
+Signed-off-by: Sam Shih <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 16 ++++++
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi    | 52 ++++++++++++++++++++
+ 2 files changed, 68 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -93,6 +93,15 @@
+ 	non-removable;
+ 	no-sd;
+ 	no-sdio;
++};
++
++&pcie {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pcie_pins>;
++	status = "okay";
++};
++
++&pcie_phy {
+ 	status = "okay";
+ };
+ 
+@@ -155,6 +164,13 @@
+ 		};
+ 	};
+ 
++	pcie_pins: pcie-pins {
++		mux {
++			function = "pcie";
++			groups = "pcie_clk", "pcie_wake", "pcie_pereset";
++		};
++	};
++
+ 	spi_flash_pins: spi-flash-pins {
+ 		mux {
+ 			function = "spi";
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -8,6 +8,7 @@
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt7986-clk.h>
+ #include <dt-bindings/reset/mt7986-resets.h>
++#include <dt-bindings/phy/phy.h>
+ 
+ / {
+ 	compatible = "mediatek,mt7986a";
+@@ -360,6 +361,57 @@
+ 			status = "disabled";
+ 		};
+ 
++		pcie: pcie@11280000 {
++			compatible = "mediatek,mt7986-pcie",
++				     "mediatek,mt8192-pcie";
++			device_type = "pci";
++			#address-cells = <3>;
++			#size-cells = <2>;
++			reg = <0x00 0x11280000 0x00 0x4000>;
++			reg-names = "pcie-mac";
++			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
++			bus-range = <0x00 0xff>;
++			ranges = <0x82000000 0x00 0x20000000 0x00
++				  0x20000000 0x00 0x10000000>;
++			clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
++				 <&infracfg CLK_INFRA_IPCIE_CK>,
++				 <&infracfg CLK_INFRA_IPCIER_CK>,
++				 <&infracfg CLK_INFRA_IPCIEB_CK>;
++			clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
++			status = "disabled";
++
++			phys = <&pcie_port PHY_TYPE_PCIE>;
++			phy-names = "pcie-phy";
++
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 0x7>;
++			interrupt-map = <0 0 0 1 &pcie_intc 0>,
++					<0 0 0 2 &pcie_intc 1>,
++					<0 0 0 3 &pcie_intc 2>,
++					<0 0 0 4 &pcie_intc 3>;
++			pcie_intc: interrupt-controller {
++				#address-cells = <0>;
++				#interrupt-cells = <1>;
++				interrupt-controller;
++			};
++		};
++
++		pcie_phy: t-phy@11c00000 {
++			compatible = "mediatek,mt7986-tphy",
++				     "mediatek,generic-tphy-v2";
++			#address-cells = <2>;
++			#size-cells = <2>;
++			ranges;
++			status = "disabled";
++
++			pcie_port: pcie-phy@11c00000 {
++				reg = <0 0x11c00000 0 0x20000>;
++				clocks = <&clk40m>;
++				clock-names = "ref";
++				#phy-cells = <1>;
++			};
++		};
++
+ 		usb_phy: t-phy@11e10000 {
+ 			compatible = "mediatek,mt7986-tphy",
+ 				     "mediatek,generic-tphy-v2";

target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch

@@ -0,0 +1,689 @@
+From a751f7412e0098801673b80bc7a4738ae7d710ce Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <[email protected]>
+Date: Fri, 6 Jan 2023 16:28:45 +0100
+Subject: [PATCH 10/19] arm64: dts: mt7986: add Bananapi R3
+
+Add support for Bananapi R3 SBC.
+
+- SD/eMMC support (switching first 4 bits of data-bus with sw6/D)
+- SPI-NAND/NOR support (switched CS by sw5/C)
+- all rj45 ports and both SFP working (eth1/lan4)
+- all USB-Ports + SIM-Slot tested
+- i2c and all uarts tested
+- wifi tested (with eeprom calibration data)
+
+The device can boot from all 4 storage options. Both, SPI and MMC, can
+be switched using hardware switches on the board, see
+https://wiki.banana-pi.org/Banana_Pi_BPI-R3#Jumper_setting
+
+Signed-off-by: Frank Wunderlich <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/Makefile         |   5 +
+ .../mt7986a-bananapi-bpi-r3-emmc.dtso         |  29 ++
+ .../mt7986a-bananapi-bpi-r3-nand.dtso         |  55 +++
+ .../mediatek/mt7986a-bananapi-bpi-r3-nor.dtso |  68 +++
+ .../mediatek/mt7986a-bananapi-bpi-r3-sd.dtso  |  23 +
+ .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts  | 450 ++++++++++++++++++
+ 6 files changed, 630 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
+ create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
+ create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
+ create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
+ create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+
+--- a/arch/arm64/boot/dts/mediatek/Makefile
++++ b/arch/arm64/boot/dts/mediatek/Makefile
+@@ -7,6 +7,11 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-ev
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb
++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo
++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo
++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo
++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
+@@ -0,0 +1,29 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++/*
++ * Copyright (C) 2021 MediaTek Inc.
++ * Author: Sam.Shih <[email protected]>
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
++
++	fragment@0 {
++		target-path = "/soc/mmc@11230000";
++		__overlay__ {
++			bus-width = <8>;
++			max-frequency = <200000000>;
++			cap-mmc-highspeed;
++			mmc-hs200-1_8v;
++			mmc-hs400-1_8v;
++			hs400-ds-delay = <0x14014>;
++			non-removable;
++			no-sd;
++			no-sdio;
++			status = "okay";
++		};
++	};
++};
++
+--- /dev/null
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
+@@ -0,0 +1,55 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
++/*
++ * Authors: Daniel Golle <[email protected]>
++ *          Frank Wunderlich <[email protected]>
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
++
++	fragment@0 {
++		target-path = "/soc/spi@1100a000";
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spi_nand: spi_nand@0 {
++				compatible = "spi-nand";
++				reg = <0>;
++				spi-max-frequency = <10000000>;
++				spi-tx-buswidth = <4>;
++				spi-rx-buswidth = <4>;
++
++				partitions {
++					compatible = "fixed-partitions";
++					#address-cells = <1>;
++					#size-cells = <1>;
++
++					partition@0 {
++						label = "bl2";
++						reg = <0x0 0x80000>;
++						read-only;
++					};
++
++					partition@80000 {
++						label = "reserved";
++						reg = <0x80000 0x300000>;
++					};
++
++					partition@380000 {
++						label = "fip";
++						reg = <0x380000 0x200000>;
++						read-only;
++					};
++
++					partition@580000 {
++						label = "ubi";
++						reg = <0x580000 0x7a80000>;
++					};
++				};
++			};
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
+@@ -0,0 +1,68 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
++/*
++ * Authors: Daniel Golle <[email protected]>
++ *          Frank Wunderlich <[email protected]>
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
++
++	fragment@0 {
++		target-path = "/soc/spi@1100a000";
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			flash@0 {
++				compatible = "jedec,spi-nor";
++				reg = <0>;
++				spi-max-frequency = <10000000>;
++
++				partitions {
++					compatible = "fixed-partitions";
++					#address-cells = <1>;
++					#size-cells = <1>;
++
++					partition@0 {
++						label = "bl2";
++						reg = <0x0 0x20000>;
++						read-only;
++					};
++
++					partition@20000 {
++						label = "reserved";
++						reg = <0x20000 0x20000>;
++					};
++
++					partition@40000 {
++						label = "u-boot-env";
++						reg = <0x40000 0x40000>;
++					};
++
++					partition@80000 {
++						label = "reserved2";
++						reg = <0x80000 0x80000>;
++					};
++
++					partition@100000 {
++						label = "fip";
++						reg = <0x100000 0x80000>;
++						read-only;
++					};
++
++					partition@180000 {
++						label = "recovery";
++						reg = <0x180000 0xa80000>;
++					};
++
++					partition@c00000 {
++						label = "fit";
++						reg = <0xc00000 0x1400000>;
++					};
++				};
++			};
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
+@@ -0,0 +1,23 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++/*
++ * Copyright (C) 2021 MediaTek Inc.
++ * Author: Sam.Shih <[email protected]>
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
++
++	fragment@0 {
++		target-path = "/soc/mmc@11230000";
++		__overlay__ {
++			bus-width = <4>;
++			max-frequency = <52000000>;
++			cap-sd-highspeed;
++			status = "okay";
++		};
++	};
++};
++
+--- /dev/null
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+@@ -0,0 +1,450 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++/*
++ * Copyright (C) 2021 MediaTek Inc.
++ * Authors: Sam.Shih <[email protected]>
++ *          Frank Wunderlich <[email protected]>
++ *          Daniel Golle <[email protected]>
++ */
++
++/dts-v1/;
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/mt65xx.h>
++
++#include "mt7986a.dtsi"
++
++/ {
++	model = "Bananapi BPI-R3";
++	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
++
++	aliases {
++		serial0 = &uart0;
++		ethernet0 = &gmac0;
++		ethernet1 = &gmac1;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	dcin: regulator-12vd {
++		compatible = "regulator-fixed";
++		regulator-name = "12vd";
++		regulator-min-microvolt = <12000000>;
++		regulator-max-microvolt = <12000000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	gpio-keys {
++		compatible = "gpio-keys";
++
++		reset-key {
++			label = "reset";
++			linux,code = <KEY_RESTART>;
++			gpios = <&pio 9 GPIO_ACTIVE_LOW>;
++		};
++
++		wps-key {
++			label = "wps";
++			linux,code = <KEY_WPS_BUTTON>;
++			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
++		};
++	};
++
++	/* i2c of the left SFP cage (wan) */
++	i2c_sfp1: i2c-gpio-0 {
++		compatible = "i2c-gpio";
++		sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		i2c-gpio,delay-us = <2>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++	};
++
++	/* i2c of the right SFP cage (lan) */
++	i2c_sfp2: i2c-gpio-1 {
++		compatible = "i2c-gpio";
++		sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		i2c-gpio,delay-us = <2>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		green_led: led-0 {
++			color = <LED_COLOR_ID_GREEN>;
++			function = LED_FUNCTION_POWER;
++			gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
++			default-state = "on";
++		};
++
++		blue_led: led-1 {
++			color = <LED_COLOR_ID_BLUE>;
++			function = LED_FUNCTION_STATUS;
++			gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
++			default-state = "off";
++		};
++	};
++
++	reg_1p8v: regulator-1p8v {
++		compatible = "regulator-fixed";
++		regulator-name = "1.8vd";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-boot-on;
++		regulator-always-on;
++		vin-supply = <&dcin>;
++	};
++
++	reg_3p3v: regulator-3p3v {
++		compatible = "regulator-fixed";
++		regulator-name = "3.3vd";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-boot-on;
++		regulator-always-on;
++		vin-supply = <&dcin>;
++	};
++
++	/* left SFP cage (wan) */
++	sfp1: sfp-1 {
++		compatible = "sff,sfp";
++		i2c-bus = <&i2c_sfp1>;
++		los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
++		mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
++		tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
++		tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
++	};
++
++	/* right SFP cage (lan) */
++	sfp2: sfp-2 {
++		compatible = "sff,sfp";
++		i2c-bus = <&i2c_sfp2>;
++		los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
++		mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
++		tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
++		tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
++	};
++};
++
++&crypto {
++	status = "okay";
++};
++
++&eth {
++	status = "okay";
++
++	gmac0: mac@0 {
++		compatible = "mediatek,eth-mac";
++		reg = <0>;
++		phy-mode = "2500base-x";
++
++		fixed-link {
++			speed = <2500>;
++			full-duplex;
++			pause;
++		};
++	};
++
++	gmac1: mac@1 {
++		compatible = "mediatek,eth-mac";
++		reg = <1>;
++		phy-mode = "2500base-x";
++		sfp = <&sfp1>;
++		managed = "in-band-status";
++	};
++
++	mdio: mdio-bus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++	};
++};
++
++&mdio {
++	switch: switch@31 {
++		compatible = "mediatek,mt7531";
++		reg = <31>;
++		interrupt-controller;
++		#interrupt-cells = <1>;
++		interrupt-parent = <&pio>;
++		interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
++		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
++	};
++};
++
++&mmc0 {
++	pinctrl-names = "default", "state_uhs";
++	pinctrl-0 = <&mmc0_pins_default>;
++	pinctrl-1 = <&mmc0_pins_uhs>;
++	vmmc-supply = <&reg_3p3v>;
++	vqmmc-supply = <&reg_1p8v>;
++};
++
++&i2c0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c_pins>;
++	status = "okay";
++};
++
++&pcie {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pcie_pins>;
++	status = "okay";
++};
++
++&pcie_phy {
++	status = "okay";
++};
++
++&pio {
++	i2c_pins: i2c-pins {
++		mux {
++			function = "i2c";
++			groups = "i2c";
++		};
++	};
++
++	mmc0_pins_default: mmc0-pins {
++		mux {
++			function = "emmc";
++			groups = "emmc_51";
++		};
++		conf-cmd-dat {
++			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
++			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
++			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
++			input-enable;
++			drive-strength = <4>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++		};
++		conf-clk {
++			pins = "EMMC_CK";
++			drive-strength = <6>;
++			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++		};
++		conf-ds {
++			pins = "EMMC_DSL";
++			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++		};
++		conf-rst {
++			pins = "EMMC_RSTB";
++			drive-strength = <4>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++		};
++	};
++
++	mmc0_pins_uhs: mmc0-uhs-pins {
++		mux {
++			function = "emmc";
++			groups = "emmc_51";
++		};
++		conf-cmd-dat {
++			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
++			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
++			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
++			input-enable;
++			drive-strength = <4>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++		};
++		conf-clk {
++			pins = "EMMC_CK";
++			drive-strength = <6>;
++			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++		};
++		conf-ds {
++			pins = "EMMC_DSL";
++			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++		};
++		conf-rst {
++			pins = "EMMC_RSTB";
++			drive-strength = <4>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++		};
++	};
++
++	pcie_pins: pcie-pins {
++		mux {
++			function = "pcie";
++			groups = "pcie_clk", "pcie_pereset";
++		};
++	};
++
++	spi_flash_pins: spi-flash-pins {
++		mux {
++			function = "spi";
++			groups = "spi0", "spi0_wp_hold";
++		};
++	};
++
++	spic_pins: spic-pins {
++		mux {
++			function = "spi";
++			groups = "spi1_0";
++		};
++	};
++
++	uart1_pins: uart1-pins {
++		mux {
++			function = "uart";
++			groups = "uart1_rx_tx";
++		};
++	};
++
++	uart2_pins: uart2-pins {
++		mux {
++			function = "uart";
++			groups = "uart2_0_rx_tx";
++		};
++	};
++
++	wf_2g_5g_pins: wf-2g-5g-pins {
++		mux {
++			function = "wifi";
++			groups = "wf_2g", "wf_5g";
++		};
++		conf {
++			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
++			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
++			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
++			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
++			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
++			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
++			       "WF1_TOP_CLK", "WF1_TOP_DATA";
++			drive-strength = <4>;
++		};
++	};
++
++	wf_dbdc_pins: wf-dbdc-pins {
++		mux {
++			function = "wifi";
++			groups = "wf_dbdc";
++		};
++		conf {
++			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
++			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
++			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
++			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
++			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
++			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
++			       "WF1_TOP_CLK", "WF1_TOP_DATA";
++			drive-strength = <4>;
++		};
++	};
++
++	wf_led_pins: wf-led-pins {
++		mux {
++			function = "led";
++			groups = "wifi_led";
++		};
++	};
++};
++
++&spi0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi_flash_pins>;
++	status = "okay";
++};
++
++&spi1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&spic_pins>;
++	status = "okay";
++};
++
++&ssusb {
++	status = "okay";
++};
++
++&switch {
++	ports {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		port@0 {
++			reg = <0>;
++			label = "wan";
++		};
++
++		port@1 {
++			reg = <1>;
++			label = "lan0";
++		};
++
++		port@2 {
++			reg = <2>;
++			label = "lan1";
++		};
++
++		port@3 {
++			reg = <3>;
++			label = "lan2";
++		};
++
++		port@4 {
++			reg = <4>;
++			label = "lan3";
++		};
++
++		port5: port@5 {
++			reg = <5>;
++			label = "lan4";
++			phy-mode = "2500base-x";
++			sfp = <&sfp2>;
++			managed = "in-band-status";
++		};
++
++		port@6 {
++			reg = <6>;
++			label = "cpu";
++			ethernet = <&gmac0>;
++			phy-mode = "2500base-x";
++
++			fixed-link {
++				speed = <2500>;
++				full-duplex;
++				pause;
++			};
++		};
++	};
++};
++
++&trng {
++	status = "okay";
++};
++
++&uart0 {
++	status = "okay";
++};
++
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pins>;
++	status = "okay";
++};
++
++&uart2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart2_pins>;
++	status = "okay";
++};
++
++&usb_phy {
++	status = "okay";
++};
++
++&watchdog {
++	status = "okay";
++};
++
++&wifi {
++	status = "okay";
++	pinctrl-names = "default", "dbdc";
++	pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
++	pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
++};
++

target/linux/mediatek/patches-6.1/011-v6.5-arm64-mediatek-Propagate-chassis-type-where-possible.patch

@@ -0,0 +1,323 @@
+From 4c2d5411f4b101f7aa0fd74f80109e3afd6dc967 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <[email protected]>
+Date: Wed, 17 May 2023 12:11:08 +0200
+Subject: [PATCH 11/19] arm64: mediatek: Propagate chassis-type where possible
+
+The chassis-type string identifies the form-factor of the system:
+add this property to all device trees of devices for which the form
+factor is known.
+
+Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt2712-evb.dts                      | 1 +
+ arch/arm64/boot/dts/mediatek/mt6755-evb.dts                      | 1 +
+ arch/arm64/boot/dts/mediatek/mt6779-evb.dts                      | 1 +
+ arch/arm64/boot/dts/mediatek/mt6795-evb.dts                      | 1 +
+ arch/arm64/boot/dts/mediatek/mt6797-evb.dts                      | 1 +
+ arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts                  | 1 +
+ arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts         | 1 +
+ arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts                     | 1 +
+ arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts         | 1 +
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts                     | 1 +
+ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts                     | 1 +
+ arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts                  | 1 +
+ arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts            | 1 +
+ arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts                 | 1 +
+ arch/arm64/boot/dts/mediatek/mt8173-elm.dts                      | 1 +
+ arch/arm64/boot/dts/mediatek/mt8173-evb.dts                      | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-evb.dts                      | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts     | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts       | 1 +
+ .../boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts     | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts       | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts             | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts       | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts      | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts      | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts         | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts       | 1 +
+ arch/arm64/boot/dts/mediatek/mt8186-evb.dts                      | 1 +
+ 28 files changed, 28 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
+@@ -11,6 +11,7 @@
+ 
+ / {
+ 	model = "MediaTek MT2712 evaluation board";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt6755-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt6755-evb.dts
+@@ -9,6 +9,7 @@
+ 
+ / {
+ 	model = "MediaTek MT6755 EVB";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt6755-evb", "mediatek,mt6755";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
+@@ -10,6 +10,7 @@
+ 
+ / {
+ 	model = "MediaTek MT6779 EVB";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt6779-evb", "mediatek,mt6779";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt6795-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt6795-evb.dts
+@@ -9,6 +9,7 @@
+ 
+ / {
+ 	model = "MediaTek MT6795 Evaluation Board";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt6797-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt6797-evb.dts
+@@ -9,6 +9,7 @@
+ 
+ / {
+ 	model = "MediaTek MT6797 Evaluation Board";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt6797-evb", "mediatek,mt6797";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts
++++ b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts
+@@ -12,6 +12,7 @@
+ 
+ / {
+ 	model = "Mediatek X20 Development Board";
++	chassis-type = "embedded";
+ 	compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -15,6 +15,7 @@
+ 
+ / {
+ 	model = "Bananapi BPI-R64";
++	chassis-type = "embedded";
+ 	compatible = "bananapi,bpi-r64", "mediatek,mt7622";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+@@ -15,6 +15,7 @@
+ 
+ / {
+ 	model = "MediaTek MT7622 RFB1 board";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+@@ -16,6 +16,7 @@
+ 
+ / {
+ 	model = "Bananapi BPI-R3";
++	chassis-type = "embedded";
+ 	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -11,6 +11,7 @@
+ 
+ / {
+ 	model = "MediaTek MT7986a RFB";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+@@ -9,6 +9,7 @@
+ 
+ / {
+ 	model = "MediaTek MT7986b RFB";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts
+@@ -11,6 +11,7 @@
+ 
+ / {
+ 	model = "Pumpkin MT8167";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt8167-pumpkin", "mediatek,mt8167";
+ 
+ 	memory@40000000 {
+--- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts
+@@ -8,6 +8,7 @@
+ 
+ / {
+ 	model = "Google Hanawl";
++	chassis-type = "laptop";
+ 	compatible = "google,hana-rev7", "mediatek,mt8173";
+ };
+ 
+--- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts
+@@ -8,6 +8,7 @@
+ 
+ / {
+ 	model = "Google Hana";
++	chassis-type = "laptop";
+ 	compatible = "google,hana-rev6", "google,hana-rev5",
+ 		     "google,hana-rev4", "google,hana-rev3",
+ 		     "google,hana", "mediatek,mt8173";
+--- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dts
+@@ -8,6 +8,7 @@
+ 
+ / {
+ 	model = "Google Elm";
++	chassis-type = "laptop";
+ 	compatible = "google,elm-rev8", "google,elm-rev7", "google,elm-rev6",
+ 		     "google,elm-rev5", "google,elm-rev4", "google,elm-rev3",
+ 		     "google,elm", "mediatek,mt8173";
+--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+@@ -10,6 +10,7 @@
+ 
+ / {
+ 	model = "MediaTek MT8173 evaluation board";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt8173-evb", "mediatek,mt8173";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+@@ -11,6 +11,7 @@
+ 
+ / {
+ 	model = "MediaTek MT8183 evaluation board";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts
+@@ -9,6 +9,7 @@
+ 
+ / {
+ 	model = "Google burnet board";
++	chassis-type = "convertible";
+ 	compatible = "google,burnet", "mediatek,mt8183";
+ };
+ 
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
+@@ -9,6 +9,7 @@
+ 
+ / {
+ 	model = "Google damu board";
++	chassis-type = "convertible";
+ 	compatible = "google,damu", "mediatek,mt8183";
+ };
+ 
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts
+@@ -9,6 +9,7 @@
+ 
+ / {
+ 	model = "Google juniper sku16 board";
++	chassis-type = "convertible";
+ 	compatible = "google,juniper-sku16", "google,juniper", "mediatek,mt8183";
+ };
+ 
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts
+@@ -9,6 +9,7 @@
+ 
+ / {
+ 	model = "MediaTek kakadu board sku22";
++	chassis-type = "tablet";
+ 	compatible = "google,kakadu-rev3-sku22", "google,kakadu-rev2-sku22",
+ 		     "google,kakadu", "mediatek,mt8183";
+ };
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts
+@@ -9,6 +9,7 @@
+ 
+ / {
+ 	model = "MediaTek kakadu board";
++	chassis-type = "tablet";
+ 	compatible = "google,kakadu-rev3", "google,kakadu-rev2",
+ 			"google,kakadu", "mediatek,mt8183";
+ };
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts
+@@ -12,6 +12,7 @@
+ 
+ / {
+ 	model = "MediaTek kodama sku16 board";
++	chassis-type = "tablet";
+ 	compatible = "google,kodama-sku16", "google,kodama", "mediatek,mt8183";
+ };
+ 
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts
+@@ -12,6 +12,7 @@
+ 
+ / {
+ 	model = "MediaTek kodama sku272 board";
++	chassis-type = "tablet";
+ 	compatible = "google,kodama-sku272", "google,kodama", "mediatek,mt8183";
+ };
+ 
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts
+@@ -12,6 +12,7 @@
+ 
+ / {
+ 	model = "MediaTek kodama sku288 board";
++	chassis-type = "tablet";
+ 	compatible = "google,kodama-sku288", "google,kodama", "mediatek,mt8183";
+ };
+ 
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts
+@@ -14,6 +14,7 @@
+ 
+ / {
+ 	model = "MediaTek krane sku0 board";
++	chassis-type = "tablet";
+ 	compatible = "google,krane-sku0", "google,krane", "mediatek,mt8183";
+ };
+ 
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts
+@@ -14,6 +14,7 @@
+ 
+ / {
+ 	model = "MediaTek krane sku176 board";
++	chassis-type = "tablet";
+ 	compatible = "google,krane-sku176", "google,krane", "mediatek,mt8183";
+ };
+ 
+--- a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
+@@ -7,6 +7,7 @@
+ 
+ / {
+ 	model = "MediaTek MT8186 evaluation board";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
+ 
+ 	aliases {

target/linux/mediatek/patches-6.1/012-v6.5-arm64-dts-mt7986-add-PWM.patch

@@ -0,0 +1,38 @@
+From 3b92c547e3d4a35c6214b3e7fa1103d0749d83b1 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Fri, 21 Apr 2023 15:20:44 +0200
+Subject: [PATCH 12/19] arm64: dts: mt7986: add PWM
+
+This adds pwm node to mt7986.
+
+Signed-off-by: Daniel Golle <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -240,6 +240,20 @@
+ 			status = "disabled";
+ 		};
+ 
++		pwm: pwm@10048000 {
++			compatible = "mediatek,mt7986-pwm";
++			reg = <0 0x10048000 0 0x1000>;
++			#clock-cells = <1>;
++			#pwm-cells = <2>;
++			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&topckgen CLK_TOP_PWM_SEL>,
++				 <&infracfg CLK_INFRA_PWM_STA>,
++				 <&infracfg CLK_INFRA_PWM1_CK>,
++				 <&infracfg CLK_INFRA_PWM2_CK>;
++			clock-names = "top", "main", "pwm1", "pwm2";
++			status = "disabled";
++		};
++
+ 		uart0: serial@11002000 {
+ 			compatible = "mediatek,mt7986-uart",
+ 				     "mediatek,mt6577-uart";

target/linux/mediatek/patches-6.1/013-v6.5-arm64-dts-mt7986-add-PWM-to-BPI-R3.patch

@@ -0,0 +1,43 @@
+From 35e482bb599df010b4869017ff576dbb7a4d4c2e Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <[email protected]>
+Date: Fri, 21 Apr 2023 15:20:45 +0200
+Subject: [PATCH 13/19] arm64: dts: mt7986: add PWM to BPI-R3
+
+Add pwm node and pinctrl to BananaPi R3 devicetree.
+
+Signed-off-by: Frank Wunderlich <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts   | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+@@ -275,6 +275,13 @@
+ 		};
+ 	};
+ 
++	pwm_pins: pwm-pins {
++		mux {
++			function = "pwm";
++			groups = "pwm0", "pwm1_0";
++		};
++	};
++
+ 	spi_flash_pins: spi-flash-pins {
+ 		mux {
+ 			function = "spi";
+@@ -345,6 +352,12 @@
+ 	};
+ };
+ 
++&pwm {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pwm_pins>;
++	status = "okay";
++};
++
+ &spi0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&spi_flash_pins>;

target/linux/mediatek/patches-6.1/014-v6.5-arm64-dts-mt7986-set-Wifi-Leds-low-active-for-BPI-R3.patch

@@ -0,0 +1,27 @@
+From ccdda5714446db8690505371442f7807f5d7c6fc Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <[email protected]>
+Date: Sun, 5 Feb 2023 18:48:33 +0100
+Subject: [PATCH 14/19] arm64: dts: mt7986: set Wifi Leds low-active for BPI-R3
+
+Leds for Wifi are low-active, so add property to devicetree.
+
+Signed-off-by: Frank Wunderlich <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+@@ -460,5 +460,9 @@
+ 	pinctrl-names = "default", "dbdc";
+ 	pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
+ 	pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
++
++	led {
++		led-active-low;
++	};
+ };
+ 

target/linux/mediatek/patches-6.1/015-v6.5-arm64-dts-mt7986-use-size-of-reserved-partition-for-.patch

@@ -0,0 +1,46 @@
+From 1423b4b780adcf3994e63a5988a62d5d1d509bb1 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <[email protected]>
+Date: Sun, 28 May 2023 13:33:42 +0200
+Subject: [PATCH 15/19] arm64: dts: mt7986: use size of reserved partition for
+ bl2
+
+To store uncompressed bl2 more space is required than partition is
+actually defined.
+
+There is currently no known usage of this reserved partition.
+Openwrt uses same partition layout.
+
+We added same change to u-boot with commit d7bb1099 [1].
+
+[1] https://source.denx.de/u-boot/u-boot/-/commit/d7bb109900c1ca754a0198b9afb50e3161ffc21e
+
+Cc: [email protected]
+Fixes: 8e01fb15b815 ("arm64: dts: mt7986: add Bananapi R3")
+Signed-off-by: Frank Wunderlich <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Reviewed-by: Daniel Golle <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso     | 7 +------
+ 1 file changed, 1 insertion(+), 6 deletions(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
+@@ -27,15 +27,10 @@
+ 
+ 					partition@0 {
+ 						label = "bl2";
+-						reg = <0x0 0x20000>;
++						reg = <0x0 0x40000>;
+ 						read-only;
+ 					};
+ 
+-					partition@20000 {
+-						label = "reserved";
+-						reg = <0x20000 0x20000>;
+-					};
+-
+ 					partition@40000 {
+ 						label = "u-boot-env";
+ 						reg = <0x40000 0x40000>;

target/linux/mediatek/patches-6.1/016-v6.5-arm64-dts-mt7986-add-thermal-and-efuse.patch

@@ -0,0 +1,80 @@
+From 40a5a767d698ef7a71f8be851ea18b0a7a8b47bd Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Tue, 30 May 2023 22:12:33 +0200
+Subject: [PATCH 16/19] arm64: dts: mt7986: add thermal and efuse
+
+Add thermal related nodes to mt7986 devicetree.
+
+Signed-off-by: Daniel Golle <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 36 ++++++++++++++++++++++-
+ 1 file changed, 35 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -337,6 +337,15 @@
+ 			status = "disabled";
+ 		};
+ 
++		auxadc: adc@1100d000 {
++			compatible = "mediatek,mt7986-auxadc";
++			reg = <0 0x1100d000 0 0x1000>;
++			clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
++			clock-names = "main";
++			#io-channel-cells = <1>;
++			status = "disabled";
++		};
++
+ 		ssusb: usb@11200000 {
+ 			compatible = "mediatek,mt7986-xhci",
+ 				     "mediatek,mtk-xhci";
+@@ -375,6 +384,21 @@
+ 			status = "disabled";
+ 		};
+ 
++		thermal: thermal@1100c800 {
++			#thermal-sensor-cells = <1>;
++			compatible = "mediatek,mt7986-thermal";
++			reg = <0 0x1100c800 0 0x800>;
++			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&infracfg CLK_INFRA_THERM_CK>,
++				 <&infracfg CLK_INFRA_ADC_26M_CK>,
++				 <&infracfg CLK_INFRA_ADC_FRC_CK>;
++			clock-names = "therm", "auxadc", "adc_32k";
++			mediatek,auxadc = <&auxadc>;
++			mediatek,apmixedsys = <&apmixedsys>;
++			nvmem-cells = <&thermal_calibration>;
++			nvmem-cell-names = "calibration-data";
++		};
++
+ 		pcie: pcie@11280000 {
+ 			compatible = "mediatek,mt7986-pcie",
+ 				     "mediatek,mt8192-pcie";
+@@ -426,6 +450,17 @@
+ 			};
+ 		};
+ 
++		efuse: efuse@11d00000 {
++			compatible = "mediatek,mt7986-efuse", "mediatek,efuse";
++			reg = <0 0x11d00000 0 0x1000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			thermal_calibration: calib@274 {
++				reg = <0x274 0xc>;
++			};
++		};
++
+ 		usb_phy: t-phy@11e10000 {
+ 			compatible = "mediatek,mt7986-tphy",
+ 				     "mediatek,generic-tphy-v2";
+@@ -567,5 +602,4 @@
+ 			memory-region = <&wmcpu_emi>;
+ 		};
+ 	};
+-
+ };

target/linux/mediatek/patches-6.1/017-v6.5-arm64-dts-mt7986-add-thermal-zones.patch

@@ -0,0 +1,51 @@
+From bb78d0cf5117517f1ed296ae71048945d9107675 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Tue, 30 May 2023 22:12:34 +0200
+Subject: [PATCH 17/19] arm64: dts: mt7986: add thermal-zones
+
+Add thermal-zones to mt7986 devicetree.
+
+Signed-off-by: Daniel Golle <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 +++++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -602,4 +602,32 @@
+ 			memory-region = <&wmcpu_emi>;
+ 		};
+ 	};
++
++	thermal-zones {
++		cpu_thermal: cpu-thermal {
++			polling-delay-passive = <1000>;
++			polling-delay = <1000>;
++			thermal-sensors = <&thermal 0>;
++
++			trips {
++				cpu_trip_active_high: active-high {
++					temperature = <115000>;
++					hysteresis = <2000>;
++					type = "active";
++				};
++
++				cpu_trip_active_low: active-low {
++					temperature = <85000>;
++					hysteresis = <2000>;
++					type = "active";
++				};
++
++				cpu_trip_passive: passive {
++					temperature = <40000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++			};
++		};
++	};
+ };

target/linux/mediatek/patches-6.1/018-v6.5-arm64-dts-mt7986-add-pwm-fan-and-cooling-maps-to-BPI.patch

@@ -0,0 +1,64 @@
+From 5d90603b09e5814ffc38c47e79ccf9bc564f9296 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Tue, 30 May 2023 22:12:35 +0200
+Subject: [PATCH 18/19] arm64: dts: mt7986: add pwm-fan and cooling-maps to
+ BPI-R3 dts
+
+Add pwm-fan and cooling-maps to BananaPi-R3 devicetree.
+
+Signed-off-by: Daniel Golle <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts  | 31 +++++++++++++++++++
+ 1 file changed, 31 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+@@ -38,6 +38,15 @@
+ 		regulator-always-on;
+ 	};
+ 
++	fan: pwm-fan {
++		compatible = "pwm-fan";
++		#cooling-cells = <2>;
++		/* cooling level (0, 1, 2) - pwm inverted */
++		cooling-levels = <255 96 0>;
++		pwms = <&pwm 0 10000 0>;
++		status = "okay";
++	};
++
+ 	gpio-keys {
+ 		compatible = "gpio-keys";
+ 
+@@ -133,6 +142,28 @@
+ 	};
+ };
+ 
++&cpu_thermal {
++	cooling-maps {
++		cpu-active-high {
++			/* active: set fan to cooling level 2 */
++			cooling-device = <&fan 2 2>;
++			trip = <&cpu_trip_active_high>;
++		};
++
++		cpu-active-low {
++			/* active: set fan to cooling level 1 */
++			cooling-device = <&fan 1 1>;
++			trip = <&cpu_trip_active_low>;
++		};
++
++		cpu-passive {
++			/* passive: set fan to cooling level 0 */
++			cooling-device = <&fan 0 0>;
++			trip = <&cpu_trip_passive>;
++		};
++	};
++};
++
+ &crypto {
+ 	status = "okay";
+ };

target/linux/mediatek/patches-6.1/019-v6.5-arm64-dts-mt7986-increase-bl2-partition-on-NAND-of-B.patch

@@ -0,0 +1,41 @@
+From 6dd3b939370094eb79529683be84500f3c757404 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Tue, 6 Jun 2023 16:43:20 +0100
+Subject: [PATCH 19/19] arm64: dts: mt7986: increase bl2 partition on NAND of
+ Bananapi R3
+
+The bootrom burned into the MT7986 SoC will try multiple locations on
+the SPI-NAND flash to load bl2 in case the bl2 image located at the the
+previously attempted offset is corrupt.
+
+Use 0x100000 instead of 0x80000 as partition size for bl2 on SPI-NAND,
+allowing for up to four redundant copies of bl2 (typically sized a
+bit less than 0x40000).
+
+Fixes: 8e01fb15b8157 ("arm64: dts: mt7986: add Bananapi R3")
+Signed-off-by: Daniel Golle <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso     | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
+@@ -29,13 +29,13 @@
+ 
+ 					partition@0 {
+ 						label = "bl2";
+-						reg = <0x0 0x80000>;
++						reg = <0x0 0x100000>;
+ 						read-only;
+ 					};
+ 
+-					partition@80000 {
++					partition@100000 {
+ 						label = "reserved";
+-						reg = <0x80000 0x300000>;
++						reg = <0x100000 0x280000>;
+ 					};
+ 
+ 					partition@380000 {

target/linux/mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch

@@ -10,7 +10,7 @@
   *
   * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   */
-@@ -23,7 +22,7 @@
+@@ -24,7 +23,7 @@
  
  	chosen {
  		stdout-path = "serial0:115200n8";
@@ -19,20 +19,15 @@
  	};
  
  	cpus {
-@@ -40,23 +39,22 @@
- 
- 	gpio-keys {
- 		compatible = "gpio-keys";
--		poll-interval = <100>;
- 
- 		factory {
+@@ -45,18 +44,18 @@
+ 		key-factory {
  			label = "factory";
  			linux,code = <BTN_0>;
 -			gpios = <&pio 0 0>;
 +			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
  		};
  
- 		wps {
+ 		key-wps {
  			label = "wps";
  			linux,code = <KEY_WPS_BUTTON>;
 -			gpios = <&pio 102 0>;
@@ -46,7 +41,7 @@
  	};
  
  	reg_1p8v: regulator-1p8v {
-@@ -132,22 +130,22 @@
+@@ -132,22 +131,22 @@
  
  				port@0 {
  					reg = <0>;
@@ -73,23 +68,16 @@
  				};
  
  				port@4 {
-@@ -236,15 +234,28 @@
- 
- &pcie {
- 	pinctrl-names = "default";
--	pinctrl-0 = <&pcie0_pins>;
-+	pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
+@@ -240,7 +239,22 @@
  	status = "okay";
- 
- 	pcie@0,0 {
- 		status = "okay";
- 	};
-+
-+	pcie@1,0 {
-+		status = "okay";
-+	};
  };
  
++&pcie1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pcie1_pins>;
++	status = "okay";
++};
++
  &pio {
 +	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
 +	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
@@ -103,7 +91,7 @@
  	/* eMMC is shared pin with parallel NAND */
  	emmc_pins_default: emmc-pins-default {
  		mux {
-@@ -521,11 +532,11 @@
+@@ -517,11 +531,11 @@
  };
  
  &sata {

target/linux/mediatek/patches-6.1/101-dts-update-mt7629-rfb.patch

@@ -40,7 +40,7 @@
  			};
  		};
  	};
-@@ -272,3 +281,17 @@
+@@ -273,3 +282,17 @@
  	pinctrl-0 = <&watchdog_pins>;
  	status = "okay";
  };

target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -559,6 +559,7 @@
+@@ -578,6 +578,7 @@
  		compatible = "mediatek,mt7622-nor",
  			     "mediatek,mt8173-nor";
  		reg = <0 0x11014000 0 0xe0>;

target/linux/mediatek/patches-6.1/105-dts-mt7622-enable-pstore.patch

@@ -1,15 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -111,7 +111,7 @@
- 	};
- 
- 	psci {
--		compatible  = "arm,psci-0.2";
-+		compatible  = "arm,psci-1.0";
- 		method      = "smc";
- 	};
- 
-@@ -127,6 +127,13 @@
+@@ -134,6 +134,13 @@
  		#size-cells = <2>;
  		ranges;
  

target/linux/mediatek/patches-6.1/111-dts-fix-bpi64-console.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -22,7 +22,7 @@
+@@ -24,7 +24,7 @@
  
  	chosen {
  		stdout-path = "serial0:115200n8";

target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -18,6 +18,7 @@
+@@ -20,6 +20,7 @@
  
  	aliases {
  		serial0 = &uart0;
@@ -8,7 +8,7 @@
  	};
  
  	chosen {
-@@ -160,22 +161,22 @@
+@@ -164,22 +165,22 @@
  
  				port@1 {
  					reg = <1>;

target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -19,6 +19,10 @@
+@@ -21,6 +21,10 @@
  	aliases {
  		serial0 = &uart0;
  		ethernet0 = &gmac0;
@@ -11,10 +11,10 @@
  	};
  
  	chosen {
-@@ -42,8 +46,8 @@
+@@ -44,8 +48,8 @@
  		compatible = "gpio-keys";
  
- 		factory {
+ 		factory-key {
 -			label = "factory";
 -			linux,code = <BTN_0>;
 +			label = "reset";
@@ -22,35 +22,26 @@
  			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
  		};
  
-@@ -57,17 +61,25 @@
+@@ -59,17 +63,17 @@
  	leds {
  		compatible = "gpio-leds";
  
--		green {
--			label = "bpi-r64:pio:green";
--			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
-+		led_system_blue: blue {
-+			label = "bpi-r64:pio:blue";
-+			gpios = <&pio 85 GPIO_ACTIVE_HIGH>;
+-		led-0 {
++		led_system_green: led-0 {
+ 			label = "bpi-r64:pio:green";
+ 			color = <LED_COLOR_ID_GREEN>;
+ 			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
  			default-state = "off";
  		};
  
--		red {
+-		led-1 {
 -			label = "bpi-r64:pio:red";
+-			color = <LED_COLOR_ID_RED>;
 -			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
-+		led_system_green: green {
-+			label = "bpi-r64:pio:green";
-+			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
++		led_system_blue: led-1 {
++			label = "bpi-r64:pio:blue";
++			color = <LED_COLOR_ID_BLUE>;
++			gpios = <&pio 85 GPIO_ACTIVE_HIGH>;
  			default-state = "off";
  		};
-+
-+/*
-+ *		red {
-+ *			label = "bpi-r64:pio:red";
-+ *			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
-+ *			default-state = "off";
-+ *		};
-+ */
  	};
- 
- 	memory {

target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -564,12 +564,16 @@
+@@ -558,12 +558,16 @@
  	status = "okay";
  };
  

target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -259,14 +259,42 @@
+@@ -255,14 +255,42 @@
  	status = "disabled";
  };
  

target/linux/mediatek/patches-6.1/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch

@@ -1,214 +0,0 @@
-From ad4944aa0b02cb043afe20bc2a018c161e65c992 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <[email protected]>
-Date: Thu, 16 Dec 2021 12:16:38 +0100
-Subject: [PATCH 01/15] mtd: nand: ecc: Add infrastructure to support hardware
- engines
-
-Add the necessary helpers to register/unregister hardware ECC engines
-that will be called from ECC engine drivers.
-
-Also add helpers to get the right engine from the user
-perspective. Keep a reference of the in use ECC engine in order to
-prevent modules to be unloaded. Put the reference when the engine gets
-retired.
-
-A static list of hardware (only) ECC engines is setup to keep track of
-the registered engines.
-
-Signed-off-by: Miquel Raynal <[email protected]>
-Link: https://lore.kernel.org/linux-mtd/[email protected]
-(cherry picked from commit 96489c1c0b53131b0e1ec33e2060538379ad6152)
----
- drivers/mtd/nand/core.c  | 10 +++--
- drivers/mtd/nand/ecc.c   | 88 ++++++++++++++++++++++++++++++++++++++++
- include/linux/mtd/nand.h | 28 +++++++++++++
- 3 files changed, 123 insertions(+), 3 deletions(-)
-
---- a/drivers/mtd/nand/core.c
-+++ b/drivers/mtd/nand/core.c
-@@ -232,7 +232,9 @@ static int nanddev_get_ecc_engine(struct
- 		nand->ecc.engine = nand_ecc_get_on_die_hw_engine(nand);
- 		break;
- 	case NAND_ECC_ENGINE_TYPE_ON_HOST:
--		pr_err("On-host hardware ECC engines not supported yet\n");
-+		nand->ecc.engine = nand_ecc_get_on_host_hw_engine(nand);
-+		if (PTR_ERR(nand->ecc.engine) == -EPROBE_DEFER)
-+			return -EPROBE_DEFER;
- 		break;
- 	default:
- 		pr_err("Missing ECC engine type\n");
-@@ -252,7 +254,7 @@ static int nanddev_put_ecc_engine(struct
- {
- 	switch (nand->ecc.ctx.conf.engine_type) {
- 	case NAND_ECC_ENGINE_TYPE_ON_HOST:
--		pr_err("On-host hardware ECC engines not supported yet\n");
-+		nand_ecc_put_on_host_hw_engine(nand);
- 		break;
- 	case NAND_ECC_ENGINE_TYPE_NONE:
- 	case NAND_ECC_ENGINE_TYPE_SOFT:
-@@ -297,7 +299,9 @@ int nanddev_ecc_engine_init(struct nand_
- 	/* Look for the ECC engine to use */
- 	ret = nanddev_get_ecc_engine(nand);
- 	if (ret) {
--		pr_err("No ECC engine found\n");
-+		if (ret != -EPROBE_DEFER)
-+			pr_err("No ECC engine found\n");
-+
- 		return ret;
- 	}
- 
---- a/drivers/mtd/nand/ecc.c
-+++ b/drivers/mtd/nand/ecc.c
-@@ -96,6 +96,12 @@
- #include <linux/module.h>
- #include <linux/mtd/nand.h>
- #include <linux/slab.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_platform.h>
-+
-+static LIST_HEAD(on_host_hw_engines);
-+static DEFINE_MUTEX(on_host_hw_engines_mutex);
- 
- /**
-  * nand_ecc_init_ctx - Init the ECC engine context
-@@ -611,6 +617,88 @@ struct nand_ecc_engine *nand_ecc_get_on_
- }
- EXPORT_SYMBOL(nand_ecc_get_on_die_hw_engine);
- 
-+int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine)
-+{
-+	struct nand_ecc_engine *item;
-+
-+	if (!engine)
-+		return -EINVAL;
-+
-+	/* Prevent multiple registrations of one engine */
-+	list_for_each_entry(item, &on_host_hw_engines, node)
-+		if (item == engine)
-+			return 0;
-+
-+	mutex_lock(&on_host_hw_engines_mutex);
-+	list_add_tail(&engine->node, &on_host_hw_engines);
-+	mutex_unlock(&on_host_hw_engines_mutex);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(nand_ecc_register_on_host_hw_engine);
-+
-+int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine)
-+{
-+	if (!engine)
-+		return -EINVAL;
-+
-+	mutex_lock(&on_host_hw_engines_mutex);
-+	list_del(&engine->node);
-+	mutex_unlock(&on_host_hw_engines_mutex);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(nand_ecc_unregister_on_host_hw_engine);
-+
-+static struct nand_ecc_engine *nand_ecc_match_on_host_hw_engine(struct device *dev)
-+{
-+	struct nand_ecc_engine *item;
-+
-+	list_for_each_entry(item, &on_host_hw_engines, node)
-+		if (item->dev == dev)
-+			return item;
-+
-+	return NULL;
-+}
-+
-+struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand)
-+{
-+	struct nand_ecc_engine *engine = NULL;
-+	struct device *dev = &nand->mtd.dev;
-+	struct platform_device *pdev;
-+	struct device_node *np;
-+
-+	if (list_empty(&on_host_hw_engines))
-+		return NULL;
-+
-+	/* Check for an explicit nand-ecc-engine property */
-+	np = of_parse_phandle(dev->of_node, "nand-ecc-engine", 0);
-+	if (np) {
-+		pdev = of_find_device_by_node(np);
-+		if (!pdev)
-+			return ERR_PTR(-EPROBE_DEFER);
-+
-+		engine = nand_ecc_match_on_host_hw_engine(&pdev->dev);
-+		platform_device_put(pdev);
-+		of_node_put(np);
-+
-+		if (!engine)
-+			return ERR_PTR(-EPROBE_DEFER);
-+	}
-+
-+	if (engine)
-+		get_device(engine->dev);
-+
-+	return engine;
-+}
-+EXPORT_SYMBOL(nand_ecc_get_on_host_hw_engine);
-+
-+void nand_ecc_put_on_host_hw_engine(struct nand_device *nand)
-+{
-+	put_device(nand->ecc.engine->dev);
-+}
-+EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine);
-+
- MODULE_LICENSE("GPL");
- MODULE_AUTHOR("Miquel Raynal <[email protected]>");
- MODULE_DESCRIPTION("Generic ECC engine");
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -264,11 +264,35 @@ struct nand_ecc_engine_ops {
- };
- 
- /**
-+ * enum nand_ecc_engine_integration - How the NAND ECC engine is integrated
-+ * @NAND_ECC_ENGINE_INTEGRATION_INVALID: Invalid value
-+ * @NAND_ECC_ENGINE_INTEGRATION_PIPELINED: Pipelined engine, performs on-the-fly
-+ *                                         correction, does not need to copy
-+ *                                         data around
-+ * @NAND_ECC_ENGINE_INTEGRATION_EXTERNAL: External engine, needs to bring the
-+ *                                        data into its own area before use
-+ */
-+enum nand_ecc_engine_integration {
-+	NAND_ECC_ENGINE_INTEGRATION_INVALID,
-+	NAND_ECC_ENGINE_INTEGRATION_PIPELINED,
-+	NAND_ECC_ENGINE_INTEGRATION_EXTERNAL,
-+};
-+
-+/**
-  * struct nand_ecc_engine - ECC engine abstraction for NAND devices
-+ * @dev: Host device
-+ * @node: Private field for registration time
-  * @ops: ECC engine operations
-+ * @integration: How the engine is integrated with the host
-+ *               (only relevant on %NAND_ECC_ENGINE_TYPE_ON_HOST engines)
-+ * @priv: Private data
-  */
- struct nand_ecc_engine {
-+	struct device *dev;
-+	struct list_head node;
- 	struct nand_ecc_engine_ops *ops;
-+	enum nand_ecc_engine_integration integration;
-+	void *priv;
- };
- 
- void of_get_nand_ecc_user_config(struct nand_device *nand);
-@@ -279,8 +303,12 @@ int nand_ecc_prepare_io_req(struct nand_
- int nand_ecc_finish_io_req(struct nand_device *nand,
- 			   struct nand_page_io_req *req);
- bool nand_ecc_is_strong_enough(struct nand_device *nand);
-+int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine);
-+int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine);
- struct nand_ecc_engine *nand_ecc_get_sw_engine(struct nand_device *nand);
- struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand);
-+struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand);
-+void nand_ecc_put_on_host_hw_engine(struct nand_device *nand);
- 
- #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING)
- struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void);

target/linux/mediatek/patches-6.1/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch

@@ -1,31 +0,0 @@
-From 840b2f8dd2d0579e517140e1f9bbc482eaf4ed07 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <[email protected]>
-Date: Thu, 16 Dec 2021 12:16:39 +0100
-Subject: [PATCH 02/15] mtd: nand: Add a new helper to retrieve the ECC context
-
-Introduce nand_to_ecc_ctx() which will allow to easily jump to the
-private pointer of an ECC context given a NAND device. This is very
-handy, from the prepare or finish ECC hook, to get the internal context
-out of the NAND device object.
-
-Signed-off-by: Miquel Raynal <[email protected]>
-Link: https://lore.kernel.org/linux-mtd/[email protected]
-(cherry picked from commit cda32a618debd3fad8e42757b198719ae180f8f4)
----
- include/linux/mtd/nand.h | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -990,6 +990,11 @@ int nanddev_markbad(struct nand_device *
- int nanddev_ecc_engine_init(struct nand_device *nand);
- void nanddev_ecc_engine_cleanup(struct nand_device *nand);
- 
-+static inline void *nand_to_ecc_ctx(struct nand_device *nand)
-+{
-+	return nand->ecc.ctx.priv;
-+}
-+
- /* BBT related functions */
- enum nand_bbt_block_status {
- 	NAND_BBT_BLOCK_STATUS_UNKNOWN,

target/linux/mediatek/patches-6.1/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch

@@ -1,73 +0,0 @@
-From 784866bc4f9f25e0494b77750f95af2a2619e498 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <[email protected]>
-Date: Thu, 16 Dec 2021 12:16:41 +0100
-Subject: [PATCH 03/15] mtd: nand: ecc: Provide a helper to retrieve a
- pilelined engine device
-
-In a pipelined engine situation, we might either have the host which
-internally has support for error correction, or have it using an
-external hardware block for this purpose. In the former case, the host
-is also the ECC engine. In the latter case, it is not. In order to get
-the right pointers on the right devices (for example: in order to devm_*
-allocate variables), let's introduce this helper which can safely be
-called by pipelined ECC engines in order to retrieve the right device
-structure.
-
-Signed-off-by: Miquel Raynal <[email protected]>
-Link: https://lore.kernel.org/linux-mtd/[email protected]
-(cherry picked from commit 5145abeb0649acf810a32e63bd762e617a9b3309)
----
- drivers/mtd/nand/ecc.c   | 31 +++++++++++++++++++++++++++++++
- include/linux/mtd/nand.h |  1 +
- 2 files changed, 32 insertions(+)
-
---- a/drivers/mtd/nand/ecc.c
-+++ b/drivers/mtd/nand/ecc.c
-@@ -699,6 +699,37 @@ void nand_ecc_put_on_host_hw_engine(stru
- }
- EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine);
- 
-+/*
-+ * In the case of a pipelined engine, the device registering the ECC
-+ * engine is not necessarily the ECC engine itself but may be a host controller.
-+ * It is then useful to provide a helper to retrieve the right device object
-+ * which actually represents the ECC engine.
-+ */
-+struct device *nand_ecc_get_engine_dev(struct device *host)
-+{
-+	struct platform_device *ecc_pdev;
-+	struct device_node *np;
-+
-+	/*
-+	 * If the device node contains this property, it means we need to follow
-+	 * it in order to get the right ECC engine device we are looking for.
-+	 */
-+	np = of_parse_phandle(host->of_node, "nand-ecc-engine", 0);
-+	if (!np)
-+		return host;
-+
-+	ecc_pdev = of_find_device_by_node(np);
-+	if (!ecc_pdev) {
-+		of_node_put(np);
-+		return NULL;
-+	}
-+
-+	platform_device_put(ecc_pdev);
-+	of_node_put(np);
-+
-+	return &ecc_pdev->dev;
-+}
-+
- MODULE_LICENSE("GPL");
- MODULE_AUTHOR("Miquel Raynal <[email protected]>");
- MODULE_DESCRIPTION("Generic ECC engine");
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -309,6 +309,7 @@ struct nand_ecc_engine *nand_ecc_get_sw_
- struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand);
- struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand);
- void nand_ecc_put_on_host_hw_engine(struct nand_device *nand);
-+struct device *nand_ecc_get_engine_dev(struct device *host);
- 
- #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING)
- struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void);

target/linux/mediatek/patches-6.1/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch

@@ -1,71 +0,0 @@
-From 3e45577e70cbf8fdc5c13033114989794a3797d5 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <[email protected]>
-Date: Thu, 27 Jan 2022 10:17:56 +0100
-Subject: [PATCH 04/15] spi: spi-mem: Introduce a capability structure
-
-Create a spi_controller_mem_caps structure and put it within the
-spi_controller structure close to the spi_controller_mem_ops
-strucure. So far the only field in this structure is the support for dtr
-operations, but soon we will add another parameter.
-
-Also create a helper to parse the capabilities and check if the
-requested capability has been set or not.
-
-Signed-off-by: Miquel Raynal <[email protected]>
-Reviewed-by: Pratyush Yadav <[email protected]>
-Reviewed-by: Boris Brezillon <[email protected]>
-Reviewed-by: Tudor Ambarus <[email protected]>
-Reviewed-by: Mark Brown <[email protected]>
-Link: https://lore.kernel.org/linux-mtd/[email protected]
-(cherry picked from commit 4a3cc7fb6e63bcfdedec25364738f1493345bd20)
----
- include/linux/spi/spi-mem.h | 11 +++++++++++
- include/linux/spi/spi.h     |  3 +++
- 2 files changed, 14 insertions(+)
-
---- a/include/linux/spi/spi-mem.h
-+++ b/include/linux/spi/spi-mem.h
-@@ -286,6 +286,17 @@ struct spi_controller_mem_ops {
- };
- 
- /**
-+ * struct spi_controller_mem_caps - SPI memory controller capabilities
-+ * @dtr: Supports DTR operations
-+ */
-+struct spi_controller_mem_caps {
-+	bool dtr;
-+};
-+
-+#define spi_mem_controller_is_capable(ctlr, cap)	\
-+	((ctlr)->mem_caps && (ctlr)->mem_caps->cap)
-+
-+/**
-  * struct spi_mem_driver - SPI memory driver
-  * @spidrv: inherit from a SPI driver
-  * @probe: probe a SPI memory. Usually where detection/initialization takes
---- a/include/linux/spi/spi.h
-+++ b/include/linux/spi/spi.h
-@@ -23,6 +23,7 @@ struct software_node;
- struct spi_controller;
- struct spi_transfer;
- struct spi_controller_mem_ops;
-+struct spi_controller_mem_caps;
- 
- /*
-  * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
-@@ -419,6 +420,7 @@ extern struct spi_device *spi_new_ancill
-  * @mem_ops: optimized/dedicated operations for interactions with SPI memory.
-  *	     This field is optional and should only be implemented if the
-  *	     controller has native support for memory like operations.
-+ * @mem_caps: controller capabilities for the handling of memory operations.
-  * @unprepare_message: undo any work done by prepare_message().
-  * @slave_abort: abort the ongoing transfer request on an SPI slave controller
-  * @cs_gpios: LEGACY: array of GPIO descs to use as chip select lines; one per
-@@ -643,6 +645,7 @@ struct spi_controller {
- 
- 	/* Optimized handlers for SPI memory-like operations. */
- 	const struct spi_controller_mem_ops *mem_ops;
-+	const struct spi_controller_mem_caps *mem_caps;
- 
- 	/* gpio chip select */
- 	int			*cs_gpios;

target/linux/mediatek/patches-6.1/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch

@@ -1,51 +0,0 @@
-From c9cae7e1e5c87d0aa76b7bededa5191a0c8cf25a Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <[email protected]>
-Date: Thu, 27 Jan 2022 10:17:57 +0100
-Subject: [PATCH 05/15] spi: spi-mem: Check the controller extra capabilities
-
-Controllers can now provide a spi-mem capabilities structure. Let's make
-use of it in spi_mem_controller_default_supports_op(). As we want to
-check for DTR operations as well as normal operations in a single
-helper, let's pull the necessary checks from spi_mem_dtr_supports_op()
-for now.
-
-However, because no controller provide these extra capabilities, this
-change has no effect so far.
-
-Signed-off-by: Miquel Raynal <[email protected]>
-Reviewed-by: Pratyush Yadav <[email protected]>
-Reviewed-by: Boris Brezillon <[email protected]>
-Reviewed-by: Tudor Ambarus <[email protected]>
-Link: https://lore.kernel.org/linux-mtd/[email protected]
-(cherry picked from commit cb7e96ee81edaa48c67d84c14df2cbe464391c37)
----
- drivers/spi/spi-mem.c | 17 +++++++++++++----
- 1 file changed, 13 insertions(+), 4 deletions(-)
-
---- a/drivers/spi/spi-mem.c
-+++ b/drivers/spi/spi-mem.c
-@@ -173,11 +173,20 @@ EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_o
- bool spi_mem_default_supports_op(struct spi_mem *mem,
- 				 const struct spi_mem_op *op)
- {
--	if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
--		return false;
-+	struct spi_controller *ctlr = mem->spi->controller;
-+	bool op_is_dtr =
-+		op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr;
- 
--	if (op->cmd.nbytes != 1)
--		return false;
-+	if (op_is_dtr) {
-+		if (!spi_mem_controller_is_capable(ctlr, dtr))
-+			return false;
-+
-+		if (op->cmd.nbytes != 2)
-+			return false;
-+	} else {
-+		if (op->cmd.nbytes != 1)
-+			return false;
-+	}
- 
- 	return spi_mem_check_buswidth(mem, op);
- }

target/linux/mediatek/patches-6.1/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch

@@ -1,111 +0,0 @@
-From 2e5fba82e4aeb72d71230eef2541881615aaf7cf Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <[email protected]>
-Date: Thu, 27 Jan 2022 10:18:00 +0100
-Subject: [PATCH 06/15] spi: spi-mem: Kill the spi_mem_dtr_supports_op() helper
-
-Now that spi_mem_default_supports_op() has access to the static
-controller capabilities (relating to memory operations), and now that
-these capabilities have been filled by the relevant controllers, there
-is no need for a specific helper checking only DTR operations, so let's
-just kill spi_mem_dtr_supports_op() and simply use
-spi_mem_default_supports_op() instead.
-
-Signed-off-by: Miquel Raynal <[email protected]>
-Reviewed-by: Pratyush Yadav <[email protected]>
-Reviewed-by: Boris Brezillon <[email protected]>
-Reviewed-by: Tudor Ambarus <[email protected]>
-Link: https://lore.kernel.org/linux-mtd/[email protected]
-(cherry picked from commit 9a15efc5d5e6b5beaed0883e5bdcd0b1384c1b20)
----
- drivers/spi/spi-cadence-quadspi.c |  5 +----
- drivers/spi/spi-mem.c             | 10 ----------
- drivers/spi/spi-mxic.c            | 10 +---------
- include/linux/spi/spi-mem.h       | 11 -----------
- 4 files changed, 2 insertions(+), 34 deletions(-)
-
---- a/drivers/spi/spi-cadence-quadspi.c
-+++ b/drivers/spi/spi-cadence-quadspi.c
-@@ -1249,10 +1249,7 @@ static bool cqspi_supports_mem_op(struct
- 		return false;
- 	}
- 
--	if (all_true)
--		return spi_mem_dtr_supports_op(mem, op);
--	else
--		return spi_mem_default_supports_op(mem, op);
-+	return spi_mem_default_supports_op(mem, op);
- }
- 
- static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
---- a/drivers/spi/spi-mem.c
-+++ b/drivers/spi/spi-mem.c
-@@ -160,16 +160,6 @@ static bool spi_mem_check_buswidth(struc
- 	return true;
- }
- 
--bool spi_mem_dtr_supports_op(struct spi_mem *mem,
--			     const struct spi_mem_op *op)
--{
--	if (op->cmd.nbytes != 2)
--		return false;
--
--	return spi_mem_check_buswidth(mem, op);
--}
--EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op);
--
- bool spi_mem_default_supports_op(struct spi_mem *mem,
- 				 const struct spi_mem_op *op)
- {
---- a/drivers/spi/spi-mxic.c
-+++ b/drivers/spi/spi-mxic.c
-@@ -331,8 +331,6 @@ static int mxic_spi_data_xfer(struct mxi
- static bool mxic_spi_mem_supports_op(struct spi_mem *mem,
- 				     const struct spi_mem_op *op)
- {
--	bool all_false;
--
- 	if (op->data.buswidth > 8 || op->addr.buswidth > 8 ||
- 	    op->dummy.buswidth > 8 || op->cmd.buswidth > 8)
- 		return false;
-@@ -344,13 +342,7 @@ static bool mxic_spi_mem_supports_op(str
- 	if (op->addr.nbytes > 7)
- 		return false;
- 
--	all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
--		    !op->data.dtr;
--
--	if (all_false)
--		return spi_mem_default_supports_op(mem, op);
--	else
--		return spi_mem_dtr_supports_op(mem, op);
-+	return spi_mem_default_supports_op(mem, op);
- }
- 
- static int mxic_spi_mem_exec_op(struct spi_mem *mem,
---- a/include/linux/spi/spi-mem.h
-+++ b/include/linux/spi/spi-mem.h
-@@ -330,10 +330,6 @@ void spi_controller_dma_unmap_mem_op_dat
- 
- bool spi_mem_default_supports_op(struct spi_mem *mem,
- 				 const struct spi_mem_op *op);
--
--bool spi_mem_dtr_supports_op(struct spi_mem *mem,
--			     const struct spi_mem_op *op);
--
- #else
- static inline int
- spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
-@@ -356,13 +352,6 @@ bool spi_mem_default_supports_op(struct
- {
- 	return false;
- }
--
--static inline
--bool spi_mem_dtr_supports_op(struct spi_mem *mem,
--			     const struct spi_mem_op *op)
--{
--	return false;
--}
- #endif /* CONFIG_SPI_MEM */
- 
- int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op);

target/linux/mediatek/patches-6.1/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch

@@ -1,72 +0,0 @@
-From 9e7eb0ea442ecb1c3fe443289e288694f10c5148 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <[email protected]>
-Date: Thu, 27 Jan 2022 10:18:01 +0100
-Subject: [PATCH 07/15] spi: spi-mem: Add an ecc parameter to the spi_mem_op
- structure
-
-Soon the SPI-NAND core will need a way to request a SPI controller to
-enable ECC support for a given operation. This is because of the
-pipelined integration of certain ECC engines, which are directly managed
-by the SPI controller itself.
-
-Introduce a spi_mem_op additional field for this purpose: ecc.
-
-So far this field is left unset and checked to be false by all
-the SPI controller drivers in their ->supports_op() hook, as they all
-call spi_mem_default_supports_op().
-
-Signed-off-by: Miquel Raynal <[email protected]>
-Acked-by: Pratyush Yadav <[email protected]>
-Reviewed-by: Boris Brezillon <[email protected]>
-Reviewed-by: Tudor Ambarus <[email protected]>
-Link: https://lore.kernel.org/linux-mtd/[email protected]
-(cherry picked from commit a433c2cbd75ab76f277364f44e76f32c7df306e7)
----
- drivers/spi/spi-mem.c       | 5 +++++
- include/linux/spi/spi-mem.h | 4 ++++
- 2 files changed, 9 insertions(+)
-
---- a/drivers/spi/spi-mem.c
-+++ b/drivers/spi/spi-mem.c
-@@ -178,6 +178,11 @@ bool spi_mem_default_supports_op(struct
- 			return false;
- 	}
- 
-+	if (op->data.ecc) {
-+		if (!spi_mem_controller_is_capable(ctlr, ecc))
-+			return false;
-+	}
-+
- 	return spi_mem_check_buswidth(mem, op);
- }
- EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
---- a/include/linux/spi/spi-mem.h
-+++ b/include/linux/spi/spi-mem.h
-@@ -89,6 +89,7 @@ enum spi_mem_data_dir {
-  * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not
-  * @data.buswidth: number of IO lanes used to send/receive the data
-  * @data.dtr: whether the data should be sent in DTR mode or not
-+ * @data.ecc: whether error correction is required or not
-  * @data.dir: direction of the transfer
-  * @data.nbytes: number of data bytes to send/receive. Can be zero if the
-  *		 operation does not involve transferring data
-@@ -119,6 +120,7 @@ struct spi_mem_op {
- 	struct {
- 		u8 buswidth;
- 		u8 dtr : 1;
-+		u8 ecc : 1;
- 		enum spi_mem_data_dir dir;
- 		unsigned int nbytes;
- 		union {
-@@ -288,9 +290,11 @@ struct spi_controller_mem_ops {
- /**
-  * struct spi_controller_mem_caps - SPI memory controller capabilities
-  * @dtr: Supports DTR operations
-+ * @ecc: Supports operations with error correction
-  */
- struct spi_controller_mem_caps {
- 	bool dtr;
-+	bool ecc;
- };
- 
- #define spi_mem_controller_is_capable(ctlr, cap)	\

target/linux/mediatek/patches-6.1/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch

@@ -1,50 +0,0 @@
-From 94ef3c35b935a63f6c156957c92f6cf33c9a8dae Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <[email protected]>
-Date: Thu, 27 Jan 2022 10:18:02 +0100
-Subject: [PATCH 08/15] mtd: spinand: Delay a little bit the dirmap creation
-
-As we will soon tweak the dirmap creation to act a little bit
-differently depending on the picked ECC engine, we need to initialize
-dirmaps after ECC engines. This should not have any effect as dirmaps
-are not yet used at this point.
-
-Signed-off-by: Miquel Raynal <[email protected]>
-Reviewed-by: Boris Brezillon <[email protected]>
-Link: https://lore.kernel.org/linux-mtd/[email protected]
-(cherry picked from commit dc4c2cbf0be2d4a8e2a65013ea2815bb2c8ba949)
----
- drivers/mtd/nand/spi/core.c | 16 ++++++++--------
- 1 file changed, 8 insertions(+), 8 deletions(-)
-
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -1221,14 +1221,6 @@ static int spinand_init(struct spinand_d
- 	if (ret)
- 		goto err_free_bufs;
- 
--	ret = spinand_create_dirmaps(spinand);
--	if (ret) {
--		dev_err(dev,
--			"Failed to create direct mappings for read/write operations (err = %d)\n",
--			ret);
--		goto err_manuf_cleanup;
--	}
--
- 	ret = nanddev_init(nand, &spinand_ops, THIS_MODULE);
- 	if (ret)
- 		goto err_manuf_cleanup;
-@@ -1263,6 +1255,14 @@ static int spinand_init(struct spinand_d
- 	mtd->ecc_strength = nanddev_get_ecc_conf(nand)->strength;
- 	mtd->ecc_step_size = nanddev_get_ecc_conf(nand)->step_size;
- 
-+	ret = spinand_create_dirmaps(spinand);
-+	if (ret) {
-+		dev_err(dev,
-+			"Failed to create direct mappings for read/write operations (err = %d)\n",
-+			ret);
-+		goto err_cleanup_ecc_engine;
-+	}
-+
- 	return 0;
- 
- err_cleanup_ecc_engine:

target/linux/mediatek/patches-6.1/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch

@@ -1,98 +0,0 @@
-From eb4a2d282c3c5752211d69be6dff2674119e5583 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <[email protected]>
-Date: Thu, 27 Jan 2022 10:18:03 +0100
-Subject: [PATCH 09/15] mtd: spinand: Create direct mapping descriptors for ECC
- operations
-
-In order for pipelined ECC engines to be able to enable/disable the ECC
-engine only when needed and avoid races when future parallel-operations
-will be supported, we need to provide the information about the use of
-the ECC engine in the direct mapping hooks. As direct mapping
-configurations are meant to be static, it is best to create two new
-mappings: one for regular 'raw' accesses and one for accesses involving
-correction. It is up to the driver to use or not the new ECC enable
-boolean contained in the spi-mem operation.
-
-As dirmaps are not free (they consume a few pages of MMIO address space)
-and because these extra entries are only meant to be used by pipelined
-engines, let's limit their use to this specific type of engine and save
-a bit of memory with all the other setups.
-
-Signed-off-by: Miquel Raynal <[email protected]>
-Reviewed-by: Boris Brezillon <[email protected]>
-Link: https://lore.kernel.org/linux-mtd/[email protected]
-(cherry picked from commit f9d7c7265bcff7d9a17425a8cddf702e8fe159c2)
----
- drivers/mtd/nand/spi/core.c | 35 +++++++++++++++++++++++++++++++++--
- include/linux/mtd/spinand.h |  2 ++
- 2 files changed, 35 insertions(+), 2 deletions(-)
-
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -381,7 +381,10 @@ static int spinand_read_from_cache_op(st
- 		}
- 	}
- 
--	rdesc = spinand->dirmaps[req->pos.plane].rdesc;
-+	if (req->mode == MTD_OPS_RAW)
-+		rdesc = spinand->dirmaps[req->pos.plane].rdesc;
-+	else
-+		rdesc = spinand->dirmaps[req->pos.plane].rdesc_ecc;
- 
- 	while (nbytes) {
- 		ret = spi_mem_dirmap_read(rdesc, column, nbytes, buf);
-@@ -452,7 +455,10 @@ static int spinand_write_to_cache_op(str
- 			       req->ooblen);
- 	}
- 
--	wdesc = spinand->dirmaps[req->pos.plane].wdesc;
-+	if (req->mode == MTD_OPS_RAW)
-+		wdesc = spinand->dirmaps[req->pos.plane].wdesc;
-+	else
-+		wdesc = spinand->dirmaps[req->pos.plane].wdesc_ecc;
- 
- 	while (nbytes) {
- 		ret = spi_mem_dirmap_write(wdesc, column, nbytes, buf);
-@@ -875,6 +881,31 @@ static int spinand_create_dirmap(struct
- 
- 	spinand->dirmaps[plane].rdesc = desc;
- 
-+	if (nand->ecc.engine->integration != NAND_ECC_ENGINE_INTEGRATION_PIPELINED) {
-+		spinand->dirmaps[plane].wdesc_ecc = spinand->dirmaps[plane].wdesc;
-+		spinand->dirmaps[plane].rdesc_ecc = spinand->dirmaps[plane].rdesc;
-+
-+		return 0;
-+	}
-+
-+	info.op_tmpl = *spinand->op_templates.update_cache;
-+	info.op_tmpl.data.ecc = true;
-+	desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
-+					  spinand->spimem, &info);
-+	if (IS_ERR(desc))
-+		return PTR_ERR(desc);
-+
-+	spinand->dirmaps[plane].wdesc_ecc = desc;
-+
-+	info.op_tmpl = *spinand->op_templates.read_cache;
-+	info.op_tmpl.data.ecc = true;
-+	desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
-+					  spinand->spimem, &info);
-+	if (IS_ERR(desc))
-+		return PTR_ERR(desc);
-+
-+	spinand->dirmaps[plane].rdesc_ecc = desc;
-+
- 	return 0;
- }
- 
---- a/include/linux/mtd/spinand.h
-+++ b/include/linux/mtd/spinand.h
-@@ -392,6 +392,8 @@ struct spinand_info {
- struct spinand_dirmap {
- 	struct spi_mem_dirmap_desc *wdesc;
- 	struct spi_mem_dirmap_desc *rdesc;
-+	struct spi_mem_dirmap_desc *wdesc_ecc;
-+	struct spi_mem_dirmap_desc *rdesc_ecc;
- };
- 
- /**

target/linux/mediatek/patches-6.1/120-11-v5.19-mtd-nand-make-mtk_ecc.c-a-separated-module.patch

@@ -1,1383 +0,0 @@
-From ebb9653d4a87c64fb679e4c339e867556dada719 Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <[email protected]>
-Date: Tue, 22 Mar 2022 18:44:21 +0800
-Subject: [PATCH 11/15] mtd: nand: make mtk_ecc.c a separated module
-
-this code will be used in mediatek snfi spi-mem controller with
-pipelined ECC engine.
-
-Signed-off-by: Chuanhong Guo <[email protected]>
-(cherry picked from commit 316f47cec4ce5b81aa8006de202d8769c117a52d)
----
- drivers/mtd/nand/Kconfig                                   | 7 +++++++
- drivers/mtd/nand/Makefile                                  | 1 +
- drivers/mtd/nand/{raw/mtk_ecc.c => ecc-mtk.c}              | 3 +--
- drivers/mtd/nand/raw/Kconfig                               | 1 +
- drivers/mtd/nand/raw/Makefile                              | 2 +-
- drivers/mtd/nand/raw/mtk_nand.c                            | 2 +-
- .../nand/raw/mtk_ecc.h => include/linux/mtd/nand-ecc-mtk.h | 0
- 7 files changed, 12 insertions(+), 4 deletions(-)
- rename drivers/mtd/nand/{raw/mtk_ecc.c => ecc-mtk.c} (99%)
- rename drivers/mtd/nand/raw/mtk_ecc.h => include/linux/mtd/nand-ecc-mtk.h (100%)
-
---- a/drivers/mtd/nand/Kconfig
-+++ b/drivers/mtd/nand/Kconfig
-@@ -50,6 +50,13 @@ config MTD_NAND_MTK_BMT
- 	bool "Support MediaTek NAND Bad-block Management Table"
- 	default n
- 
-+config MTD_NAND_ECC_MEDIATEK
-+	tristate "Mediatek hardware ECC engine"
-+	depends on HAS_IOMEM
-+	select MTD_NAND_ECC
-+	help
-+	  This enables support for the hardware ECC engine from Mediatek.
-+
- endmenu
- 
- endmenu
---- a/drivers/mtd/nand/Makefile
-+++ b/drivers/mtd/nand/Makefile
-@@ -3,6 +3,7 @@
- nandcore-objs := core.o bbt.o
- obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o
- obj-$(CONFIG_MTD_NAND_MTK_BMT)	+= mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o
-+obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o
- 
- obj-y	+= onenand/
- obj-y	+= raw/
---- a/drivers/mtd/nand/raw/mtk_ecc.c
-+++ /dev/null
-@@ -1,599 +0,0 @@
--// SPDX-License-Identifier: GPL-2.0 OR MIT
--/*
-- * MTK ECC controller driver.
-- * Copyright (C) 2016  MediaTek Inc.
-- * Authors:	Xiaolei Li		<[email protected]>
-- *		Jorge Ramirez-Ortiz	<[email protected]>
-- */
--
--#include <linux/platform_device.h>
--#include <linux/dma-mapping.h>
--#include <linux/interrupt.h>
--#include <linux/clk.h>
--#include <linux/module.h>
--#include <linux/iopoll.h>
--#include <linux/of.h>
--#include <linux/of_platform.h>
--#include <linux/mutex.h>
--
--#include "mtk_ecc.h"
--
--#define ECC_IDLE_MASK		BIT(0)
--#define ECC_IRQ_EN		BIT(0)
--#define ECC_PG_IRQ_SEL		BIT(1)
--#define ECC_OP_ENABLE		(1)
--#define ECC_OP_DISABLE		(0)
--
--#define ECC_ENCCON		(0x00)
--#define ECC_ENCCNFG		(0x04)
--#define		ECC_MS_SHIFT		(16)
--#define ECC_ENCDIADDR		(0x08)
--#define ECC_ENCIDLE		(0x0C)
--#define ECC_DECCON		(0x100)
--#define ECC_DECCNFG		(0x104)
--#define		DEC_EMPTY_EN		BIT(31)
--#define		DEC_CNFG_CORRECT	(0x3 << 12)
--#define ECC_DECIDLE		(0x10C)
--#define ECC_DECENUM0		(0x114)
--
--#define ECC_TIMEOUT		(500000)
--
--#define ECC_IDLE_REG(op)	((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
--#define ECC_CTL_REG(op)		((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
--
--struct mtk_ecc_caps {
--	u32 err_mask;
--	u32 err_shift;
--	const u8 *ecc_strength;
--	const u32 *ecc_regs;
--	u8 num_ecc_strength;
--	u8 ecc_mode_shift;
--	u32 parity_bits;
--	int pg_irq_sel;
--};
--
--struct mtk_ecc {
--	struct device *dev;
--	const struct mtk_ecc_caps *caps;
--	void __iomem *regs;
--	struct clk *clk;
--
--	struct completion done;
--	struct mutex lock;
--	u32 sectors;
--
--	u8 *eccdata;
--};
--
--/* ecc strength that each IP supports */
--static const u8 ecc_strength_mt2701[] = {
--	4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
--	40, 44, 48, 52, 56, 60
--};
--
--static const u8 ecc_strength_mt2712[] = {
--	4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
--	40, 44, 48, 52, 56, 60, 68, 72, 80
--};
--
--static const u8 ecc_strength_mt7622[] = {
--	4, 6, 8, 10, 12
--};
--
--enum mtk_ecc_regs {
--	ECC_ENCPAR00,
--	ECC_ENCIRQ_EN,
--	ECC_ENCIRQ_STA,
--	ECC_DECDONE,
--	ECC_DECIRQ_EN,
--	ECC_DECIRQ_STA,
--};
--
--static int mt2701_ecc_regs[] = {
--	[ECC_ENCPAR00] =        0x10,
--	[ECC_ENCIRQ_EN] =       0x80,
--	[ECC_ENCIRQ_STA] =      0x84,
--	[ECC_DECDONE] =         0x124,
--	[ECC_DECIRQ_EN] =       0x200,
--	[ECC_DECIRQ_STA] =      0x204,
--};
--
--static int mt2712_ecc_regs[] = {
--	[ECC_ENCPAR00] =        0x300,
--	[ECC_ENCIRQ_EN] =       0x80,
--	[ECC_ENCIRQ_STA] =      0x84,
--	[ECC_DECDONE] =         0x124,
--	[ECC_DECIRQ_EN] =       0x200,
--	[ECC_DECIRQ_STA] =      0x204,
--};
--
--static int mt7622_ecc_regs[] = {
--	[ECC_ENCPAR00] =        0x10,
--	[ECC_ENCIRQ_EN] =       0x30,
--	[ECC_ENCIRQ_STA] =      0x34,
--	[ECC_DECDONE] =         0x11c,
--	[ECC_DECIRQ_EN] =       0x140,
--	[ECC_DECIRQ_STA] =      0x144,
--};
--
--static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
--				     enum mtk_ecc_operation op)
--{
--	struct device *dev = ecc->dev;
--	u32 val;
--	int ret;
--
--	ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,
--					val & ECC_IDLE_MASK,
--					10, ECC_TIMEOUT);
--	if (ret)
--		dev_warn(dev, "%s NOT idle\n",
--			 op == ECC_ENCODE ? "encoder" : "decoder");
--}
--
--static irqreturn_t mtk_ecc_irq(int irq, void *id)
--{
--	struct mtk_ecc *ecc = id;
--	u32 dec, enc;
--
--	dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
--		    & ECC_IRQ_EN;
--	if (dec) {
--		dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
--		if (dec & ecc->sectors) {
--			/*
--			 * Clear decode IRQ status once again to ensure that
--			 * there will be no extra IRQ.
--			 */
--			readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
--			ecc->sectors = 0;
--			complete(&ecc->done);
--		} else {
--			return IRQ_HANDLED;
--		}
--	} else {
--		enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
--		      & ECC_IRQ_EN;
--		if (enc)
--			complete(&ecc->done);
--		else
--			return IRQ_NONE;
--	}
--
--	return IRQ_HANDLED;
--}
--
--static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
--{
--	u32 ecc_bit, dec_sz, enc_sz;
--	u32 reg, i;
--
--	for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
--		if (ecc->caps->ecc_strength[i] == config->strength)
--			break;
--	}
--
--	if (i == ecc->caps->num_ecc_strength) {
--		dev_err(ecc->dev, "invalid ecc strength %d\n",
--			config->strength);
--		return -EINVAL;
--	}
--
--	ecc_bit = i;
--
--	if (config->op == ECC_ENCODE) {
--		/* configure ECC encoder (in bits) */
--		enc_sz = config->len << 3;
--
--		reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
--		reg |= (enc_sz << ECC_MS_SHIFT);
--		writel(reg, ecc->regs + ECC_ENCCNFG);
--
--		if (config->mode != ECC_NFI_MODE)
--			writel(lower_32_bits(config->addr),
--			       ecc->regs + ECC_ENCDIADDR);
--
--	} else {
--		/* configure ECC decoder (in bits) */
--		dec_sz = (config->len << 3) +
--			 config->strength * ecc->caps->parity_bits;
--
--		reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
--		reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
--		reg |= DEC_EMPTY_EN;
--		writel(reg, ecc->regs + ECC_DECCNFG);
--
--		if (config->sectors)
--			ecc->sectors = 1 << (config->sectors - 1);
--	}
--
--	return 0;
--}
--
--void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
--		       int sectors)
--{
--	u32 offset, i, err;
--	u32 bitflips = 0;
--
--	stats->corrected = 0;
--	stats->failed = 0;
--
--	for (i = 0; i < sectors; i++) {
--		offset = (i >> 2) << 2;
--		err = readl(ecc->regs + ECC_DECENUM0 + offset);
--		err = err >> ((i % 4) * ecc->caps->err_shift);
--		err &= ecc->caps->err_mask;
--		if (err == ecc->caps->err_mask) {
--			/* uncorrectable errors */
--			stats->failed++;
--			continue;
--		}
--
--		stats->corrected += err;
--		bitflips = max_t(u32, bitflips, err);
--	}
--
--	stats->bitflips = bitflips;
--}
--EXPORT_SYMBOL(mtk_ecc_get_stats);
--
--void mtk_ecc_release(struct mtk_ecc *ecc)
--{
--	clk_disable_unprepare(ecc->clk);
--	put_device(ecc->dev);
--}
--EXPORT_SYMBOL(mtk_ecc_release);
--
--static void mtk_ecc_hw_init(struct mtk_ecc *ecc)
--{
--	mtk_ecc_wait_idle(ecc, ECC_ENCODE);
--	writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
--
--	mtk_ecc_wait_idle(ecc, ECC_DECODE);
--	writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
--}
--
--static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
--{
--	struct platform_device *pdev;
--	struct mtk_ecc *ecc;
--
--	pdev = of_find_device_by_node(np);
--	if (!pdev)
--		return ERR_PTR(-EPROBE_DEFER);
--
--	ecc = platform_get_drvdata(pdev);
--	if (!ecc) {
--		put_device(&pdev->dev);
--		return ERR_PTR(-EPROBE_DEFER);
--	}
--
--	clk_prepare_enable(ecc->clk);
--	mtk_ecc_hw_init(ecc);
--
--	return ecc;
--}
--
--struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)
--{
--	struct mtk_ecc *ecc = NULL;
--	struct device_node *np;
--
--	np = of_parse_phandle(of_node, "ecc-engine", 0);
--	if (np) {
--		ecc = mtk_ecc_get(np);
--		of_node_put(np);
--	}
--
--	return ecc;
--}
--EXPORT_SYMBOL(of_mtk_ecc_get);
--
--int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
--{
--	enum mtk_ecc_operation op = config->op;
--	u16 reg_val;
--	int ret;
--
--	ret = mutex_lock_interruptible(&ecc->lock);
--	if (ret) {
--		dev_err(ecc->dev, "interrupted when attempting to lock\n");
--		return ret;
--	}
--
--	mtk_ecc_wait_idle(ecc, op);
--
--	ret = mtk_ecc_config(ecc, config);
--	if (ret) {
--		mutex_unlock(&ecc->lock);
--		return ret;
--	}
--
--	if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) {
--		init_completion(&ecc->done);
--		reg_val = ECC_IRQ_EN;
--		/*
--		 * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it
--		 * means this chip can only generate one ecc irq during page
--		 * read / write. If is 0, generate one ecc irq each ecc step.
--		 */
--		if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
--			reg_val |= ECC_PG_IRQ_SEL;
--		if (op == ECC_ENCODE)
--			writew(reg_val, ecc->regs +
--			       ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
--		else
--			writew(reg_val, ecc->regs +
--			       ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
--	}
--
--	writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
--
--	return 0;
--}
--EXPORT_SYMBOL(mtk_ecc_enable);
--
--void mtk_ecc_disable(struct mtk_ecc *ecc)
--{
--	enum mtk_ecc_operation op = ECC_ENCODE;
--
--	/* find out the running operation */
--	if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
--		op = ECC_DECODE;
--
--	/* disable it */
--	mtk_ecc_wait_idle(ecc, op);
--	if (op == ECC_DECODE) {
--		/*
--		 * Clear decode IRQ status in case there is a timeout to wait
--		 * decode IRQ.
--		 */
--		readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
--		writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
--	} else {
--		writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
--	}
--
--	writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
--
--	mutex_unlock(&ecc->lock);
--}
--EXPORT_SYMBOL(mtk_ecc_disable);
--
--int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)
--{
--	int ret;
--
--	ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
--	if (!ret) {
--		dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
--			(op == ECC_ENCODE) ? "encoder" : "decoder");
--		return -ETIMEDOUT;
--	}
--
--	return 0;
--}
--EXPORT_SYMBOL(mtk_ecc_wait_done);
--
--int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
--		   u8 *data, u32 bytes)
--{
--	dma_addr_t addr;
--	u32 len;
--	int ret;
--
--	addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
--	ret = dma_mapping_error(ecc->dev, addr);
--	if (ret) {
--		dev_err(ecc->dev, "dma mapping error\n");
--		return -EINVAL;
--	}
--
--	config->op = ECC_ENCODE;
--	config->addr = addr;
--	ret = mtk_ecc_enable(ecc, config);
--	if (ret) {
--		dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
--		return ret;
--	}
--
--	ret = mtk_ecc_wait_done(ecc, ECC_ENCODE);
--	if (ret)
--		goto timeout;
--
--	mtk_ecc_wait_idle(ecc, ECC_ENCODE);
--
--	/* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
--	len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
--
--	/* write the parity bytes generated by the ECC back to temp buffer */
--	__ioread32_copy(ecc->eccdata,
--			ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
--			round_up(len, 4));
--
--	/* copy into possibly unaligned OOB region with actual length */
--	memcpy(data + bytes, ecc->eccdata, len);
--timeout:
--
--	dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
--	mtk_ecc_disable(ecc);
--
--	return ret;
--}
--EXPORT_SYMBOL(mtk_ecc_encode);
--
--void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
--{
--	const u8 *ecc_strength = ecc->caps->ecc_strength;
--	int i;
--
--	for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
--		if (*p <= ecc_strength[i]) {
--			if (!i)
--				*p = ecc_strength[i];
--			else if (*p != ecc_strength[i])
--				*p = ecc_strength[i - 1];
--			return;
--		}
--	}
--
--	*p = ecc_strength[ecc->caps->num_ecc_strength - 1];
--}
--EXPORT_SYMBOL(mtk_ecc_adjust_strength);
--
--unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
--{
--	return ecc->caps->parity_bits;
--}
--EXPORT_SYMBOL(mtk_ecc_get_parity_bits);
--
--static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
--	.err_mask = 0x3f,
--	.err_shift = 8,
--	.ecc_strength = ecc_strength_mt2701,
--	.ecc_regs = mt2701_ecc_regs,
--	.num_ecc_strength = 20,
--	.ecc_mode_shift = 5,
--	.parity_bits = 14,
--	.pg_irq_sel = 0,
--};
--
--static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
--	.err_mask = 0x7f,
--	.err_shift = 8,
--	.ecc_strength = ecc_strength_mt2712,
--	.ecc_regs = mt2712_ecc_regs,
--	.num_ecc_strength = 23,
--	.ecc_mode_shift = 5,
--	.parity_bits = 14,
--	.pg_irq_sel = 1,
--};
--
--static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
--	.err_mask = 0x1f,
--	.err_shift = 5,
--	.ecc_strength = ecc_strength_mt7622,
--	.ecc_regs = mt7622_ecc_regs,
--	.num_ecc_strength = 5,
--	.ecc_mode_shift = 4,
--	.parity_bits = 13,
--	.pg_irq_sel = 0,
--};
--
--static const struct of_device_id mtk_ecc_dt_match[] = {
--	{
--		.compatible = "mediatek,mt2701-ecc",
--		.data = &mtk_ecc_caps_mt2701,
--	}, {
--		.compatible = "mediatek,mt2712-ecc",
--		.data = &mtk_ecc_caps_mt2712,
--	}, {
--		.compatible = "mediatek,mt7622-ecc",
--		.data = &mtk_ecc_caps_mt7622,
--	},
--	{},
--};
--
--static int mtk_ecc_probe(struct platform_device *pdev)
--{
--	struct device *dev = &pdev->dev;
--	struct mtk_ecc *ecc;
--	struct resource *res;
--	u32 max_eccdata_size;
--	int irq, ret;
--
--	ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
--	if (!ecc)
--		return -ENOMEM;
--
--	ecc->caps = of_device_get_match_data(dev);
--
--	max_eccdata_size = ecc->caps->num_ecc_strength - 1;
--	max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
--	max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
--	max_eccdata_size = round_up(max_eccdata_size, 4);
--	ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
--	if (!ecc->eccdata)
--		return -ENOMEM;
--
--	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--	ecc->regs = devm_ioremap_resource(dev, res);
--	if (IS_ERR(ecc->regs))
--		return PTR_ERR(ecc->regs);
--
--	ecc->clk = devm_clk_get(dev, NULL);
--	if (IS_ERR(ecc->clk)) {
--		dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
--		return PTR_ERR(ecc->clk);
--	}
--
--	irq = platform_get_irq(pdev, 0);
--	if (irq < 0)
--		return irq;
--
--	ret = dma_set_mask(dev, DMA_BIT_MASK(32));
--	if (ret) {
--		dev_err(dev, "failed to set DMA mask\n");
--		return ret;
--	}
--
--	ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
--	if (ret) {
--		dev_err(dev, "failed to request irq\n");
--		return -EINVAL;
--	}
--
--	ecc->dev = dev;
--	mutex_init(&ecc->lock);
--	platform_set_drvdata(pdev, ecc);
--	dev_info(dev, "probed\n");
--
--	return 0;
--}
--
--#ifdef CONFIG_PM_SLEEP
--static int mtk_ecc_suspend(struct device *dev)
--{
--	struct mtk_ecc *ecc = dev_get_drvdata(dev);
--
--	clk_disable_unprepare(ecc->clk);
--
--	return 0;
--}
--
--static int mtk_ecc_resume(struct device *dev)
--{
--	struct mtk_ecc *ecc = dev_get_drvdata(dev);
--	int ret;
--
--	ret = clk_prepare_enable(ecc->clk);
--	if (ret) {
--		dev_err(dev, "failed to enable clk\n");
--		return ret;
--	}
--
--	return 0;
--}
--
--static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);
--#endif
--
--MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);
--
--static struct platform_driver mtk_ecc_driver = {
--	.probe  = mtk_ecc_probe,
--	.driver = {
--		.name  = "mtk-ecc",
--		.of_match_table = of_match_ptr(mtk_ecc_dt_match),
--#ifdef CONFIG_PM_SLEEP
--		.pm = &mtk_ecc_pm_ops,
--#endif
--	},
--};
--
--module_platform_driver(mtk_ecc_driver);
--
--MODULE_AUTHOR("Xiaolei Li <[email protected]>");
--MODULE_DESCRIPTION("MTK Nand ECC Driver");
--MODULE_LICENSE("Dual MIT/GPL");
---- /dev/null
-+++ b/drivers/mtd/nand/ecc-mtk.c
-@@ -0,0 +1,598 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/*
-+ * MTK ECC controller driver.
-+ * Copyright (C) 2016  MediaTek Inc.
-+ * Authors:	Xiaolei Li		<[email protected]>
-+ *		Jorge Ramirez-Ortiz	<[email protected]>
-+ */
-+
-+#include <linux/platform_device.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/interrupt.h>
-+#include <linux/clk.h>
-+#include <linux/module.h>
-+#include <linux/iopoll.h>
-+#include <linux/of.h>
-+#include <linux/of_platform.h>
-+#include <linux/mutex.h>
-+#include <linux/mtd/nand-ecc-mtk.h>
-+
-+#define ECC_IDLE_MASK		BIT(0)
-+#define ECC_IRQ_EN		BIT(0)
-+#define ECC_PG_IRQ_SEL		BIT(1)
-+#define ECC_OP_ENABLE		(1)
-+#define ECC_OP_DISABLE		(0)
-+
-+#define ECC_ENCCON		(0x00)
-+#define ECC_ENCCNFG		(0x04)
-+#define		ECC_MS_SHIFT		(16)
-+#define ECC_ENCDIADDR		(0x08)
-+#define ECC_ENCIDLE		(0x0C)
-+#define ECC_DECCON		(0x100)
-+#define ECC_DECCNFG		(0x104)
-+#define		DEC_EMPTY_EN		BIT(31)
-+#define		DEC_CNFG_CORRECT	(0x3 << 12)
-+#define ECC_DECIDLE		(0x10C)
-+#define ECC_DECENUM0		(0x114)
-+
-+#define ECC_TIMEOUT		(500000)
-+
-+#define ECC_IDLE_REG(op)	((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
-+#define ECC_CTL_REG(op)		((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
-+
-+struct mtk_ecc_caps {
-+	u32 err_mask;
-+	u32 err_shift;
-+	const u8 *ecc_strength;
-+	const u32 *ecc_regs;
-+	u8 num_ecc_strength;
-+	u8 ecc_mode_shift;
-+	u32 parity_bits;
-+	int pg_irq_sel;
-+};
-+
-+struct mtk_ecc {
-+	struct device *dev;
-+	const struct mtk_ecc_caps *caps;
-+	void __iomem *regs;
-+	struct clk *clk;
-+
-+	struct completion done;
-+	struct mutex lock;
-+	u32 sectors;
-+
-+	u8 *eccdata;
-+};
-+
-+/* ecc strength that each IP supports */
-+static const u8 ecc_strength_mt2701[] = {
-+	4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
-+	40, 44, 48, 52, 56, 60
-+};
-+
-+static const u8 ecc_strength_mt2712[] = {
-+	4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
-+	40, 44, 48, 52, 56, 60, 68, 72, 80
-+};
-+
-+static const u8 ecc_strength_mt7622[] = {
-+	4, 6, 8, 10, 12
-+};
-+
-+enum mtk_ecc_regs {
-+	ECC_ENCPAR00,
-+	ECC_ENCIRQ_EN,
-+	ECC_ENCIRQ_STA,
-+	ECC_DECDONE,
-+	ECC_DECIRQ_EN,
-+	ECC_DECIRQ_STA,
-+};
-+
-+static int mt2701_ecc_regs[] = {
-+	[ECC_ENCPAR00] =        0x10,
-+	[ECC_ENCIRQ_EN] =       0x80,
-+	[ECC_ENCIRQ_STA] =      0x84,
-+	[ECC_DECDONE] =         0x124,
-+	[ECC_DECIRQ_EN] =       0x200,
-+	[ECC_DECIRQ_STA] =      0x204,
-+};
-+
-+static int mt2712_ecc_regs[] = {
-+	[ECC_ENCPAR00] =        0x300,
-+	[ECC_ENCIRQ_EN] =       0x80,
-+	[ECC_ENCIRQ_STA] =      0x84,
-+	[ECC_DECDONE] =         0x124,
-+	[ECC_DECIRQ_EN] =       0x200,
-+	[ECC_DECIRQ_STA] =      0x204,
-+};
-+
-+static int mt7622_ecc_regs[] = {
-+	[ECC_ENCPAR00] =        0x10,
-+	[ECC_ENCIRQ_EN] =       0x30,
-+	[ECC_ENCIRQ_STA] =      0x34,
-+	[ECC_DECDONE] =         0x11c,
-+	[ECC_DECIRQ_EN] =       0x140,
-+	[ECC_DECIRQ_STA] =      0x144,
-+};
-+
-+static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
-+				     enum mtk_ecc_operation op)
-+{
-+	struct device *dev = ecc->dev;
-+	u32 val;
-+	int ret;
-+
-+	ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,
-+					val & ECC_IDLE_MASK,
-+					10, ECC_TIMEOUT);
-+	if (ret)
-+		dev_warn(dev, "%s NOT idle\n",
-+			 op == ECC_ENCODE ? "encoder" : "decoder");
-+}
-+
-+static irqreturn_t mtk_ecc_irq(int irq, void *id)
-+{
-+	struct mtk_ecc *ecc = id;
-+	u32 dec, enc;
-+
-+	dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
-+		    & ECC_IRQ_EN;
-+	if (dec) {
-+		dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
-+		if (dec & ecc->sectors) {
-+			/*
-+			 * Clear decode IRQ status once again to ensure that
-+			 * there will be no extra IRQ.
-+			 */
-+			readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
-+			ecc->sectors = 0;
-+			complete(&ecc->done);
-+		} else {
-+			return IRQ_HANDLED;
-+		}
-+	} else {
-+		enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
-+		      & ECC_IRQ_EN;
-+		if (enc)
-+			complete(&ecc->done);
-+		else
-+			return IRQ_NONE;
-+	}
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
-+{
-+	u32 ecc_bit, dec_sz, enc_sz;
-+	u32 reg, i;
-+
-+	for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
-+		if (ecc->caps->ecc_strength[i] == config->strength)
-+			break;
-+	}
-+
-+	if (i == ecc->caps->num_ecc_strength) {
-+		dev_err(ecc->dev, "invalid ecc strength %d\n",
-+			config->strength);
-+		return -EINVAL;
-+	}
-+
-+	ecc_bit = i;
-+
-+	if (config->op == ECC_ENCODE) {
-+		/* configure ECC encoder (in bits) */
-+		enc_sz = config->len << 3;
-+
-+		reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
-+		reg |= (enc_sz << ECC_MS_SHIFT);
-+		writel(reg, ecc->regs + ECC_ENCCNFG);
-+
-+		if (config->mode != ECC_NFI_MODE)
-+			writel(lower_32_bits(config->addr),
-+			       ecc->regs + ECC_ENCDIADDR);
-+
-+	} else {
-+		/* configure ECC decoder (in bits) */
-+		dec_sz = (config->len << 3) +
-+			 config->strength * ecc->caps->parity_bits;
-+
-+		reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
-+		reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
-+		reg |= DEC_EMPTY_EN;
-+		writel(reg, ecc->regs + ECC_DECCNFG);
-+
-+		if (config->sectors)
-+			ecc->sectors = 1 << (config->sectors - 1);
-+	}
-+
-+	return 0;
-+}
-+
-+void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
-+		       int sectors)
-+{
-+	u32 offset, i, err;
-+	u32 bitflips = 0;
-+
-+	stats->corrected = 0;
-+	stats->failed = 0;
-+
-+	for (i = 0; i < sectors; i++) {
-+		offset = (i >> 2) << 2;
-+		err = readl(ecc->regs + ECC_DECENUM0 + offset);
-+		err = err >> ((i % 4) * ecc->caps->err_shift);
-+		err &= ecc->caps->err_mask;
-+		if (err == ecc->caps->err_mask) {
-+			/* uncorrectable errors */
-+			stats->failed++;
-+			continue;
-+		}
-+
-+		stats->corrected += err;
-+		bitflips = max_t(u32, bitflips, err);
-+	}
-+
-+	stats->bitflips = bitflips;
-+}
-+EXPORT_SYMBOL(mtk_ecc_get_stats);
-+
-+void mtk_ecc_release(struct mtk_ecc *ecc)
-+{
-+	clk_disable_unprepare(ecc->clk);
-+	put_device(ecc->dev);
-+}
-+EXPORT_SYMBOL(mtk_ecc_release);
-+
-+static void mtk_ecc_hw_init(struct mtk_ecc *ecc)
-+{
-+	mtk_ecc_wait_idle(ecc, ECC_ENCODE);
-+	writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
-+
-+	mtk_ecc_wait_idle(ecc, ECC_DECODE);
-+	writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
-+}
-+
-+static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
-+{
-+	struct platform_device *pdev;
-+	struct mtk_ecc *ecc;
-+
-+	pdev = of_find_device_by_node(np);
-+	if (!pdev)
-+		return ERR_PTR(-EPROBE_DEFER);
-+
-+	ecc = platform_get_drvdata(pdev);
-+	if (!ecc) {
-+		put_device(&pdev->dev);
-+		return ERR_PTR(-EPROBE_DEFER);
-+	}
-+
-+	clk_prepare_enable(ecc->clk);
-+	mtk_ecc_hw_init(ecc);
-+
-+	return ecc;
-+}
-+
-+struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)
-+{
-+	struct mtk_ecc *ecc = NULL;
-+	struct device_node *np;
-+
-+	np = of_parse_phandle(of_node, "ecc-engine", 0);
-+	if (np) {
-+		ecc = mtk_ecc_get(np);
-+		of_node_put(np);
-+	}
-+
-+	return ecc;
-+}
-+EXPORT_SYMBOL(of_mtk_ecc_get);
-+
-+int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
-+{
-+	enum mtk_ecc_operation op = config->op;
-+	u16 reg_val;
-+	int ret;
-+
-+	ret = mutex_lock_interruptible(&ecc->lock);
-+	if (ret) {
-+		dev_err(ecc->dev, "interrupted when attempting to lock\n");
-+		return ret;
-+	}
-+
-+	mtk_ecc_wait_idle(ecc, op);
-+
-+	ret = mtk_ecc_config(ecc, config);
-+	if (ret) {
-+		mutex_unlock(&ecc->lock);
-+		return ret;
-+	}
-+
-+	if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) {
-+		init_completion(&ecc->done);
-+		reg_val = ECC_IRQ_EN;
-+		/*
-+		 * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it
-+		 * means this chip can only generate one ecc irq during page
-+		 * read / write. If is 0, generate one ecc irq each ecc step.
-+		 */
-+		if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
-+			reg_val |= ECC_PG_IRQ_SEL;
-+		if (op == ECC_ENCODE)
-+			writew(reg_val, ecc->regs +
-+			       ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
-+		else
-+			writew(reg_val, ecc->regs +
-+			       ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
-+	}
-+
-+	writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(mtk_ecc_enable);
-+
-+void mtk_ecc_disable(struct mtk_ecc *ecc)
-+{
-+	enum mtk_ecc_operation op = ECC_ENCODE;
-+
-+	/* find out the running operation */
-+	if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
-+		op = ECC_DECODE;
-+
-+	/* disable it */
-+	mtk_ecc_wait_idle(ecc, op);
-+	if (op == ECC_DECODE) {
-+		/*
-+		 * Clear decode IRQ status in case there is a timeout to wait
-+		 * decode IRQ.
-+		 */
-+		readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
-+		writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
-+	} else {
-+		writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
-+	}
-+
-+	writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
-+
-+	mutex_unlock(&ecc->lock);
-+}
-+EXPORT_SYMBOL(mtk_ecc_disable);
-+
-+int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)
-+{
-+	int ret;
-+
-+	ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
-+	if (!ret) {
-+		dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
-+			(op == ECC_ENCODE) ? "encoder" : "decoder");
-+		return -ETIMEDOUT;
-+	}
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(mtk_ecc_wait_done);
-+
-+int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
-+		   u8 *data, u32 bytes)
-+{
-+	dma_addr_t addr;
-+	u32 len;
-+	int ret;
-+
-+	addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
-+	ret = dma_mapping_error(ecc->dev, addr);
-+	if (ret) {
-+		dev_err(ecc->dev, "dma mapping error\n");
-+		return -EINVAL;
-+	}
-+
-+	config->op = ECC_ENCODE;
-+	config->addr = addr;
-+	ret = mtk_ecc_enable(ecc, config);
-+	if (ret) {
-+		dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
-+		return ret;
-+	}
-+
-+	ret = mtk_ecc_wait_done(ecc, ECC_ENCODE);
-+	if (ret)
-+		goto timeout;
-+
-+	mtk_ecc_wait_idle(ecc, ECC_ENCODE);
-+
-+	/* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
-+	len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
-+
-+	/* write the parity bytes generated by the ECC back to temp buffer */
-+	__ioread32_copy(ecc->eccdata,
-+			ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
-+			round_up(len, 4));
-+
-+	/* copy into possibly unaligned OOB region with actual length */
-+	memcpy(data + bytes, ecc->eccdata, len);
-+timeout:
-+
-+	dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
-+	mtk_ecc_disable(ecc);
-+
-+	return ret;
-+}
-+EXPORT_SYMBOL(mtk_ecc_encode);
-+
-+void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
-+{
-+	const u8 *ecc_strength = ecc->caps->ecc_strength;
-+	int i;
-+
-+	for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
-+		if (*p <= ecc_strength[i]) {
-+			if (!i)
-+				*p = ecc_strength[i];
-+			else if (*p != ecc_strength[i])
-+				*p = ecc_strength[i - 1];
-+			return;
-+		}
-+	}
-+
-+	*p = ecc_strength[ecc->caps->num_ecc_strength - 1];
-+}
-+EXPORT_SYMBOL(mtk_ecc_adjust_strength);
-+
-+unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
-+{
-+	return ecc->caps->parity_bits;
-+}
-+EXPORT_SYMBOL(mtk_ecc_get_parity_bits);
-+
-+static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
-+	.err_mask = 0x3f,
-+	.err_shift = 8,
-+	.ecc_strength = ecc_strength_mt2701,
-+	.ecc_regs = mt2701_ecc_regs,
-+	.num_ecc_strength = 20,
-+	.ecc_mode_shift = 5,
-+	.parity_bits = 14,
-+	.pg_irq_sel = 0,
-+};
-+
-+static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
-+	.err_mask = 0x7f,
-+	.err_shift = 8,
-+	.ecc_strength = ecc_strength_mt2712,
-+	.ecc_regs = mt2712_ecc_regs,
-+	.num_ecc_strength = 23,
-+	.ecc_mode_shift = 5,
-+	.parity_bits = 14,
-+	.pg_irq_sel = 1,
-+};
-+
-+static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
-+	.err_mask = 0x1f,
-+	.err_shift = 5,
-+	.ecc_strength = ecc_strength_mt7622,
-+	.ecc_regs = mt7622_ecc_regs,
-+	.num_ecc_strength = 5,
-+	.ecc_mode_shift = 4,
-+	.parity_bits = 13,
-+	.pg_irq_sel = 0,
-+};
-+
-+static const struct of_device_id mtk_ecc_dt_match[] = {
-+	{
-+		.compatible = "mediatek,mt2701-ecc",
-+		.data = &mtk_ecc_caps_mt2701,
-+	}, {
-+		.compatible = "mediatek,mt2712-ecc",
-+		.data = &mtk_ecc_caps_mt2712,
-+	}, {
-+		.compatible = "mediatek,mt7622-ecc",
-+		.data = &mtk_ecc_caps_mt7622,
-+	},
-+	{},
-+};
-+
-+static int mtk_ecc_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct mtk_ecc *ecc;
-+	struct resource *res;
-+	u32 max_eccdata_size;
-+	int irq, ret;
-+
-+	ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
-+	if (!ecc)
-+		return -ENOMEM;
-+
-+	ecc->caps = of_device_get_match_data(dev);
-+
-+	max_eccdata_size = ecc->caps->num_ecc_strength - 1;
-+	max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
-+	max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
-+	max_eccdata_size = round_up(max_eccdata_size, 4);
-+	ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
-+	if (!ecc->eccdata)
-+		return -ENOMEM;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	ecc->regs = devm_ioremap_resource(dev, res);
-+	if (IS_ERR(ecc->regs))
-+		return PTR_ERR(ecc->regs);
-+
-+	ecc->clk = devm_clk_get(dev, NULL);
-+	if (IS_ERR(ecc->clk)) {
-+		dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
-+		return PTR_ERR(ecc->clk);
-+	}
-+
-+	irq = platform_get_irq(pdev, 0);
-+	if (irq < 0)
-+		return irq;
-+
-+	ret = dma_set_mask(dev, DMA_BIT_MASK(32));
-+	if (ret) {
-+		dev_err(dev, "failed to set DMA mask\n");
-+		return ret;
-+	}
-+
-+	ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
-+	if (ret) {
-+		dev_err(dev, "failed to request irq\n");
-+		return -EINVAL;
-+	}
-+
-+	ecc->dev = dev;
-+	mutex_init(&ecc->lock);
-+	platform_set_drvdata(pdev, ecc);
-+	dev_info(dev, "probed\n");
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_PM_SLEEP
-+static int mtk_ecc_suspend(struct device *dev)
-+{
-+	struct mtk_ecc *ecc = dev_get_drvdata(dev);
-+
-+	clk_disable_unprepare(ecc->clk);
-+
-+	return 0;
-+}
-+
-+static int mtk_ecc_resume(struct device *dev)
-+{
-+	struct mtk_ecc *ecc = dev_get_drvdata(dev);
-+	int ret;
-+
-+	ret = clk_prepare_enable(ecc->clk);
-+	if (ret) {
-+		dev_err(dev, "failed to enable clk\n");
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);
-+#endif
-+
-+MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);
-+
-+static struct platform_driver mtk_ecc_driver = {
-+	.probe  = mtk_ecc_probe,
-+	.driver = {
-+		.name  = "mtk-ecc",
-+		.of_match_table = of_match_ptr(mtk_ecc_dt_match),
-+#ifdef CONFIG_PM_SLEEP
-+		.pm = &mtk_ecc_pm_ops,
-+#endif
-+	},
-+};
-+
-+module_platform_driver(mtk_ecc_driver);
-+
-+MODULE_AUTHOR("Xiaolei Li <[email protected]>");
-+MODULE_DESCRIPTION("MTK Nand ECC Driver");
-+MODULE_LICENSE("Dual MIT/GPL");
---- a/drivers/mtd/nand/raw/Kconfig
-+++ b/drivers/mtd/nand/raw/Kconfig
-@@ -360,6 +360,7 @@ config MTD_NAND_QCOM
- 
- config MTD_NAND_MTK
- 	tristate "MTK NAND controller"
-+	depends on MTD_NAND_ECC_MEDIATEK
- 	depends on ARCH_MEDIATEK || COMPILE_TEST
- 	depends on HAS_IOMEM
- 	help
---- a/drivers/mtd/nand/raw/Makefile
-+++ b/drivers/mtd/nand/raw/Makefile
-@@ -48,7 +48,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI)		+= sunxi_n
- obj-$(CONFIG_MTD_NAND_HISI504)	        += hisi504_nand.o
- obj-$(CONFIG_MTD_NAND_BRCMNAND)		+= brcmnand/
- obj-$(CONFIG_MTD_NAND_QCOM)		+= qcom_nandc.o
--obj-$(CONFIG_MTD_NAND_MTK)		+= mtk_ecc.o mtk_nand.o
-+obj-$(CONFIG_MTD_NAND_MTK)		+= mtk_nand.o
- obj-$(CONFIG_MTD_NAND_MXIC)		+= mxic_nand.o
- obj-$(CONFIG_MTD_NAND_TEGRA)		+= tegra_nand.o
- obj-$(CONFIG_MTD_NAND_STM32_FMC2)	+= stm32_fmc2_nand.o
---- a/drivers/mtd/nand/raw/mtk_nand.c
-+++ b/drivers/mtd/nand/raw/mtk_nand.c
-@@ -17,7 +17,7 @@
- #include <linux/iopoll.h>
- #include <linux/of.h>
- #include <linux/of_device.h>
--#include "mtk_ecc.h"
-+#include <linux/mtd/nand-ecc-mtk.h>
- 
- /* NAND controller register definition */
- #define NFI_CNFG		(0x00)
---- a/drivers/mtd/nand/raw/mtk_ecc.h
-+++ /dev/null
-@@ -1,47 +0,0 @@
--/* SPDX-License-Identifier: GPL-2.0 OR MIT */
--/*
-- * MTK SDG1 ECC controller
-- *
-- * Copyright (c) 2016 Mediatek
-- * Authors:	Xiaolei Li		<[email protected]>
-- *		Jorge Ramirez-Ortiz	<[email protected]>
-- */
--
--#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__
--#define __DRIVERS_MTD_NAND_MTK_ECC_H__
--
--#include <linux/types.h>
--
--enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1};
--enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE};
--
--struct device_node;
--struct mtk_ecc;
--
--struct mtk_ecc_stats {
--	u32 corrected;
--	u32 bitflips;
--	u32 failed;
--};
--
--struct mtk_ecc_config {
--	enum mtk_ecc_operation op;
--	enum mtk_ecc_mode mode;
--	dma_addr_t addr;
--	u32 strength;
--	u32 sectors;
--	u32 len;
--};
--
--int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32);
--void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int);
--int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation);
--int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);
--void mtk_ecc_disable(struct mtk_ecc *);
--void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p);
--unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc);
--
--struct mtk_ecc *of_mtk_ecc_get(struct device_node *);
--void mtk_ecc_release(struct mtk_ecc *);
--
--#endif
---- /dev/null
-+++ b/include/linux/mtd/nand-ecc-mtk.h
-@@ -0,0 +1,47 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/*
-+ * MTK SDG1 ECC controller
-+ *
-+ * Copyright (c) 2016 Mediatek
-+ * Authors:	Xiaolei Li		<[email protected]>
-+ *		Jorge Ramirez-Ortiz	<[email protected]>
-+ */
-+
-+#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__
-+#define __DRIVERS_MTD_NAND_MTK_ECC_H__
-+
-+#include <linux/types.h>
-+
-+enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1};
-+enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE};
-+
-+struct device_node;
-+struct mtk_ecc;
-+
-+struct mtk_ecc_stats {
-+	u32 corrected;
-+	u32 bitflips;
-+	u32 failed;
-+};
-+
-+struct mtk_ecc_config {
-+	enum mtk_ecc_operation op;
-+	enum mtk_ecc_mode mode;
-+	dma_addr_t addr;
-+	u32 strength;
-+	u32 sectors;
-+	u32 len;
-+};
-+
-+int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32);
-+void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int);
-+int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation);
-+int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);
-+void mtk_ecc_disable(struct mtk_ecc *);
-+void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p);
-+unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc);
-+
-+struct mtk_ecc *of_mtk_ecc_get(struct device_node *);
-+void mtk_ecc_release(struct mtk_ecc *);
-+
-+#endif

target/linux/mediatek/patches-6.1/120-12-v5.19-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch

@@ -1,1537 +0,0 @@
-From 8170bafa8936e9fbfdce992932a63bd20eca3bc3 Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <[email protected]>
-Date: Sat, 2 Apr 2022 10:16:11 +0800
-Subject: [PATCH v6 2/5] spi: add driver for MTK SPI NAND Flash Interface
-
-This driver implements support for the SPI-NAND mode of MTK NAND Flash
-Interface as a SPI-MEM controller with pipelined ECC capability.
-
-Signed-off-by: Chuanhong Guo <[email protected]>
-Tested-by: Daniel Golle <[email protected]>
----
-Change since v1:
-  fix CI warnings
-
-Changes since v2:
- use streamed DMA api to avoid an extra memory copy during read
- make ECC engine config a per-nand context
- take user-requested ECC strength into account
-
-Change since v3: none
-Changes since v4:
- fix missing OOB write
- print page format with dev_dbg
- replace uint*_t copied from vendor driver with u*
-
-Changes since v5:
- add missing nfi mode register configuration in probe
- fix an off-by-one bug in mtk_snand_mac_io
-
- drivers/spi/Kconfig        |   10 +
- drivers/spi/Makefile       |    1 +
- drivers/spi/spi-mtk-snfi.c | 1470 ++++++++++++++++++++++++++++++++++++
- 3 files changed, 1481 insertions(+)
- create mode 100644 drivers/spi/spi-mtk-snfi.c
-
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -529,6 +529,16 @@ config SPI_MTK_NOR
- 	  SPI interface as well as several SPI NOR specific instructions
- 	  via SPI MEM interface.
- 
-+config SPI_MTK_SNFI
-+	tristate "MediaTek SPI NAND Flash Interface"
-+	depends on ARCH_MEDIATEK || COMPILE_TEST
-+	depends on MTD_NAND_ECC_MEDIATEK
-+	help
-+	  This enables support for SPI-NAND mode on the MediaTek NAND
-+	  Flash Interface found on MediaTek ARM SoCs. This controller
-+	  is implemented as a SPI-MEM controller with pipelined ECC
-+	  capcability.
-+
- config SPI_NPCM_FIU
- 	tristate "Nuvoton NPCM FLASH Interface Unit"
- 	depends on ARCH_NPCM || COMPILE_TEST
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -71,6 +71,7 @@ obj-$(CONFIG_SPI_MPC52xx)		+= spi-mpc52x
- obj-$(CONFIG_SPI_MT65XX)                += spi-mt65xx.o
- obj-$(CONFIG_SPI_MT7621)		+= spi-mt7621.o
- obj-$(CONFIG_SPI_MTK_NOR)		+= spi-mtk-nor.o
-+obj-$(CONFIG_SPI_MTK_SNFI)		+= spi-mtk-snfi.o
- obj-$(CONFIG_SPI_MXIC)			+= spi-mxic.o
- obj-$(CONFIG_SPI_MXS)			+= spi-mxs.o
- obj-$(CONFIG_SPI_NPCM_FIU)		+= spi-npcm-fiu.o
---- /dev/null
-+++ b/drivers/spi/spi-mtk-snfi.c
-@@ -0,0 +1,1470 @@
-+// SPDX-License-Identifier: GPL-2.0
-+//
-+// Driver for the SPI-NAND mode of Mediatek NAND Flash Interface
-+//
-+// Copyright (c) 2022 Chuanhong Guo <[email protected]>
-+//
-+// This driver is based on the SPI-NAND mtd driver from Mediatek SDK:
-+//
-+// Copyright (C) 2020 MediaTek Inc.
-+// Author: Weijie Gao <[email protected]>
-+//
-+// This controller organize the page data as several interleaved sectors
-+// like the following: (sizeof(FDM + ECC) = snf->nfi_cfg.spare_size)
-+// +---------+------+------+---------+------+------+-----+
-+// | Sector1 | FDM1 | ECC1 | Sector2 | FDM2 | ECC2 | ... |
-+// +---------+------+------+---------+------+------+-----+
-+// With auto-format turned on, DMA only returns this part:
-+// +---------+---------+-----+
-+// | Sector1 | Sector2 | ... |
-+// +---------+---------+-----+
-+// The FDM data will be filled to the registers, and ECC parity data isn't
-+// accessible.
-+// With auto-format off, all ((Sector+FDM+ECC)*nsectors) will be read over DMA
-+// in it's original order shown in the first table. ECC can't be turned on when
-+// auto-format is off.
-+//
-+// However, Linux SPI-NAND driver expects the data returned as:
-+// +------+-----+
-+// | Page | OOB |
-+// +------+-----+
-+// where the page data is continuously stored instead of interleaved.
-+// So we assume all instructions matching the page_op template between ECC
-+// prepare_io_req and finish_io_req are for page cache r/w.
-+// Here's how this spi-mem driver operates when reading:
-+//  1. Always set snf->autofmt = true in prepare_io_req (even when ECC is off).
-+//  2. Perform page ops and let the controller fill the DMA bounce buffer with
-+//     de-interleaved sector data and set FDM registers.
-+//  3. Return the data as:
-+//     +---------+---------+-----+------+------+-----+
-+//     | Sector1 | Sector2 | ... | FDM1 | FDM2 | ... |
-+//     +---------+---------+-----+------+------+-----+
-+//  4. For other matching spi_mem ops outside a prepare/finish_io_req pair,
-+//     read the data with auto-format off into the bounce buffer and copy
-+//     needed data to the buffer specified in the request.
-+//
-+// Write requests operates in a similar manner.
-+// As a limitation of this strategy, we won't be able to access any ECC parity
-+// data at all in Linux.
-+//
-+// Here's the bad block mark situation on MTK chips:
-+// In older chips like mt7622, MTK uses the first FDM byte in the first sector
-+// as the bad block mark. After de-interleaving, this byte appears at [pagesize]
-+// in the returned data, which is the BBM position expected by kernel. However,
-+// the conventional bad block mark is the first byte of the OOB, which is part
-+// of the last sector data in the interleaved layout. Instead of fixing their
-+// hardware, MTK decided to address this inconsistency in software. On these
-+// later chips, the BootROM expects the following:
-+// 1. The [pagesize] byte on a nand page is used as BBM, which will appear at
-+//    (page_size - (nsectors - 1) * spare_size) in the DMA buffer.
-+// 2. The original byte stored at that position in the DMA buffer will be stored
-+//    as the first byte of the FDM section in the last sector.
-+// We can't disagree with the BootROM, so after de-interleaving, we need to
-+// perform the following swaps in read:
-+// 1. Store the BBM at [page_size - (nsectors - 1) * spare_size] to [page_size],
-+//    which is the expected BBM position by kernel.
-+// 2. Store the page data byte at [pagesize + (nsectors-1) * fdm] back to
-+//    [page_size - (nsectors - 1) * spare_size]
-+// Similarly, when writing, we need to perform swaps in the other direction.
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/mutex.h>
-+#include <linux/clk.h>
-+#include <linux/interrupt.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/iopoll.h>
-+#include <linux/of_platform.h>
-+#include <linux/mtd/nand-ecc-mtk.h>
-+#include <linux/spi/spi.h>
-+#include <linux/spi/spi-mem.h>
-+#include <linux/mtd/nand.h>
-+
-+// NFI registers
-+#define NFI_CNFG 0x000
-+#define CNFG_OP_MODE_S 12
-+#define CNFG_OP_MODE_CUST 6
-+#define CNFG_OP_MODE_PROGRAM 3
-+#define CNFG_AUTO_FMT_EN BIT(9)
-+#define CNFG_HW_ECC_EN BIT(8)
-+#define CNFG_DMA_BURST_EN BIT(2)
-+#define CNFG_READ_MODE BIT(1)
-+#define CNFG_DMA_MODE BIT(0)
-+
-+#define NFI_PAGEFMT 0x0004
-+#define NFI_SPARE_SIZE_LS_S 16
-+#define NFI_FDM_ECC_NUM_S 12
-+#define NFI_FDM_NUM_S 8
-+#define NFI_SPARE_SIZE_S 4
-+#define NFI_SEC_SEL_512 BIT(2)
-+#define NFI_PAGE_SIZE_S 0
-+#define NFI_PAGE_SIZE_512_2K 0
-+#define NFI_PAGE_SIZE_2K_4K 1
-+#define NFI_PAGE_SIZE_4K_8K 2
-+#define NFI_PAGE_SIZE_8K_16K 3
-+
-+#define NFI_CON 0x008
-+#define CON_SEC_NUM_S 12
-+#define CON_BWR BIT(9)
-+#define CON_BRD BIT(8)
-+#define CON_NFI_RST BIT(1)
-+#define CON_FIFO_FLUSH BIT(0)
-+
-+#define NFI_INTR_EN 0x010
-+#define NFI_INTR_STA 0x014
-+#define NFI_IRQ_INTR_EN BIT(31)
-+#define NFI_IRQ_CUS_READ BIT(8)
-+#define NFI_IRQ_CUS_PG BIT(7)
-+
-+#define NFI_CMD 0x020
-+#define NFI_CMD_DUMMY_READ 0x00
-+#define NFI_CMD_DUMMY_WRITE 0x80
-+
-+#define NFI_STRDATA 0x040
-+#define STR_DATA BIT(0)
-+
-+#define NFI_STA 0x060
-+#define NFI_NAND_FSM GENMASK(28, 24)
-+#define NFI_FSM GENMASK(19, 16)
-+#define READ_EMPTY BIT(12)
-+
-+#define NFI_FIFOSTA 0x064
-+#define FIFO_WR_REMAIN_S 8
-+#define FIFO_RD_REMAIN_S 0
-+
-+#define NFI_ADDRCNTR 0x070
-+#define SEC_CNTR GENMASK(16, 12)
-+#define SEC_CNTR_S 12
-+#define NFI_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S)
-+
-+#define NFI_STRADDR 0x080
-+
-+#define NFI_BYTELEN 0x084
-+#define BUS_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S)
-+
-+#define NFI_FDM0L 0x0a0
-+#define NFI_FDM0M 0x0a4
-+#define NFI_FDML(n) (NFI_FDM0L + (n)*8)
-+#define NFI_FDMM(n) (NFI_FDM0M + (n)*8)
-+
-+#define NFI_DEBUG_CON1 0x220
-+#define WBUF_EN BIT(2)
-+
-+#define NFI_MASTERSTA 0x224
-+#define MAS_ADDR GENMASK(11, 9)
-+#define MAS_RD GENMASK(8, 6)
-+#define MAS_WR GENMASK(5, 3)
-+#define MAS_RDDLY GENMASK(2, 0)
-+#define NFI_MASTERSTA_MASK_7622 (MAS_ADDR | MAS_RD | MAS_WR | MAS_RDDLY)
-+
-+// SNFI registers
-+#define SNF_MAC_CTL 0x500
-+#define MAC_XIO_SEL BIT(4)
-+#define SF_MAC_EN BIT(3)
-+#define SF_TRIG BIT(2)
-+#define WIP_READY BIT(1)
-+#define WIP BIT(0)
-+
-+#define SNF_MAC_OUTL 0x504
-+#define SNF_MAC_INL 0x508
-+
-+#define SNF_RD_CTL2 0x510
-+#define DATA_READ_DUMMY_S 8
-+#define DATA_READ_MAX_DUMMY 0xf
-+#define DATA_READ_CMD_S 0
-+
-+#define SNF_RD_CTL3 0x514
-+
-+#define SNF_PG_CTL1 0x524
-+#define PG_LOAD_CMD_S 8
-+
-+#define SNF_PG_CTL2 0x528
-+
-+#define SNF_MISC_CTL 0x538
-+#define SW_RST BIT(28)
-+#define FIFO_RD_LTC_S 25
-+#define PG_LOAD_X4_EN BIT(20)
-+#define DATA_READ_MODE_S 16
-+#define DATA_READ_MODE GENMASK(18, 16)
-+#define DATA_READ_MODE_X1 0
-+#define DATA_READ_MODE_X2 1
-+#define DATA_READ_MODE_X4 2
-+#define DATA_READ_MODE_DUAL 5
-+#define DATA_READ_MODE_QUAD 6
-+#define PG_LOAD_CUSTOM_EN BIT(7)
-+#define DATARD_CUSTOM_EN BIT(6)
-+#define CS_DESELECT_CYC_S 0
-+
-+#define SNF_MISC_CTL2 0x53c
-+#define PROGRAM_LOAD_BYTE_NUM_S 16
-+#define READ_DATA_BYTE_NUM_S 11
-+
-+#define SNF_DLY_CTL3 0x548
-+#define SFCK_SAM_DLY_S 0
-+
-+#define SNF_STA_CTL1 0x550
-+#define CUS_PG_DONE BIT(28)
-+#define CUS_READ_DONE BIT(27)
-+#define SPI_STATE_S 0
-+#define SPI_STATE GENMASK(3, 0)
-+
-+#define SNF_CFG 0x55c
-+#define SPI_MODE BIT(0)
-+
-+#define SNF_GPRAM 0x800
-+#define SNF_GPRAM_SIZE 0xa0
-+
-+#define SNFI_POLL_INTERVAL 1000000
-+
-+static const u8 mt7622_spare_sizes[] = { 16, 26, 27, 28 };
-+
-+struct mtk_snand_caps {
-+	u16 sector_size;
-+	u16 max_sectors;
-+	u16 fdm_size;
-+	u16 fdm_ecc_size;
-+	u16 fifo_size;
-+
-+	bool bbm_swap;
-+	bool empty_page_check;
-+	u32 mastersta_mask;
-+
-+	const u8 *spare_sizes;
-+	u32 num_spare_size;
-+};
-+
-+static const struct mtk_snand_caps mt7622_snand_caps = {
-+	.sector_size = 512,
-+	.max_sectors = 8,
-+	.fdm_size = 8,
-+	.fdm_ecc_size = 1,
-+	.fifo_size = 32,
-+	.bbm_swap = false,
-+	.empty_page_check = false,
-+	.mastersta_mask = NFI_MASTERSTA_MASK_7622,
-+	.spare_sizes = mt7622_spare_sizes,
-+	.num_spare_size = ARRAY_SIZE(mt7622_spare_sizes)
-+};
-+
-+static const struct mtk_snand_caps mt7629_snand_caps = {
-+	.sector_size = 512,
-+	.max_sectors = 8,
-+	.fdm_size = 8,
-+	.fdm_ecc_size = 1,
-+	.fifo_size = 32,
-+	.bbm_swap = true,
-+	.empty_page_check = false,
-+	.mastersta_mask = NFI_MASTERSTA_MASK_7622,
-+	.spare_sizes = mt7622_spare_sizes,
-+	.num_spare_size = ARRAY_SIZE(mt7622_spare_sizes)
-+};
-+
-+struct mtk_snand_conf {
-+	size_t page_size;
-+	size_t oob_size;
-+	u8 nsectors;
-+	u8 spare_size;
-+};
-+
-+struct mtk_snand {
-+	struct spi_controller *ctlr;
-+	struct device *dev;
-+	struct clk *nfi_clk;
-+	struct clk *pad_clk;
-+	void __iomem *nfi_base;
-+	int irq;
-+	struct completion op_done;
-+	const struct mtk_snand_caps *caps;
-+	struct mtk_ecc_config *ecc_cfg;
-+	struct mtk_ecc *ecc;
-+	struct mtk_snand_conf nfi_cfg;
-+	struct mtk_ecc_stats ecc_stats;
-+	struct nand_ecc_engine ecc_eng;
-+	bool autofmt;
-+	u8 *buf;
-+	size_t buf_len;
-+};
-+
-+static struct mtk_snand *nand_to_mtk_snand(struct nand_device *nand)
-+{
-+	struct nand_ecc_engine *eng = nand->ecc.engine;
-+
-+	return container_of(eng, struct mtk_snand, ecc_eng);
-+}
-+
-+static inline int snand_prepare_bouncebuf(struct mtk_snand *snf, size_t size)
-+{
-+	if (snf->buf_len >= size)
-+		return 0;
-+	kfree(snf->buf);
-+	snf->buf = kmalloc(size, GFP_KERNEL);
-+	if (!snf->buf)
-+		return -ENOMEM;
-+	snf->buf_len = size;
-+	memset(snf->buf, 0xff, snf->buf_len);
-+	return 0;
-+}
-+
-+static inline u32 nfi_read32(struct mtk_snand *snf, u32 reg)
-+{
-+	return readl(snf->nfi_base + reg);
-+}
-+
-+static inline void nfi_write32(struct mtk_snand *snf, u32 reg, u32 val)
-+{
-+	writel(val, snf->nfi_base + reg);
-+}
-+
-+static inline void nfi_write16(struct mtk_snand *snf, u32 reg, u16 val)
-+{
-+	writew(val, snf->nfi_base + reg);
-+}
-+
-+static inline void nfi_rmw32(struct mtk_snand *snf, u32 reg, u32 clr, u32 set)
-+{
-+	u32 val;
-+
-+	val = readl(snf->nfi_base + reg);
-+	val &= ~clr;
-+	val |= set;
-+	writel(val, snf->nfi_base + reg);
-+}
-+
-+static void nfi_read_data(struct mtk_snand *snf, u32 reg, u8 *data, u32 len)
-+{
-+	u32 i, val = 0, es = sizeof(u32);
-+
-+	for (i = reg; i < reg + len; i++) {
-+		if (i == reg || i % es == 0)
-+			val = nfi_read32(snf, i & ~(es - 1));
-+
-+		*data++ = (u8)(val >> (8 * (i % es)));
-+	}
-+}
-+
-+static int mtk_nfi_reset(struct mtk_snand *snf)
-+{
-+	u32 val, fifo_mask;
-+	int ret;
-+
-+	nfi_write32(snf, NFI_CON, CON_FIFO_FLUSH | CON_NFI_RST);
-+
-+	ret = readw_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val,
-+				 !(val & snf->caps->mastersta_mask), 0,
-+				 SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "NFI master is still busy after reset\n");
-+		return ret;
-+	}
-+
-+	ret = readl_poll_timeout(snf->nfi_base + NFI_STA, val,
-+				 !(val & (NFI_FSM | NFI_NAND_FSM)), 0,
-+				 SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "Failed to reset NFI\n");
-+		return ret;
-+	}
-+
-+	fifo_mask = ((snf->caps->fifo_size - 1) << FIFO_RD_REMAIN_S) |
-+		    ((snf->caps->fifo_size - 1) << FIFO_WR_REMAIN_S);
-+	ret = readw_poll_timeout(snf->nfi_base + NFI_FIFOSTA, val,
-+				 !(val & fifo_mask), 0, SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "NFI FIFOs are not empty\n");
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_snand_mac_reset(struct mtk_snand *snf)
-+{
-+	int ret;
-+	u32 val;
-+
-+	nfi_rmw32(snf, SNF_MISC_CTL, 0, SW_RST);
-+
-+	ret = readl_poll_timeout(snf->nfi_base + SNF_STA_CTL1, val,
-+				 !(val & SPI_STATE), 0, SNFI_POLL_INTERVAL);
-+	if (ret)
-+		dev_err(snf->dev, "Failed to reset SNFI MAC\n");
-+
-+	nfi_write32(snf, SNF_MISC_CTL,
-+		    (2 << FIFO_RD_LTC_S) | (10 << CS_DESELECT_CYC_S));
-+
-+	return ret;
-+}
-+
-+static int mtk_snand_mac_trigger(struct mtk_snand *snf, u32 outlen, u32 inlen)
-+{
-+	int ret;
-+	u32 val;
-+
-+	nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN);
-+	nfi_write32(snf, SNF_MAC_OUTL, outlen);
-+	nfi_write32(snf, SNF_MAC_INL, inlen);
-+
-+	nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN | SF_TRIG);
-+
-+	ret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val,
-+				 val & WIP_READY, 0, SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "Timed out waiting for WIP_READY\n");
-+		goto cleanup;
-+	}
-+
-+	ret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val, !(val & WIP),
-+				 0, SNFI_POLL_INTERVAL);
-+	if (ret)
-+		dev_err(snf->dev, "Timed out waiting for WIP cleared\n");
-+
-+cleanup:
-+	nfi_write32(snf, SNF_MAC_CTL, 0);
-+
-+	return ret;
-+}
-+
-+static int mtk_snand_mac_io(struct mtk_snand *snf, const struct spi_mem_op *op)
-+{
-+	u32 rx_len = 0;
-+	u32 reg_offs = 0;
-+	u32 val = 0;
-+	const u8 *tx_buf = NULL;
-+	u8 *rx_buf = NULL;
-+	int i, ret;
-+	u8 b;
-+
-+	if (op->data.dir == SPI_MEM_DATA_IN) {
-+		rx_len = op->data.nbytes;
-+		rx_buf = op->data.buf.in;
-+	} else {
-+		tx_buf = op->data.buf.out;
-+	}
-+
-+	mtk_snand_mac_reset(snf);
-+
-+	for (i = 0; i < op->cmd.nbytes; i++, reg_offs++) {
-+		b = (op->cmd.opcode >> ((op->cmd.nbytes - i - 1) * 8)) & 0xff;
-+		val |= b << (8 * (reg_offs % 4));
-+		if (reg_offs % 4 == 3) {
-+			nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);
-+			val = 0;
-+		}
-+	}
-+
-+	for (i = 0; i < op->addr.nbytes; i++, reg_offs++) {
-+		b = (op->addr.val >> ((op->addr.nbytes - i - 1) * 8)) & 0xff;
-+		val |= b << (8 * (reg_offs % 4));
-+		if (reg_offs % 4 == 3) {
-+			nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);
-+			val = 0;
-+		}
-+	}
-+
-+	for (i = 0; i < op->dummy.nbytes; i++, reg_offs++) {
-+		if (reg_offs % 4 == 3) {
-+			nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);
-+			val = 0;
-+		}
-+	}
-+
-+	if (op->data.dir == SPI_MEM_DATA_OUT) {
-+		for (i = 0; i < op->data.nbytes; i++, reg_offs++) {
-+			val |= tx_buf[i] << (8 * (reg_offs % 4));
-+			if (reg_offs % 4 == 3) {
-+				nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);
-+				val = 0;
-+			}
-+		}
-+	}
-+
-+	if (reg_offs % 4)
-+		nfi_write32(snf, SNF_GPRAM + (reg_offs & ~3), val);
-+
-+	for (i = 0; i < reg_offs; i += 4)
-+		dev_dbg(snf->dev, "%d: %08X", i,
-+			nfi_read32(snf, SNF_GPRAM + i));
-+
-+	dev_dbg(snf->dev, "SNF TX: %u RX: %u", reg_offs, rx_len);
-+
-+	ret = mtk_snand_mac_trigger(snf, reg_offs, rx_len);
-+	if (ret)
-+		return ret;
-+
-+	if (!rx_len)
-+		return 0;
-+
-+	nfi_read_data(snf, SNF_GPRAM + reg_offs, rx_buf, rx_len);
-+	return 0;
-+}
-+
-+static int mtk_snand_setup_pagefmt(struct mtk_snand *snf, u32 page_size,
-+				   u32 oob_size)
-+{
-+	int spare_idx = -1;
-+	u32 spare_size, spare_size_shift, pagesize_idx;
-+	u32 sector_size_512;
-+	u8 nsectors;
-+	int i;
-+
-+	// skip if it's already configured as required.
-+	if (snf->nfi_cfg.page_size == page_size &&
-+	    snf->nfi_cfg.oob_size == oob_size)
-+		return 0;
-+
-+	nsectors = page_size / snf->caps->sector_size;
-+	if (nsectors > snf->caps->max_sectors) {
-+		dev_err(snf->dev, "too many sectors required.\n");
-+		goto err;
-+	}
-+
-+	if (snf->caps->sector_size == 512) {
-+		sector_size_512 = NFI_SEC_SEL_512;
-+		spare_size_shift = NFI_SPARE_SIZE_S;
-+	} else {
-+		sector_size_512 = 0;
-+		spare_size_shift = NFI_SPARE_SIZE_LS_S;
-+	}
-+
-+	switch (page_size) {
-+	case SZ_512:
-+		pagesize_idx = NFI_PAGE_SIZE_512_2K;
-+		break;
-+	case SZ_2K:
-+		if (snf->caps->sector_size == 512)
-+			pagesize_idx = NFI_PAGE_SIZE_2K_4K;
-+		else
-+			pagesize_idx = NFI_PAGE_SIZE_512_2K;
-+		break;
-+	case SZ_4K:
-+		if (snf->caps->sector_size == 512)
-+			pagesize_idx = NFI_PAGE_SIZE_4K_8K;
-+		else
-+			pagesize_idx = NFI_PAGE_SIZE_2K_4K;
-+		break;
-+	case SZ_8K:
-+		if (snf->caps->sector_size == 512)
-+			pagesize_idx = NFI_PAGE_SIZE_8K_16K;
-+		else
-+			pagesize_idx = NFI_PAGE_SIZE_4K_8K;
-+		break;
-+	case SZ_16K:
-+		pagesize_idx = NFI_PAGE_SIZE_8K_16K;
-+		break;
-+	default:
-+		dev_err(snf->dev, "unsupported page size.\n");
-+		goto err;
-+	}
-+
-+	spare_size = oob_size / nsectors;
-+	// If we're using the 1KB sector size, HW will automatically double the
-+	// spare size. We should only use half of the value in this case.
-+	if (snf->caps->sector_size == 1024)
-+		spare_size /= 2;
-+
-+	for (i = snf->caps->num_spare_size - 1; i >= 0; i--) {
-+		if (snf->caps->spare_sizes[i] <= spare_size) {
-+			spare_size = snf->caps->spare_sizes[i];
-+			if (snf->caps->sector_size == 1024)
-+				spare_size *= 2;
-+			spare_idx = i;
-+			break;
-+		}
-+	}
-+
-+	if (spare_idx < 0) {
-+		dev_err(snf->dev, "unsupported spare size: %u\n", spare_size);
-+		goto err;
-+	}
-+
-+	nfi_write32(snf, NFI_PAGEFMT,
-+		    (snf->caps->fdm_ecc_size << NFI_FDM_ECC_NUM_S) |
-+			    (snf->caps->fdm_size << NFI_FDM_NUM_S) |
-+			    (spare_idx << spare_size_shift) |
-+			    (pagesize_idx << NFI_PAGE_SIZE_S) |
-+			    sector_size_512);
-+
-+	snf->nfi_cfg.page_size = page_size;
-+	snf->nfi_cfg.oob_size = oob_size;
-+	snf->nfi_cfg.nsectors = nsectors;
-+	snf->nfi_cfg.spare_size = spare_size;
-+
-+	dev_dbg(snf->dev, "page format: (%u + %u) * %u\n",
-+		snf->caps->sector_size, spare_size, nsectors);
-+	return snand_prepare_bouncebuf(snf, page_size + oob_size);
-+err:
-+	dev_err(snf->dev, "page size %u + %u is not supported\n", page_size,
-+		oob_size);
-+	return -EOPNOTSUPP;
-+}
-+
-+static int mtk_snand_ooblayout_ecc(struct mtd_info *mtd, int section,
-+				   struct mtd_oob_region *oobecc)
-+{
-+	// ECC area is not accessible
-+	return -ERANGE;
-+}
-+
-+static int mtk_snand_ooblayout_free(struct mtd_info *mtd, int section,
-+				    struct mtd_oob_region *oobfree)
-+{
-+	struct nand_device *nand = mtd_to_nanddev(mtd);
-+	struct mtk_snand *ms = nand_to_mtk_snand(nand);
-+
-+	if (section >= ms->nfi_cfg.nsectors)
-+		return -ERANGE;
-+
-+	oobfree->length = ms->caps->fdm_size - 1;
-+	oobfree->offset = section * ms->caps->fdm_size + 1;
-+	return 0;
-+}
-+
-+static const struct mtd_ooblayout_ops mtk_snand_ooblayout = {
-+	.ecc = mtk_snand_ooblayout_ecc,
-+	.free = mtk_snand_ooblayout_free,
-+};
-+
-+static int mtk_snand_ecc_init_ctx(struct nand_device *nand)
-+{
-+	struct mtk_snand *snf = nand_to_mtk_snand(nand);
-+	struct nand_ecc_props *conf = &nand->ecc.ctx.conf;
-+	struct nand_ecc_props *reqs = &nand->ecc.requirements;
-+	struct nand_ecc_props *user = &nand->ecc.user_conf;
-+	struct mtd_info *mtd = nanddev_to_mtd(nand);
-+	int step_size = 0, strength = 0, desired_correction = 0, steps;
-+	bool ecc_user = false;
-+	int ret;
-+	u32 parity_bits, max_ecc_bytes;
-+	struct mtk_ecc_config *ecc_cfg;
-+
-+	ret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize,
-+				      nand->memorg.oobsize);
-+	if (ret)
-+		return ret;
-+
-+	ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL);
-+	if (!ecc_cfg)
-+		return -ENOMEM;
-+
-+	nand->ecc.ctx.priv = ecc_cfg;
-+
-+	if (user->step_size && user->strength) {
-+		step_size = user->step_size;
-+		strength = user->strength;
-+		ecc_user = true;
-+	} else if (reqs->step_size && reqs->strength) {
-+		step_size = reqs->step_size;
-+		strength = reqs->strength;
-+	}
-+
-+	if (step_size && strength) {
-+		steps = mtd->writesize / step_size;
-+		desired_correction = steps * strength;
-+		strength = desired_correction / snf->nfi_cfg.nsectors;
-+	}
-+
-+	ecc_cfg->mode = ECC_NFI_MODE;
-+	ecc_cfg->sectors = snf->nfi_cfg.nsectors;
-+	ecc_cfg->len = snf->caps->sector_size + snf->caps->fdm_ecc_size;
-+
-+	// calculate the max possible strength under current page format
-+	parity_bits = mtk_ecc_get_parity_bits(snf->ecc);
-+	max_ecc_bytes = snf->nfi_cfg.spare_size - snf->caps->fdm_size;
-+	ecc_cfg->strength = max_ecc_bytes * 8 / parity_bits;
-+	mtk_ecc_adjust_strength(snf->ecc, &ecc_cfg->strength);
-+
-+	// if there's a user requested strength, find the minimum strength that
-+	// meets the requirement. Otherwise use the maximum strength which is
-+	// expected by BootROM.
-+	if (ecc_user && strength) {
-+		u32 s_next = ecc_cfg->strength - 1;
-+
-+		while (1) {
-+			mtk_ecc_adjust_strength(snf->ecc, &s_next);
-+			if (s_next >= ecc_cfg->strength)
-+				break;
-+			if (s_next < strength)
-+				break;
-+			s_next = ecc_cfg->strength - 1;
-+		}
-+	}
-+
-+	mtd_set_ooblayout(mtd, &mtk_snand_ooblayout);
-+
-+	conf->step_size = snf->caps->sector_size;
-+	conf->strength = ecc_cfg->strength;
-+
-+	if (ecc_cfg->strength < strength)
-+		dev_warn(snf->dev, "unable to fulfill ECC of %u bits.\n",
-+			 strength);
-+	dev_info(snf->dev, "ECC strength: %u bits per %u bytes\n",
-+		 ecc_cfg->strength, snf->caps->sector_size);
-+
-+	return 0;
-+}
-+
-+static void mtk_snand_ecc_cleanup_ctx(struct nand_device *nand)
-+{
-+	struct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand);
-+
-+	kfree(ecc_cfg);
-+}
-+
-+static int mtk_snand_ecc_prepare_io_req(struct nand_device *nand,
-+					struct nand_page_io_req *req)
-+{
-+	struct mtk_snand *snf = nand_to_mtk_snand(nand);
-+	struct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand);
-+	int ret;
-+
-+	ret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize,
-+				      nand->memorg.oobsize);
-+	if (ret)
-+		return ret;
-+	snf->autofmt = true;
-+	snf->ecc_cfg = ecc_cfg;
-+	return 0;
-+}
-+
-+static int mtk_snand_ecc_finish_io_req(struct nand_device *nand,
-+				       struct nand_page_io_req *req)
-+{
-+	struct mtk_snand *snf = nand_to_mtk_snand(nand);
-+	struct mtd_info *mtd = nanddev_to_mtd(nand);
-+
-+	snf->ecc_cfg = NULL;
-+	snf->autofmt = false;
-+	if ((req->mode == MTD_OPS_RAW) || (req->type != NAND_PAGE_READ))
-+		return 0;
-+
-+	if (snf->ecc_stats.failed)
-+		mtd->ecc_stats.failed += snf->ecc_stats.failed;
-+	mtd->ecc_stats.corrected += snf->ecc_stats.corrected;
-+	return snf->ecc_stats.failed ? -EBADMSG : snf->ecc_stats.bitflips;
-+}
-+
-+static struct nand_ecc_engine_ops mtk_snfi_ecc_engine_ops = {
-+	.init_ctx = mtk_snand_ecc_init_ctx,
-+	.cleanup_ctx = mtk_snand_ecc_cleanup_ctx,
-+	.prepare_io_req = mtk_snand_ecc_prepare_io_req,
-+	.finish_io_req = mtk_snand_ecc_finish_io_req,
-+};
-+
-+static void mtk_snand_read_fdm(struct mtk_snand *snf, u8 *buf)
-+{
-+	u32 vall, valm;
-+	u8 *oobptr = buf;
-+	int i, j;
-+
-+	for (i = 0; i < snf->nfi_cfg.nsectors; i++) {
-+		vall = nfi_read32(snf, NFI_FDML(i));
-+		valm = nfi_read32(snf, NFI_FDMM(i));
-+
-+		for (j = 0; j < snf->caps->fdm_size; j++)
-+			oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8);
-+
-+		oobptr += snf->caps->fdm_size;
-+	}
-+}
-+
-+static void mtk_snand_write_fdm(struct mtk_snand *snf, const u8 *buf)
-+{
-+	u32 fdm_size = snf->caps->fdm_size;
-+	const u8 *oobptr = buf;
-+	u32 vall, valm;
-+	int i, j;
-+
-+	for (i = 0; i < snf->nfi_cfg.nsectors; i++) {
-+		vall = 0;
-+		valm = 0;
-+
-+		for (j = 0; j < 8; j++) {
-+			if (j < 4)
-+				vall |= (j < fdm_size ? oobptr[j] : 0xff)
-+					<< (j * 8);
-+			else
-+				valm |= (j < fdm_size ? oobptr[j] : 0xff)
-+					<< ((j - 4) * 8);
-+		}
-+
-+		nfi_write32(snf, NFI_FDML(i), vall);
-+		nfi_write32(snf, NFI_FDMM(i), valm);
-+
-+		oobptr += fdm_size;
-+	}
-+}
-+
-+static void mtk_snand_bm_swap(struct mtk_snand *snf, u8 *buf)
-+{
-+	u32 buf_bbm_pos, fdm_bbm_pos;
-+
-+	if (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1)
-+		return;
-+
-+	// swap [pagesize] byte on nand with the first fdm byte
-+	// in the last sector.
-+	buf_bbm_pos = snf->nfi_cfg.page_size -
-+		      (snf->nfi_cfg.nsectors - 1) * snf->nfi_cfg.spare_size;
-+	fdm_bbm_pos = snf->nfi_cfg.page_size +
-+		      (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size;
-+
-+	swap(snf->buf[fdm_bbm_pos], buf[buf_bbm_pos]);
-+}
-+
-+static void mtk_snand_fdm_bm_swap(struct mtk_snand *snf)
-+{
-+	u32 fdm_bbm_pos1, fdm_bbm_pos2;
-+
-+	if (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1)
-+		return;
-+
-+	// swap the first fdm byte in the first and the last sector.
-+	fdm_bbm_pos1 = snf->nfi_cfg.page_size;
-+	fdm_bbm_pos2 = snf->nfi_cfg.page_size +
-+		       (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size;
-+	swap(snf->buf[fdm_bbm_pos1], snf->buf[fdm_bbm_pos2]);
-+}
-+
-+static int mtk_snand_read_page_cache(struct mtk_snand *snf,
-+				     const struct spi_mem_op *op)
-+{
-+	u8 *buf = snf->buf;
-+	u8 *buf_fdm = buf + snf->nfi_cfg.page_size;
-+	// the address part to be sent by the controller
-+	u32 op_addr = op->addr.val;
-+	// where to start copying data from bounce buffer
-+	u32 rd_offset = 0;
-+	u32 dummy_clk = (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth);
-+	u32 op_mode = 0;
-+	u32 dma_len = snf->buf_len;
-+	int ret = 0;
-+	u32 rd_mode, rd_bytes, val;
-+	dma_addr_t buf_dma;
-+
-+	if (snf->autofmt) {
-+		u32 last_bit;
-+		u32 mask;
-+
-+		dma_len = snf->nfi_cfg.page_size;
-+		op_mode = CNFG_AUTO_FMT_EN;
-+		if (op->data.ecc)
-+			op_mode |= CNFG_HW_ECC_EN;
-+		// extract the plane bit:
-+		// Find the highest bit set in (pagesize+oobsize).
-+		// Bits higher than that in op->addr are kept and sent over SPI
-+		// Lower bits are used as an offset for copying data from DMA
-+		// bounce buffer.
-+		last_bit = fls(snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size);
-+		mask = (1 << last_bit) - 1;
-+		rd_offset = op_addr & mask;
-+		op_addr &= ~mask;
-+
-+		// check if we can dma to the caller memory
-+		if (rd_offset == 0 && op->data.nbytes >= snf->nfi_cfg.page_size)
-+			buf = op->data.buf.in;
-+	}
-+	mtk_snand_mac_reset(snf);
-+	mtk_nfi_reset(snf);
-+
-+	// command and dummy cycles
-+	nfi_write32(snf, SNF_RD_CTL2,
-+		    (dummy_clk << DATA_READ_DUMMY_S) |
-+			    (op->cmd.opcode << DATA_READ_CMD_S));
-+
-+	// read address
-+	nfi_write32(snf, SNF_RD_CTL3, op_addr);
-+
-+	// Set read op_mode
-+	if (op->data.buswidth == 4)
-+		rd_mode = op->addr.buswidth == 4 ? DATA_READ_MODE_QUAD :
-+						   DATA_READ_MODE_X4;
-+	else if (op->data.buswidth == 2)
-+		rd_mode = op->addr.buswidth == 2 ? DATA_READ_MODE_DUAL :
-+						   DATA_READ_MODE_X2;
-+	else
-+		rd_mode = DATA_READ_MODE_X1;
-+	rd_mode <<= DATA_READ_MODE_S;
-+	nfi_rmw32(snf, SNF_MISC_CTL, DATA_READ_MODE,
-+		  rd_mode | DATARD_CUSTOM_EN);
-+
-+	// Set bytes to read
-+	rd_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) *
-+		   snf->nfi_cfg.nsectors;
-+	nfi_write32(snf, SNF_MISC_CTL2,
-+		    (rd_bytes << PROGRAM_LOAD_BYTE_NUM_S) | rd_bytes);
-+
-+	// NFI read prepare
-+	nfi_write16(snf, NFI_CNFG,
-+		    (CNFG_OP_MODE_CUST << CNFG_OP_MODE_S) | CNFG_DMA_BURST_EN |
-+			    CNFG_READ_MODE | CNFG_DMA_MODE | op_mode);
-+
-+	nfi_write32(snf, NFI_CON, (snf->nfi_cfg.nsectors << CON_SEC_NUM_S));
-+
-+	buf_dma = dma_map_single(snf->dev, buf, dma_len, DMA_FROM_DEVICE);
-+	if (dma_mapping_error(snf->dev, buf_dma)) {
-+		dev_err(snf->dev, "DMA mapping failed.\n");
-+		goto cleanup;
-+	}
-+	nfi_write32(snf, NFI_STRADDR, buf_dma);
-+	if (op->data.ecc) {
-+		snf->ecc_cfg->op = ECC_DECODE;
-+		ret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg);
-+		if (ret)
-+			goto cleanup_dma;
-+	}
-+	// Prepare for custom read interrupt
-+	nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_READ);
-+	reinit_completion(&snf->op_done);
-+
-+	// Trigger NFI into custom mode
-+	nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_READ);
-+
-+	// Start DMA read
-+	nfi_rmw32(snf, NFI_CON, 0, CON_BRD);
-+	nfi_write16(snf, NFI_STRDATA, STR_DATA);
-+
-+	if (!wait_for_completion_timeout(
-+		    &snf->op_done, usecs_to_jiffies(SNFI_POLL_INTERVAL))) {
-+		dev_err(snf->dev, "DMA timed out for reading from cache.\n");
-+		ret = -ETIMEDOUT;
-+		goto cleanup;
-+	}
-+
-+	// Wait for BUS_SEC_CNTR returning expected value
-+	ret = readl_poll_timeout(snf->nfi_base + NFI_BYTELEN, val,
-+				 BUS_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0,
-+				 SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "Timed out waiting for BUS_SEC_CNTR\n");
-+		goto cleanup2;
-+	}
-+
-+	// Wait for bus becoming idle
-+	ret = readl_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val,
-+				 !(val & snf->caps->mastersta_mask), 0,
-+				 SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "Timed out waiting for bus becoming idle\n");
-+		goto cleanup2;
-+	}
-+
-+	if (op->data.ecc) {
-+		ret = mtk_ecc_wait_done(snf->ecc, ECC_DECODE);
-+		if (ret) {
-+			dev_err(snf->dev, "wait ecc done timeout\n");
-+			goto cleanup2;
-+		}
-+		// save status before disabling ecc
-+		mtk_ecc_get_stats(snf->ecc, &snf->ecc_stats,
-+				  snf->nfi_cfg.nsectors);
-+	}
-+
-+	dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE);
-+
-+	if (snf->autofmt) {
-+		mtk_snand_read_fdm(snf, buf_fdm);
-+		if (snf->caps->bbm_swap) {
-+			mtk_snand_bm_swap(snf, buf);
-+			mtk_snand_fdm_bm_swap(snf);
-+		}
-+	}
-+
-+	// copy data back
-+	if (nfi_read32(snf, NFI_STA) & READ_EMPTY) {
-+		memset(op->data.buf.in, 0xff, op->data.nbytes);
-+		snf->ecc_stats.bitflips = 0;
-+		snf->ecc_stats.failed = 0;
-+		snf->ecc_stats.corrected = 0;
-+	} else {
-+		if (buf == op->data.buf.in) {
-+			u32 cap_len = snf->buf_len - snf->nfi_cfg.page_size;
-+			u32 req_left = op->data.nbytes - snf->nfi_cfg.page_size;
-+
-+			if (req_left)
-+				memcpy(op->data.buf.in + snf->nfi_cfg.page_size,
-+				       buf_fdm,
-+				       cap_len < req_left ? cap_len : req_left);
-+		} else if (rd_offset < snf->buf_len) {
-+			u32 cap_len = snf->buf_len - rd_offset;
-+
-+			if (op->data.nbytes < cap_len)
-+				cap_len = op->data.nbytes;
-+			memcpy(op->data.buf.in, snf->buf + rd_offset, cap_len);
-+		}
-+	}
-+cleanup2:
-+	if (op->data.ecc)
-+		mtk_ecc_disable(snf->ecc);
-+cleanup_dma:
-+	// unmap dma only if any error happens. (otherwise it's done before
-+	// data copying)
-+	if (ret)
-+		dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE);
-+cleanup:
-+	// Stop read
-+	nfi_write32(snf, NFI_CON, 0);
-+	nfi_write16(snf, NFI_CNFG, 0);
-+
-+	// Clear SNF done flag
-+	nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_READ_DONE);
-+	nfi_write32(snf, SNF_STA_CTL1, 0);
-+
-+	// Disable interrupt
-+	nfi_read32(snf, NFI_INTR_STA);
-+	nfi_write32(snf, NFI_INTR_EN, 0);
-+
-+	nfi_rmw32(snf, SNF_MISC_CTL, DATARD_CUSTOM_EN, 0);
-+	return ret;
-+}
-+
-+static int mtk_snand_write_page_cache(struct mtk_snand *snf,
-+				      const struct spi_mem_op *op)
-+{
-+	// the address part to be sent by the controller
-+	u32 op_addr = op->addr.val;
-+	// where to start copying data from bounce buffer
-+	u32 wr_offset = 0;
-+	u32 op_mode = 0;
-+	int ret = 0;
-+	u32 wr_mode = 0;
-+	u32 dma_len = snf->buf_len;
-+	u32 wr_bytes, val;
-+	size_t cap_len;
-+	dma_addr_t buf_dma;
-+
-+	if (snf->autofmt) {
-+		u32 last_bit;
-+		u32 mask;
-+
-+		dma_len = snf->nfi_cfg.page_size;
-+		op_mode = CNFG_AUTO_FMT_EN;
-+		if (op->data.ecc)
-+			op_mode |= CNFG_HW_ECC_EN;
-+
-+		last_bit = fls(snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size);
-+		mask = (1 << last_bit) - 1;
-+		wr_offset = op_addr & mask;
-+		op_addr &= ~mask;
-+	}
-+	mtk_snand_mac_reset(snf);
-+	mtk_nfi_reset(snf);
-+
-+	if (wr_offset)
-+		memset(snf->buf, 0xff, wr_offset);
-+
-+	cap_len = snf->buf_len - wr_offset;
-+	if (op->data.nbytes < cap_len)
-+		cap_len = op->data.nbytes;
-+	memcpy(snf->buf + wr_offset, op->data.buf.out, cap_len);
-+	if (snf->autofmt) {
-+		if (snf->caps->bbm_swap) {
-+			mtk_snand_fdm_bm_swap(snf);
-+			mtk_snand_bm_swap(snf, snf->buf);
-+		}
-+		mtk_snand_write_fdm(snf, snf->buf + snf->nfi_cfg.page_size);
-+	}
-+
-+	// Command
-+	nfi_write32(snf, SNF_PG_CTL1, (op->cmd.opcode << PG_LOAD_CMD_S));
-+
-+	// write address
-+	nfi_write32(snf, SNF_PG_CTL2, op_addr);
-+
-+	// Set read op_mode
-+	if (op->data.buswidth == 4)
-+		wr_mode = PG_LOAD_X4_EN;
-+
-+	nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_X4_EN,
-+		  wr_mode | PG_LOAD_CUSTOM_EN);
-+
-+	// Set bytes to write
-+	wr_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) *
-+		   snf->nfi_cfg.nsectors;
-+	nfi_write32(snf, SNF_MISC_CTL2,
-+		    (wr_bytes << PROGRAM_LOAD_BYTE_NUM_S) | wr_bytes);
-+
-+	// NFI write prepare
-+	nfi_write16(snf, NFI_CNFG,
-+		    (CNFG_OP_MODE_PROGRAM << CNFG_OP_MODE_S) |
-+			    CNFG_DMA_BURST_EN | CNFG_DMA_MODE | op_mode);
-+
-+	nfi_write32(snf, NFI_CON, (snf->nfi_cfg.nsectors << CON_SEC_NUM_S));
-+	buf_dma = dma_map_single(snf->dev, snf->buf, dma_len, DMA_TO_DEVICE);
-+	if (dma_mapping_error(snf->dev, buf_dma)) {
-+		dev_err(snf->dev, "DMA mapping failed.\n");
-+		goto cleanup;
-+	}
-+	nfi_write32(snf, NFI_STRADDR, buf_dma);
-+	if (op->data.ecc) {
-+		snf->ecc_cfg->op = ECC_ENCODE;
-+		ret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg);
-+		if (ret)
-+			goto cleanup_dma;
-+	}
-+	// Prepare for custom write interrupt
-+	nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_PG);
-+	reinit_completion(&snf->op_done);
-+	;
-+
-+	// Trigger NFI into custom mode
-+	nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_WRITE);
-+
-+	// Start DMA write
-+	nfi_rmw32(snf, NFI_CON, 0, CON_BWR);
-+	nfi_write16(snf, NFI_STRDATA, STR_DATA);
-+
-+	if (!wait_for_completion_timeout(
-+		    &snf->op_done, usecs_to_jiffies(SNFI_POLL_INTERVAL))) {
-+		dev_err(snf->dev, "DMA timed out for program load.\n");
-+		ret = -ETIMEDOUT;
-+		goto cleanup_ecc;
-+	}
-+
-+	// Wait for NFI_SEC_CNTR returning expected value
-+	ret = readl_poll_timeout(snf->nfi_base + NFI_ADDRCNTR, val,
-+				 NFI_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0,
-+				 SNFI_POLL_INTERVAL);
-+	if (ret)
-+		dev_err(snf->dev, "Timed out waiting for NFI_SEC_CNTR\n");
-+
-+cleanup_ecc:
-+	if (op->data.ecc)
-+		mtk_ecc_disable(snf->ecc);
-+cleanup_dma:
-+	dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_TO_DEVICE);
-+cleanup:
-+	// Stop write
-+	nfi_write32(snf, NFI_CON, 0);
-+	nfi_write16(snf, NFI_CNFG, 0);
-+
-+	// Clear SNF done flag
-+	nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_PG_DONE);
-+	nfi_write32(snf, SNF_STA_CTL1, 0);
-+
-+	// Disable interrupt
-+	nfi_read32(snf, NFI_INTR_STA);
-+	nfi_write32(snf, NFI_INTR_EN, 0);
-+
-+	nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_CUSTOM_EN, 0);
-+
-+	return ret;
-+}
-+
-+/**
-+ * mtk_snand_is_page_ops() - check if the op is a controller supported page op.
-+ * @op spi-mem op to check
-+ *
-+ * Check whether op can be executed with read_from_cache or program_load
-+ * mode in the controller.
-+ * This controller can execute typical Read From Cache and Program Load
-+ * instructions found on SPI-NAND with 2-byte address.
-+ * DTR and cmd buswidth & nbytes should be checked before calling this.
-+ *
-+ * Return: true if the op matches the instruction template
-+ */
-+static bool mtk_snand_is_page_ops(const struct spi_mem_op *op)
-+{
-+	if (op->addr.nbytes != 2)
-+		return false;
-+
-+	if (op->addr.buswidth != 1 && op->addr.buswidth != 2 &&
-+	    op->addr.buswidth != 4)
-+		return false;
-+
-+	// match read from page instructions
-+	if (op->data.dir == SPI_MEM_DATA_IN) {
-+		// check dummy cycle first
-+		if (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth >
-+		    DATA_READ_MAX_DUMMY)
-+			return false;
-+		// quad io / quad out
-+		if ((op->addr.buswidth == 4 || op->addr.buswidth == 1) &&
-+		    op->data.buswidth == 4)
-+			return true;
-+
-+		// dual io / dual out
-+		if ((op->addr.buswidth == 2 || op->addr.buswidth == 1) &&
-+		    op->data.buswidth == 2)
-+			return true;
-+
-+		// standard spi
-+		if (op->addr.buswidth == 1 && op->data.buswidth == 1)
-+			return true;
-+	} else if (op->data.dir == SPI_MEM_DATA_OUT) {
-+		// check dummy cycle first
-+		if (op->dummy.nbytes)
-+			return false;
-+		// program load quad out
-+		if (op->addr.buswidth == 1 && op->data.buswidth == 4)
-+			return true;
-+		// standard spi
-+		if (op->addr.buswidth == 1 && op->data.buswidth == 1)
-+			return true;
-+	}
-+	return false;
-+}
-+
-+static bool mtk_snand_supports_op(struct spi_mem *mem,
-+				  const struct spi_mem_op *op)
-+{
-+	if (!spi_mem_default_supports_op(mem, op))
-+		return false;
-+	if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1)
-+		return false;
-+	if (mtk_snand_is_page_ops(op))
-+		return true;
-+	return ((op->addr.nbytes == 0 || op->addr.buswidth == 1) &&
-+		(op->dummy.nbytes == 0 || op->dummy.buswidth == 1) &&
-+		(op->data.nbytes == 0 || op->data.buswidth == 1));
-+}
-+
-+static int mtk_snand_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
-+{
-+	struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master);
-+	// page ops transfer size must be exactly ((sector_size + spare_size) *
-+	// nsectors). Limit the op size if the caller requests more than that.
-+	// exec_op will read more than needed and discard the leftover if the
-+	// caller requests less data.
-+	if (mtk_snand_is_page_ops(op)) {
-+		size_t l;
-+		// skip adjust_op_size for page ops
-+		if (ms->autofmt)
-+			return 0;
-+		l = ms->caps->sector_size + ms->nfi_cfg.spare_size;
-+		l *= ms->nfi_cfg.nsectors;
-+		if (op->data.nbytes > l)
-+			op->data.nbytes = l;
-+	} else {
-+		size_t hl = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
-+
-+		if (hl >= SNF_GPRAM_SIZE)
-+			return -EOPNOTSUPP;
-+		if (op->data.nbytes > SNF_GPRAM_SIZE - hl)
-+			op->data.nbytes = SNF_GPRAM_SIZE - hl;
-+	}
-+	return 0;
-+}
-+
-+static int mtk_snand_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
-+{
-+	struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master);
-+
-+	dev_dbg(ms->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode,
-+		op->addr.val, op->addr.buswidth, op->addr.nbytes,
-+		op->data.buswidth, op->data.nbytes);
-+	if (mtk_snand_is_page_ops(op)) {
-+		if (op->data.dir == SPI_MEM_DATA_IN)
-+			return mtk_snand_read_page_cache(ms, op);
-+		else
-+			return mtk_snand_write_page_cache(ms, op);
-+	} else {
-+		return mtk_snand_mac_io(ms, op);
-+	}
-+}
-+
-+static const struct spi_controller_mem_ops mtk_snand_mem_ops = {
-+	.adjust_op_size = mtk_snand_adjust_op_size,
-+	.supports_op = mtk_snand_supports_op,
-+	.exec_op = mtk_snand_exec_op,
-+};
-+
-+static const struct spi_controller_mem_caps mtk_snand_mem_caps = {
-+	.ecc = true,
-+};
-+
-+static irqreturn_t mtk_snand_irq(int irq, void *id)
-+{
-+	struct mtk_snand *snf = id;
-+	u32 sta, ien;
-+
-+	sta = nfi_read32(snf, NFI_INTR_STA);
-+	ien = nfi_read32(snf, NFI_INTR_EN);
-+
-+	if (!(sta & ien))
-+		return IRQ_NONE;
-+
-+	nfi_write32(snf, NFI_INTR_EN, 0);
-+	complete(&snf->op_done);
-+	return IRQ_HANDLED;
-+}
-+
-+static const struct of_device_id mtk_snand_ids[] = {
-+	{ .compatible = "mediatek,mt7622-snand", .data = &mt7622_snand_caps },
-+	{ .compatible = "mediatek,mt7629-snand", .data = &mt7629_snand_caps },
-+	{},
-+};
-+
-+MODULE_DEVICE_TABLE(of, mtk_snand_ids);
-+
-+static int mtk_snand_enable_clk(struct mtk_snand *ms)
-+{
-+	int ret;
-+
-+	ret = clk_prepare_enable(ms->nfi_clk);
-+	if (ret) {
-+		dev_err(ms->dev, "unable to enable nfi clk\n");
-+		return ret;
-+	}
-+	ret = clk_prepare_enable(ms->pad_clk);
-+	if (ret) {
-+		dev_err(ms->dev, "unable to enable pad clk\n");
-+		goto err1;
-+	}
-+	return 0;
-+err1:
-+	clk_disable_unprepare(ms->nfi_clk);
-+	return ret;
-+}
-+
-+static void mtk_snand_disable_clk(struct mtk_snand *ms)
-+{
-+	clk_disable_unprepare(ms->pad_clk);
-+	clk_disable_unprepare(ms->nfi_clk);
-+}
-+
-+static int mtk_snand_probe(struct platform_device *pdev)
-+{
-+	struct device_node *np = pdev->dev.of_node;
-+	const struct of_device_id *dev_id;
-+	struct spi_controller *ctlr;
-+	struct mtk_snand *ms;
-+	int ret;
-+
-+	dev_id = of_match_node(mtk_snand_ids, np);
-+	if (!dev_id)
-+		return -EINVAL;
-+
-+	ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*ms));
-+	if (!ctlr)
-+		return -ENOMEM;
-+	platform_set_drvdata(pdev, ctlr);
-+
-+	ms = spi_controller_get_devdata(ctlr);
-+
-+	ms->ctlr = ctlr;
-+	ms->caps = dev_id->data;
-+
-+	ms->ecc = of_mtk_ecc_get(np);
-+	if (IS_ERR(ms->ecc))
-+		return PTR_ERR(ms->ecc);
-+	else if (!ms->ecc)
-+		return -ENODEV;
-+
-+	ms->nfi_base = devm_platform_ioremap_resource(pdev, 0);
-+	if (IS_ERR(ms->nfi_base)) {
-+		ret = PTR_ERR(ms->nfi_base);
-+		goto release_ecc;
-+	}
-+
-+	ms->dev = &pdev->dev;
-+
-+	ms->nfi_clk = devm_clk_get(&pdev->dev, "nfi_clk");
-+	if (IS_ERR(ms->nfi_clk)) {
-+		ret = PTR_ERR(ms->nfi_clk);
-+		dev_err(&pdev->dev, "unable to get nfi_clk, err = %d\n", ret);
-+		goto release_ecc;
-+	}
-+
-+	ms->pad_clk = devm_clk_get(&pdev->dev, "pad_clk");
-+	if (IS_ERR(ms->pad_clk)) {
-+		ret = PTR_ERR(ms->pad_clk);
-+		dev_err(&pdev->dev, "unable to get pad_clk, err = %d\n", ret);
-+		goto release_ecc;
-+	}
-+
-+	ret = mtk_snand_enable_clk(ms);
-+	if (ret)
-+		goto release_ecc;
-+
-+	init_completion(&ms->op_done);
-+
-+	ms->irq = platform_get_irq(pdev, 0);
-+	if (ms->irq < 0) {
-+		ret = ms->irq;
-+		goto disable_clk;
-+	}
-+	ret = devm_request_irq(ms->dev, ms->irq, mtk_snand_irq, 0x0,
-+			       "mtk-snand", ms);
-+	if (ret) {
-+		dev_err(ms->dev, "failed to request snfi irq\n");
-+		goto disable_clk;
-+	}
-+
-+	ret = dma_set_mask(ms->dev, DMA_BIT_MASK(32));
-+	if (ret) {
-+		dev_err(ms->dev, "failed to set dma mask\n");
-+		goto disable_clk;
-+	}
-+
-+	// switch to SNFI mode
-+	nfi_write32(ms, SNF_CFG, SPI_MODE);
-+
-+	// setup an initial page format for ops matching page_cache_op template
-+	// before ECC is called.
-+	ret = mtk_snand_setup_pagefmt(ms, ms->caps->sector_size,
-+				      ms->caps->spare_sizes[0]);
-+	if (ret) {
-+		dev_err(ms->dev, "failed to set initial page format\n");
-+		goto disable_clk;
-+	}
-+
-+	// setup ECC engine
-+	ms->ecc_eng.dev = &pdev->dev;
-+	ms->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED;
-+	ms->ecc_eng.ops = &mtk_snfi_ecc_engine_ops;
-+	ms->ecc_eng.priv = ms;
-+
-+	ret = nand_ecc_register_on_host_hw_engine(&ms->ecc_eng);
-+	if (ret) {
-+		dev_err(&pdev->dev, "failed to register ecc engine.\n");
-+		goto disable_clk;
-+	}
-+
-+	ctlr->num_chipselect = 1;
-+	ctlr->mem_ops = &mtk_snand_mem_ops;
-+	ctlr->mem_caps = &mtk_snand_mem_caps;
-+	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
-+	ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
-+	ctlr->dev.of_node = pdev->dev.of_node;
-+	ret = spi_register_controller(ctlr);
-+	if (ret) {
-+		dev_err(&pdev->dev, "spi_register_controller failed.\n");
-+		goto disable_clk;
-+	}
-+
-+	return 0;
-+disable_clk:
-+	mtk_snand_disable_clk(ms);
-+release_ecc:
-+	mtk_ecc_release(ms->ecc);
-+	return ret;
-+}
-+
-+static int mtk_snand_remove(struct platform_device *pdev)
-+{
-+	struct spi_controller *ctlr = platform_get_drvdata(pdev);
-+	struct mtk_snand *ms = spi_controller_get_devdata(ctlr);
-+
-+	spi_unregister_controller(ctlr);
-+	mtk_snand_disable_clk(ms);
-+	mtk_ecc_release(ms->ecc);
-+	kfree(ms->buf);
-+	return 0;
-+}
-+
-+static struct platform_driver mtk_snand_driver = {
-+	.probe = mtk_snand_probe,
-+	.remove = mtk_snand_remove,
-+	.driver = {
-+		.name = "mtk-snand",
-+		.of_match_table = mtk_snand_ids,
-+	},
-+};
-+
-+module_platform_driver(mtk_snand_driver);
-+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Chuanhong Guo <[email protected]>");
-+MODULE_DESCRIPTION("MeidaTek SPI-NAND Flash Controller Driver");

target/linux/mediatek/patches-6.1/120-13-v5.19-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch

@@ -1,30 +0,0 @@
-From 433b76fa0f3ca2865841abc21538dd8077ca3edd Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <[email protected]>
-Date: Mon, 4 Apr 2022 00:05:38 +0800
-Subject: [PATCH 13/15] mtd: nand: mtk-ecc: also parse nand-ecc-engine if
- available
-
-The recently added ECC engine support introduced a generic property
-named nand-ecc-engine for ecc engine phandle. This patch adds support
-for this new property.
-
-Signed-off-by: Chuanhong Guo <[email protected]>
-(cherry picked from commit a41f25feb6e47c1c4d8d3279ae990ccbd8dfab54)
----
- drivers/mtd/nand/ecc-mtk.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/ecc-mtk.c
-+++ b/drivers/mtd/nand/ecc-mtk.c
-@@ -279,7 +279,10 @@ struct mtk_ecc *of_mtk_ecc_get(struct de
- 	struct mtk_ecc *ecc = NULL;
- 	struct device_node *np;
- 
--	np = of_parse_phandle(of_node, "ecc-engine", 0);
-+	np = of_parse_phandle(of_node, "nand-ecc-engine", 0);
-+	/* for backward compatibility */
-+	if (!np)
-+		np = of_parse_phandle(of_node, "ecc-engine", 0);
- 	if (np) {
- 		ecc = mtk_ecc_get(np);
- 		of_node_put(np);

target/linux/mediatek/patches-6.1/120-14-v5.19-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch

@@ -1,35 +0,0 @@
-From 9ba7c246063ae43baf2e53ccc8c8b5f8d025aaaa Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <[email protected]>
-Date: Sun, 3 Apr 2022 10:19:29 +0800
-Subject: [PATCH 15/15] arm64: dts: mediatek: add mtk-snfi for mt7622
-
-This patch adds a device-tree node for the MTK SPI-NAND Flash Interface
-for MT7622 device tree.
-
-Signed-off-by: Chuanhong Guo <[email protected]>
-(cherry picked from commit 2e022641709011ef0843d0416b0f264b5fc217af)
----
- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -553,6 +553,18 @@
- 		status = "disabled";
- 	};
- 
-+	snfi: spi@1100d000 {
-+		compatible = "mediatek,mt7622-snand";
-+		reg = <0 0x1100d000 0 0x1000>;
-+		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
-+		clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
-+		clock-names = "nfi_clk", "pad_clk";
-+		nand-ecc-engine = <&bch>;
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		status = "disabled";
-+	};
-+
- 	bch: ecc@1100e000 {
- 		compatible = "mediatek,mt7622-ecc";
- 		reg = <0 0x1100e000 0 0x1000>;

target/linux/mediatek/patches-6.1/130-dts-mt7629-add-snand-support.patch

@@ -41,7 +41,7 @@ Signed-off-by: Xiangsheng Hou <[email protected]>
  				     "mediatek,mt7622-spi";
 --- a/arch/arm/boot/dts/mt7629-rfb.dts
 +++ b/arch/arm/boot/dts/mt7629-rfb.dts
-@@ -254,6 +254,50 @@
+@@ -255,6 +255,50 @@
  	};
  };
  

target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -539,6 +539,65 @@
+@@ -538,6 +538,65 @@
  	status = "disabled";
  };
  

target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -580,7 +580,7 @@
+@@ -579,7 +579,7 @@
  				reg = <0x140000 0x0080000>;
  			};
  
@@ -9,7 +9,7 @@
  				label = "Factory";
  				reg = <0x1c0000 0x0100000>;
  			};
-@@ -641,5 +641,6 @@
+@@ -640,5 +640,6 @@
  &wmac {
  	pinctrl-names = "default";
  	pinctrl-0 = <&wmac_pins>;

target/linux/mediatek/patches-6.1/150-dts-mt7623-eip97-inside-secure-support.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm/boot/dts/mt7623.dtsi
 +++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -951,17 +951,15 @@
+@@ -984,17 +984,15 @@
  	};
  
  	crypto: crypto@1b240000 {

target/linux/mediatek/patches-6.1/173-arm-dts-mt7623-add-musb-device-nodes.patch

@@ -1,69 +0,0 @@
-From 21d106f15262f5a2ef7531636e0703ee61c33c61 Mon Sep 17 00:00:00 2001
-From: Sungbo Eo <[email protected]>
-Date: Sun, 8 Aug 2021 21:38:40 +0900
-Subject: [PATCH 2/2] arm: dts: mt7623: add musb device nodes
-
-MT7623 has an musb controller that is compatible with the one from MT2701.
-
-Signed-off-by: Sungbo Eo <[email protected]>
----
- arch/arm/boot/dts/mt7623.dtsi  | 34 ++++++++++++++++++++++++++++++++++
- arch/arm/boot/dts/mt7623a.dtsi |  4 ++++
- 2 files changed, 38 insertions(+)
-
---- a/arch/arm/boot/dts/mt7623.dtsi
-+++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -585,6 +585,40 @@
- 		status = "disabled";
- 	};
- 
-+	usb0: usb@11200000 {
-+		compatible = "mediatek,mt7623-musb",
-+			     "mediatek,mtk-musb";
-+		reg = <0 0x11200000 0 0x1000>;
-+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
-+		interrupt-names = "mc";
-+		phys = <&u2port2 PHY_TYPE_USB2>;
-+		dr_mode = "otg";
-+		clocks = <&pericfg CLK_PERI_USB0>,
-+			 <&pericfg CLK_PERI_USB0_MCU>,
-+			 <&pericfg CLK_PERI_USB_SLV>;
-+		clock-names = "main","mcu","univpll";
-+		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
-+		status = "disabled";
-+	};
-+
-+	u2phy1: t-phy@11210000 {
-+		compatible = "mediatek,mt7623-tphy",
-+			     "mediatek,generic-tphy-v1";
-+		reg = <0 0x11210000 0 0x0800>;
-+		#address-cells = <2>;
-+		#size-cells = <2>;
-+		ranges;
-+		status = "disabled";
-+
-+		u2port2: usb-phy@11210800 {
-+			reg = <0 0x11210800 0 0x0100>;
-+			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
-+			clock-names = "ref";
-+			#phy-cells = <1>;
-+			status = "okay";
-+		};
-+	};
-+
- 	audsys: clock-controller@11220000 {
- 		compatible = "mediatek,mt7623-audsys",
- 			     "mediatek,mt2701-audsys",
---- a/arch/arm/boot/dts/mt7623a.dtsi
-+++ b/arch/arm/boot/dts/mt7623a.dtsi
-@@ -35,6 +35,10 @@
- 	clock-names = "ethif";
- };
- 
-+&usb0 {
-+	power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>;
-+};
-+
- &usb1 {
- 	power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>;
- };

target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -160,6 +160,10 @@
+@@ -156,6 +156,10 @@
  		switch@0 {
  			compatible = "mediatek,mt7531";
  			reg = <0>;

target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch

@@ -95,7 +95,7 @@ Signed-off-by: Daniel Golle <[email protected]>
 
 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -339,7 +339,7 @@
+@@ -346,7 +346,7 @@
  		#interrupt-cells = <3>;
  		interrupt-parent = <&gic>;
  		reg = <0 0x10310000 0 0x1000>,

target/linux/mediatek/patches-6.1/191-v5.19-arm64-dts-mt7622-specify-the-L2-cache-topology.patch

@@ -1,132 +0,0 @@
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-Subject: [PATCH] arm64: dts: mt7622: specify the L2 cache topology
-Date: Thu, 28 Apr 2022 23:57:55 +0100
-Message-Id: <[email protected]>
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-
-On an MT7622 system, the kernel complains of not being able to detect the cache
-hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in
-order to fix this.
-
-Signed-off-by: Rui Salvaterra <[email protected]>
----
- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -80,6 +80,7 @@
- 			enable-method = "psci";
- 			clock-frequency = <1300000000>;
- 			cci-control-port = <&cci_control2>;
-+			next-level-cache = <&L2>;
- 		};
- 
- 		cpu1: cpu@1 {
-@@ -94,6 +95,12 @@
- 			enable-method = "psci";
- 			clock-frequency = <1300000000>;
- 			cci-control-port = <&cci_control2>;
-+			next-level-cache = <&L2>;
-+		};
-+
-+		L2: l2-cache {
-+			compatible = "cache";
-+			cache-level = <2>;
- 		};
- 	};
- 

target/linux/mediatek/patches-6.1/192-v5.19-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch

@@ -1,122 +0,0 @@
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-Subject: [PATCH] arm64: dts: mt7622: specify the number of DMA requests
-Date: Fri, 29 Apr 2022 09:42:25 +0100
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-
-The MT7622 device tree never bothered to specify the number of virtual DMA
-channels for the HSDMA controller, always falling back to the default value of
-3. Make this value explicit, in order to avoid the following dmesg notification:
-
-mtk_hsdma 1b007000.dma-controller: Using 3 as missing dma-requests property
-
-Signed-off-by: Rui Salvaterra <[email protected]>
----
- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -942,6 +942,7 @@
- 		clock-names = "hsdma";
- 		power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
- 		#dma-cells = <1>;
-+		dma-requests = <3>;
- 	};
- 
- 	pcie_mirror: pcie-mirror@10000400 {

target/linux/mediatek/patches-6.1/200-phy-phy-mtk-tphy-Add-hifsys-support.patch

@@ -9,16 +9,16 @@ Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support
 
 --- a/drivers/phy/mediatek/phy-mtk-tphy.c
 +++ b/drivers/phy/mediatek/phy-mtk-tphy.c
-@@ -18,6 +18,8 @@
+@@ -17,6 +17,8 @@
  #include <linux/phy/phy.h>
  #include <linux/platform_device.h>
  #include <linux/regmap.h>
 +#include <linux/mfd/syscon.h>
 +#include <linux/regmap.h>
  
- /* version V1 sub-banks offset base address */
- /* banks shared by multiple phys */
-@@ -311,6 +313,9 @@
+ #include "phy-mtk-io.h"
+ 
+@@ -264,6 +266,9 @@
  
  #define TPHY_CLKS_CNT	2
  
@@ -28,7 +28,7 @@ Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support
  enum mtk_phy_version {
  	MTK_PHY_V1 = 1,
  	MTK_PHY_V2,
-@@ -377,6 +382,7 @@ struct mtk_tphy {
+@@ -331,6 +336,7 @@ struct mtk_tphy {
  	void __iomem *sif_base;	/* only shared sif */
  	const struct mtk_phy_pdata *pdata;
  	struct mtk_phy_instance **phys;
@@ -36,7 +36,7 @@ Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support
  	int nphys;
  	int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
  	int src_coef; /* coefficient for slew rate calibrate */
-@@ -730,6 +736,10 @@ static void pcie_phy_instance_init(struc
+@@ -596,6 +602,10 @@ static void pcie_phy_instance_init(struc
  	if (tphy->pdata->version != MTK_PHY_V1)
  		return;
  
@@ -44,10 +44,10 @@ Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support
 +		regmap_update_bits(tphy->hif, HIF_SYSCFG1,
 +				   HIF_SYSCFG1_PHY2_MASK, 0);
 +
- 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
- 	tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H);
- 	tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2);
-@@ -1437,6 +1447,16 @@ static int mtk_tphy_probe(struct platfor
+ 	mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0,
+ 			    P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
+ 			    FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) |
+@@ -1241,6 +1251,16 @@ static int mtk_tphy_probe(struct platfor
  					 &tphy->src_coef);
  	}
  

target/linux/mediatek/patches-6.1/210-v6.1-pinctrl-mediatek-add-support-for-MT7986-SoC.patch

@@ -1,26 +0,0 @@
---- a/drivers/pinctrl/mediatek/Kconfig
-+++ b/drivers/pinctrl/mediatek/Kconfig
-@@ -120,6 +120,13 @@ config PINCTRL_MT7622
- 	default ARM64 && ARCH_MEDIATEK
- 	select PINCTRL_MTK_MOORE
- 
-+config PINCTRL_MT7986
-+	bool "Mediatek MT7986 pin control"
-+	depends on OF
-+	depends on ARM64 || COMPILE_TEST
-+	default ARM64 && ARCH_MEDIATEK
-+	select PINCTRL_MTK_MOORE
-+
- config PINCTRL_MT8167
- 	bool "Mediatek MT8167 pin control"
- 	depends on OF
---- a/drivers/pinctrl/mediatek/Makefile
-+++ b/drivers/pinctrl/mediatek/Makefile
-@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MT6797)	+= pinctrl-
- obj-$(CONFIG_PINCTRL_MT7622)	+= pinctrl-mt7622.o
- obj-$(CONFIG_PINCTRL_MT7623)	+= pinctrl-mt7623.o
- obj-$(CONFIG_PINCTRL_MT7629)	+= pinctrl-mt7629.o
-+obj-$(CONFIG_PINCTRL_MT7986)	+= pinctrl-mt7986.o
- obj-$(CONFIG_PINCTRL_MT8167)	+= pinctrl-mt8167.o
- obj-$(CONFIG_PINCTRL_MT8173)	+= pinctrl-mt8173.o
- obj-$(CONFIG_PINCTRL_MT8183)	+= pinctrl-mt8183.o

target/linux/mediatek/patches-6.1/210-v6.2-pinctrl-mt7986-allow-configuring-uart-rx-tx-and-rts-.patch

@@ -0,0 +1,88 @@
+From f76e8bc416bebb0f7b9f57b1247eae945421c0b9 Mon Sep 17 00:00:00 2001
+From: Sam Shih <[email protected]>
+Date: Sat, 8 Oct 2022 18:48:06 +0200
+Subject: [PATCH 1/2] pinctrl: mt7986: allow configuring uart rx/tx and rts/cts
+ separately
+
+Some mt7986 boards use uart rts/cts pins as gpio,
+This patch allows to change rts/cts to gpio mode, but keep
+rx/tx as UART function.
+
+Signed-off-by: Frank Wunderlich <[email protected]>
+Signed-off-by: Sam Shih <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Linus Walleij <[email protected]>
+---
+ drivers/pinctrl/mediatek/pinctrl-mt7986.c | 32 ++++++++++++++++++-----
+ 1 file changed, 25 insertions(+), 7 deletions(-)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c
++++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
+@@ -675,11 +675,17 @@ static int mt7986_uart1_1_funcs[] = { 4,
+ static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
+ static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
+ 
+-static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, };
+-static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, };
++static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, };
++static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, };
+ 
+-static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, };
+-static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, };
++static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, };
++static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, };
++
++static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, };
++static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, };
++
++static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, };
++static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, };
+ 
+ static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
+ static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
+@@ -708,6 +714,12 @@ static int mt7986_pcie_reset_funcs[] = {
+ static int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
+ static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
+ 
++static int mt7986_uart1_rx_tx_pins[] = { 42, 43, };
++static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, };
++
++static int mt7986_uart1_cts_rts_pins[] = { 44, 45, };
++static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, };
++
+ static int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
+ static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
+ 
+@@ -749,6 +761,8 @@ static const struct group_desc mt7986_gr
+ 	PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led),
+ 	PINCTRL_PIN_GROUP("i2c", mt7986_i2c),
+ 	PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0),
++	PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx),
++	PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts),
+ 	PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk),
+ 	PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake),
+ 	PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0),
+@@ -760,8 +774,10 @@ static const struct group_desc mt7986_gr
+ 	PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1),
+ 	PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1),
+ 	PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2),
+-	PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2),
+-	PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0),
++	PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx),
++	PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts),
++	PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx),
++	PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts),
+ 	PINCTRL_PIN_GROUP("spi0", mt7986_spi0),
+ 	PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold),
+ 	PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1),
+@@ -800,7 +816,9 @@ static const char *mt7986_pwm_groups[] =
+ static const char *mt7986_spi_groups[] = {
+ 	"spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", };
+ static const char *mt7986_uart_groups[] = {
+-	"uart1_0", "uart1_1", "uart1_2", "uart1_3_rx_tx", "uart1_3_cts_rts",
++	"uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts",
++	"uart1_2_rx_tx", "uart1_2_cts_rts",
++	"uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts",
+ 	"uart2_0", "uart2_1", "uart0", "uart1", "uart2",
+ };
+ static const char *mt7986_wdt_groups[] = { "watchdog", };

target/linux/mediatek/patches-6.1/211-v5.16-clk-mediatek-Add-API-for-clock-resource-recycle.patch

@@ -1,28 +0,0 @@
---- a/drivers/clk/mediatek/clk-mtk.c
-+++ b/drivers/clk/mediatek/clk-mtk.c
-@@ -43,6 +43,15 @@ err_out:
- 	return NULL;
- }
- 
-+void mtk_free_clk_data(struct clk_onecell_data *clk_data)
-+{
-+	if (!clk_data)
-+		return;
-+
-+	kfree(clk_data->clks);
-+	kfree(clk_data);
-+}
-+
- void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
- 		int num, struct clk_onecell_data *clk_data)
- {
---- a/drivers/clk/mediatek/clk-mtk.h
-+++ b/drivers/clk/mediatek/clk-mtk.h
-@@ -202,6 +202,7 @@ void mtk_clk_register_dividers(const str
- 				struct clk_onecell_data *clk_data);
- 
- struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
-+void mtk_free_clk_data(struct clk_onecell_data *clk_data);
- 
- #define HAVE_RST_BAR	BIT(0)
- #define PLL_AO		BIT(1)

target/linux/mediatek/patches-6.1/211-v6.2-pinctrl-mediatek-add-pull_type-attribute-for-mediate.patch

@@ -0,0 +1,100 @@
+From 822d774abbcc66b811e28c68b59b40b964ba5b46 Mon Sep 17 00:00:00 2001
+From: Sam Shih <[email protected]>
+Date: Sun, 6 Nov 2022 09:01:13 +0100
+Subject: [PATCH 2/2] pinctrl: mediatek: add pull_type attribute for mediatek
+ MT7986 SoC
+
+Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature")
+add SoC specify 'pull_type' attribute for bias configuration.
+
+This patch add pull_type attribute to pinctrl-mt7986.c, and make
+bias_set_combo and bias_get_combo available to mediatek MT7986 SoC.
+
+Signed-off-by: Sam Shih <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Linus Walleij <[email protected]>
+---
+ drivers/pinctrl/mediatek/pinctrl-mt7986.c | 56 +++++++++++++++++++++++
+ 1 file changed, 56 insertions(+)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c
++++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
+@@ -407,6 +407,60 @@ static const struct mtk_pin_field_calc m
+ 	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
+ };
+ 
++static const unsigned int mt7986_pull_type[] = {
++	MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
++	MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
++	MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
++	MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
++	MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
++	MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
++	MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
++	MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
++	MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
++	MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
++	MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
++	MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
++	MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
++	MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
++	MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
++	MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
++	MTK_PULL_PU_PD_TYPE,/*100*/
++};
++
+ static const struct mtk_pin_reg_calc mt7986_reg_cals[] = {
+ 	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range),
+ 	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range),
+@@ -868,6 +922,7 @@ static struct mtk_pin_soc mt7986a_data =
+ 	.ies_present = false,
+ 	.base_names = mt7986_pinctrl_register_base_names,
+ 	.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
++	.pull_type = mt7986_pull_type,
+ 	.bias_set_combo = mtk_pinconf_bias_set_combo,
+ 	.bias_get_combo = mtk_pinconf_bias_get_combo,
+ 	.drive_set = mtk_pinconf_drive_set_rev1,
+@@ -889,6 +944,7 @@ static struct mtk_pin_soc mt7986b_data =
+ 	.ies_present = false,
+ 	.base_names = mt7986_pinctrl_register_base_names,
+ 	.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
++	.pull_type = mt7986_pull_type,
+ 	.bias_set_combo = mtk_pinconf_bias_set_combo,
+ 	.bias_get_combo = mtk_pinconf_bias_get_combo,
+ 	.drive_set = mtk_pinconf_drive_set_rev1,

target/linux/mediatek/patches-6.1/212-v5.17-clk-mediatek-add-mt7986-clock-support.patch

@@ -1,39 +0,0 @@
---- a/drivers/clk/mediatek/Kconfig
-+++ b/drivers/clk/mediatek/Kconfig
-@@ -344,6 +344,23 @@ config COMMON_CLK_MT7629_HIFSYS
- 	  This driver supports MediaTek MT7629 HIFSYS clocks providing
- 	  to PCI-E and USB.
- 
-+config COMMON_CLK_MT7986
-+	bool "Clock driver for MediaTek MT7986"
-+	depends on ARCH_MEDIATEK || COMPILE_TEST
-+	select COMMON_CLK_MEDIATEK
-+	default ARCH_MEDIATEK
-+	help
-+	  This driver supports MediaTek MT7986 basic clocks and clocks
-+	  required for various periperals found on MediaTek.
-+
-+config COMMON_CLK_MT7986_ETHSYS
-+	bool "Clock driver for MediaTek MT7986 ETHSYS"
-+	depends on COMMON_CLK_MT7986
-+	default COMMON_CLK_MT7986
-+	help
-+	  This driver add support for clocks for Ethernet and SGMII
-+	  required on MediaTek MT7986 SoC.
-+
- config COMMON_CLK_MT8135
- 	bool "Clock driver for MediaTek MT8135"
- 	depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
---- a/drivers/clk/mediatek/Makefile
-+++ b/drivers/clk/mediatek/Makefile
-@@ -46,6 +46,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) +
- obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o
- obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
- obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
-+obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o
-+obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
-+obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
-+obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o
- obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
- obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o
- obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o

target/linux/mediatek/patches-6.1/213-spi-mediatek-add-mt7986-spi-support.patch

@@ -1,917 +0,0 @@
-From 7d99750f96fc6904d54affebdc8c9b0bfae1e9e8 Mon Sep 17 00:00:00 2001
-From: Sam Shih <[email protected]>
-Date: Sun, 17 Apr 2022 11:40:22 +0800
-Subject: [PATCH] spi: mediatek: backport document and driver to support mt7986
- spi design
-
-this patch add the support of ipm design and upgrade devicetree binding
-
-The patch is comming from following threads
-- https://lore.kernel.org/all/[email protected]/
-- https://lore.kernel.org/all/[email protected]/
-
-Signed-off-by: Sam Shih <[email protected]>
----
- .../bindings/spi/mediatek,spi-mt65xx.yaml     | 111 ++++
- drivers/spi/spi-mt65xx.c                      | 509 ++++++++++++++++--
- 2 files changed, 572 insertions(+), 48 deletions(-)
- create mode 100644 Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
-@@ -0,0 +1,111 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: SPI Bus controller for MediaTek ARM SoCs
-+
-+maintainers:
-+  - Leilk Liu <[email protected]>
-+
-+allOf:
-+  - $ref: "/schemas/spi/spi-controller.yaml#"
-+
-+properties:
-+  compatible:
-+    oneOf:
-+      - items:
-+          - enum:
-+              - mediatek,mt7629-spi
-+          - const: mediatek,mt7622-spi
-+      - items:
-+          - enum:
-+              - mediatek,mt8516-spi
-+          - const: mediatek,mt2712-spi
-+      - items:
-+          - enum:
-+              - mediatek,mt6779-spi
-+              - mediatek,mt8186-spi
-+              - mediatek,mt8192-spi
-+              - mediatek,mt8195-spi
-+          - const: mediatek,mt6765-spi
-+      - items:
-+          - enum:
-+              - mediatek,mt7986-spi-ipm
-+          - const: mediatek,spi-ipm
-+      - items:
-+          - enum:
-+              - mediatek,mt2701-spi
-+              - mediatek,mt2712-spi
-+              - mediatek,mt6589-spi
-+              - mediatek,mt6765-spi
-+              - mediatek,mt6893-spi
-+              - mediatek,mt7622-spi
-+              - mediatek,mt8135-spi
-+              - mediatek,mt8173-spi
-+              - mediatek,mt8183-spi
-+
-+  reg:
-+    maxItems: 1
-+
-+  interrupts:
-+    maxItems: 1
-+
-+  clocks:
-+    minItems: 3
-+    items:
-+      - description: clock used for the parent clock
-+      - description: clock used for the muxes clock
-+      - description: clock used for the clock gate
-+      - description: clock used for the AHB bus, this clock is optional
-+
-+  clock-names:
-+    minItems: 3
-+    items:
-+      - const: parent-clk
-+      - const: sel-clk
-+      - const: spi-clk
-+      - const: hclk
-+
-+  mediatek,pad-select:
-+    $ref: /schemas/types.yaml#/definitions/uint32-array
-+    minItems: 1
-+    maxItems: 4
-+    items:
-+      enum: [0, 1, 2, 3]
-+    description:
-+      specify which pins group(ck/mi/mo/cs) spi controller used.
-+      This is an array.
-+
-+required:
-+  - compatible
-+  - reg
-+  - interrupts
-+  - clocks
-+  - clock-names
-+  - '#address-cells'
-+  - '#size-cells'
-+
-+unevaluatedProperties: false
-+
-+examples:
-+  - |
-+    #include <dt-bindings/clock/mt8173-clk.h>
-+    #include <dt-bindings/gpio/gpio.h>
-+    #include <dt-bindings/interrupt-controller/arm-gic.h>
-+    #include <dt-bindings/interrupt-controller/irq.h>
-+
-+    spi@1100a000 {
-+      compatible = "mediatek,mt8173-spi";
-+      #address-cells = <1>;
-+      #size-cells = <0>;
-+      reg = <0x1100a000 0x1000>;
-+      interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
-+      clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
-+               <&topckgen CLK_TOP_SPI_SEL>,
-+               <&pericfg CLK_PERI_SPI0>;
-+      clock-names = "parent-clk", "sel-clk", "spi-clk";
-+      cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>;
-+      mediatek,pad-select = <1>, <0>;
-+    };
---- a/drivers/spi/spi-mt65xx.c
-+++ b/drivers/spi/spi-mt65xx.c
-@@ -12,11 +12,12 @@
- #include <linux/ioport.h>
- #include <linux/module.h>
- #include <linux/of.h>
--#include <linux/of_gpio.h>
-+#include <linux/gpio/consumer.h>
- #include <linux/platform_device.h>
- #include <linux/platform_data/spi-mt65xx.h>
- #include <linux/pm_runtime.h>
- #include <linux/spi/spi.h>
-+#include <linux/spi/spi-mem.h>
- #include <linux/dma-mapping.h>
- 
- #define SPI_CFG0_REG                      0x0000
-@@ -31,6 +32,7 @@
- #define SPI_CFG2_REG                      0x0028
- #define SPI_TX_SRC_REG_64                 0x002c
- #define SPI_RX_DST_REG_64                 0x0030
-+#define SPI_CFG3_IPM_REG                  0x0040
- 
- #define SPI_CFG0_SCK_HIGH_OFFSET          0
- #define SPI_CFG0_SCK_LOW_OFFSET           8
-@@ -51,6 +53,7 @@
- #define SPI_CFG1_CS_IDLE_MASK             0xff
- #define SPI_CFG1_PACKET_LOOP_MASK         0xff00
- #define SPI_CFG1_PACKET_LENGTH_MASK       0x3ff0000
-+#define SPI_CFG1_IPM_PACKET_LENGTH_MASK   GENMASK(31, 16)
- #define SPI_CFG2_SCK_HIGH_OFFSET          0
- #define SPI_CFG2_SCK_LOW_OFFSET           16
- 
-@@ -71,6 +74,24 @@
- #define SPI_CMD_TX_ENDIAN            BIT(15)
- #define SPI_CMD_FINISH_IE            BIT(16)
- #define SPI_CMD_PAUSE_IE             BIT(17)
-+#define SPI_CMD_IPM_NONIDLE_MODE     BIT(19)
-+#define SPI_CMD_IPM_SPIM_LOOP        BIT(21)
-+#define SPI_CMD_IPM_GET_TICKDLY_OFFSET    22
-+
-+#define SPI_CMD_IPM_GET_TICKDLY_MASK	GENMASK(24, 22)
-+
-+#define PIN_MODE_CFG(x)	((x) / 2)
-+
-+#define SPI_CFG3_IPM_HALF_DUPLEX_DIR		BIT(2)
-+#define SPI_CFG3_IPM_HALF_DUPLEX_EN		BIT(3)
-+#define SPI_CFG3_IPM_XMODE_EN			BIT(4)
-+#define SPI_CFG3_IPM_NODATA_FLAG		BIT(5)
-+#define SPI_CFG3_IPM_CMD_BYTELEN_OFFSET		8
-+#define SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET	12
-+
-+#define SPI_CFG3_IPM_CMD_PIN_MODE_MASK		GENMASK(1, 0)
-+#define SPI_CFG3_IPM_CMD_BYTELEN_MASK		GENMASK(11, 8)
-+#define SPI_CFG3_IPM_ADDR_BYTELEN_MASK		GENMASK(15, 12)
- 
- #define MT8173_SPI_MAX_PAD_SEL 3
- 
-@@ -81,6 +102,9 @@
- 
- #define MTK_SPI_MAX_FIFO_SIZE 32U
- #define MTK_SPI_PACKET_SIZE 1024
-+#define MTK_SPI_IPM_PACKET_SIZE SZ_64K
-+#define MTK_SPI_IPM_PACKET_LOOP SZ_256
-+
- #define MTK_SPI_32BITS_MASK  (0xffffffff)
- 
- #define DMA_ADDR_EXT_BITS (36)
-@@ -96,6 +120,8 @@ struct mtk_spi_compatible {
- 	bool dma_ext;
- 	/* some IC no need unprepare SPI clk */
- 	bool no_need_unprepare;
-+	/* IPM design adjust and extend register to support more features */
-+	bool ipm_design;
- };
- 
- struct mtk_spi {
-@@ -103,7 +129,7 @@ struct mtk_spi {
- 	u32 state;
- 	int pad_num;
- 	u32 *pad_sel;
--	struct clk *parent_clk, *sel_clk, *spi_clk;
-+	struct clk *parent_clk, *sel_clk, *spi_clk, *spi_hclk;
- 	struct spi_transfer *cur_transfer;
- 	u32 xfer_len;
- 	u32 num_xfered;
-@@ -111,6 +137,11 @@ struct mtk_spi {
- 	u32 tx_sgl_len, rx_sgl_len;
- 	const struct mtk_spi_compatible *dev_comp;
- 	u32 spi_clk_hz;
-+	struct completion spimem_done;
-+	bool use_spimem;
-+	struct device *dev;
-+	dma_addr_t tx_dma;
-+	dma_addr_t rx_dma;
- };
- 
- static const struct mtk_spi_compatible mtk_common_compat;
-@@ -119,6 +150,12 @@ static const struct mtk_spi_compatible m
- 	.must_tx = true,
- };
- 
-+static const struct mtk_spi_compatible mtk_ipm_compat = {
-+	.enhance_timing = true,
-+	.dma_ext = true,
-+	.ipm_design = true,
-+};
-+
- static const struct mtk_spi_compatible mt6765_compat = {
- 	.need_pad_sel = true,
- 	.must_tx = true,
-@@ -160,6 +197,9 @@ static const struct mtk_chip_config mtk_
- };
- 
- static const struct of_device_id mtk_spi_of_match[] = {
-+	{ .compatible = "mediatek,spi-ipm",
-+		.data = (void *)&mtk_ipm_compat,
-+	},
- 	{ .compatible = "mediatek,mt2701-spi",
- 		.data = (void *)&mtk_common_compat,
- 	},
-@@ -278,12 +318,11 @@ static int mtk_spi_set_hw_cs_timing(stru
- 	return 0;
- }
- 
--static int mtk_spi_prepare_message(struct spi_master *master,
--				   struct spi_message *msg)
-+static int mtk_spi_hw_init(struct spi_master *master,
-+			   struct spi_device *spi)
- {
- 	u16 cpha, cpol;
- 	u32 reg_val;
--	struct spi_device *spi = msg->spi;
- 	struct mtk_chip_config *chip_config = spi->controller_data;
- 	struct mtk_spi *mdata = spi_master_get_devdata(master);
- 
-@@ -291,6 +330,15 @@ static int mtk_spi_prepare_message(struc
- 	cpol = spi->mode & SPI_CPOL ? 1 : 0;
- 
- 	reg_val = readl(mdata->base + SPI_CMD_REG);
-+	if (mdata->dev_comp->ipm_design) {
-+		/* SPI transfer without idle time until packet length done */
-+		reg_val |= SPI_CMD_IPM_NONIDLE_MODE;
-+		if (spi->mode & SPI_LOOP)
-+			reg_val |= SPI_CMD_IPM_SPIM_LOOP;
-+		else
-+			reg_val &= ~SPI_CMD_IPM_SPIM_LOOP;
-+	}
-+
- 	if (cpha)
- 		reg_val |= SPI_CMD_CPHA;
- 	else
-@@ -348,23 +396,39 @@ static int mtk_spi_prepare_message(struc
- 		       mdata->base + SPI_PAD_SEL_REG);
- 
- 	/* tick delay */
--	reg_val = readl(mdata->base + SPI_CFG1_REG);
- 	if (mdata->dev_comp->enhance_timing) {
--		reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
--		reg_val |= ((chip_config->tick_delay & 0x7)
--			    << SPI_CFG1_GET_TICK_DLY_OFFSET);
-+		if (mdata->dev_comp->ipm_design) {
-+			reg_val = readl(mdata->base + SPI_CMD_REG);
-+			reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
-+			reg_val |= ((chip_config->tick_delay & 0x7)
-+				    << SPI_CMD_IPM_GET_TICKDLY_OFFSET);
-+			writel(reg_val, mdata->base + SPI_CMD_REG);
-+		} else {
-+			reg_val = readl(mdata->base + SPI_CFG1_REG);
-+			reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
-+			reg_val |= ((chip_config->tick_delay & 0x7)
-+				    << SPI_CFG1_GET_TICK_DLY_OFFSET);
-+			writel(reg_val, mdata->base + SPI_CFG1_REG);
-+		}
- 	} else {
-+		reg_val = readl(mdata->base + SPI_CFG1_REG);
- 		reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
- 		reg_val |= ((chip_config->tick_delay & 0x3)
- 			    << SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
-+		writel(reg_val, mdata->base + SPI_CFG1_REG);
- 	}
--	writel(reg_val, mdata->base + SPI_CFG1_REG);
- 
- 	/* set hw cs timing */
- 	mtk_spi_set_hw_cs_timing(spi);
- 	return 0;
- }
- 
-+static int mtk_spi_prepare_message(struct spi_master *master,
-+				   struct spi_message *msg)
-+{
-+	return mtk_spi_hw_init(master, msg->spi);
-+}
-+
- static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
- {
- 	u32 reg_val;
-@@ -386,13 +450,13 @@ static void mtk_spi_set_cs(struct spi_de
- }
- 
- static void mtk_spi_prepare_transfer(struct spi_master *master,
--				     struct spi_transfer *xfer)
-+				     u32 speed_hz)
- {
- 	u32 div, sck_time, reg_val;
- 	struct mtk_spi *mdata = spi_master_get_devdata(master);
- 
--	if (xfer->speed_hz < mdata->spi_clk_hz / 2)
--		div = DIV_ROUND_UP(mdata->spi_clk_hz, xfer->speed_hz);
-+	if (speed_hz < mdata->spi_clk_hz / 2)
-+		div = DIV_ROUND_UP(mdata->spi_clk_hz, speed_hz);
- 	else
- 		div = 1;
- 
-@@ -423,12 +487,24 @@ static void mtk_spi_setup_packet(struct
- 	u32 packet_size, packet_loop, reg_val;
- 	struct mtk_spi *mdata = spi_master_get_devdata(master);
- 
--	packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
-+	if (mdata->dev_comp->ipm_design)
-+		packet_size = min_t(u32,
-+				    mdata->xfer_len,
-+				    MTK_SPI_IPM_PACKET_SIZE);
-+	else
-+		packet_size = min_t(u32,
-+				    mdata->xfer_len,
-+				    MTK_SPI_PACKET_SIZE);
-+
- 	packet_loop = mdata->xfer_len / packet_size;
- 
- 	reg_val = readl(mdata->base + SPI_CFG1_REG);
--	reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
-+	if (mdata->dev_comp->ipm_design)
-+		reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK;
-+	else
-+		reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK;
- 	reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
-+	reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK;
- 	reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
- 	writel(reg_val, mdata->base + SPI_CFG1_REG);
- }
-@@ -523,7 +599,7 @@ static int mtk_spi_fifo_transfer(struct
- 	mdata->cur_transfer = xfer;
- 	mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
- 	mdata->num_xfered = 0;
--	mtk_spi_prepare_transfer(master, xfer);
-+	mtk_spi_prepare_transfer(master, xfer->speed_hz);
- 	mtk_spi_setup_packet(master);
- 
- 	if (xfer->tx_buf) {
-@@ -556,7 +632,7 @@ static int mtk_spi_dma_transfer(struct s
- 	mdata->cur_transfer = xfer;
- 	mdata->num_xfered = 0;
- 
--	mtk_spi_prepare_transfer(master, xfer);
-+	mtk_spi_prepare_transfer(master, xfer->speed_hz);
- 
- 	cmd = readl(mdata->base + SPI_CMD_REG);
- 	if (xfer->tx_buf)
-@@ -591,6 +667,19 @@ static int mtk_spi_transfer_one(struct s
- 				struct spi_device *spi,
- 				struct spi_transfer *xfer)
- {
-+	struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
-+	u32 reg_val = 0;
-+
-+	/* prepare xfer direction and duplex mode */
-+	if (mdata->dev_comp->ipm_design) {
-+		if (!xfer->tx_buf || !xfer->rx_buf) {
-+			reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
-+			if (xfer->rx_buf)
-+				reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
-+		}
-+		writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
-+	}
-+
- 	if (master->can_dma(master, spi, xfer))
- 		return mtk_spi_dma_transfer(master, spi, xfer);
- 	else
-@@ -614,8 +703,9 @@ static int mtk_spi_setup(struct spi_devi
- 	if (!spi->controller_data)
- 		spi->controller_data = (void *)&mtk_default_chip_info;
- 
--	if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio))
--		gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
-+	if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod)
-+		/* CS de-asserted, gpiolib will handle inversion */
-+		gpiod_direction_output(spi->cs_gpiod, 0);
- 
- 	return 0;
- }
-@@ -633,6 +723,12 @@ static irqreturn_t mtk_spi_interrupt(int
- 	else
- 		mdata->state = MTK_SPI_IDLE;
- 
-+	/* SPI-MEM ops */
-+	if (mdata->use_spimem) {
-+		complete(&mdata->spimem_done);
-+		return IRQ_HANDLED;
-+	}
-+
- 	if (!master->can_dma(master, NULL, trans)) {
- 		if (trans->rx_buf) {
- 			cnt = mdata->xfer_len / 4;
-@@ -716,6 +812,274 @@ static irqreturn_t mtk_spi_interrupt(int
- 	return IRQ_HANDLED;
- }
- 
-+static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem,
-+				      struct spi_mem_op *op)
-+{
-+	int opcode_len;
-+
-+	if (op->data.dir != SPI_MEM_NO_DATA) {
-+		opcode_len = 1 + op->addr.nbytes + op->dummy.nbytes;
-+		if (opcode_len + op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) {
-+			op->data.nbytes = MTK_SPI_IPM_PACKET_SIZE - opcode_len;
-+			/* force data buffer dma-aligned. */
-+			op->data.nbytes -= op->data.nbytes % 4;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static bool mtk_spi_mem_supports_op(struct spi_mem *mem,
-+				    const struct spi_mem_op *op)
-+{
-+	if (!spi_mem_default_supports_op(mem, op))
-+		return false;
-+
-+	if (op->addr.nbytes && op->dummy.nbytes &&
-+	    op->addr.buswidth != op->dummy.buswidth)
-+		return false;
-+
-+	if (op->addr.nbytes + op->dummy.nbytes > 16)
-+		return false;
-+
-+	if (op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) {
-+		if (op->data.nbytes / MTK_SPI_IPM_PACKET_SIZE >
-+		    MTK_SPI_IPM_PACKET_LOOP ||
-+		    op->data.nbytes % MTK_SPI_IPM_PACKET_SIZE != 0)
-+			return false;
-+	}
-+
-+	return true;
-+}
-+
-+static void mtk_spi_mem_setup_dma_xfer(struct spi_master *master,
-+				       const struct spi_mem_op *op)
-+{
-+	struct mtk_spi *mdata = spi_master_get_devdata(master);
-+
-+	writel((u32)(mdata->tx_dma & MTK_SPI_32BITS_MASK),
-+	       mdata->base + SPI_TX_SRC_REG);
-+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
-+	if (mdata->dev_comp->dma_ext)
-+		writel((u32)(mdata->tx_dma >> 32),
-+		       mdata->base + SPI_TX_SRC_REG_64);
-+#endif
-+
-+	if (op->data.dir == SPI_MEM_DATA_IN) {
-+		writel((u32)(mdata->rx_dma & MTK_SPI_32BITS_MASK),
-+		       mdata->base + SPI_RX_DST_REG);
-+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
-+		if (mdata->dev_comp->dma_ext)
-+			writel((u32)(mdata->rx_dma >> 32),
-+			       mdata->base + SPI_RX_DST_REG_64);
-+#endif
-+	}
-+}
-+
-+static int mtk_spi_transfer_wait(struct spi_mem *mem,
-+				 const struct spi_mem_op *op)
-+{
-+	struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master);
-+	/*
-+	 * For each byte we wait for 8 cycles of the SPI clock.
-+	 * Since speed is defined in Hz and we want milliseconds,
-+	 * so it should be 8 * 1000.
-+	 */
-+	u64 ms = 8000LL;
-+
-+	if (op->data.dir == SPI_MEM_NO_DATA)
-+		ms *= 32; /* prevent we may get 0 for short transfers. */
-+	else
-+		ms *= op->data.nbytes;
-+	ms = div_u64(ms, mem->spi->max_speed_hz);
-+	ms += ms + 1000; /* 1s tolerance */
-+
-+	if (ms > UINT_MAX)
-+		ms = UINT_MAX;
-+
-+	if (!wait_for_completion_timeout(&mdata->spimem_done,
-+					 msecs_to_jiffies(ms))) {
-+		dev_err(mdata->dev, "spi-mem transfer timeout\n");
-+		return -ETIMEDOUT;
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_spi_mem_exec_op(struct spi_mem *mem,
-+			       const struct spi_mem_op *op)
-+{
-+	struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master);
-+	u32 reg_val, nio, tx_size;
-+	char *tx_tmp_buf, *rx_tmp_buf;
-+	int ret = 0;
-+
-+	mdata->use_spimem = true;
-+	reinit_completion(&mdata->spimem_done);
-+
-+	mtk_spi_reset(mdata);
-+	mtk_spi_hw_init(mem->spi->master, mem->spi);
-+	mtk_spi_prepare_transfer(mem->spi->master, mem->spi->max_speed_hz);
-+
-+	reg_val = readl(mdata->base + SPI_CFG3_IPM_REG);
-+	/* opcode byte len */
-+	reg_val &= ~SPI_CFG3_IPM_CMD_BYTELEN_MASK;
-+	reg_val |= 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET;
-+
-+	/* addr & dummy byte len */
-+	reg_val &= ~SPI_CFG3_IPM_ADDR_BYTELEN_MASK;
-+	if (op->addr.nbytes || op->dummy.nbytes)
-+		reg_val |= (op->addr.nbytes + op->dummy.nbytes) <<
-+			    SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET;
-+
-+	/* data byte len */
-+	if (op->data.dir == SPI_MEM_NO_DATA) {
-+		reg_val |= SPI_CFG3_IPM_NODATA_FLAG;
-+		writel(0, mdata->base + SPI_CFG1_REG);
-+	} else {
-+		reg_val &= ~SPI_CFG3_IPM_NODATA_FLAG;
-+		mdata->xfer_len = op->data.nbytes;
-+		mtk_spi_setup_packet(mem->spi->master);
-+	}
-+
-+	if (op->addr.nbytes || op->dummy.nbytes) {
-+		if (op->addr.buswidth == 1 || op->dummy.buswidth == 1)
-+			reg_val |= SPI_CFG3_IPM_XMODE_EN;
-+		else
-+			reg_val &= ~SPI_CFG3_IPM_XMODE_EN;
-+	}
-+
-+	if (op->addr.buswidth == 2 ||
-+	    op->dummy.buswidth == 2 ||
-+	    op->data.buswidth == 2)
-+		nio = 2;
-+	else if (op->addr.buswidth == 4 ||
-+		 op->dummy.buswidth == 4 ||
-+		 op->data.buswidth == 4)
-+		nio = 4;
-+	else
-+		nio = 1;
-+
-+	reg_val &= ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK;
-+	reg_val |= PIN_MODE_CFG(nio);
-+
-+	reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
-+	if (op->data.dir == SPI_MEM_DATA_IN)
-+		reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
-+	else
-+		reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR;
-+	writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
-+
-+	tx_size = 1 + op->addr.nbytes + op->dummy.nbytes;
-+	if (op->data.dir == SPI_MEM_DATA_OUT)
-+		tx_size += op->data.nbytes;
-+
-+	tx_size = max_t(u32, tx_size, 32);
-+
-+	tx_tmp_buf = kzalloc(tx_size, GFP_KERNEL | GFP_DMA);
-+	if (!tx_tmp_buf) {
-+		mdata->use_spimem = false;
-+		return -ENOMEM;
-+	}
-+
-+	tx_tmp_buf[0] = op->cmd.opcode;
-+
-+	if (op->addr.nbytes) {
-+		int i;
-+
-+		for (i = 0; i < op->addr.nbytes; i++)
-+			tx_tmp_buf[i + 1] = op->addr.val >>
-+					(8 * (op->addr.nbytes - i - 1));
-+	}
-+
-+	if (op->dummy.nbytes)
-+		memset(tx_tmp_buf + op->addr.nbytes + 1,
-+		       0xff,
-+		       op->dummy.nbytes);
-+
-+	if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
-+		memcpy(tx_tmp_buf + op->dummy.nbytes + op->addr.nbytes + 1,
-+		       op->data.buf.out,
-+		       op->data.nbytes);
-+
-+	mdata->tx_dma = dma_map_single(mdata->dev, tx_tmp_buf,
-+				       tx_size, DMA_TO_DEVICE);
-+	if (dma_mapping_error(mdata->dev, mdata->tx_dma)) {
-+		ret = -ENOMEM;
-+		goto err_exit;
-+	}
-+
-+	if (op->data.dir == SPI_MEM_DATA_IN) {
-+		if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) {
-+			rx_tmp_buf = kzalloc(op->data.nbytes,
-+					     GFP_KERNEL | GFP_DMA);
-+			if (!rx_tmp_buf) {
-+				ret = -ENOMEM;
-+				goto unmap_tx_dma;
-+			}
-+		} else {
-+			rx_tmp_buf = op->data.buf.in;
-+		}
-+
-+		mdata->rx_dma = dma_map_single(mdata->dev,
-+					       rx_tmp_buf,
-+					       op->data.nbytes,
-+					       DMA_FROM_DEVICE);
-+		if (dma_mapping_error(mdata->dev, mdata->rx_dma)) {
-+			ret = -ENOMEM;
-+			goto kfree_rx_tmp_buf;
-+		}
-+	}
-+
-+	reg_val = readl(mdata->base + SPI_CMD_REG);
-+	reg_val |= SPI_CMD_TX_DMA;
-+	if (op->data.dir == SPI_MEM_DATA_IN)
-+		reg_val |= SPI_CMD_RX_DMA;
-+	writel(reg_val, mdata->base + SPI_CMD_REG);
-+
-+	mtk_spi_mem_setup_dma_xfer(mem->spi->master, op);
-+
-+	mtk_spi_enable_transfer(mem->spi->master);
-+
-+	/* Wait for the interrupt. */
-+	ret = mtk_spi_transfer_wait(mem, op);
-+	if (ret)
-+		goto unmap_rx_dma;
-+
-+	/* spi disable dma */
-+	reg_val = readl(mdata->base + SPI_CMD_REG);
-+	reg_val &= ~SPI_CMD_TX_DMA;
-+	if (op->data.dir == SPI_MEM_DATA_IN)
-+		reg_val &= ~SPI_CMD_RX_DMA;
-+	writel(reg_val, mdata->base + SPI_CMD_REG);
-+
-+unmap_rx_dma:
-+	if (op->data.dir == SPI_MEM_DATA_IN) {
-+		dma_unmap_single(mdata->dev, mdata->rx_dma,
-+				 op->data.nbytes, DMA_FROM_DEVICE);
-+		if (!IS_ALIGNED((size_t)op->data.buf.in, 4))
-+			memcpy(op->data.buf.in, rx_tmp_buf, op->data.nbytes);
-+	}
-+kfree_rx_tmp_buf:
-+	if (op->data.dir == SPI_MEM_DATA_IN &&
-+	    !IS_ALIGNED((size_t)op->data.buf.in, 4))
-+		kfree(rx_tmp_buf);
-+unmap_tx_dma:
-+	dma_unmap_single(mdata->dev, mdata->tx_dma,
-+			 tx_size, DMA_TO_DEVICE);
-+err_exit:
-+	kfree(tx_tmp_buf);
-+	mdata->use_spimem = false;
-+
-+	return ret;
-+}
-+
-+static const struct spi_controller_mem_ops mtk_spi_mem_ops = {
-+	.adjust_op_size = mtk_spi_mem_adjust_op_size,
-+	.supports_op = mtk_spi_mem_supports_op,
-+	.exec_op = mtk_spi_mem_exec_op,
-+};
-+
- static int mtk_spi_probe(struct platform_device *pdev)
- {
- 	struct spi_master *master;
-@@ -739,6 +1103,7 @@ static int mtk_spi_probe(struct platform
- 	master->can_dma = mtk_spi_can_dma;
- 	master->setup = mtk_spi_setup;
- 	master->set_cs_timing = mtk_spi_set_hw_cs_timing;
-+	master->use_gpio_descriptors = true;
- 
- 	of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
- 	if (!of_id) {
-@@ -755,6 +1120,14 @@ static int mtk_spi_probe(struct platform
- 
- 	if (mdata->dev_comp->must_tx)
- 		master->flags = SPI_MASTER_MUST_TX;
-+	if (mdata->dev_comp->ipm_design)
-+		master->mode_bits |= SPI_LOOP;
-+
-+	if (mdata->dev_comp->ipm_design) {
-+		mdata->dev = &pdev->dev;
-+		master->mem_ops = &mtk_spi_mem_ops;
-+		init_completion(&mdata->spimem_done);
-+	}
- 
- 	if (mdata->dev_comp->need_pad_sel) {
- 		mdata->pad_num = of_property_count_u32_elems(
-@@ -831,25 +1204,40 @@ static int mtk_spi_probe(struct platform
- 		goto err_put_master;
- 	}
- 
-+	mdata->spi_hclk = devm_clk_get_optional(&pdev->dev, "hclk");
-+	if (IS_ERR(mdata->spi_hclk)) {
-+		ret = PTR_ERR(mdata->spi_hclk);
-+		dev_err(&pdev->dev, "failed to get hclk: %d\n", ret);
-+		goto err_put_master;
-+	}
-+
-+	ret = clk_prepare_enable(mdata->spi_hclk);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "failed to enable hclk (%d)\n", ret);
-+		goto err_put_master;
-+	}
-+
- 	ret = clk_prepare_enable(mdata->spi_clk);
- 	if (ret < 0) {
- 		dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
--		goto err_put_master;
-+		goto err_disable_spi_hclk;
- 	}
- 
- 	ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
- 	if (ret < 0) {
- 		dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
--		clk_disable_unprepare(mdata->spi_clk);
--		goto err_put_master;
-+		goto err_disable_spi_clk;
- 	}
- 
- 	mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk);
- 
--	if (mdata->dev_comp->no_need_unprepare)
-+	if (mdata->dev_comp->no_need_unprepare) {
- 		clk_disable(mdata->spi_clk);
--	else
-+		clk_disable(mdata->spi_hclk);
-+	} else {
- 		clk_disable_unprepare(mdata->spi_clk);
-+		clk_disable_unprepare(mdata->spi_hclk);
-+	}
- 
- 	pm_runtime_enable(&pdev->dev);
- 
-@@ -862,25 +1250,12 @@ static int mtk_spi_probe(struct platform
- 			goto err_disable_runtime_pm;
- 		}
- 
--		if (!master->cs_gpios && master->num_chipselect > 1) {
-+		if (!master->cs_gpiods && master->num_chipselect > 1) {
- 			dev_err(&pdev->dev,
- 				"cs_gpios not specified and num_chipselect > 1\n");
- 			ret = -EINVAL;
- 			goto err_disable_runtime_pm;
- 		}
--
--		if (master->cs_gpios) {
--			for (i = 0; i < master->num_chipselect; i++) {
--				ret = devm_gpio_request(&pdev->dev,
--							master->cs_gpios[i],
--							dev_name(&pdev->dev));
--				if (ret) {
--					dev_err(&pdev->dev,
--						"can't get CS GPIO %i\n", i);
--					goto err_disable_runtime_pm;
--				}
--			}
--		}
- 	}
- 
- 	if (mdata->dev_comp->dma_ext)
-@@ -902,6 +1277,10 @@ static int mtk_spi_probe(struct platform
- 
- err_disable_runtime_pm:
- 	pm_runtime_disable(&pdev->dev);
-+err_disable_spi_clk:
-+	clk_disable_unprepare(mdata->spi_clk);
-+err_disable_spi_hclk:
-+	clk_disable_unprepare(mdata->spi_hclk);
- err_put_master:
- 	spi_master_put(master);
- 
-@@ -920,8 +1299,10 @@ static int mtk_spi_remove(struct platfor
- 
- 	mtk_spi_reset(mdata);
- 
--	if (mdata->dev_comp->no_need_unprepare)
-+	if (mdata->dev_comp->no_need_unprepare) {
- 		clk_unprepare(mdata->spi_clk);
-+		clk_unprepare(mdata->spi_hclk);
-+	}
- 
- 	pm_runtime_put_noidle(&pdev->dev);
- 	pm_runtime_disable(&pdev->dev);
-@@ -940,8 +1321,10 @@ static int mtk_spi_suspend(struct device
- 	if (ret)
- 		return ret;
- 
--	if (!pm_runtime_suspended(dev))
-+	if (!pm_runtime_suspended(dev)) {
- 		clk_disable_unprepare(mdata->spi_clk);
-+		clk_disable_unprepare(mdata->spi_hclk);
-+	}
- 
- 	return ret;
- }
-@@ -958,11 +1341,20 @@ static int mtk_spi_resume(struct device
- 			dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
- 			return ret;
- 		}
-+
-+		ret = clk_prepare_enable(mdata->spi_hclk);
-+		if (ret < 0) {
-+			dev_err(dev, "failed to enable spi_hclk (%d)\n", ret);
-+			clk_disable_unprepare(mdata->spi_clk);
-+			return ret;
-+		}
- 	}
- 
- 	ret = spi_master_resume(master);
--	if (ret < 0)
-+	if (ret < 0) {
- 		clk_disable_unprepare(mdata->spi_clk);
-+		clk_disable_unprepare(mdata->spi_hclk);
-+	}
- 
- 	return ret;
- }
-@@ -974,10 +1366,13 @@ static int mtk_spi_runtime_suspend(struc
- 	struct spi_master *master = dev_get_drvdata(dev);
- 	struct mtk_spi *mdata = spi_master_get_devdata(master);
- 
--	if (mdata->dev_comp->no_need_unprepare)
-+	if (mdata->dev_comp->no_need_unprepare) {
- 		clk_disable(mdata->spi_clk);
--	else
-+		clk_disable(mdata->spi_hclk);
-+	} else {
- 		clk_disable_unprepare(mdata->spi_clk);
-+		clk_disable_unprepare(mdata->spi_hclk);
-+	}
- 
- 	return 0;
- }
-@@ -988,13 +1383,31 @@ static int mtk_spi_runtime_resume(struct
- 	struct mtk_spi *mdata = spi_master_get_devdata(master);
- 	int ret;
- 
--	if (mdata->dev_comp->no_need_unprepare)
-+	if (mdata->dev_comp->no_need_unprepare) {
- 		ret = clk_enable(mdata->spi_clk);
--	else
-+		if (ret < 0) {
-+			dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
-+			return ret;
-+		}
-+		ret = clk_enable(mdata->spi_hclk);
-+		if (ret < 0) {
-+			dev_err(dev, "failed to enable spi_hclk (%d)\n", ret);
-+			clk_disable(mdata->spi_clk);
-+			return ret;
-+		}
-+	} else {
- 		ret = clk_prepare_enable(mdata->spi_clk);
--	if (ret < 0) {
--		dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
--		return ret;
-+		if (ret < 0) {
-+			dev_err(dev, "failed to prepare_enable spi_clk (%d)\n", ret);
-+			return ret;
-+		}
-+
-+		ret = clk_prepare_enable(mdata->spi_hclk);
-+		if (ret < 0) {
-+			dev_err(dev, "failed to prepare_enable spi_hclk (%d)\n", ret);
-+			clk_disable_unprepare(mdata->spi_clk);
-+			return ret;
-+		}
- 	}
- 
- 	return 0;

target/linux/mediatek/patches-6.1/214-v6.3-clk-mediatek-add-mt7981-clock-support.patch

@@ -1,39 +0,0 @@
---- a/drivers/clk/mediatek/Kconfig
-+++ b/drivers/clk/mediatek/Kconfig
-@@ -344,6 +344,23 @@ config COMMON_CLK_MT7629_HIFSYS
- 	  This driver supports MediaTek MT7629 HIFSYS clocks providing
- 	  to PCI-E and USB.
- 
-+config COMMON_CLK_MT7981
-+	bool "Clock driver for MediaTek MT7981"
-+	depends on ARCH_MEDIATEK || COMPILE_TEST
-+	select COMMON_CLK_MEDIATEK
-+	default ARCH_MEDIATEK
-+	help
-+	  This driver supports MediaTek MT7981 basic clocks and clocks
-+	  required for various periperals found on MediaTek.
-+
-+config COMMON_CLK_MT7981_ETHSYS
-+	bool "Clock driver for MediaTek MT7981 ETHSYS"
-+	depends on COMMON_CLK_MT7981
-+	default COMMON_CLK_MT7981
-+	help
-+	  This driver add support for clocks for Ethernet and SGMII
-+	  required on MediaTek MT7981 SoC.
-+
- config COMMON_CLK_MT7986
- 	bool "Clock driver for MediaTek MT7986"
- 	depends on ARCH_MEDIATEK || COMPILE_TEST
---- a/drivers/clk/mediatek/Makefile
-+++ b/drivers/clk/mediatek/Makefile
-@@ -46,6 +46,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) +
- obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o
- obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
- obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
-+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-apmixed.o
-+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o
-+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o
-+obj-$(CONFIG_COMMON_CLK_MT7981_ETHSYS) += clk-mt7981-eth.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o

target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-add-mt7981-pinctrl-driver.patch

@@ -0,0 +1,1094 @@
+From 6c83b2d94fcca735cf7d8aa7a55a4957eb404a9d Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Thu, 26 Jan 2023 00:34:56 +0000
+Subject: [PATCH] pinctrl: add mt7981 pinctrl driver
+
+Add pinctrl driver for the MediaTek MT7981 SoC, based on the driver
+which can also be found the SDK.
+
+Signed-off-by: Daniel Golle <[email protected]>
+Reviewed-by: Rob Herring <[email protected]>
+Link: https://lore.kernel.org/r/ef5112946d16cacc67e65e439ba7b52a9950c1bb.1674693008.git.daniel@makrotopia.org
+Signed-off-by: Linus Walleij <[email protected]>
+---
+ drivers/pinctrl/mediatek/Kconfig          |    5 +
+ drivers/pinctrl/mediatek/Makefile         |    1 +
+ drivers/pinctrl/mediatek/pinctrl-mt7981.c | 1048 +++++++++++++++++++++
+ 3 files changed, 1054 insertions(+)
+ create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7981.c
+
+--- a/drivers/pinctrl/mediatek/Kconfig
++++ b/drivers/pinctrl/mediatek/Kconfig
+@@ -127,6 +127,11 @@ config PINCTRL_MT7622
+ 	default ARM64 && ARCH_MEDIATEK
+ 	select PINCTRL_MTK_MOORE
+ 
++config PINCTRL_MT7981
++	bool "Mediatek MT7981 pin control"
++	depends on OF
++	select PINCTRL_MTK_MOORE
++
+ config PINCTRL_MT7986
+ 	bool "Mediatek MT7986 pin control"
+ 	depends on OF
+--- a/drivers/pinctrl/mediatek/Makefile
++++ b/drivers/pinctrl/mediatek/Makefile
+@@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_MT6797)	+= pinctrl-
+ obj-$(CONFIG_PINCTRL_MT7622)	+= pinctrl-mt7622.o
+ obj-$(CONFIG_PINCTRL_MT7623)	+= pinctrl-mt7623.o
+ obj-$(CONFIG_PINCTRL_MT7629)	+= pinctrl-mt7629.o
++obj-$(CONFIG_PINCTRL_MT7981)	+= pinctrl-mt7981.o
+ obj-$(CONFIG_PINCTRL_MT7986)	+= pinctrl-mt7986.o
+ obj-$(CONFIG_PINCTRL_MT8167)	+= pinctrl-mt8167.o
+ obj-$(CONFIG_PINCTRL_MT8173)	+= pinctrl-mt8173.o
+--- /dev/null
++++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
+@@ -0,0 +1,1048 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * The MT7981 driver based on Linux generic pinctrl binding.
++ *
++ * Copyright (C) 2020 MediaTek Inc.
++ * Author: Sam Shih <[email protected]>
++ */
++
++#include "pinctrl-moore.h"
++
++#define MT7981_PIN(_number, _name)				\
++	MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
++
++#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits)	\
++	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
++		       _x_bits, 32, 0)
++
++#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits)	\
++	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
++		      _x_bits, 32, 1)
++
++static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = {
++	PIN_FIELD(0, 56, 0x300, 0x10, 0, 4),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = {
++	PIN_FIELD(0, 56, 0x0, 0x10, 0, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_di_range[] = {
++	PIN_FIELD(0, 56, 0x200, 0x10, 0, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_do_range[] = {
++	PIN_FIELD(0, 56, 0x100, 0x10, 0, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = {
++	PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1),
++	PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1),
++	PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1),
++	PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1),
++	PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1),
++	PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1),
++	PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1),
++	PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1),
++	PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1),
++
++	PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1),
++	PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1),
++	PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
++	PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1),
++	PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1),
++
++	PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1),
++
++	PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1),
++	PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1),
++	PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1),
++	PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1),
++	PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1),
++	PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1),
++	PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1),
++	PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1),
++	PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1),
++	PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1),
++	PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1),
++
++	PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1),
++	PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1),
++	PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1),
++	PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1),
++	PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1),
++	PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1),
++
++	PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1),
++	PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1),
++
++	PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1),
++	PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1),
++
++	PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1),
++	PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1),
++	PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1),
++	PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1),
++
++	PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1),
++	PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1),
++	PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1),
++	PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1),
++	PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
++	PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1),
++	PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1),
++	PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1),
++	PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1),
++	PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1),
++
++	PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1),
++	PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1),
++	PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1),
++	PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1),
++	PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1),
++	PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1),
++	PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = {
++	PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1),
++	PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1),
++	PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1),
++	PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1),
++	PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1),
++	PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1),
++	PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1),
++	PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1),
++	PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1),
++
++	PIN_FIELD_BASE(9, 9, 5, 0x90, 0x10, 9, 1),
++	PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1),
++	PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1),
++	PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1),
++	PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1),
++
++	PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1),
++
++	PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1),
++	PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1),
++	PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1),
++	PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1),
++	PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1),
++	PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
++	PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1),
++	PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1),
++	PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1),
++	PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1),
++	PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1),
++
++	PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1),
++	PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1),
++	PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1),
++	PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1),
++	PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1),
++	PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1),
++
++	PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1),
++	PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1),
++
++	PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1),
++	PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1),
++
++	PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1),
++	PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1),
++	PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1),
++	PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1),
++
++	PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1),
++	PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1),
++	PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1),
++	PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1),
++	PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
++	PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1),
++	PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1),
++	PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1),
++	PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1),
++	PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1),
++
++	PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1),
++	PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1),
++	PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1),
++	PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1),
++	PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1),
++	PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1),
++	PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = {
++	PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1),
++	PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1),
++	PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1),
++	PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1),
++	PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1),
++	PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1),
++	PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1),
++	PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1),
++	PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1),
++	PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1),
++
++	PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1),
++	PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1),
++	PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1),
++	PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1),
++	PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1),
++	PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1),
++	PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = {
++	PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1),
++	PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1),
++	PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1),
++	PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1),
++	PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1),
++	PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1),
++	PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1),
++	PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1),
++	PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1),
++	PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1),
++
++	PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1),
++	PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1),
++	PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1),
++	PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1),
++	PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1),
++	PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1),
++	PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = {
++	PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3),
++	PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3),
++
++	PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3),
++
++	PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1),
++	PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1),
++	PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3),
++	PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3),
++	PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3),
++	PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3),
++
++	PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3),
++	PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3),
++	PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3),
++	PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3),
++	PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3),
++
++	PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3),
++
++	PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3),
++	PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3),
++	PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3),
++	PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3),
++	PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3),
++	PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3),
++	PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3),
++	PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3),
++	PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3),
++	PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3),
++	PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3),
++
++	PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3),
++	PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3),
++	PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3),
++	PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3),
++	PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3),
++	PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3),
++
++	PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3),
++	PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3),
++
++	PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3),
++	PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3),
++
++	PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3),
++	PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3),
++	PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3),
++	PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3),
++
++	PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3),
++	PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3),
++	PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3),
++	PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3),
++	PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3),
++	PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3),
++	PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3),
++	PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3),
++	PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3),
++	PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3),
++
++	PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3),
++	PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3),
++	PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3),
++	PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3),
++	PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3),
++	PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3),
++	PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = {
++	PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1),
++	PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1),
++	PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1),
++	PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1),
++	PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1),
++	PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1),
++	PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1),
++	PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1),
++	PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1),
++
++	PIN_FIELD_BASE(9, 9, 5, 0x30, 0x10, 9, 1),
++	PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1),
++	PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1),
++	PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1),
++	PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1),
++
++	PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1),
++
++	PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1),
++	PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1),
++	PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1),
++	PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1),
++	PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1),
++	PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
++	PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1),
++	PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1),
++	PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1),
++	PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1),
++	PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1),
++
++	PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1),
++	PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1),
++	PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1),
++	PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1),
++	PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1),
++	PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1),
++
++	PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1),
++	PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1),
++
++	PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1),
++	PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1),
++
++	PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1),
++	PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1),
++	PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1),
++	PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = {
++	PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1),
++	PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1),
++	PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1),
++	PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1),
++	PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1),
++	PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1),
++	PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1),
++	PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1),
++	PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
++
++	PIN_FIELD_BASE(9, 9, 5, 0x40, 0x10, 9, 1),
++	PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1),
++	PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
++	PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1),
++	PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1),
++
++	PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1),
++
++	PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1),
++	PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1),
++	PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1),
++	PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1),
++	PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1),
++	PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1),
++	PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1),
++	PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1),
++	PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1),
++	PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1),
++	PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1),
++
++	PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1),
++	PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1),
++	PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1),
++	PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1),
++	PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1),
++	PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1),
++
++	PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1),
++	PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1),
++
++	PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1),
++	PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1),
++
++	PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1),
++	PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1),
++	PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1),
++	PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = {
++	PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1),
++	PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1),
++	PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1),
++	PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1),
++	PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1),
++	PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1),
++	PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1),
++	PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1),
++	PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1),
++
++	PIN_FIELD_BASE(9, 9, 5, 0x50, 0x10, 9, 1),
++	PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1),
++	PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1),
++	PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1),
++	PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1),
++
++	PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1),
++
++	PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1),
++	PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1),
++	PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1),
++	PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1),
++	PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1),
++	PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1),
++	PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1),
++	PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1),
++	PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1),
++	PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1),
++	PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1),
++
++	PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1),
++	PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1),
++	PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1),
++	PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1),
++	PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1),
++	PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1),
++
++	PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1),
++	PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1),
++
++	PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1),
++	PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1),
++
++	PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1),
++	PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1),
++	PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1),
++	PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1),
++};
++
++static const unsigned int mt7981_pull_type[] = {
++	MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
++	MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
++	MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
++	MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
++	MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
++	MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
++	MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
++	MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
++	MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
++	MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
++	MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
++	MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
++	MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
++	MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
++	MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
++	MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
++	MTK_PULL_PU_PD_TYPE,/*100*/
++};
++
++static const struct mtk_pin_reg_calc mt7981_reg_cals[] = {
++	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range),
++	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range),
++	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range),
++	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range),
++	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range),
++	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range),
++	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range),
++	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range),
++	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range),
++	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range),
++	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range),
++	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range),
++};
++
++static const struct mtk_pin_desc mt7981_pins[] = {
++	MT7981_PIN(0, "GPIO_WPS"),
++	MT7981_PIN(1, "GPIO_RESET"),
++	MT7981_PIN(2, "SYS_WATCHDOG"),
++	MT7981_PIN(3, "PCIE_PERESET_N"),
++	MT7981_PIN(4, "JTAG_JTDO"),
++	MT7981_PIN(5, "JTAG_JTDI"),
++	MT7981_PIN(6, "JTAG_JTMS"),
++	MT7981_PIN(7, "JTAG_JTCLK"),
++	MT7981_PIN(8, "JTAG_JTRST_N"),
++	MT7981_PIN(9, "WO_JTAG_JTDO"),
++	MT7981_PIN(10, "WO_JTAG_JTDI"),
++	MT7981_PIN(11, "WO_JTAG_JTMS"),
++	MT7981_PIN(12, "WO_JTAG_JTCLK"),
++	MT7981_PIN(13, "WO_JTAG_JTRST_N"),
++	MT7981_PIN(14, "USB_VBUS"),
++	MT7981_PIN(15, "PWM0"),
++	MT7981_PIN(16, "SPI0_CLK"),
++	MT7981_PIN(17, "SPI0_MOSI"),
++	MT7981_PIN(18, "SPI0_MISO"),
++	MT7981_PIN(19, "SPI0_CS"),
++	MT7981_PIN(20, "SPI0_HOLD"),
++	MT7981_PIN(21, "SPI0_WP"),
++	MT7981_PIN(22, "SPI1_CLK"),
++	MT7981_PIN(23, "SPI1_MOSI"),
++	MT7981_PIN(24, "SPI1_MISO"),
++	MT7981_PIN(25, "SPI1_CS"),
++	MT7981_PIN(26, "SPI2_CLK"),
++	MT7981_PIN(27, "SPI2_MOSI"),
++	MT7981_PIN(28, "SPI2_MISO"),
++	MT7981_PIN(29, "SPI2_CS"),
++	MT7981_PIN(30, "SPI2_HOLD"),
++	MT7981_PIN(31, "SPI2_WP"),
++	MT7981_PIN(32, "UART0_RXD"),
++	MT7981_PIN(33, "UART0_TXD"),
++	MT7981_PIN(34, "PCIE_CLK_REQ"),
++	MT7981_PIN(35, "PCIE_WAKE_N"),
++	MT7981_PIN(36, "SMI_MDC"),
++	MT7981_PIN(37, "SMI_MDIO"),
++	MT7981_PIN(38, "GBE_INT"),
++	MT7981_PIN(39, "GBE_RESET"),
++	MT7981_PIN(40, "WF_DIG_RESETB"),
++	MT7981_PIN(41, "WF_CBA_RESETB"),
++	MT7981_PIN(42, "WF_XO_REQ"),
++	MT7981_PIN(43, "WF_TOP_CLK"),
++	MT7981_PIN(44, "WF_TOP_DATA"),
++	MT7981_PIN(45, "WF_HB1"),
++	MT7981_PIN(46, "WF_HB2"),
++	MT7981_PIN(47, "WF_HB3"),
++	MT7981_PIN(48, "WF_HB4"),
++	MT7981_PIN(49, "WF_HB0"),
++	MT7981_PIN(50, "WF_HB0_B"),
++	MT7981_PIN(51, "WF_HB5"),
++	MT7981_PIN(52, "WF_HB6"),
++	MT7981_PIN(53, "WF_HB7"),
++	MT7981_PIN(54, "WF_HB8"),
++	MT7981_PIN(55, "WF_HB9"),
++	MT7981_PIN(56, "WF_HB10"),
++};
++
++/* List all groups consisting of these pins dedicated to the enablement of
++ * certain hardware block and the corresponding mode for all of the pins.
++ * The hardware probably has multiple combinations of these pinouts.
++ */
++
++/* WA_AICE */
++static int mt7981_wa_aice1_pins[] = { 0, 1, };
++static int mt7981_wa_aice1_funcs[] = { 2, 2, };
++
++static int mt7981_wa_aice2_pins[] = { 0, 1, };
++static int mt7981_wa_aice2_funcs[] = { 3, 3, };
++
++static int mt7981_wa_aice3_pins[] = { 28, 29, };
++static int mt7981_wa_aice3_funcs[] = { 3, 3, };
++
++static int mt7981_wm_aice1_pins[] = { 9, 10, };
++static int mt7981_wm_aice1_funcs[] = { 2, 2, };
++
++static int mt7981_wm_aice2_pins[] = { 30, 31, };
++static int mt7981_wm_aice2_funcs[] = { 5, 5, };
++
++/* WM_UART */
++static int mt7981_wm_uart_0_pins[] = { 0, 1, };
++static int mt7981_wm_uart_0_funcs[] = { 5, 5, };
++
++static int mt7981_wm_uart_1_pins[] = { 20, 21, };
++static int mt7981_wm_uart_1_funcs[] = { 4, 4, };
++
++static int mt7981_wm_uart_2_pins[] = { 30, 31, };
++static int mt7981_wm_uart_2_funcs[] = { 3, 3, };
++
++/* DFD */
++static int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
++static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
++
++/* SYS_WATCHDOG */
++static int mt7981_watchdog_pins[] = { 2, };
++static int mt7981_watchdog_funcs[] = { 1, };
++
++static int mt7981_watchdog1_pins[] = { 13, };
++static int mt7981_watchdog1_funcs[] = { 5, };
++
++/* PCIE_PERESET_N */
++static int mt7981_pcie_pereset_pins[] = { 3, };
++static int mt7981_pcie_pereset_funcs[] = { 1, };
++
++/* JTAG */
++static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
++static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
++
++/* WM_JTAG */
++static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
++static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
++
++static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
++static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
++
++/* WO0_JTAG */
++static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
++static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
++
++static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
++static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
++
++/* UART2 */
++static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
++static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
++
++/* GBE_LED0 */
++static int mt7981_gbe_led0_pins[] = { 8, };
++static int mt7981_gbe_led0_funcs[] = { 3, };
++
++/* PTA_EXT */
++static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
++static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
++
++static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
++static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
++
++/* PWM2 */
++static int mt7981_pwm2_pins[] = { 7, };
++static int mt7981_pwm2_funcs[] = { 4, };
++
++/* NET_WO0_UART_TXD */
++static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
++static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
++
++static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
++static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
++
++static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
++static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
++
++/* SPI1 */
++static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
++static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
++
++/* I2C */
++static int mt7981_i2c0_0_pins[] = { 6, 7, };
++static int mt7981_i2c0_0_funcs[] = { 6, 6, };
++
++static int mt7981_i2c0_1_pins[] = { 30, 31, };
++static int mt7981_i2c0_1_funcs[] = { 4, 4, };
++
++static int mt7981_i2c0_2_pins[] = { 36, 37, };
++static int mt7981_i2c0_2_funcs[] = { 2, 2, };
++
++static int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
++static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
++
++static int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
++static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
++
++static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
++static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
++
++static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
++static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
++
++/* DFD_NTRST */
++static int mt7981_dfd_ntrst_pins[] = { 8, };
++static int mt7981_dfd_ntrst_funcs[] = { 6, };
++
++/* PWM0 */
++static int mt7981_pwm0_0_pins[] = { 13, };
++static int mt7981_pwm0_0_funcs[] = { 2, };
++
++static int mt7981_pwm0_1_pins[] = { 15, };
++static int mt7981_pwm0_1_funcs[] = { 1, };
++
++/* PWM1 */
++static int mt7981_pwm1_0_pins[] = { 14, };
++static int mt7981_pwm1_0_funcs[] = { 2, };
++
++static int mt7981_pwm1_1_pins[] = { 15, };
++static int mt7981_pwm1_1_funcs[] = { 3, };
++
++/* GBE_LED1 */
++static int mt7981_gbe_led1_pins[] = { 13, };
++static int mt7981_gbe_led1_funcs[] = { 3, };
++
++/* PCM */
++static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
++static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
++
++/* UDI */
++static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
++static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
++
++/* DRV_VBUS */
++static int mt7981_drv_vbus_pins[] = { 14, };
++static int mt7981_drv_vbus_funcs[] = { 1, };
++
++/* EMMC */
++static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
++static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
++
++/* SNFI */
++static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
++static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
++
++/* SPI0 */
++static int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
++static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
++
++/* SPI0 */
++static int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
++static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
++
++/* SPI1 */
++static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
++static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
++
++/* SPI2 */
++static int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
++static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
++
++/* SPI2 */
++static int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
++static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
++
++/* UART1 */
++static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
++static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
++
++static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
++static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
++
++/* UART2 */
++static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
++static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
++
++/* UART0 */
++static int mt7981_uart0_pins[] = { 32, 33, };
++static int mt7981_uart0_funcs[] = { 1, 1, };
++
++/* PCIE_CLK_REQ */
++static int mt7981_pcie_clk_pins[] = { 34, };
++static int mt7981_pcie_clk_funcs[] = { 2, };
++
++/* PCIE_WAKE_N */
++static int mt7981_pcie_wake_pins[] = { 35, };
++static int mt7981_pcie_wake_funcs[] = { 2, };
++
++/* MDC_MDIO */
++static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
++static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
++
++static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
++static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
++
++/* WF0_MODE1 */
++static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 };
++static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
++
++/* WF0_MODE3 */
++static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
++static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
++
++/* WF2G_LED */
++static int mt7981_wf2g_led0_pins[] = { 30, };
++static int mt7981_wf2g_led0_funcs[] = { 2, };
++
++static int mt7981_wf2g_led1_pins[] = { 34, };
++static int mt7981_wf2g_led1_funcs[] = { 1, };
++
++/* WF5G_LED */
++static int mt7981_wf5g_led0_pins[] = { 31, };
++static int mt7981_wf5g_led0_funcs[] = { 2, };
++
++static int mt7981_wf5g_led1_pins[] = { 35, };
++static int mt7981_wf5g_led1_funcs[] = { 1, };
++
++/* MT7531_INT */
++static int mt7981_mt7531_int_pins[] = { 38, };
++static int mt7981_mt7531_int_funcs[] = { 1, };
++
++/* ANT_SEL */
++static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
++static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
++
++static const struct group_desc mt7981_groups[] = {
++	/* @GPIO(0,1): WA_AICE(2) */
++	PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1),
++	/* @GPIO(0,1): WA_AICE(3) */
++	PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2),
++	/* @GPIO(0,1): WM_UART(5) */
++	PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0),
++	/* @GPIO(0,1,4,5): DFD(6) */
++	PINCTRL_PIN_GROUP("dfd", mt7981_dfd),
++	/* @GPIO(2): SYS_WATCHDOG(1) */
++	PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog),
++	/* @GPIO(3): PCIE_PERESET_N(1) */
++	PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset),
++	/* @GPIO(4,8) JTAG(1) */
++	PINCTRL_PIN_GROUP("jtag", mt7981_jtag),
++	/* @GPIO(4,8) WM_JTAG(2) */
++	PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0),
++	/* @GPIO(9,13) WO0_JTAG(1) */
++	PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
++	/* @GPIO(4,7) WM_JTAG(3) */
++	PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
++	/* @GPIO(8) GBE_LED0(3) */
++	PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
++	/* @GPIO(4,6) PTA_EXT(4) */
++	PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0),
++	/* @GPIO(7) PWM2(4) */
++	PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2),
++	/* @GPIO(8) NET_WO0_UART_TXD(4) */
++	PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0),
++	/* @GPIO(4,7) SPI1(5) */
++	PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0),
++	/* @GPIO(6,7) I2C(5) */
++	PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0),
++	/* @GPIO(0,1,4,5): DFD_NTRST(6) */
++	PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst),
++	/* @GPIO(9,10): WM_AICE(2) */
++	PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1),
++	/* @GPIO(13): PWM0(2) */
++	PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0),
++	/* @GPIO(15): PWM0(1) */
++	PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1),
++	/* @GPIO(14): PWM1(2) */
++	PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0),
++	/* @GPIO(15): PWM1(3) */
++	PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1),
++	/* @GPIO(14) NET_WO0_UART_TXD(3) */
++	PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1),
++	/* @GPIO(15) NET_WO0_UART_TXD(4) */
++	PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2),
++	/* @GPIO(13) GBE_LED0(3) */
++	PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1),
++	/* @GPIO(9,13) PCM(4) */
++	PINCTRL_PIN_GROUP("pcm", mt7981_pcm),
++	/* @GPIO(13): SYS_WATCHDOG1(5) */
++	PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1),
++	/* @GPIO(9,13) UDI(4) */
++	PINCTRL_PIN_GROUP("udi", mt7981_udi),
++	/* @GPIO(14) DRV_VBUS(1) */
++	PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus),
++	/* @GPIO(15,25): EMMC(2) */
++	PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45),
++	/* @GPIO(16,21): SNFI(3) */
++	PINCTRL_PIN_GROUP("snfi", mt7981_snfi),
++	/* @GPIO(16,19): SPI0(1) */
++	PINCTRL_PIN_GROUP("spi0", mt7981_spi0),
++	/* @GPIO(20,21): SPI0(1) */
++	PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold),
++	/* @GPIO(22,25) SPI1(1) */
++	PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1),
++	/* @GPIO(26,29): SPI2(1) */
++	PINCTRL_PIN_GROUP("spi2", mt7981_spi2),
++	/* @GPIO(30,31): SPI0(1) */
++	PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold),
++	/* @GPIO(16,19): UART1(4) */
++	PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
++	/* @GPIO(26,29): UART1(2) */
++	PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
++	/* @GPIO(22,25): UART1(3) */
++	PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
++	/* @GPIO(22,24) PTA_EXT(4) */
++	PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1),
++	/* @GPIO(20,21): WM_UART(4) */
++	PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1),
++	/* @GPIO(30,31): WM_UART(3) */
++	PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2),
++	/* @GPIO(20,24) WM_JTAG(5) */
++	PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1),
++	/* @GPIO(25,29) WO0_JTAG(5) */
++	PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1),
++	/* @GPIO(28,29): WA_AICE(3) */
++	PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3),
++	/* @GPIO(30,31): WM_AICE(5) */
++	PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2),
++	/* @GPIO(30,31): I2C(4) */
++	PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1),
++	/* @GPIO(30,31): I2C(6) */
++	PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c),
++	/* @GPIO(32,33): I2C(1) */
++	PINCTRL_PIN_GROUP("uart0", mt7981_uart0),
++	/* @GPIO(32,33): I2C(2) */
++	PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c),
++	/* @GPIO(32,33): I2C(3) */
++	PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c),
++	/* @GPIO(32,33): I2C(5) */
++	PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c),
++	/* @GPIO(34): PCIE_CLK_REQ(2) */
++	PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk),
++	/* @GPIO(35): PCIE_WAKE_N(2) */
++	PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake),
++	/* @GPIO(36,37): I2C(2) */
++	PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2),
++	/* @GPIO(36,37): MDC_MDIO(1) */
++	PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio),
++	/* @GPIO(36,37): MDC_MDIO(3) */
++	PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio),
++	/* @GPIO(69,85): WF0_MODE1(1) */
++	PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1),
++	/* @GPIO(74,80): WF0_MODE3(3) */
++	PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3),
++	/* @GPIO(30): WF2G_LED(2) */
++	PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0),
++	/* @GPIO(34): WF2G_LED(1) */
++	PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1),
++	/* @GPIO(31): WF5G_LED(2) */
++	PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0),
++	/* @GPIO(35): WF5G_LED(1) */
++	PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1),
++	/* @GPIO(38): MT7531_INT(1) */
++	PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int),
++	/* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */
++	PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel),
++};
++
++/* Joint those groups owning the same capability in user point of view which
++ * allows that people tend to use through the device tree.
++ */
++static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
++	"wa_aice3", "wm_aice1_2", };
++static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
++	"net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
++	"uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", };
++static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
++static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
++static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", };
++static const char *mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", "wo0_jtag_0",
++	"wo0_jtag_1", "wm_jtag_1", };
++static const char *mt7981_led_groups[] = { "gbe_led0", "gbe_led1", "wf2g_led0",
++	"wf2g_led1", "wf5g_led0", "wf5g_led1", };
++static const char *mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", };
++static const char *mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1",
++	"pwm1_0", "pwm1_1", };
++static const char *mt7981_spi_groups[] = { "spi1_0", "spi0", "spi0_wp_hold", "spi1_1", "spi2",
++	"spi2_wp_hold", };
++static const char *mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", "u2_phy_i2c",
++	"sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", "i2c0_2", };
++static const char *mt7981_pcm_groups[] = { "pcm", };
++static const char *mt7981_udi_groups[] = { "udi", };
++static const char *mt7981_usb_groups[] = { "drv_vbus", };
++static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", };
++static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio",
++	"wf0_mode1", "wf0_mode3", "mt7531_int", };
++static const char *mt7981_ant_groups[] = { "ant_sel", };
++
++static const struct function_desc mt7981_functions[] = {
++	{"wa_aice",	mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)},
++	{"dfd",	mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)},
++	{"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)},
++	{"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)},
++	{"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)},
++	{"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)},
++	{"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)},
++	{"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)},
++	{"eth",	mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)},
++	{"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)},
++	{"led",	mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)},
++	{"pwm",	mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)},
++	{"spi",	mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)},
++	{"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)},
++	{"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)},
++	{"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)},
++	{"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)},
++};
++
++static const struct mtk_eint_hw mt7981_eint_hw = {
++	.port_mask = 7,
++	.ports     = 7,
++	.ap_num    = ARRAY_SIZE(mt7981_pins),
++	.db_cnt    = 16,
++};
++
++static const char * const mt7981_pinctrl_register_base_names[] = {
++	"gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb",
++	"iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl",
++};
++
++static struct mtk_pin_soc mt7981_data = {
++	.reg_cal = mt7981_reg_cals,
++	.pins = mt7981_pins,
++	.npins = ARRAY_SIZE(mt7981_pins),
++	.grps = mt7981_groups,
++	.ngrps = ARRAY_SIZE(mt7981_groups),
++	.funcs = mt7981_functions,
++	.nfuncs = ARRAY_SIZE(mt7981_functions),
++	.eint_hw = &mt7981_eint_hw,
++	.gpio_m = 0,
++	.ies_present = false,
++	.base_names = mt7981_pinctrl_register_base_names,
++	.nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names),
++	.pull_type = mt7981_pull_type,
++	.bias_set_combo = mtk_pinconf_bias_set_combo,
++	.bias_get_combo = mtk_pinconf_bias_get_combo,
++	.drive_set = mtk_pinconf_drive_set_rev1,
++	.drive_get = mtk_pinconf_drive_get_rev1,
++	.adv_pull_get = mtk_pinconf_adv_pull_get,
++	.adv_pull_set = mtk_pinconf_adv_pull_set,
++};
++
++static const struct of_device_id mt7981_pinctrl_of_match[] = {
++	{ .compatible = "mediatek,mt7981-pinctrl", },
++	{}
++};
++
++static int mt7981_pinctrl_probe(struct platform_device *pdev)
++{
++	return mtk_moore_pinctrl_probe(pdev, &mt7981_data);
++}
++
++static struct platform_driver mt7981_pinctrl_driver = {
++	.driver = {
++		.name = "mt7981-pinctrl",
++		.of_match_table = mt7981_pinctrl_of_match,
++	},
++	.probe = mt7981_pinctrl_probe,
++};
++
++static int __init mt7981_pinctrl_init(void)
++{
++	return platform_driver_register(&mt7981_pinctrl_driver);
++}
++arch_initcall(mt7981_pinctrl_init);

target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-mediatek-add-support-for-MT7981-SoC.patch

@@ -1,26 +0,0 @@
---- a/drivers/pinctrl/mediatek/Kconfig
-+++ b/drivers/pinctrl/mediatek/Kconfig
-@@ -120,6 +120,13 @@ config PINCTRL_MT7622
- 	default ARM64 && ARCH_MEDIATEK
- 	select PINCTRL_MTK_MOORE
- 
-+config PINCTRL_MT7981
-+	bool "Mediatek MT7981 pin control"
-+	depends on OF
-+	depends on ARM64 || COMPILE_TEST
-+	default ARM64 && ARCH_MEDIATEK
-+	select PINCTRL_MTK_MOORE
-+
- config PINCTRL_MT7986
- 	bool "Mediatek MT7986 pin control"
- 	depends on OF
---- a/drivers/pinctrl/mediatek/Makefile
-+++ b/drivers/pinctrl/mediatek/Makefile
-@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MT6797)	+= pinctrl-
- obj-$(CONFIG_PINCTRL_MT7622)	+= pinctrl-mt7622.o
- obj-$(CONFIG_PINCTRL_MT7623)	+= pinctrl-mt7623.o
- obj-$(CONFIG_PINCTRL_MT7629)	+= pinctrl-mt7629.o
-+obj-$(CONFIG_PINCTRL_MT7986)	+= pinctrl-mt7981.o
- obj-$(CONFIG_PINCTRL_MT7986)	+= pinctrl-mt7986.o
- obj-$(CONFIG_PINCTRL_MT8167)	+= pinctrl-mt8167.o
- obj-$(CONFIG_PINCTRL_MT8173)	+= pinctrl-mt8173.o

target/linux/mediatek/patches-6.1/216-v6.3-pinctrl-mediatek-add-missing-options-to-PINCTRL_MT79.patch

@@ -0,0 +1,30 @@
+From c0ad453e94e5c404efbcf668648d07eaa1a71ed7 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <[email protected]>
+Date: Sat, 18 Feb 2023 09:51:06 +0300
+Subject: [PATCH] pinctrl: mediatek: add missing options to PINCTRL_MT7981
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There are options missing from PINCTRL_MT7981 whilst being on every other
+pin controller. Add them.
+
+Signed-off-by: Arınç ÜNAL <[email protected]>
+Acked-by: Daniel Golle <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Linus Walleij <[email protected]>
+---
+ drivers/pinctrl/mediatek/Kconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/pinctrl/mediatek/Kconfig
++++ b/drivers/pinctrl/mediatek/Kconfig
+@@ -130,6 +130,8 @@ config PINCTRL_MT7622
+ config PINCTRL_MT7981
+ 	bool "Mediatek MT7981 pin control"
+ 	depends on OF
++	depends on ARM64 || COMPILE_TEST
++	default ARM64 && ARCH_MEDIATEK
+ 	select PINCTRL_MTK_MOORE
+ 
+ config PINCTRL_MT7986

target/linux/mediatek/patches-6.1/220-v6.3-clk-mediatek-clk-gate-Propagate-struct-device-with-m.patch

@@ -0,0 +1,536 @@
+From fe5c8d03f3de89ae058e365b783f8c1314f47490 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <[email protected]>
+Date: Fri, 20 Jan 2023 10:20:33 +0100
+Subject: [PATCH 01/15] clk: mediatek: clk-gate: Propagate struct device with
+ mtk_clk_register_gates()
+
+Commit e4c23e19aa2a ("clk: mediatek: Register clock gate with device")
+introduces a helper function for the sole purpose of propagating a
+struct device pointer to the clk API when registering the mtk-gate
+clocks to take advantage of Runtime PM when/where needed and where
+a power domain is defined in devicetree.
+
+Function mtk_clk_register_gates() then becomes a wrapper around the
+new mtk_clk_register_gates_with_dev() function that will simply pass
+NULL as struct device: this is essential when registering drivers
+with CLK_OF_DECLARE instead of as a platform device, as there will
+be no struct device to pass... but we can as well simply have only
+one function that always takes such pointer as a param and pass NULL
+when unavoidable.
+
+This commit removes the mtk_clk_register_gates() wrapper and renames
+mtk_clk_register_gates_with_dev() to the former and all of the calls
+to either of the two functions were fixed in all drivers in order to
+reflect this change; also, to improve consistency with other kernel
+functions, the pointer to struct device was moved as the first param.
+
+Since a lot of MediaTek clock drivers are actually registering as a
+platform device, but were still registering the mtk-gate clocks
+without passing any struct device to the clock framework, they've
+been changed to pass a valid one now, as to make all those platforms
+able to use runtime power management where available.
+
+While at it, some much needed indentation changes were also done.
+
+Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
+Reviewed-by: Chen-Yu Tsai <[email protected]>
+Reviewed-by: Markus Schneider-Pargmann <[email protected]>
+Tested-by: Miles Chen <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Tested-by: Mingming Su <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+
+[[email protected]: dropped parts not relevant for OpenWrt]
+---
+ drivers/clk/mediatek/clk-gate.c            | 23 +++++++---------------
+ drivers/clk/mediatek/clk-gate.h            |  7 +------
+ drivers/clk/mediatek/clk-mt2701-aud.c      |  4 ++--
+ drivers/clk/mediatek/clk-mt2701-eth.c      |  4 ++--
+ drivers/clk/mediatek/clk-mt2701-g3d.c      |  2 +-
+ drivers/clk/mediatek/clk-mt2701-hif.c      |  4 ++--
+ drivers/clk/mediatek/clk-mt2701-mm.c       |  4 ++--
+ drivers/clk/mediatek/clk-mt2701.c          | 12 +++++------
+ drivers/clk/mediatek/clk-mt2712-mm.c       |  4 ++--
+ drivers/clk/mediatek/clk-mt2712.c          | 12 +++++------
+ drivers/clk/mediatek/clk-mt7622-aud.c      |  4 ++--
+ drivers/clk/mediatek/clk-mt7622-eth.c      |  8 ++++----
+ drivers/clk/mediatek/clk-mt7622-hif.c      |  8 ++++----
+ drivers/clk/mediatek/clk-mt7622.c          | 14 ++++++-------
+ drivers/clk/mediatek/clk-mt7629-eth.c      |  7 ++++---
+ drivers/clk/mediatek/clk-mt7629-hif.c      |  8 ++++----
+ drivers/clk/mediatek/clk-mt7629.c          | 10 +++++-----
+ drivers/clk/mediatek/clk-mt7986-eth.c      | 10 +++++-----
+ drivers/clk/mediatek/clk-mt7986-infracfg.c |  4 ++--
+ 19 files changed, 68 insertions(+), 81 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-gate.c
++++ b/drivers/clk/mediatek/clk-gate.c
+@@ -152,12 +152,12 @@ const struct clk_ops mtk_clk_gate_ops_no
+ };
+ EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv);
+ 
+-static struct clk_hw *mtk_clk_register_gate(const char *name,
++static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name,
+ 					 const char *parent_name,
+ 					 struct regmap *regmap, int set_ofs,
+ 					 int clr_ofs, int sta_ofs, u8 bit,
+ 					 const struct clk_ops *ops,
+-					 unsigned long flags, struct device *dev)
++					 unsigned long flags)
+ {
+ 	struct mtk_clk_gate *cg;
+ 	int ret;
+@@ -202,10 +202,9 @@ static void mtk_clk_unregister_gate(stru
+ 	kfree(cg);
+ }
+ 
+-int mtk_clk_register_gates_with_dev(struct device_node *node,
+-				    const struct mtk_gate *clks, int num,
+-				    struct clk_hw_onecell_data *clk_data,
+-				    struct device *dev)
++int mtk_clk_register_gates(struct device *dev, struct device_node *node,
++			   const struct mtk_gate *clks, int num,
++			   struct clk_hw_onecell_data *clk_data)
+ {
+ 	int i;
+ 	struct clk_hw *hw;
+@@ -229,13 +228,13 @@ int mtk_clk_register_gates_with_dev(stru
+ 			continue;
+ 		}
+ 
+-		hw = mtk_clk_register_gate(gate->name, gate->parent_name,
++		hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name,
+ 					    regmap,
+ 					    gate->regs->set_ofs,
+ 					    gate->regs->clr_ofs,
+ 					    gate->regs->sta_ofs,
+ 					    gate->shift, gate->ops,
+-					    gate->flags, dev);
++					    gate->flags);
+ 
+ 		if (IS_ERR(hw)) {
+ 			pr_err("Failed to register clk %s: %pe\n", gate->name,
+@@ -261,14 +260,6 @@ err:
+ 
+ 	return PTR_ERR(hw);
+ }
+-EXPORT_SYMBOL_GPL(mtk_clk_register_gates_with_dev);
+-
+-int mtk_clk_register_gates(struct device_node *node,
+-			   const struct mtk_gate *clks, int num,
+-			   struct clk_hw_onecell_data *clk_data)
+-{
+-	return mtk_clk_register_gates_with_dev(node, clks, num, clk_data, NULL);
+-}
+ EXPORT_SYMBOL_GPL(mtk_clk_register_gates);
+ 
+ void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
+--- a/drivers/clk/mediatek/clk-gate.h
++++ b/drivers/clk/mediatek/clk-gate.h
+@@ -50,15 +50,10 @@ struct mtk_gate {
+ #define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops)		\
+ 	GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0)
+ 
+-int mtk_clk_register_gates(struct device_node *node,
++int mtk_clk_register_gates(struct device *dev, struct device_node *node,
+ 			   const struct mtk_gate *clks, int num,
+ 			   struct clk_hw_onecell_data *clk_data);
+ 
+-int mtk_clk_register_gates_with_dev(struct device_node *node,
+-				    const struct mtk_gate *clks, int num,
+-				    struct clk_hw_onecell_data *clk_data,
+-				    struct device *dev);
+-
+ void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
+ 			      struct clk_hw_onecell_data *clk_data);
+ 
+--- a/drivers/clk/mediatek/clk-mt2701-aud.c
++++ b/drivers/clk/mediatek/clk-mt2701-aud.c
+@@ -127,8 +127,8 @@ static int clk_mt2701_aud_probe(struct p
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
+ 
+-	mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, audio_clks,
++			       ARRAY_SIZE(audio_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r) {
+--- a/drivers/clk/mediatek/clk-mt2701-eth.c
++++ b/drivers/clk/mediatek/clk-mt2701-eth.c
+@@ -51,8 +51,8 @@ static int clk_mt2701_eth_probe(struct p
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
+ 
+-	mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
+-						clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, eth_clks,
++			       ARRAY_SIZE(eth_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+--- a/drivers/clk/mediatek/clk-mt2701-g3d.c
++++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
+@@ -45,7 +45,7 @@ static int clk_mt2701_g3dsys_init(struct
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
+ 
+-	mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks),
++	mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks),
+ 			       clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+--- a/drivers/clk/mediatek/clk-mt2701-hif.c
++++ b/drivers/clk/mediatek/clk-mt2701-hif.c
+@@ -48,8 +48,8 @@ static int clk_mt2701_hif_probe(struct p
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
+ 
+-	mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks),
+-						clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, hif_clks,
++			       ARRAY_SIZE(hif_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r) {
+--- a/drivers/clk/mediatek/clk-mt2701-mm.c
++++ b/drivers/clk/mediatek/clk-mt2701-mm.c
+@@ -76,8 +76,8 @@ static int clk_mt2701_mm_probe(struct pl
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_MM_NR);
+ 
+-	mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
+-						clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, mm_clks,
++			       ARRAY_SIZE(mm_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+--- a/drivers/clk/mediatek/clk-mt2701.c
++++ b/drivers/clk/mediatek/clk-mt2701.c
+@@ -683,8 +683,8 @@ static int mtk_topckgen_init(struct plat
+ 	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
+ 				base, &mt2701_clk_lock, clk_data);
+ 
+-	mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
+-						clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, top_clks,
++			       ARRAY_SIZE(top_clks), clk_data);
+ 
+ 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ }
+@@ -783,8 +783,8 @@ static int mtk_infrasys_init(struct plat
+ 		}
+ 	}
+ 
+-	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+-						infra_clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
++			       ARRAY_SIZE(infra_clks), infra_clk_data);
+ 	mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
+ 						infra_clk_data);
+ 
+@@ -894,8 +894,8 @@ static int mtk_pericfg_init(struct platf
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_PERI_NR);
+ 
+-	mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
+-						clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
++			       ARRAY_SIZE(peri_clks), clk_data);
+ 
+ 	mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
+ 			&mt2701_clk_lock, clk_data);
+--- a/drivers/clk/mediatek/clk-mt2712-mm.c
++++ b/drivers/clk/mediatek/clk-mt2712-mm.c
+@@ -117,8 +117,8 @@ static int clk_mt2712_mm_probe(struct pl
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
+-			clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, mm_clks,
++			       ARRAY_SIZE(mm_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 
+--- a/drivers/clk/mediatek/clk-mt2712.c
++++ b/drivers/clk/mediatek/clk-mt2712.c
+@@ -1324,8 +1324,8 @@ static int clk_mt2712_top_probe(struct p
+ 			&mt2712_clk_lock, top_clk_data);
+ 	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
+ 			&mt2712_clk_lock, top_clk_data);
+-	mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
+-			top_clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, top_clks,
++			       ARRAY_SIZE(top_clks), top_clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
+ 
+@@ -1344,8 +1344,8 @@ static int clk_mt2712_infra_probe(struct
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+-			clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
++			       ARRAY_SIZE(infra_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 
+@@ -1366,8 +1366,8 @@ static int clk_mt2712_peri_probe(struct
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
+-			clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
++			       ARRAY_SIZE(peri_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 
+--- a/drivers/clk/mediatek/clk-mt7622-aud.c
++++ b/drivers/clk/mediatek/clk-mt7622-aud.c
+@@ -114,8 +114,8 @@ static int clk_mt7622_audiosys_init(stru
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, audio_clks,
++			       ARRAY_SIZE(audio_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r) {
+--- a/drivers/clk/mediatek/clk-mt7622-eth.c
++++ b/drivers/clk/mediatek/clk-mt7622-eth.c
+@@ -69,8 +69,8 @@ static int clk_mt7622_ethsys_init(struct
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, eth_clks,
++			       ARRAY_SIZE(eth_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+@@ -91,8 +91,8 @@ static int clk_mt7622_sgmiisys_init(stru
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, sgmii_clks,
++			       ARRAY_SIZE(sgmii_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+--- a/drivers/clk/mediatek/clk-mt7622-hif.c
++++ b/drivers/clk/mediatek/clk-mt7622-hif.c
+@@ -80,8 +80,8 @@ static int clk_mt7622_ssusbsys_init(stru
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
++			       ARRAY_SIZE(ssusb_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+@@ -102,8 +102,8 @@ static int clk_mt7622_pciesys_init(struc
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
++			       ARRAY_SIZE(pcie_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+--- a/drivers/clk/mediatek/clk-mt7622.c
++++ b/drivers/clk/mediatek/clk-mt7622.c
+@@ -621,8 +621,8 @@ static int mtk_topckgen_init(struct plat
+ 	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
+ 				  base, &mt7622_clk_lock, clk_data);
+ 
+-	mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, top_clks,
++			       ARRAY_SIZE(top_clks), clk_data);
+ 
+ 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ }
+@@ -635,8 +635,8 @@ static int mtk_infrasys_init(struct plat
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
++			       ARRAY_SIZE(infra_clks), clk_data);
+ 
+ 	mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
+ 				  clk_data);
+@@ -663,7 +663,7 @@ static int mtk_apmixedsys_init(struct pl
+ 	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
+ 			      clk_data);
+ 
+-	mtk_clk_register_gates(node, apmixed_clks,
++	mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
+ 			       ARRAY_SIZE(apmixed_clks), clk_data);
+ 
+ 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+@@ -682,8 +682,8 @@ static int mtk_pericfg_init(struct platf
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
++			       ARRAY_SIZE(peri_clks), clk_data);
+ 
+ 	mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
+ 				    &mt7622_clk_lock, clk_data);
+--- a/drivers/clk/mediatek/clk-mt7629-eth.c
++++ b/drivers/clk/mediatek/clk-mt7629-eth.c
+@@ -80,7 +80,8 @@ static int clk_mt7629_ethsys_init(struct
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, eth_clks,
++			       CLK_ETH_NR_CLK, clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+@@ -102,8 +103,8 @@ static int clk_mt7629_sgmiisys_init(stru
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK,
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, sgmii_clks[id++],
++			       CLK_SGMII_NR_CLK, clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+--- a/drivers/clk/mediatek/clk-mt7629-hif.c
++++ b/drivers/clk/mediatek/clk-mt7629-hif.c
+@@ -75,8 +75,8 @@ static int clk_mt7629_ssusbsys_init(stru
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
++			       ARRAY_SIZE(ssusb_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+@@ -97,8 +97,8 @@ static int clk_mt7629_pciesys_init(struc
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
++			       ARRAY_SIZE(pcie_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+--- a/drivers/clk/mediatek/clk-mt7629.c
++++ b/drivers/clk/mediatek/clk-mt7629.c
+@@ -581,8 +581,8 @@ static int mtk_infrasys_init(struct plat
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
++			       ARRAY_SIZE(infra_clks), clk_data);
+ 
+ 	mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
+ 				  clk_data);
+@@ -604,8 +604,8 @@ static int mtk_pericfg_init(struct platf
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
++			       ARRAY_SIZE(peri_clks), clk_data);
+ 
+ 	mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
+ 				    &mt7629_clk_lock, clk_data);
+@@ -631,7 +631,7 @@ static int mtk_apmixedsys_init(struct pl
+ 	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
+ 			      clk_data);
+ 
+-	mtk_clk_register_gates(node, apmixed_clks,
++	mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
+ 			       ARRAY_SIZE(apmixed_clks), clk_data);
+ 
+ 	clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
+--- a/drivers/clk/mediatek/clk-mt7986-eth.c
++++ b/drivers/clk/mediatek/clk-mt7986-eth.c
+@@ -72,8 +72,8 @@ static void __init mtk_sgmiisys_0_init(s
+ 
+ 	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
+ 
+-	mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
+-			       clk_data);
++	mtk_clk_register_gates(NULL, node, sgmii0_clks,
++			       ARRAY_SIZE(sgmii0_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+@@ -90,8 +90,8 @@ static void __init mtk_sgmiisys_1_init(s
+ 
+ 	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
+ 
+-	mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
+-			       clk_data);
++	mtk_clk_register_gates(NULL, node, sgmii1_clks,
++			       ARRAY_SIZE(sgmii1_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 
+@@ -109,7 +109,7 @@ static void __init mtk_ethsys_init(struc
+ 
+ 	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
+ 
+-	mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
++	mtk_clk_register_gates(NULL, node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 
+--- a/drivers/clk/mediatek/clk-mt7986-infracfg.c
++++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c
+@@ -180,8 +180,8 @@ static int clk_mt7986_infracfg_probe(str
+ 	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
+ 	mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
+ 			       &mt7986_clk_lock, clk_data);
+-	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
++			       ARRAY_SIZE(infra_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r) {
+--- a/drivers/clk/mediatek/clk-mtk.c
++++ b/drivers/clk/mediatek/clk-mtk.c
+@@ -459,8 +459,8 @@ int mtk_clk_simple_probe(struct platform
+ 	if (!clk_data)
+ 		return -ENOMEM;
+ 
+-	r = mtk_clk_register_gates_with_dev(node, mcd->clks, mcd->num_clks,
+-					    clk_data, &pdev->dev);
++	r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, mcd->num_clks,
++				   clk_data);
+ 	if (r)
+ 		goto free_data;
+ 

target/linux/mediatek/patches-6.1/221-v6.3-clk-mediatek-cpumux-Propagate-struct-device-where-po.patch

@@ -0,0 +1,140 @@
+From b888303c7d23d7bd0c8667cfc657669e5d153fea Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <[email protected]>
+Date: Fri, 20 Jan 2023 10:20:34 +0100
+Subject: [PATCH 02/15] clk: mediatek: cpumux: Propagate struct device where
+ possible
+
+Take a pointer to a struct device in mtk_clk_register_cpumuxes() and
+propagate the same to mtk_clk_register_cpumux() => clk_hw_register().
+Even though runtime pm is unlikely to be used with CPU muxes, this
+helps with code consistency and possibly opens to commonization of
+some mtk_clk_register_(x) functions.
+
+Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
+Reviewed-by: Chen-Yu Tsai <[email protected]>
+Reviewed-by: Markus Schneider-Pargmann <[email protected]>
+Tested-by: Miles Chen <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Tested-by: Mingming Su <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/mediatek/clk-cpumux.c          | 8 ++++----
+ drivers/clk/mediatek/clk-cpumux.h          | 2 +-
+ drivers/clk/mediatek/clk-mt2701.c          | 2 +-
+ drivers/clk/mediatek/clk-mt6795-infracfg.c | 3 ++-
+ drivers/clk/mediatek/clk-mt7622.c          | 4 ++--
+ drivers/clk/mediatek/clk-mt7629.c          | 4 ++--
+ drivers/clk/mediatek/clk-mt8173.c          | 4 ++--
+ 7 files changed, 14 insertions(+), 13 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-cpumux.c
++++ b/drivers/clk/mediatek/clk-cpumux.c
+@@ -58,7 +58,7 @@ static const struct clk_ops clk_cpumux_o
+ };
+ 
+ static struct clk_hw *
+-mtk_clk_register_cpumux(const struct mtk_composite *mux,
++mtk_clk_register_cpumux(struct device *dev, const struct mtk_composite *mux,
+ 			struct regmap *regmap)
+ {
+ 	struct mtk_clk_cpumux *cpumux;
+@@ -81,7 +81,7 @@ mtk_clk_register_cpumux(const struct mtk
+ 	cpumux->regmap = regmap;
+ 	cpumux->hw.init = &init;
+ 
+-	ret = clk_hw_register(NULL, &cpumux->hw);
++	ret = clk_hw_register(dev, &cpumux->hw);
+ 	if (ret) {
+ 		kfree(cpumux);
+ 		return ERR_PTR(ret);
+@@ -102,7 +102,7 @@ static void mtk_clk_unregister_cpumux(st
+ 	kfree(cpumux);
+ }
+ 
+-int mtk_clk_register_cpumuxes(struct device_node *node,
++int mtk_clk_register_cpumuxes(struct device *dev, struct device_node *node,
+ 			      const struct mtk_composite *clks, int num,
+ 			      struct clk_hw_onecell_data *clk_data)
+ {
+@@ -125,7 +125,7 @@ int mtk_clk_register_cpumuxes(struct dev
+ 			continue;
+ 		}
+ 
+-		hw = mtk_clk_register_cpumux(mux, regmap);
++		hw = mtk_clk_register_cpumux(dev, mux, regmap);
+ 		if (IS_ERR(hw)) {
+ 			pr_err("Failed to register clk %s: %pe\n", mux->name,
+ 			       hw);
+--- a/drivers/clk/mediatek/clk-cpumux.h
++++ b/drivers/clk/mediatek/clk-cpumux.h
+@@ -11,7 +11,7 @@ struct clk_hw_onecell_data;
+ struct device_node;
+ struct mtk_composite;
+ 
+-int mtk_clk_register_cpumuxes(struct device_node *node,
++int mtk_clk_register_cpumuxes(struct device *dev, struct device_node *node,
+ 			      const struct mtk_composite *clks, int num,
+ 			      struct clk_hw_onecell_data *clk_data);
+ 
+--- a/drivers/clk/mediatek/clk-mt2701.c
++++ b/drivers/clk/mediatek/clk-mt2701.c
+@@ -757,7 +757,7 @@ static void __init mtk_infrasys_init_ear
+ 	mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
+ 						infra_clk_data);
+ 
+-	mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
++	mtk_clk_register_cpumuxes(NULL, node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
+ 				  infra_clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
+--- a/drivers/clk/mediatek/clk-mt6795-infracfg.c
++++ b/drivers/clk/mediatek/clk-mt6795-infracfg.c
+@@ -105,7 +105,8 @@ static int clk_mt6795_infracfg_probe(str
+ 	if (ret)
+ 		goto free_clk_data;
+ 
+-	ret = mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
++	ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes,
++					ARRAY_SIZE(cpu_muxes), clk_data);
+ 	if (ret)
+ 		goto unregister_gates;
+ 
+--- a/drivers/clk/mediatek/clk-mt7622.c
++++ b/drivers/clk/mediatek/clk-mt7622.c
+@@ -638,8 +638,8 @@ static int mtk_infrasys_init(struct plat
+ 	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
+ 			       ARRAY_SIZE(infra_clks), clk_data);
+ 
+-	mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
+-				  clk_data);
++	mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes,
++				  ARRAY_SIZE(infra_muxes), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
+ 				   clk_data);
+--- a/drivers/clk/mediatek/clk-mt7629.c
++++ b/drivers/clk/mediatek/clk-mt7629.c
+@@ -584,8 +584,8 @@ static int mtk_infrasys_init(struct plat
+ 	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
+ 			       ARRAY_SIZE(infra_clks), clk_data);
+ 
+-	mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
+-				  clk_data);
++	mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes,
++				  ARRAY_SIZE(infra_muxes), clk_data);
+ 
+ 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
+ 				      clk_data);
+--- a/drivers/clk/mediatek/clk-mt8173.c
++++ b/drivers/clk/mediatek/clk-mt8173.c
+@@ -892,8 +892,8 @@ static void __init mtk_infrasys_init(str
+ 						clk_data);
+ 	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
+ 
+-	mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
+-				  clk_data);
++	mtk_clk_register_cpumuxes(NULL, node, cpu_muxes,
++				  ARRAY_SIZE(cpu_muxes), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)

target/linux/mediatek/patches-6.1/222-v6.3-clk-mediatek-clk-mtk-Propagate-struct-device-for-com.patch

@@ -0,0 +1,181 @@
+From f23375db001ec0fe9f565be75eff43adde15407e Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <[email protected]>
+Date: Fri, 20 Jan 2023 10:20:35 +0100
+Subject: [PATCH 03/15] clk: mediatek: clk-mtk: Propagate struct device for
+ composites
+
+Like done for cpumux clocks, propagate struct device for composite
+clocks registered through clk-mtk helpers to be able to get runtime
+pm support for MTK clocks.
+
+Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
+Tested-by: Miles Chen <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Tested-by: Mingming Su <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+
+[[email protected]: remove parts not relevant for OpenWrt]
+---
+ drivers/clk/mediatek/clk-mt2701.c | 10 ++++++----
+ drivers/clk/mediatek/clk-mt2712.c | 12 ++++++++----
+ drivers/clk/mediatek/clk-mt7622.c |  8 +++++---
+ drivers/clk/mediatek/clk-mt7629.c |  8 +++++---
+ drivers/clk/mediatek/clk-mtk.c    | 11 ++++++-----
+ drivers/clk/mediatek/clk-mtk.h    |  3 ++-
+ 6 files changed, 32 insertions(+), 20 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt2701.c
++++ b/drivers/clk/mediatek/clk-mt2701.c
+@@ -677,8 +677,9 @@ static int mtk_topckgen_init(struct plat
+ 	mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
+ 								clk_data);
+ 
+-	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
+-				base, &mt2701_clk_lock, clk_data);
++	mtk_clk_register_composites(&pdev->dev, top_muxes,
++				    ARRAY_SIZE(top_muxes), base,
++				    &mt2701_clk_lock, clk_data);
+ 
+ 	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
+ 				base, &mt2701_clk_lock, clk_data);
+@@ -897,8 +898,9 @@ static int mtk_pericfg_init(struct platf
+ 	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
+ 			       ARRAY_SIZE(peri_clks), clk_data);
+ 
+-	mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
+-			&mt2701_clk_lock, clk_data);
++	mtk_clk_register_composites(&pdev->dev, peri_muxs,
++				    ARRAY_SIZE(peri_muxs), base,
++				    &mt2701_clk_lock, clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+--- a/drivers/clk/mediatek/clk-mt2712.c
++++ b/drivers/clk/mediatek/clk-mt2712.c
+@@ -1320,8 +1320,9 @@ static int clk_mt2712_top_probe(struct p
+ 	mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
+ 			top_clk_data);
+ 	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
+-	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
+-			&mt2712_clk_lock, top_clk_data);
++	mtk_clk_register_composites(&pdev->dev, top_muxes,
++				    ARRAY_SIZE(top_muxes), base,
++				    &mt2712_clk_lock, top_clk_data);
+ 	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
+ 			&mt2712_clk_lock, top_clk_data);
+ 	mtk_clk_register_gates(&pdev->dev, node, top_clks,
+@@ -1395,8 +1396,11 @@ static int clk_mt2712_mcu_probe(struct p
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
+ 
+-	mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
+-			&mt2712_clk_lock, clk_data);
++	r = mtk_clk_register_composites(&pdev->dev, mcu_muxes,
++					ARRAY_SIZE(mcu_muxes), base,
++					&mt2712_clk_lock, clk_data);
++	if (r)
++		dev_err(&pdev->dev, "Could not register composites: %d\n", r);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 
+--- a/drivers/clk/mediatek/clk-mt7622.c
++++ b/drivers/clk/mediatek/clk-mt7622.c
+@@ -615,8 +615,9 @@ static int mtk_topckgen_init(struct plat
+ 	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
+ 				 clk_data);
+ 
+-	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
+-				    base, &mt7622_clk_lock, clk_data);
++	mtk_clk_register_composites(&pdev->dev, top_muxes,
++				    ARRAY_SIZE(top_muxes), base,
++				    &mt7622_clk_lock, clk_data);
+ 
+ 	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
+ 				  base, &mt7622_clk_lock, clk_data);
+@@ -685,7 +686,8 @@ static int mtk_pericfg_init(struct platf
+ 	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
+ 			       ARRAY_SIZE(peri_clks), clk_data);
+ 
+-	mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
++	mtk_clk_register_composites(&pdev->dev, peri_muxes,
++				    ARRAY_SIZE(peri_muxes), base,
+ 				    &mt7622_clk_lock, clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+--- a/drivers/clk/mediatek/clk-mt7629.c
++++ b/drivers/clk/mediatek/clk-mt7629.c
+@@ -564,8 +564,9 @@ static int mtk_topckgen_init(struct plat
+ 	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
+ 				 clk_data);
+ 
+-	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
+-				    base, &mt7629_clk_lock, clk_data);
++	mtk_clk_register_composites(&pdev->dev, top_muxes,
++				    ARRAY_SIZE(top_muxes), base,
++				    &mt7629_clk_lock, clk_data);
+ 
+ 	clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk);
+ 	clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk);
+@@ -607,7 +608,8 @@ static int mtk_pericfg_init(struct platf
+ 	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
+ 			       ARRAY_SIZE(peri_clks), clk_data);
+ 
+-	mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
++	mtk_clk_register_composites(&pdev->dev, peri_muxes,
++				    ARRAY_SIZE(peri_muxes), base,
+ 				    &mt7629_clk_lock, clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+--- a/drivers/clk/mediatek/clk-mtk.c
++++ b/drivers/clk/mediatek/clk-mtk.c
+@@ -197,8 +197,8 @@ void mtk_clk_unregister_factors(const st
+ }
+ EXPORT_SYMBOL_GPL(mtk_clk_unregister_factors);
+ 
+-static struct clk_hw *mtk_clk_register_composite(const struct mtk_composite *mc,
+-		void __iomem *base, spinlock_t *lock)
++static struct clk_hw *mtk_clk_register_composite(struct device *dev,
++		const struct mtk_composite *mc, void __iomem *base, spinlock_t *lock)
+ {
+ 	struct clk_hw *hw;
+ 	struct clk_mux *mux = NULL;
+@@ -264,7 +264,7 @@ static struct clk_hw *mtk_clk_register_c
+ 		div_ops = &clk_divider_ops;
+ 	}
+ 
+-	hw = clk_hw_register_composite(NULL, mc->name, parent_names, num_parents,
++	hw = clk_hw_register_composite(dev, mc->name, parent_names, num_parents,
+ 		mux_hw, mux_ops,
+ 		div_hw, div_ops,
+ 		gate_hw, gate_ops,
+@@ -308,7 +308,8 @@ static void mtk_clk_unregister_composite
+ 	kfree(mux);
+ }
+ 
+-int mtk_clk_register_composites(const struct mtk_composite *mcs, int num,
++int mtk_clk_register_composites(struct device *dev,
++				const struct mtk_composite *mcs, int num,
+ 				void __iomem *base, spinlock_t *lock,
+ 				struct clk_hw_onecell_data *clk_data)
+ {
+@@ -327,7 +328,7 @@ int mtk_clk_register_composites(const st
+ 			continue;
+ 		}
+ 
+-		hw = mtk_clk_register_composite(mc, base, lock);
++		hw = mtk_clk_register_composite(dev, mc, base, lock);
+ 
+ 		if (IS_ERR(hw)) {
+ 			pr_err("Failed to register clk %s: %pe\n", mc->name,
+--- a/drivers/clk/mediatek/clk-mtk.h
++++ b/drivers/clk/mediatek/clk-mtk.h
+@@ -149,7 +149,8 @@ struct mtk_composite {
+ 		.flags = 0,						\
+ 	}
+ 
+-int mtk_clk_register_composites(const struct mtk_composite *mcs, int num,
++int mtk_clk_register_composites(struct device *dev,
++				const struct mtk_composite *mcs, int num,
+ 				void __iomem *base, spinlock_t *lock,
+ 				struct clk_hw_onecell_data *clk_data);
+ void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num,

target/linux/mediatek/patches-6.1/223-v6.3-clk-mediatek-clk-mux-Propagate-struct-device-for-mtk.patch

@@ -0,0 +1,103 @@
+From 5d911479e4c732729bfa798e4a9e3e5aec3e30a7 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <[email protected]>
+Date: Fri, 20 Jan 2023 10:20:36 +0100
+Subject: [PATCH 04/15] clk: mediatek: clk-mux: Propagate struct device for
+ mtk-mux
+
+Like done for other clocks, propagate struct device for mtk mux clocks
+registered through clk-mux helpers to enable runtime pm support.
+
+Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
+Tested-by: Miles Chen <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Tested-by: Mingming Su <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+
+[[email protected]: removed parts not relevant for OpenWrt]
+---
+ drivers/clk/mediatek/clk-mt7986-infracfg.c |  3 ++-
+ drivers/clk/mediatek/clk-mt7986-topckgen.c |  3 ++-
+ drivers/clk/mediatek/clk-mux.c             | 14 ++++++++------
+ drivers/clk/mediatek/clk-mux.h             |  3 ++-
+ 4 files changed, 14 insertions(+), 9 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt7986-infracfg.c
++++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c
+@@ -178,7 +178,8 @@ static int clk_mt7986_infracfg_probe(str
+ 		return -ENOMEM;
+ 
+ 	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
+-	mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
++	mtk_clk_register_muxes(&pdev->dev, infra_muxes,
++			       ARRAY_SIZE(infra_muxes), node,
+ 			       &mt7986_clk_lock, clk_data);
+ 	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
+ 			       ARRAY_SIZE(infra_clks), clk_data);
+--- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
++++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
+@@ -303,7 +303,8 @@ static int clk_mt7986_topckgen_probe(str
+ 	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
+ 				    clk_data);
+ 	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
+-	mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
++	mtk_clk_register_muxes(&pdev->dev, top_muxes,
++			       ARRAY_SIZE(top_muxes), node,
+ 			       &mt7986_clk_lock, clk_data);
+ 
+ 	clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk);
+--- a/drivers/clk/mediatek/clk-mux.c
++++ b/drivers/clk/mediatek/clk-mux.c
+@@ -154,9 +154,10 @@ const struct clk_ops mtk_mux_gate_clr_se
+ };
+ EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops);
+ 
+-static struct clk_hw *mtk_clk_register_mux(const struct mtk_mux *mux,
+-				 struct regmap *regmap,
+-				 spinlock_t *lock)
++static struct clk_hw *mtk_clk_register_mux(struct device *dev,
++					   const struct mtk_mux *mux,
++					   struct regmap *regmap,
++					   spinlock_t *lock)
+ {
+ 	struct mtk_clk_mux *clk_mux;
+ 	struct clk_init_data init = {};
+@@ -177,7 +178,7 @@ static struct clk_hw *mtk_clk_register_m
+ 	clk_mux->lock = lock;
+ 	clk_mux->hw.init = &init;
+ 
+-	ret = clk_hw_register(NULL, &clk_mux->hw);
++	ret = clk_hw_register(dev, &clk_mux->hw);
+ 	if (ret) {
+ 		kfree(clk_mux);
+ 		return ERR_PTR(ret);
+@@ -198,7 +199,8 @@ static void mtk_clk_unregister_mux(struc
+ 	kfree(mux);
+ }
+ 
+-int mtk_clk_register_muxes(const struct mtk_mux *muxes,
++int mtk_clk_register_muxes(struct device *dev,
++			   const struct mtk_mux *muxes,
+ 			   int num, struct device_node *node,
+ 			   spinlock_t *lock,
+ 			   struct clk_hw_onecell_data *clk_data)
+@@ -222,7 +224,7 @@ int mtk_clk_register_muxes(const struct
+ 			continue;
+ 		}
+ 
+-		hw = mtk_clk_register_mux(mux, regmap, lock);
++		hw = mtk_clk_register_mux(dev, mux, regmap, lock);
+ 
+ 		if (IS_ERR(hw)) {
+ 			pr_err("Failed to register clk %s: %pe\n", mux->name,
+--- a/drivers/clk/mediatek/clk-mux.h
++++ b/drivers/clk/mediatek/clk-mux.h
+@@ -83,7 +83,8 @@ extern const struct clk_ops mtk_mux_gate
+ 			0, _upd_ofs, _upd, CLK_SET_RATE_PARENT,		\
+ 			mtk_mux_clr_set_upd_ops)
+ 
+-int mtk_clk_register_muxes(const struct mtk_mux *muxes,
++int mtk_clk_register_muxes(struct device *dev,
++			   const struct mtk_mux *muxes,
+ 			   int num, struct device_node *node,
+ 			   spinlock_t *lock,
+ 			   struct clk_hw_onecell_data *clk_data);

target/linux/mediatek/patches-6.1/224-v6.3-clk-mediatek-clk-mtk-Add-dummy-clock-ops.patch

@@ -0,0 +1,74 @@
+From b8eb1081d267708ba976525a1fe2162901b34f3a Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <[email protected]>
+Date: Fri, 20 Jan 2023 10:20:37 +0100
+Subject: [PATCH] clk: mediatek: clk-mtk: Add dummy clock ops
+
+In order to migrate some (few) old clock drivers to the common
+mtk_clk_simple_probe() function, add dummy clock ops to be able
+to insert a dummy clock with ID 0 at the beginning of the list.
+
+Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
+Reviewed-by: Miles Chen <[email protected]>
+Reviewed-by: Chen-Yu Tsai <[email protected]>
+Tested-by: Miles Chen <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Tested-by: Mingming Su <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/mediatek/clk-mtk.c | 16 ++++++++++++++++
+ drivers/clk/mediatek/clk-mtk.h | 19 +++++++++++++++++++
+ 2 files changed, 35 insertions(+)
+
+--- a/drivers/clk/mediatek/clk-mtk.c
++++ b/drivers/clk/mediatek/clk-mtk.c
+@@ -18,6 +18,22 @@
+ #include "clk-mtk.h"
+ #include "clk-gate.h"
+ 
++const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 };
++EXPORT_SYMBOL_GPL(cg_regs_dummy);
++
++static int mtk_clk_dummy_enable(struct clk_hw *hw)
++{
++	return 0;
++}
++
++static void mtk_clk_dummy_disable(struct clk_hw *hw) { }
++
++const struct clk_ops mtk_clk_dummy_ops = {
++	.enable		= mtk_clk_dummy_enable,
++	.disable	= mtk_clk_dummy_disable,
++};
++EXPORT_SYMBOL_GPL(mtk_clk_dummy_ops);
++
+ static void mtk_init_clk_data(struct clk_hw_onecell_data *clk_data,
+ 			      unsigned int clk_num)
+ {
+--- a/drivers/clk/mediatek/clk-mtk.h
++++ b/drivers/clk/mediatek/clk-mtk.h
+@@ -22,6 +22,25 @@
+ 
+ struct platform_device;
+ 
++/*
++ * We need the clock IDs to start from zero but to maintain devicetree
++ * backwards compatibility we can't change bindings to start from zero.
++ * Only a few platforms are affected, so we solve issues given by the
++ * commonized MTK clocks probe function(s) by adding a dummy clock at
++ * the beginning where needed.
++ */
++#define CLK_DUMMY		0
++
++extern const struct clk_ops mtk_clk_dummy_ops;
++extern const struct mtk_gate_regs cg_regs_dummy;
++
++#define GATE_DUMMY(_id, _name) {				\
++		.id = _id,					\
++		.name = _name,					\
++		.regs = &cg_regs_dummy,				\
++		.ops = &mtk_clk_dummy_ops,			\
++	}
++
+ struct mtk_fixed_clk {
+ 	int id;
+ 	const char *name;

target/linux/mediatek/patches-6.1/225-v6.3-clk-mediatek-Switch-to-mtk_clk_simple_probe-where-po.patch

@@ -0,0 +1,790 @@
+From c26e28015b74af73e0b299f6ad3ff22931e600b4 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <[email protected]>
+Date: Fri, 20 Jan 2023 10:20:41 +0100
+Subject: [PATCH 05/15] clk: mediatek: Switch to mtk_clk_simple_probe() where
+ possible
+
+mtk_clk_simple_probe() is a function that registers mtk gate clocks
+and, if reset data is present, a reset controller and across all of
+the MTK clock drivers, such a function is duplicated many times:
+switch to the common mtk_clk_simple_probe() function for all of the
+clock drivers that are registering as platform drivers.
+
+Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
+Reviewed-by: Miles Chen <[email protected]>
+Tested-by: Miles Chen <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Tested-by: Mingming Su <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+
+[[email protected]: removed parts not relevant for OpenWrt]
+---
+ drivers/clk/mediatek/clk-mt2701-aud.c | 31 ++++++----
+ drivers/clk/mediatek/clk-mt2701-eth.c | 36 ++++--------
+ drivers/clk/mediatek/clk-mt2701-g3d.c | 56 ++++--------------
+ drivers/clk/mediatek/clk-mt2701-hif.c | 38 ++++--------
+ drivers/clk/mediatek/clk-mt2712.c     | 83 ++++++++++----------------
+ drivers/clk/mediatek/clk-mt7622-aud.c | 54 ++++++-----------
+ drivers/clk/mediatek/clk-mt7622-eth.c | 82 +++++---------------------
+ drivers/clk/mediatek/clk-mt7622-hif.c | 85 +++++----------------------
+ drivers/clk/mediatek/clk-mt7629-hif.c | 85 +++++----------------------
+ 9 files changed, 144 insertions(+), 406 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt2701-aud.c
++++ b/drivers/clk/mediatek/clk-mt2701-aud.c
+@@ -52,6 +52,7 @@ static const struct mtk_gate_regs audio3
+ };
+ 
+ static const struct mtk_gate audio_clks[] = {
++	GATE_DUMMY(CLK_DUMMY, "aud_dummy"),
+ 	/* AUDIO0 */
+ 	GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2),
+ 	GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20),
+@@ -114,29 +115,27 @@ static const struct mtk_gate audio_clks[
+ 	GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
+ };
+ 
++static const struct mtk_clk_desc audio_desc = {
++	.clks = audio_clks,
++	.num_clks = ARRAY_SIZE(audio_clks),
++};
++
+ static const struct of_device_id of_match_clk_mt2701_aud[] = {
+-	{ .compatible = "mediatek,mt2701-audsys", },
+-	{}
++	{ .compatible = "mediatek,mt2701-audsys", .data = &audio_desc },
++	{ /* sentinel */ }
+ };
+ 
+ static int clk_mt2701_aud_probe(struct platform_device *pdev)
+ {
+-	struct clk_hw_onecell_data *clk_data;
+-	struct device_node *node = pdev->dev.of_node;
+ 	int r;
+ 
+-	clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, audio_clks,
+-			       ARRAY_SIZE(audio_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
++	r = mtk_clk_simple_probe(pdev);
+ 	if (r) {
+ 		dev_err(&pdev->dev,
+ 			"could not register clock provider: %s: %d\n",
+ 			pdev->name, r);
+ 
+-		goto err_clk_provider;
++		return r;
+ 	}
+ 
+ 	r = devm_of_platform_populate(&pdev->dev);
+@@ -146,13 +145,19 @@ static int clk_mt2701_aud_probe(struct p
+ 	return 0;
+ 
+ err_plat_populate:
+-	of_clk_del_provider(node);
+-err_clk_provider:
++	mtk_clk_simple_remove(pdev);
+ 	return r;
+ }
+ 
++static int clk_mt2701_aud_remove(struct platform_device *pdev)
++{
++	of_platform_depopulate(&pdev->dev);
++	return mtk_clk_simple_remove(pdev);
++}
++
+ static struct platform_driver clk_mt2701_aud_drv = {
+ 	.probe = clk_mt2701_aud_probe,
++	.remove = clk_mt2701_aud_remove,
+ 	.driver = {
+ 		.name = "clk-mt2701-aud",
+ 		.of_match_table = of_match_clk_mt2701_aud,
+--- a/drivers/clk/mediatek/clk-mt2701-eth.c
++++ b/drivers/clk/mediatek/clk-mt2701-eth.c
+@@ -20,6 +20,7 @@ static const struct mtk_gate_regs eth_cg
+ 	GATE_MTK(_id, _name, _parent, &eth_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+ 
+ static const struct mtk_gate eth_clks[] = {
++	GATE_DUMMY(CLK_DUMMY, "eth_dummy"),
+ 	GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),
+ 	GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),
+ 	GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),
+@@ -38,35 +39,20 @@ static const struct mtk_clk_rst_desc clk
+ 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
+ };
+ 
+-static const struct of_device_id of_match_clk_mt2701_eth[] = {
+-	{ .compatible = "mediatek,mt2701-ethsys", },
+-	{}
++static const struct mtk_clk_desc eth_desc = {
++	.clks = eth_clks,
++	.num_clks = ARRAY_SIZE(eth_clks),
++	.rst_desc = &clk_rst_desc,
+ };
+ 
+-static int clk_mt2701_eth_probe(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	int r;
+-	struct device_node *node = pdev->dev.of_node;
+-
+-	clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, eth_clks,
+-			       ARRAY_SIZE(eth_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+-
+-	return r;
+-}
++static const struct of_device_id of_match_clk_mt2701_eth[] = {
++	{ .compatible = "mediatek,mt2701-ethsys", .data = &eth_desc },
++	{ /* sentinel */ }
++};
+ 
+ static struct platform_driver clk_mt2701_eth_drv = {
+-	.probe = clk_mt2701_eth_probe,
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
+ 	.driver = {
+ 		.name = "clk-mt2701-eth",
+ 		.of_match_table = of_match_clk_mt2701_eth,
+--- a/drivers/clk/mediatek/clk-mt2701-g3d.c
++++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
+@@ -26,6 +26,7 @@ static const struct mtk_gate_regs g3d_cg
+ };
+ 
+ static const struct mtk_gate g3d_clks[] = {
++	GATE_DUMMY(CLK_DUMMY, "g3d_dummy"),
+ 	GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
+ };
+ 
+@@ -37,57 +38,20 @@ static const struct mtk_clk_rst_desc clk
+ 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
+ };
+ 
+-static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	struct device_node *node = pdev->dev.of_node;
+-	int r;
+-
+-	clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks),
+-			       clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+-
+-	return r;
+-}
++static const struct mtk_clk_desc g3d_desc = {
++	.clks = g3d_clks,
++	.num_clks = ARRAY_SIZE(g3d_clks),
++	.rst_desc = &clk_rst_desc,
++};
+ 
+ static const struct of_device_id of_match_clk_mt2701_g3d[] = {
+-	{
+-		.compatible = "mediatek,mt2701-g3dsys",
+-		.data = clk_mt2701_g3dsys_init,
+-	}, {
+-		/* sentinel */
+-	}
++	{ .compatible = "mediatek,mt2701-g3dsys", .data = &g3d_desc },
++	{ /* sentinel */ }
+ };
+ 
+-static int clk_mt2701_g3d_probe(struct platform_device *pdev)
+-{
+-	int (*clk_init)(struct platform_device *);
+-	int r;
+-
+-	clk_init = of_device_get_match_data(&pdev->dev);
+-	if (!clk_init)
+-		return -EINVAL;
+-
+-	r = clk_init(pdev);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	return r;
+-}
+-
+ static struct platform_driver clk_mt2701_g3d_drv = {
+-	.probe = clk_mt2701_g3d_probe,
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
+ 	.driver = {
+ 		.name = "clk-mt2701-g3d",
+ 		.of_match_table = of_match_clk_mt2701_g3d,
+--- a/drivers/clk/mediatek/clk-mt2701-hif.c
++++ b/drivers/clk/mediatek/clk-mt2701-hif.c
+@@ -20,6 +20,7 @@ static const struct mtk_gate_regs hif_cg
+ 	GATE_MTK(_id, _name, _parent, &hif_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+ 
+ static const struct mtk_gate hif_clks[] = {
++	GATE_DUMMY(CLK_DUMMY, "hif_dummy"),
+ 	GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21),
+ 	GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22),
+ 	GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24),
+@@ -35,37 +36,20 @@ static const struct mtk_clk_rst_desc clk
+ 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
+ };
+ 
+-static const struct of_device_id of_match_clk_mt2701_hif[] = {
+-	{ .compatible = "mediatek,mt2701-hifsys", },
+-	{}
++static const struct mtk_clk_desc hif_desc = {
++	.clks = hif_clks,
++	.num_clks = ARRAY_SIZE(hif_clks),
++	.rst_desc = &clk_rst_desc,
+ };
+ 
+-static int clk_mt2701_hif_probe(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	int r;
+-	struct device_node *node = pdev->dev.of_node;
+-
+-	clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, hif_clks,
+-			       ARRAY_SIZE(hif_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-	if (r) {
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-		return r;
+-	}
+-
+-	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+-
+-	return 0;
+-}
++static const struct of_device_id of_match_clk_mt2701_hif[] = {
++	{ .compatible = "mediatek,mt2701-hifsys", .data = &hif_desc },
++	{ /* sentinel */ }
++};
+ 
+ static struct platform_driver clk_mt2701_hif_drv = {
+-	.probe = clk_mt2701_hif_probe,
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
+ 	.driver = {
+ 		.name = "clk-mt2701-hif",
+ 		.of_match_table = of_match_clk_mt2701_hif,
+--- a/drivers/clk/mediatek/clk-mt2712.c
++++ b/drivers/clk/mediatek/clk-mt2712.c
+@@ -1337,50 +1337,6 @@ static int clk_mt2712_top_probe(struct p
+ 	return r;
+ }
+ 
+-static int clk_mt2712_infra_probe(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	int r;
+-	struct device_node *node = pdev->dev.of_node;
+-
+-	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
+-			       ARRAY_SIZE(infra_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-
+-	if (r != 0)
+-		pr_err("%s(): could not register clock provider: %d\n",
+-			__func__, r);
+-
+-	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
+-
+-	return r;
+-}
+-
+-static int clk_mt2712_peri_probe(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	int r;
+-	struct device_node *node = pdev->dev.of_node;
+-
+-	clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
+-			       ARRAY_SIZE(peri_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-
+-	if (r != 0)
+-		pr_err("%s(): could not register clock provider: %d\n",
+-			__func__, r);
+-
+-	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
+-
+-	return r;
+-}
+-
+ static int clk_mt2712_mcu_probe(struct platform_device *pdev)
+ {
+ 	struct clk_hw_onecell_data *clk_data;
+@@ -1419,12 +1375,6 @@ static const struct of_device_id of_matc
+ 		.compatible = "mediatek,mt2712-topckgen",
+ 		.data = clk_mt2712_top_probe,
+ 	}, {
+-		.compatible = "mediatek,mt2712-infracfg",
+-		.data = clk_mt2712_infra_probe,
+-	}, {
+-		.compatible = "mediatek,mt2712-pericfg",
+-		.data = clk_mt2712_peri_probe,
+-	}, {
+ 		.compatible = "mediatek,mt2712-mcucfg",
+ 		.data = clk_mt2712_mcu_probe,
+ 	}, {
+@@ -1450,6 +1400,33 @@ static int clk_mt2712_probe(struct platf
+ 	return r;
+ }
+ 
++static const struct mtk_clk_desc infra_desc = {
++	.clks = infra_clks,
++	.num_clks = ARRAY_SIZE(infra_clks),
++	.rst_desc = &clk_rst_desc[0],
++};
++
++static const struct mtk_clk_desc peri_desc = {
++	.clks = peri_clks,
++	.num_clks = ARRAY_SIZE(peri_clks),
++	.rst_desc = &clk_rst_desc[1],
++};
++
++static const struct of_device_id of_match_clk_mt2712_simple[] = {
++	{ .compatible = "mediatek,mt2712-infracfg", .data = &infra_desc },
++	{ .compatible = "mediatek,mt2712-pericfg", .data = &peri_desc, },
++	{ /* sentinel */ }
++};
++
++static struct platform_driver clk_mt2712_simple_drv = {
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
++	.driver = {
++		.name = "clk-mt2712-simple",
++		.of_match_table = of_match_clk_mt2712_simple,
++	},
++};
++
+ static struct platform_driver clk_mt2712_drv = {
+ 	.probe = clk_mt2712_probe,
+ 	.driver = {
+@@ -1460,7 +1437,11 @@ static struct platform_driver clk_mt2712
+ 
+ static int __init clk_mt2712_init(void)
+ {
+-	return platform_driver_register(&clk_mt2712_drv);
++	int ret = platform_driver_register(&clk_mt2712_drv);
++
++	if (ret)
++		return ret;
++	return platform_driver_register(&clk_mt2712_simple_drv);
+ }
+ 
+ arch_initcall(clk_mt2712_init);
+--- a/drivers/clk/mediatek/clk-mt7622-aud.c
++++ b/drivers/clk/mediatek/clk-mt7622-aud.c
+@@ -106,24 +106,22 @@ static const struct mtk_gate audio_clks[
+ 	GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
+ };
+ 
+-static int clk_mt7622_audiosys_init(struct platform_device *pdev)
++static const struct mtk_clk_desc audio_desc = {
++	.clks = audio_clks,
++	.num_clks = ARRAY_SIZE(audio_clks),
++};
++
++static int clk_mt7622_aud_probe(struct platform_device *pdev)
+ {
+-	struct clk_hw_onecell_data *clk_data;
+-	struct device_node *node = pdev->dev.of_node;
+ 	int r;
+ 
+-	clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, audio_clks,
+-			       ARRAY_SIZE(audio_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
++	r = mtk_clk_simple_probe(pdev);
+ 	if (r) {
+ 		dev_err(&pdev->dev,
+ 			"could not register clock provider: %s: %d\n",
+ 			pdev->name, r);
+ 
+-		goto err_clk_provider;
++		return r;
+ 	}
+ 
+ 	r = devm_of_platform_populate(&pdev->dev);
+@@ -133,40 +131,24 @@ static int clk_mt7622_audiosys_init(stru
+ 	return 0;
+ 
+ err_plat_populate:
+-	of_clk_del_provider(node);
+-err_clk_provider:
++	mtk_clk_simple_remove(pdev);
+ 	return r;
+ }
+ 
+-static const struct of_device_id of_match_clk_mt7622_aud[] = {
+-	{
+-		.compatible = "mediatek,mt7622-audsys",
+-		.data = clk_mt7622_audiosys_init,
+-	}, {
+-		/* sentinel */
+-	}
+-};
+-
+-static int clk_mt7622_aud_probe(struct platform_device *pdev)
++static int clk_mt7622_aud_remove(struct platform_device *pdev)
+ {
+-	int (*clk_init)(struct platform_device *);
+-	int r;
+-
+-	clk_init = of_device_get_match_data(&pdev->dev);
+-	if (!clk_init)
+-		return -EINVAL;
+-
+-	r = clk_init(pdev);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	return r;
++	of_platform_depopulate(&pdev->dev);
++	return mtk_clk_simple_remove(pdev);
+ }
+ 
++static const struct of_device_id of_match_clk_mt7622_aud[] = {
++	{ .compatible = "mediatek,mt7622-audsys", .data = &audio_desc },
++	{ /* sentinel */ }
++};
++
+ static struct platform_driver clk_mt7622_aud_drv = {
+ 	.probe = clk_mt7622_aud_probe,
++	.remove = clk_mt7622_aud_remove,
+ 	.driver = {
+ 		.name = "clk-mt7622-aud",
+ 		.of_match_table = of_match_clk_mt7622_aud,
+--- a/drivers/clk/mediatek/clk-mt7622-eth.c
++++ b/drivers/clk/mediatek/clk-mt7622-eth.c
+@@ -61,80 +61,26 @@ static const struct mtk_clk_rst_desc clk
+ 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
+ };
+ 
+-static int clk_mt7622_ethsys_init(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	struct device_node *node = pdev->dev.of_node;
+-	int r;
+-
+-	clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, eth_clks,
+-			       ARRAY_SIZE(eth_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+-
+-	return r;
+-}
+-
+-static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	struct device_node *node = pdev->dev.of_node;
+-	int r;
+-
+-	clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, sgmii_clks,
+-			       ARRAY_SIZE(sgmii_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
++static const struct mtk_clk_desc eth_desc = {
++	.clks = eth_clks,
++	.num_clks = ARRAY_SIZE(eth_clks),
++	.rst_desc = &clk_rst_desc,
++};
+ 
+-	return r;
+-}
++static const struct mtk_clk_desc sgmii_desc = {
++	.clks = sgmii_clks,
++	.num_clks = ARRAY_SIZE(sgmii_clks),
++};
+ 
+ static const struct of_device_id of_match_clk_mt7622_eth[] = {
+-	{
+-		.compatible = "mediatek,mt7622-ethsys",
+-		.data = clk_mt7622_ethsys_init,
+-	}, {
+-		.compatible = "mediatek,mt7622-sgmiisys",
+-		.data = clk_mt7622_sgmiisys_init,
+-	}, {
+-		/* sentinel */
+-	}
++	{ .compatible = "mediatek,mt7622-ethsys", .data = &eth_desc },
++	{ .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc },
++	{ /* sentinel */ }
+ };
+ 
+-static int clk_mt7622_eth_probe(struct platform_device *pdev)
+-{
+-	int (*clk_init)(struct platform_device *);
+-	int r;
+-
+-	clk_init = of_device_get_match_data(&pdev->dev);
+-	if (!clk_init)
+-		return -EINVAL;
+-
+-	r = clk_init(pdev);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	return r;
+-}
+-
+ static struct platform_driver clk_mt7622_eth_drv = {
+-	.probe = clk_mt7622_eth_probe,
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
+ 	.driver = {
+ 		.name = "clk-mt7622-eth",
+ 		.of_match_table = of_match_clk_mt7622_eth,
+--- a/drivers/clk/mediatek/clk-mt7622-hif.c
++++ b/drivers/clk/mediatek/clk-mt7622-hif.c
+@@ -72,82 +72,27 @@ static const struct mtk_clk_rst_desc clk
+ 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
+ };
+ 
+-static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	struct device_node *node = pdev->dev.of_node;
+-	int r;
+-
+-	clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
+-			       ARRAY_SIZE(ssusb_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+-
+-	return r;
+-}
+-
+-static int clk_mt7622_pciesys_init(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	struct device_node *node = pdev->dev.of_node;
+-	int r;
+-
+-	clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
+-			       ARRAY_SIZE(pcie_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
++static const struct mtk_clk_desc ssusb_desc = {
++	.clks = ssusb_clks,
++	.num_clks = ARRAY_SIZE(ssusb_clks),
++	.rst_desc = &clk_rst_desc,
++};
+ 
+-	return r;
+-}
++static const struct mtk_clk_desc pcie_desc = {
++	.clks = pcie_clks,
++	.num_clks = ARRAY_SIZE(pcie_clks),
++	.rst_desc = &clk_rst_desc,
++};
+ 
+ static const struct of_device_id of_match_clk_mt7622_hif[] = {
+-	{
+-		.compatible = "mediatek,mt7622-pciesys",
+-		.data = clk_mt7622_pciesys_init,
+-	}, {
+-		.compatible = "mediatek,mt7622-ssusbsys",
+-		.data = clk_mt7622_ssusbsys_init,
+-	}, {
+-		/* sentinel */
+-	}
++	{ .compatible = "mediatek,mt7622-pciesys", .data = &pcie_desc },
++	{ .compatible = "mediatek,mt7622-ssusbsys", .data = &ssusb_desc },
++	{ /* sentinel */ }
+ };
+ 
+-static int clk_mt7622_hif_probe(struct platform_device *pdev)
+-{
+-	int (*clk_init)(struct platform_device *);
+-	int r;
+-
+-	clk_init = of_device_get_match_data(&pdev->dev);
+-	if (!clk_init)
+-		return -EINVAL;
+-
+-	r = clk_init(pdev);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	return r;
+-}
+-
+ static struct platform_driver clk_mt7622_hif_drv = {
+-	.probe = clk_mt7622_hif_probe,
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
+ 	.driver = {
+ 		.name = "clk-mt7622-hif",
+ 		.of_match_table = of_match_clk_mt7622_hif,
+--- a/drivers/clk/mediatek/clk-mt7629-hif.c
++++ b/drivers/clk/mediatek/clk-mt7629-hif.c
+@@ -67,82 +67,27 @@ static const struct mtk_clk_rst_desc clk
+ 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
+ };
+ 
+-static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	struct device_node *node = pdev->dev.of_node;
+-	int r;
+-
+-	clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
+-			       ARRAY_SIZE(ssusb_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+-
+-	return r;
+-}
+-
+-static int clk_mt7629_pciesys_init(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	struct device_node *node = pdev->dev.of_node;
+-	int r;
+-
+-	clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
+-			       ARRAY_SIZE(pcie_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
++static const struct mtk_clk_desc ssusb_desc = {
++	.clks = ssusb_clks,
++	.num_clks = ARRAY_SIZE(ssusb_clks),
++	.rst_desc = &clk_rst_desc,
++};
+ 
+-	return r;
+-}
++static const struct mtk_clk_desc pcie_desc = {
++	.clks = pcie_clks,
++	.num_clks = ARRAY_SIZE(pcie_clks),
++	.rst_desc = &clk_rst_desc,
++};
+ 
+ static const struct of_device_id of_match_clk_mt7629_hif[] = {
+-	{
+-		.compatible = "mediatek,mt7629-pciesys",
+-		.data = clk_mt7629_pciesys_init,
+-	}, {
+-		.compatible = "mediatek,mt7629-ssusbsys",
+-		.data = clk_mt7629_ssusbsys_init,
+-	}, {
+-		/* sentinel */
+-	}
++	{ .compatible = "mediatek,mt7629-pciesys", .data = &pcie_desc },
++	{ .compatible = "mediatek,mt7629-ssusbsys", .data = &ssusb_desc },
++	{ /* sentinel */ }
+ };
+ 
+-static int clk_mt7629_hif_probe(struct platform_device *pdev)
+-{
+-	int (*clk_init)(struct platform_device *);
+-	int r;
+-
+-	clk_init = of_device_get_match_data(&pdev->dev);
+-	if (!clk_init)
+-		return -EINVAL;
+-
+-	r = clk_init(pdev);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	return r;
+-}
+-
+ static struct platform_driver clk_mt7629_hif_drv = {
+-	.probe = clk_mt7629_hif_probe,
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
+ 	.driver = {
+ 		.name = "clk-mt7629-hif",
+ 		.of_match_table = of_match_clk_mt7629_hif,

target/linux/mediatek/patches-6.1/226-v6.3-clk-mediatek-clk-mtk-Extend-mtk_clk_simple_probe.patch

@@ -0,0 +1,189 @@
+From 7b6183108c8ccf0dc295f39cdf78bd8078455636 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <[email protected]>
+Date: Fri, 20 Jan 2023 10:20:42 +0100
+Subject: [PATCH] clk: mediatek: clk-mtk: Extend mtk_clk_simple_probe()
+
+As a preparation to increase probe functions commonization across
+various MediaTek SoC clock controller drivers, extend function
+mtk_clk_simple_probe() to be able to register not only gates, but
+also fixed clocks, factors, muxes and composites.
+
+Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
+Reviewed-by: Miles Chen <[email protected]>
+Reviewed-by: Chen-Yu Tsai <[email protected]>
+Tested-by: Miles Chen <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Tested-by: Mingming Su <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/mediatek/clk-mtk.c | 101 ++++++++++++++++++++++++++++++---
+ drivers/clk/mediatek/clk-mtk.h |  10 ++++
+ 2 files changed, 103 insertions(+), 8 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mtk.c
++++ b/drivers/clk/mediatek/clk-mtk.c
+@@ -11,12 +11,14 @@
+ #include <linux/mfd/syscon.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
++#include <linux/of_address.h>
+ #include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/slab.h>
+ 
+ #include "clk-mtk.h"
+ #include "clk-gate.h"
++#include "clk-mux.h"
+ 
+ const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 };
+ EXPORT_SYMBOL_GPL(cg_regs_dummy);
+@@ -466,20 +468,71 @@ int mtk_clk_simple_probe(struct platform
+ 	const struct mtk_clk_desc *mcd;
+ 	struct clk_hw_onecell_data *clk_data;
+ 	struct device_node *node = pdev->dev.of_node;
+-	int r;
++	void __iomem *base;
++	int num_clks, r;
+ 
+ 	mcd = of_device_get_match_data(&pdev->dev);
+ 	if (!mcd)
+ 		return -EINVAL;
+ 
+-	clk_data = mtk_alloc_clk_data(mcd->num_clks);
++	/* Composite clocks needs us to pass iomem pointer */
++	if (mcd->composite_clks) {
++		if (!mcd->shared_io)
++			base = devm_platform_ioremap_resource(pdev, 0);
++		else
++			base = of_iomap(node, 0);
++
++		if (IS_ERR_OR_NULL(base))
++			return IS_ERR(base) ? PTR_ERR(base) : -ENOMEM;
++	}
++
++	/* Calculate how many clk_hw_onecell_data entries to allocate */
++	num_clks = mcd->num_clks + mcd->num_composite_clks;
++	num_clks += mcd->num_fixed_clks + mcd->num_factor_clks;
++	num_clks += mcd->num_mux_clks;
++
++	clk_data = mtk_alloc_clk_data(num_clks);
+ 	if (!clk_data)
+ 		return -ENOMEM;
+ 
+-	r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, mcd->num_clks,
+-				   clk_data);
+-	if (r)
+-		goto free_data;
++	if (mcd->fixed_clks) {
++		r = mtk_clk_register_fixed_clks(mcd->fixed_clks,
++						mcd->num_fixed_clks, clk_data);
++		if (r)
++			goto free_data;
++	}
++
++	if (mcd->factor_clks) {
++		r = mtk_clk_register_factors(mcd->factor_clks,
++					     mcd->num_factor_clks, clk_data);
++		if (r)
++			goto unregister_fixed_clks;
++	}
++
++	if (mcd->mux_clks) {
++		r = mtk_clk_register_muxes(&pdev->dev, mcd->mux_clks,
++					   mcd->num_mux_clks, node,
++					   mcd->clk_lock, clk_data);
++		if (r)
++			goto unregister_factors;
++	};
++
++	if (mcd->composite_clks) {
++		/* We don't check composite_lock because it's optional */
++		r = mtk_clk_register_composites(&pdev->dev,
++						mcd->composite_clks,
++						mcd->num_composite_clks,
++						base, mcd->clk_lock, clk_data);
++		if (r)
++			goto unregister_muxes;
++	}
++
++	if (mcd->clks) {
++		r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks,
++					   mcd->num_clks, clk_data);
++		if (r)
++			goto unregister_composites;
++	}
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+@@ -497,9 +550,28 @@ int mtk_clk_simple_probe(struct platform
+ 	return r;
+ 
+ unregister_clks:
+-	mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
++	if (mcd->clks)
++		mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
++unregister_composites:
++	if (mcd->composite_clks)
++		mtk_clk_unregister_composites(mcd->composite_clks,
++					      mcd->num_composite_clks, clk_data);
++unregister_muxes:
++	if (mcd->mux_clks)
++		mtk_clk_unregister_muxes(mcd->mux_clks,
++					 mcd->num_mux_clks, clk_data);
++unregister_factors:
++	if (mcd->factor_clks)
++		mtk_clk_unregister_factors(mcd->factor_clks,
++					   mcd->num_factor_clks, clk_data);
++unregister_fixed_clks:
++	if (mcd->fixed_clks)
++		mtk_clk_unregister_fixed_clks(mcd->fixed_clks,
++					      mcd->num_fixed_clks, clk_data);
+ free_data:
+ 	mtk_free_clk_data(clk_data);
++	if (mcd->shared_io && base)
++		iounmap(base);
+ 	return r;
+ }
+ EXPORT_SYMBOL_GPL(mtk_clk_simple_probe);
+@@ -511,7 +583,20 @@ int mtk_clk_simple_remove(struct platfor
+ 	struct device_node *node = pdev->dev.of_node;
+ 
+ 	of_clk_del_provider(node);
+-	mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
++	if (mcd->clks)
++		mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
++	if (mcd->composite_clks)
++		mtk_clk_unregister_composites(mcd->composite_clks,
++					      mcd->num_composite_clks, clk_data);
++	if (mcd->mux_clks)
++		mtk_clk_unregister_muxes(mcd->mux_clks,
++					 mcd->num_mux_clks, clk_data);
++	if (mcd->factor_clks)
++		mtk_clk_unregister_factors(mcd->factor_clks,
++					   mcd->num_factor_clks, clk_data);
++	if (mcd->fixed_clks)
++		mtk_clk_unregister_fixed_clks(mcd->fixed_clks,
++					      mcd->num_fixed_clks, clk_data);
+ 	mtk_free_clk_data(clk_data);
+ 
+ 	return 0;
+--- a/drivers/clk/mediatek/clk-mtk.h
++++ b/drivers/clk/mediatek/clk-mtk.h
+@@ -215,7 +215,17 @@ void mtk_clk_unregister_ref2usb_tx(struc
+ struct mtk_clk_desc {
+ 	const struct mtk_gate *clks;
+ 	size_t num_clks;
++	const struct mtk_composite *composite_clks;
++	size_t num_composite_clks;
++	const struct mtk_fixed_clk *fixed_clks;
++	size_t num_fixed_clks;
++	const struct mtk_fixed_factor *factor_clks;
++	size_t num_factor_clks;
++	const struct mtk_mux *mux_clks;
++	size_t num_mux_clks;
+ 	const struct mtk_clk_rst_desc *rst_desc;
++	spinlock_t *clk_lock;
++	bool shared_io;
+ };
+ 
+ int mtk_clk_simple_probe(struct platform_device *pdev);

target/linux/mediatek/patches-6.1/227-v6.3-clk-mediatek-clk-mt7986-topckgen-Properly-keep-some-.patch

@@ -0,0 +1,97 @@
+From 3511004225ce917a4aa6e6ac61481ac60f08f401 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <[email protected]>
+Date: Fri, 20 Jan 2023 10:20:52 +0100
+Subject: [PATCH 06/15] clk: mediatek: clk-mt7986-topckgen: Properly keep some
+ clocks enabled
+
+Instead of calling clk_prepare_enable() on a bunch of clocks at probe
+time, set the CLK_IS_CRITICAL flag to the same as these are required
+to be always on, and this is the right way of achieving that.
+
+Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
+Reviewed-by: Chen-Yu Tsai <[email protected]>
+Reviewed-by: Miles Chen <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Tested-by: Mingming Su <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/mediatek/clk-mt7986-topckgen.c | 46 +++++++++++-----------
+ 1 file changed, 24 insertions(+), 22 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
++++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
+@@ -202,16 +202,23 @@ static const struct mtk_mux top_muxes[]
+ 	MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",
+ 			     f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23,
+ 			     0x1C0, 10),
+-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents,
+-			     0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
++				   f_26m_adc_parents, 0x020, 0x024, 0x028,
++				   24, 1, 31, 0x1C0, 11,
++				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ 	/* CLK_CFG_3 */
+-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
+-			     dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7,
+-			     0x1C0, 12),
+-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents,
+-			     0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13),
+-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents,
+-			     0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
++				   dramc_md32_parents, 0x030, 0x034, 0x038,
++				   0, 1, 7, 0x1C0, 12,
++				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
++				   sysaxi_parents, 0x030, 0x034, 0x038,
++				   8, 2, 15, 0x1C0, 13,
++				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
++				   sysapb_parents, 0x030, 0x034, 0x038,
++				   16, 2, 23, 0x1C0, 14,
++				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
+ 			     arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1,
+ 			     31, 0x1C0, 15),
+@@ -234,9 +241,10 @@ static const struct mtk_mux top_muxes[]
+ 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
+ 			     sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
+ 			     0x1C0, 21),
+-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
+-			     sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23,
+-			     0x1C0, 22),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
++				   sgm_reg_parents, 0x050, 0x054, 0x058,
++				   16, 1, 23, 0x1C0, 22,
++				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ 	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
+ 			     0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23),
+ 	/* CLK_CFG_6 */
+@@ -252,9 +260,10 @@ static const struct mtk_mux top_muxes[]
+ 			     f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31,
+ 			     0x1C0, 27),
+ 	/* CLK_CFG_7 */
+-	MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel",
+-			     f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7,
+-			     0x1C0, 28),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
++				   f_26m_adc_parents, 0x070, 0x074, 0x078,
++				   0, 1, 7, 0x1C0, 28,
++				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
+ 			     0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29),
+ 	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
+@@ -307,13 +316,6 @@ static int clk_mt7986_topckgen_probe(str
+ 			       ARRAY_SIZE(top_muxes), node,
+ 			       &mt7986_clk_lock, clk_data);
+ 
+-	clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk);
+-	clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAPB_SEL]->clk);
+-	clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_SEL]->clk);
+-	clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_MD32_SEL]->clk);
+-	clk_prepare_enable(clk_data->hws[CLK_TOP_F26M_SEL]->clk);
+-	clk_prepare_enable(clk_data->hws[CLK_TOP_SGM_REG_SEL]->clk);
+-
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 
+ 	if (r) {

target/linux/mediatek/patches-6.1/228-v6.3-clk-mediatek-clk-mt7986-topckgen-Migrate-to-mtk_clk_.patch

@@ -0,0 +1,88 @@
+From 9ce3b4e4719d4eec38b2c8da939c073835573d1d Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <[email protected]>
+Date: Fri, 20 Jan 2023 10:20:53 +0100
+Subject: [PATCH 07/15] clk: mediatek: clk-mt7986-topckgen: Migrate to
+ mtk_clk_simple_probe()
+
+There are no more non-common calls in clk_mt7986_topckgen_probe():
+migrate this driver to mtk_clk_simple_probe().
+
+Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
+Reviewed-by: Miles Chen <[email protected]>
+Reviewed-by: Chen-Yu Tsai <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Tested-by: Mingming Su <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/mediatek/clk-mt7986-topckgen.c | 55 +++++-----------------
+ 1 file changed, 13 insertions(+), 42 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
++++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
+@@ -290,53 +290,24 @@ static const struct mtk_mux top_muxes[]
+ 			     0x1C4, 5),
+ };
+ 
+-static int clk_mt7986_topckgen_probe(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	struct device_node *node = pdev->dev.of_node;
+-	int r;
+-	void __iomem *base;
+-	int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) +
+-		 ARRAY_SIZE(top_muxes);
+-
+-	base = of_iomap(node, 0);
+-	if (!base) {
+-		pr_err("%s(): ioremap failed\n", __func__);
+-		return -ENOMEM;
+-	}
+-
+-	clk_data = mtk_alloc_clk_data(nr);
+-	if (!clk_data)
+-		return -ENOMEM;
+-
+-	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
+-				    clk_data);
+-	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
+-	mtk_clk_register_muxes(&pdev->dev, top_muxes,
+-			       ARRAY_SIZE(top_muxes), node,
+-			       &mt7986_clk_lock, clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-
+-	if (r) {
+-		pr_err("%s(): could not register clock provider: %d\n",
+-		       __func__, r);
+-		goto free_topckgen_data;
+-	}
+-	return r;
+-
+-free_topckgen_data:
+-	mtk_free_clk_data(clk_data);
+-	return r;
+-}
++static const struct mtk_clk_desc topck_desc = {
++	.fixed_clks = top_fixed_clks,
++	.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
++	.factor_clks = top_divs,
++	.num_factor_clks = ARRAY_SIZE(top_divs),
++	.mux_clks = top_muxes,
++	.num_mux_clks = ARRAY_SIZE(top_muxes),
++	.clk_lock = &mt7986_clk_lock,
++};
+ 
+ static const struct of_device_id of_match_clk_mt7986_topckgen[] = {
+-	{ .compatible = "mediatek,mt7986-topckgen", },
+-	{}
++	{ .compatible = "mediatek,mt7986-topckgen", .data = &topck_desc },
++	{ /* sentinel */ }
+ };
+ 
+ static struct platform_driver clk_mt7986_topckgen_drv = {
+-	.probe = clk_mt7986_topckgen_probe,
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
+ 	.driver = {
+ 		.name = "clk-mt7986-topckgen",
+ 		.of_match_table = of_match_clk_mt7986_topckgen,

target/linux/mediatek/patches-6.1/229-v6.4-clk-mediatek-mt7986-apmixed-Use-PLL_AO-flag-to-set-c.patch

@@ -0,0 +1,38 @@
+From 06abdc84080729dc2c54946e1712c5ee1589ca1c Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <[email protected]>
+Date: Mon, 6 Mar 2023 15:05:21 +0100
+Subject: [PATCH 13/15] clk: mediatek: mt7986-apmixed: Use PLL_AO flag to set
+ critical clock
+
+Instead of calling clk_prepare_enable() at probe time, add the PLL_AO
+flag to CLK_APMIXED_ARMPLL clock: this will set CLK_IS_CRITICAL.
+
+Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
+Reviewed-by: Chen-Yu Tsai <[email protected]>
+Tested-by: Daniel Golle <[email protected]>
+Link: https://lore.kernel.org/r/20230306140543.1813621-33-angelogioacchino.delregno@collabora.com
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/mediatek/clk-mt7986-apmixed.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt7986-apmixed.c
++++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c
+@@ -42,7 +42,7 @@
+ 		 "clkxtal")
+ 
+ static const struct mtk_pll_data plls[] = {
+-	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, 0, 32,
++	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32,
+ 	    0x0200, 4, 0, 0x0204, 0),
+ 	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32,
+ 	    0x0210, 4, 0, 0x0214, 0),
+@@ -77,8 +77,6 @@ static int clk_mt7986_apmixed_probe(stru
+ 
+ 	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+ 
+-	clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
+-
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r) {
+ 		pr_err("%s(): could not register clock provider: %d\n",

target/linux/mediatek/patches-6.1/230-v6.4-dt-bindings-clock-mediatek-add-mt7981-clock-IDs.patch

@@ -0,0 +1,237 @@
+From a6473d0f9f07b1196f3a67099826f50a2a4e84e8 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Thu, 26 Jan 2023 03:34:05 +0000
+Subject: [PATCH] dt-bindings: clock: mediatek: add mt7981 clock IDs
+
+Add MT7981 clock dt-bindings, include topckgen, apmixedsys,
+infracfg, and ethernet subsystem clocks.
+
+Acked-by: Krzysztof Kozlowski <[email protected]>
+Signed-off-by: Jianhui Zhao <[email protected]>
+Signed-off-by: Daniel Golle <[email protected]>
+Link: https://lore.kernel.org/r/e353d32b5a4481766519a037afe1ed44e31ece1a.1674703830.git.daniel@makrotopia.org
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ .../dt-bindings/clock/mediatek,mt7981-clk.h   | 215 ++++++++++++++++++
+ 1 file changed, 215 insertions(+)
+ create mode 100644 include/dt-bindings/clock/mediatek,mt7981-clk.h
+
+--- /dev/null
++++ b/include/dt-bindings/clock/mediatek,mt7981-clk.h
+@@ -0,0 +1,215 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
++/*
++ * Copyright (c) 2021 MediaTek Inc.
++ * Author: Wenzhen.Yu <[email protected]>
++ * Author: Jianhui Zhao <[email protected]>
++ * Author: Daniel Golle <[email protected]>
++ */
++
++#ifndef _DT_BINDINGS_CLK_MT7981_H
++#define _DT_BINDINGS_CLK_MT7981_H
++
++/* TOPCKGEN */
++#define CLK_TOP_CB_CKSQ_40M		0
++#define CLK_TOP_CB_M_416M		1
++#define CLK_TOP_CB_M_D2			2
++#define CLK_TOP_CB_M_D3			3
++#define CLK_TOP_M_D3_D2			4
++#define CLK_TOP_CB_M_D4			5
++#define CLK_TOP_CB_M_D8			6
++#define CLK_TOP_M_D8_D2			7
++#define CLK_TOP_CB_MM_720M		8
++#define CLK_TOP_CB_MM_D2		9
++#define CLK_TOP_CB_MM_D3		10
++#define CLK_TOP_CB_MM_D3_D5		11
++#define CLK_TOP_CB_MM_D4		12
++#define CLK_TOP_CB_MM_D6		13
++#define CLK_TOP_MM_D6_D2		14
++#define CLK_TOP_CB_MM_D8		15
++#define CLK_TOP_CB_APLL2_196M		16
++#define CLK_TOP_APLL2_D2		17
++#define CLK_TOP_APLL2_D4		18
++#define CLK_TOP_NET1_2500M		19
++#define CLK_TOP_CB_NET1_D4		20
++#define CLK_TOP_CB_NET1_D5		21
++#define CLK_TOP_NET1_D5_D2		22
++#define CLK_TOP_NET1_D5_D4		23
++#define CLK_TOP_CB_NET1_D8		24
++#define CLK_TOP_NET1_D8_D2		25
++#define CLK_TOP_NET1_D8_D4		26
++#define CLK_TOP_CB_NET2_800M		27
++#define CLK_TOP_CB_NET2_D2		28
++#define CLK_TOP_CB_NET2_D4		29
++#define CLK_TOP_NET2_D4_D2		30
++#define CLK_TOP_NET2_D4_D4		31
++#define CLK_TOP_CB_NET2_D6		32
++#define CLK_TOP_CB_WEDMCU_208M		33
++#define CLK_TOP_CB_SGM_325M		34
++#define CLK_TOP_CKSQ_40M_D2		35
++#define CLK_TOP_CB_RTC_32K		36
++#define CLK_TOP_CB_RTC_32P7K		37
++#define CLK_TOP_USB_TX250M		38
++#define CLK_TOP_FAUD			39
++#define CLK_TOP_NFI1X			40
++#define CLK_TOP_USB_EQ_RX250M		41
++#define CLK_TOP_USB_CDR_CK		42
++#define CLK_TOP_USB_LN0_CK		43
++#define CLK_TOP_SPINFI_BCK		44
++#define CLK_TOP_SPI			45
++#define CLK_TOP_SPIM_MST		46
++#define CLK_TOP_UART_BCK		47
++#define CLK_TOP_PWM_BCK			48
++#define CLK_TOP_I2C_BCK			49
++#define CLK_TOP_PEXTP_TL		50
++#define CLK_TOP_EMMC_208M		51
++#define CLK_TOP_EMMC_400M		52
++#define CLK_TOP_DRAMC_REF		53
++#define CLK_TOP_DRAMC_MD32		54
++#define CLK_TOP_SYSAXI			55
++#define CLK_TOP_SYSAPB			56
++#define CLK_TOP_ARM_DB_MAIN		57
++#define CLK_TOP_AP2CNN_HOST		58
++#define CLK_TOP_NETSYS			59
++#define CLK_TOP_NETSYS_500M		60
++#define CLK_TOP_NETSYS_WED_MCU		61
++#define CLK_TOP_NETSYS_2X		62
++#define CLK_TOP_SGM_325M		63
++#define CLK_TOP_SGM_REG			64
++#define CLK_TOP_F26M			65
++#define CLK_TOP_EIP97B			66
++#define CLK_TOP_USB3_PHY		67
++#define CLK_TOP_AUD			68
++#define CLK_TOP_A1SYS			69
++#define CLK_TOP_AUD_L			70
++#define CLK_TOP_A_TUNER			71
++#define CLK_TOP_U2U3_REF		72
++#define CLK_TOP_U2U3_SYS		73
++#define CLK_TOP_U2U3_XHCI		74
++#define CLK_TOP_USB_FRMCNT		75
++#define CLK_TOP_NFI1X_SEL		76
++#define CLK_TOP_SPINFI_SEL		77
++#define CLK_TOP_SPI_SEL			78
++#define CLK_TOP_SPIM_MST_SEL		79
++#define CLK_TOP_UART_SEL		80
++#define CLK_TOP_PWM_SEL			81
++#define CLK_TOP_I2C_SEL			82
++#define CLK_TOP_PEXTP_TL_SEL		83
++#define CLK_TOP_EMMC_208M_SEL		84
++#define CLK_TOP_EMMC_400M_SEL		85
++#define CLK_TOP_F26M_SEL		86
++#define CLK_TOP_DRAMC_SEL		87
++#define CLK_TOP_DRAMC_MD32_SEL		88
++#define CLK_TOP_SYSAXI_SEL		89
++#define CLK_TOP_SYSAPB_SEL		90
++#define CLK_TOP_ARM_DB_MAIN_SEL		91
++#define CLK_TOP_AP2CNN_HOST_SEL		92
++#define CLK_TOP_NETSYS_SEL		93
++#define CLK_TOP_NETSYS_500M_SEL		94
++#define CLK_TOP_NETSYS_MCU_SEL		95
++#define CLK_TOP_NETSYS_2X_SEL		96
++#define CLK_TOP_SGM_325M_SEL		97
++#define CLK_TOP_SGM_REG_SEL		98
++#define CLK_TOP_EIP97B_SEL		99
++#define CLK_TOP_USB3_PHY_SEL		100
++#define CLK_TOP_AUD_SEL			101
++#define CLK_TOP_A1SYS_SEL		102
++#define CLK_TOP_AUD_L_SEL		103
++#define CLK_TOP_A_TUNER_SEL		104
++#define CLK_TOP_U2U3_SEL		105
++#define CLK_TOP_U2U3_SYS_SEL		106
++#define CLK_TOP_U2U3_XHCI_SEL		107
++#define CLK_TOP_USB_FRMCNT_SEL		108
++#define CLK_TOP_AUD_I2S_M		109
++
++/* INFRACFG */
++#define CLK_INFRA_66M_MCK		0
++#define CLK_INFRA_UART0_SEL		1
++#define CLK_INFRA_UART1_SEL		2
++#define CLK_INFRA_UART2_SEL		3
++#define CLK_INFRA_SPI0_SEL		4
++#define CLK_INFRA_SPI1_SEL		5
++#define CLK_INFRA_SPI2_SEL		6
++#define CLK_INFRA_PWM1_SEL		7
++#define CLK_INFRA_PWM2_SEL		8
++#define CLK_INFRA_PWM3_SEL		9
++#define CLK_INFRA_PWM_BSEL		10
++#define CLK_INFRA_PCIE_SEL		11
++#define CLK_INFRA_GPT_STA		12
++#define CLK_INFRA_PWM_HCK		13
++#define CLK_INFRA_PWM_STA		14
++#define CLK_INFRA_PWM1_CK		15
++#define CLK_INFRA_PWM2_CK		16
++#define CLK_INFRA_PWM3_CK		17
++#define CLK_INFRA_CQ_DMA_CK		18
++#define CLK_INFRA_AUD_BUS_CK		19
++#define CLK_INFRA_AUD_26M_CK		20
++#define CLK_INFRA_AUD_L_CK		21
++#define CLK_INFRA_AUD_AUD_CK		22
++#define CLK_INFRA_AUD_EG2_CK		23
++#define CLK_INFRA_DRAMC_26M_CK		24
++#define CLK_INFRA_DBG_CK		25
++#define CLK_INFRA_AP_DMA_CK		26
++#define CLK_INFRA_SEJ_CK		27
++#define CLK_INFRA_SEJ_13M_CK		28
++#define CLK_INFRA_THERM_CK		29
++#define CLK_INFRA_I2C0_CK		30
++#define CLK_INFRA_UART0_CK		31
++#define CLK_INFRA_UART1_CK		32
++#define CLK_INFRA_UART2_CK		33
++#define CLK_INFRA_SPI2_CK		34
++#define CLK_INFRA_SPI2_HCK_CK		35
++#define CLK_INFRA_NFI1_CK		36
++#define CLK_INFRA_SPINFI1_CK		37
++#define CLK_INFRA_NFI_HCK_CK		38
++#define CLK_INFRA_SPI0_CK		39
++#define CLK_INFRA_SPI1_CK		40
++#define CLK_INFRA_SPI0_HCK_CK		41
++#define CLK_INFRA_SPI1_HCK_CK		42
++#define CLK_INFRA_FRTC_CK		43
++#define CLK_INFRA_MSDC_CK		44
++#define CLK_INFRA_MSDC_HCK_CK		45
++#define CLK_INFRA_MSDC_133M_CK		46
++#define CLK_INFRA_MSDC_66M_CK		47
++#define CLK_INFRA_ADC_26M_CK		48
++#define CLK_INFRA_ADC_FRC_CK		49
++#define CLK_INFRA_FBIST2FPC_CK		50
++#define CLK_INFRA_I2C_MCK_CK		51
++#define CLK_INFRA_I2C_PCK_CK		52
++#define CLK_INFRA_IUSB_133_CK		53
++#define CLK_INFRA_IUSB_66M_CK		54
++#define CLK_INFRA_IUSB_SYS_CK		55
++#define CLK_INFRA_IUSB_CK		56
++#define CLK_INFRA_IPCIE_CK		57
++#define CLK_INFRA_IPCIE_PIPE_CK		58
++#define CLK_INFRA_IPCIER_CK		59
++#define CLK_INFRA_IPCIEB_CK		60
++
++/* APMIXEDSYS */
++#define CLK_APMIXED_ARMPLL		0
++#define CLK_APMIXED_NET2PLL		1
++#define CLK_APMIXED_MMPLL		2
++#define CLK_APMIXED_SGMPLL		3
++#define CLK_APMIXED_WEDMCUPLL		4
++#define CLK_APMIXED_NET1PLL		5
++#define CLK_APMIXED_MPLL		6
++#define CLK_APMIXED_APLL2		7
++
++/* SGMIISYS_0 */
++#define CLK_SGM0_TX_EN			0
++#define CLK_SGM0_RX_EN			1
++#define CLK_SGM0_CK0_EN			2
++#define CLK_SGM0_CDR_CK0_EN		3
++
++/* SGMIISYS_1 */
++#define CLK_SGM1_TX_EN			0
++#define CLK_SGM1_RX_EN			1
++#define CLK_SGM1_CK1_EN			2
++#define CLK_SGM1_CDR_CK1_EN		3
++
++/* ETHSYS */
++#define CLK_ETH_FE_EN			0
++#define CLK_ETH_GP2_EN			1
++#define CLK_ETH_GP1_EN			2
++#define CLK_ETH_WOCPU0_EN		3
++
++#endif /* _DT_BINDINGS_CLK_MT7981_H */