brcm63xx: add kernel 4.9 support

Add support for kernel 4.9 based on the more upstream comformant
partition defintions. Increases compressed kernel size by ~95k
compared to 4.4.

Signed-off-by: Jonas Gorski <[email protected]>

target/linux/brcm63xx/config-4.9

@@ -0,0 +1,261 @@
+CONFIG_ARCH_BINFMT_ELF_STATE=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set
+# CONFIG_ARCH_HAS_SG_CHAIN is not set
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_BCM6345_EXT_IRQ=y
+CONFIG_BCM6345_PERIPH_IRQ=y
+CONFIG_BCM63XX=y
+CONFIG_BCM63XX_CPU_3368=y
+CONFIG_BCM63XX_CPU_6318=y
+CONFIG_BCM63XX_CPU_63268=y
+CONFIG_BCM63XX_CPU_6328=y
+CONFIG_BCM63XX_CPU_6338=y
+CONFIG_BCM63XX_CPU_6345=y
+CONFIG_BCM63XX_CPU_6348=y
+CONFIG_BCM63XX_CPU_6358=y
+CONFIG_BCM63XX_CPU_6362=y
+CONFIG_BCM63XX_CPU_6368=y
+CONFIG_BCM63XX_EHCI=y
+CONFIG_BCM63XX_ENET=y
+CONFIG_BCM63XX_OHCI=y
+CONFIG_BCM63XX_PHY=y
+CONFIG_BCM63XX_WDT=y
+CONFIG_BCMA=y
+CONFIG_BCMA_BLOCKIO=y
+# CONFIG_BCMA_DEBUG is not set
+# CONFIG_BCMA_DRIVER_GMAC_CMN is not set
+# CONFIG_BCMA_DRIVER_MIPS is not set
+CONFIG_BCMA_DRIVER_PCI=y
+# CONFIG_BCMA_DRIVER_PCI_HOSTMODE is not set
+CONFIG_BCMA_HOST_PCI=y
+CONFIG_BCMA_HOST_PCI_POSSIBLE=y
+# CONFIG_BCMA_HOST_SOC is not set
+CONFIG_BCM_NET_PHYLIB=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BOARD_BCM63XX_DT=y
+CONFIG_BOARD_BCM963XX=y
+CONFIG_BOARD_LIVEBOX=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_BMIPS=y
+CONFIG_CPU_BMIPS32_3300=y
+CONFIG_CPU_BMIPS4350=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_FIXED_PHY=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_BCM63XX=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+# CONFIG_HAVE_ARCH_BITREVERSE is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_CBPF_JIT=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_BCM63XX=y
+CONFIG_HZ=250
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_KEXEC=y
+CONFIG_KEXEC_CORE=y
+CONFIG_LEDS_BCM6328=y
+CONFIG_LEDS_BCM6358=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LIBFDT=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+# CONFIG_MIPS_ELF_APPENDED_DTB is not set
+# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=4
+CONFIG_MIPS_L1_CACHE_SHIFT_4=y
+# CONFIG_MIPS_MACHINE is not set
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MTD_BCM63XX_PARTS=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_BE_BYTE_SWAP=y
+# CONFIG_MTD_CFI_GEOMETRY is not set
+# CONFIG_MTD_CFI_NOSWAP is not set
+CONFIG_MTD_CFI_STAA=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_PARSER_IMAGETAG=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+# CONFIG_NO_IOPORT_MAP is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_PCI=y
+# CONFIG_PCIEAER is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_BCM6318=y
+CONFIG_PINCTRL_BCM63268=y
+CONFIG_PINCTRL_BCM6328=y
+CONFIG_PINCTRL_BCM6348=y
+CONFIG_PINCTRL_BCM6358=y
+CONFIG_PINCTRL_BCM6362=y
+CONFIG_PINCTRL_BCM6368=y
+CONFIG_PINCTRL_BCM63XX=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_RCU_STALL_COMMON is not set
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RELAY=y
+CONFIG_RTL8366_SMI=y
+CONFIG_RTL8367_PHY=y
+# CONFIG_SCHED_INFO is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_BCM63XX=y
+CONFIG_SERIAL_BCM63XX_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_SPI_BCM63XX=y
+CONFIG_SPI_BCM63XX_HSSPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SQUASHFS_EMBEDDED=y
+CONFIG_SRCU=y
+CONFIG_SSB=y
+CONFIG_SSB_B43_PCI_BRIDGE=y
+CONFIG_SSB_BLOCKIO=y
+# CONFIG_SSB_DRIVER_MIPS is not set
+CONFIG_SSB_DRIVER_PCICORE=y
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_SPROM=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_SWCONFIG=y
+CONFIG_SWCONFIG_B53=y
+CONFIG_SWCONFIG_B53_MMAP_DRIVER=y
+CONFIG_SWCONFIG_B53_PHY_DRIVER=y
+CONFIG_SWCONFIG_B53_PHY_FIXUP=y
+CONFIG_SWCONFIG_B53_SPI_DRIVER=y
+# CONFIG_SWCONFIG_B53_SRAB_DRIVER is not set
+CONFIG_SWPHY=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_BMIPS=y
+CONFIG_SYS_HAS_CPU_BMIPS32_3300=y
+CONFIG_SYS_HAS_CPU_BMIPS4350=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_WEAK_ORDERING=y

target/linux/brcm63xx/patches-4.9/001-4.11-01-mtd-m25p80-consider-max-message-size-in-m25p80_read.patch

@@ -0,0 +1,30 @@
+From 80a79a889ce5df16c5261ab2f1e8e63b94b78102 Mon Sep 17 00:00:00 2001
+From: Heiner Kallweit <[email protected]>
+Date: Fri, 28 Oct 2016 07:58:46 +0200
+Subject: [PATCH 1/8] mtd: m25p80: consider max message size in m25p80_read
+
+Consider a message size limit when calculating the maximum amount
+of data that can be read.
+
+The message size limit has been introduced with 4.9, so cc it
+to stable.
+
+Signed-off-by: Heiner Kallweit <[email protected]>
+Cc: <[email protected]> # 4.9.x
+Signed-off-by: Cyrille Pitchen <[email protected]>
+---
+ drivers/mtd/devices/m25p80.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -172,7 +172,8 @@ static ssize_t m25p80_read(struct spi_no
+ 
+ 	t[1].rx_buf = buf;
+ 	t[1].rx_nbits = m25p80_rx_nbits(nor);
+-	t[1].len = min(len, spi_max_transfer_size(spi));
++	t[1].len = min3(len, spi_max_transfer_size(spi),
++			spi_max_message_size(spi) - t[0].len);
+ 	spi_message_add_tail(&t[1], &m);
+ 
+ 	ret = spi_sync(spi, &m);

target/linux/brcm63xx/patches-4.9/001-4.12-01-spi-bcm63xx-make-spi-subsystem-aware-of-message-size.patch

@@ -0,0 +1,42 @@
+From 3fcc36962c32ad0af2d5904103e2b2b824b6b1aa Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sat, 4 Feb 2017 12:32:59 +0100
+Subject: [PATCH 2/8] spi/bcm63xx: make spi subsystem aware of message size
+ limits
+
+The bcm63xx LS SPI controller does not allow manual control of the CS
+lines and will toggle it automatically before after sending data, so we
+are limited to messages that fit in the FIFO buffer. Since the CS lines
+aren't available as GPIOs either, we will need to make slave drivers
+aware of this limitation and handle it accordingly.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/spi/spi-bcm63xx.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/drivers/spi/spi-bcm63xx.c
++++ b/drivers/spi/spi-bcm63xx.c
+@@ -428,6 +428,13 @@ static irqreturn_t bcm63xx_spi_interrupt
+ 	return IRQ_HANDLED;
+ }
+ 
++static size_t bcm63xx_spi_max_length(struct spi_device *spi)
++{
++	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
++
++	return bs->fifo_size;
++}
++
+ static const unsigned long bcm6348_spi_reg_offsets[] = {
+ 	[SPI_CMD]		= SPI_6348_CMD,
+ 	[SPI_INT_STATUS]	= SPI_6348_INT_STATUS,
+@@ -541,6 +548,8 @@ static int bcm63xx_spi_probe(struct plat
+ 	master->transfer_one_message = bcm63xx_spi_transfer_one;
+ 	master->mode_bits = MODEBITS;
+ 	master->bits_per_word_mask = SPI_BPW_MASK(8);
++	master->max_transfer_size = bcm63xx_spi_max_length;
++	master->max_message_size = bcm63xx_spi_max_length;
+ 	master->auto_runtime_pm = true;
+ 	bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT];
+ 	bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH];

target/linux/brcm63xx/patches-4.9/001-4.12-02-spi-bcm63xx-document-device-tree-bindings.patch

@@ -0,0 +1,50 @@
+From 0a0c39044332a75eaf4a3c5654079df953b0d839 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Mon, 7 Sep 2015 21:00:38 +0200
+Subject: [PATCH 3/8] spi/bcm63xx: document device tree bindings
+
+Add documentation for the bindings of the low speed SPI controller found
+on most bcm63xx SoCs.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ .../devicetree/bindings/spi/spi-bcm63xx.txt        | 33 ++++++++++++++++++++++
+ 1 file changed, 33 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/spi/spi-bcm63xx.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/spi/spi-bcm63xx.txt
+@@ -0,0 +1,33 @@
++Binding for Broadcom BCM6348/BCM6358 SPI controller
++
++Required properties:
++- compatible: must contain one of "brcm,bcm6348-spi", "brcm,bcm6358-spi".
++- reg: Base address and size of the controllers memory area.
++- interrupts: Interrupt for the SPI block.
++- clocks: phandle of the SPI clock.
++- clock-names: has to be "spi".
++- #address-cells: <1>, as required by generic SPI binding.
++- #size-cells: <0>, also as required by generic SPI binding.
++
++Optional properties:
++- num-cs: some controllers have less than 8 cs signals. Defaults to 8
++  if absent.
++
++Child nodes as per the generic SPI binding.
++
++Example:
++
++	spi@10000800 {
++		compatible = "brcm,bcm6368-spi", "brcm,bcm6358-spi";
++		reg = <0x10000800 0x70c>;
++
++		interrupts = <1>;
++
++		clocks = <&clkctl 9>;
++		clock-names = "spi";
++
++		num-cs = <5>;
++
++		#address-cells = <1>;
++		#size-cells = <0>;
++	};

target/linux/brcm63xx/patches-4.9/001-4.12-03-spi-bcm63xx-add-support-for-probing-through-devicetr.patch

@@ -0,0 +1,98 @@
+From 3353228a04a004ec67073871f40cf58dc4e209aa Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Mon, 7 Sep 2015 21:01:38 +0200
+Subject: [PATCH 4/8] spi/bcm63xx: add support for probing through devicetree
+
+Add required binding support to probe through device tree.
+
+Use the compatible instead of the resource size for identifiying the
+block type, and allow reducing the number of cs lines through OF.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/spi/spi-bcm63xx.c | 42 ++++++++++++++++++++++++++++++++++++------
+ 1 file changed, 36 insertions(+), 6 deletions(-)
+
+--- a/drivers/spi/spi-bcm63xx.c
++++ b/drivers/spi/spi-bcm63xx.c
+@@ -26,6 +26,7 @@
+ #include <linux/completion.h>
+ #include <linux/err.h>
+ #include <linux/pm_runtime.h>
++#include <linux/of.h>
+ 
+ /* BCM 6338/6348 SPI core */
+ #define SPI_6348_RSET_SIZE		64
+@@ -484,21 +485,48 @@ static const struct platform_device_id b
+ 	},
+ };
+ 
++static const struct of_device_id bcm63xx_spi_of_match[] = {
++	{ .compatible = "brcm,bcm6348-spi", .data = &bcm6348_spi_reg_offsets },
++	{ .compatible = "brcm,bcm6358-spi", .data = &bcm6358_spi_reg_offsets },
++	{ },
++};
++
+ static int bcm63xx_spi_probe(struct platform_device *pdev)
+ {
+ 	struct resource *r;
+ 	const unsigned long *bcm63xx_spireg;
+ 	struct device *dev = &pdev->dev;
+-	int irq;
++	int irq, bus_num;
+ 	struct spi_master *master;
+ 	struct clk *clk;
+ 	struct bcm63xx_spi *bs;
+ 	int ret;
++	u32 num_cs = BCM63XX_SPI_MAX_CS;
+ 
+-	if (!pdev->id_entry->driver_data)
+-		return -EINVAL;
++	if (dev->of_node) {
++		const struct of_device_id *match;
+ 
+-	bcm63xx_spireg = (const unsigned long *)pdev->id_entry->driver_data;
++		match = of_match_node(bcm63xx_spi_of_match, dev->of_node);
++		if (!match)
++			return -EINVAL;
++		bcm63xx_spireg = match->data;
++
++		of_property_read_u32(dev->of_node, "num-cs", &num_cs);
++		if (num_cs > BCM63XX_SPI_MAX_CS) {
++			dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
++				 num_cs);
++			num_cs = BCM63XX_SPI_MAX_CS;
++		}
++
++		bus_num = -1;
++	} else if (pdev->id_entry->driver_data) {
++		const struct platform_device_id *match = pdev->id_entry;
++
++		bcm63xx_spireg = (const unsigned long *)match->driver_data;
++		bus_num = BCM63XX_SPI_BUS_NUM;
++	} else {
++		return -EINVAL;
++	}
+ 
+ 	irq = platform_get_irq(pdev, 0);
+ 	if (irq < 0) {
+@@ -543,8 +571,9 @@ static int bcm63xx_spi_probe(struct plat
+ 		goto out_err;
+ 	}
+ 
+-	master->bus_num = BCM63XX_SPI_BUS_NUM;
+-	master->num_chipselect = BCM63XX_SPI_MAX_CS;
++	master->dev.of_node = dev->of_node;
++	master->bus_num = bus_num;
++	master->num_chipselect = num_cs;
+ 	master->transfer_one_message = bcm63xx_spi_transfer_one;
+ 	master->mode_bits = MODEBITS;
+ 	master->bits_per_word_mask = SPI_BPW_MASK(8);
+@@ -633,6 +662,7 @@ static struct platform_driver bcm63xx_sp
+ 	.driver = {
+ 		.name	= "bcm63xx-spi",
+ 		.pm	= &bcm63xx_spi_pm_ops,
++		.of_match_table = bcm63xx_spi_of_match,
+ 	},
+ 	.id_table	= bcm63xx_spi_dev_match,
+ 	.probe		= bcm63xx_spi_probe,

target/linux/brcm63xx/patches-4.9/001-4.12-04-spi-bcm63xx-hsspi-allow-providing-clock-rate-through.patch

@@ -0,0 +1,35 @@
+From d03f23df6ff47898d76f06b3aa5dadcfa1ec8f4f Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 19 Feb 2017 23:40:22 +0100
+Subject: [PATCH 1/3] spi/bcm63xx-hsspi: allow providing clock rate through a
+ second clock
+
+Instead of requiring the hsspi clock to have a rate, allow using a second
+clock for providing the Hz rate, which is probably more correct anyway.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/spi/spi-bcm63xx-hsspi.c | 12 ++++++++++--
+ 1 file changed, 10 insertions(+), 2 deletions(-)
+
+--- a/drivers/spi/spi-bcm63xx-hsspi.c
++++ b/drivers/spi/spi-bcm63xx-hsspi.c
+@@ -351,8 +351,16 @@ static int bcm63xx_hsspi_probe(struct pl
+ 		return PTR_ERR(clk);
+ 
+ 	rate = clk_get_rate(clk);
+-	if (!rate)
+-		return -EINVAL;
++	if (!rate) {
++		struct clk *pll_clk = devm_clk_get(dev, "pll");
++
++		if (IS_ERR(pll_clk))
++			return PTR_ERR(pll_clk);
++
++		rate = clk_get_rate(pll_clk);
++		if (!rate)
++			return -EINVAL;
++	}
+ 
+ 	ret = clk_prepare_enable(clk);
+ 	if (ret)

target/linux/brcm63xx/patches-4.9/001-4.12-05-spi-bcm63xx-hsspi-document-device-tree-bindings.patch

@@ -0,0 +1,51 @@
+From ff759cc25db31bbb3469abb16a0306f110c4c7fa Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Thu, 10 Sep 2015 14:52:32 +0200
+Subject: [PATCH 2/3] dt-bindings: spi: document bcm63xx HS SPI devicetree
+ bindings
+
+Add documentation for the bindings of the high speed SPI controller found
+on newer bcm63xx SoCs.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ .../devicetree/bindings/spi/spi-bcm63xx-hsspi.txt  | 33 ++++++++++++++++++++++
+ 1 file changed, 33 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/spi/spi-bcm63xx-hsspi.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/spi/spi-bcm63xx-hsspi.txt
+@@ -0,0 +1,33 @@
++Binding for Broadcom BCM6328 High Speed SPI controller
++
++Required properties:
++- compatible: must contain of "brcm,bcm6328-hsspi".
++- reg: Base address and size of the controllers memory area.
++- interrupts: Interrupt for the SPI block.
++- clocks: phandles of the SPI clock and the PLL clock.
++- clock-names: must be "hsspi", "pll".
++- #address-cells: <1>, as required by generic SPI binding.
++- #size-cells: <0>, also as required by generic SPI binding.
++
++Optional properties:
++- num-cs: some controllers have less than 8 cs signals. Defaults to 8
++  if absent.
++
++Child nodes as per the generic SPI binding.
++
++Example:
++
++	spi@10001000 {
++		compatible = "brcm,bcm6328-hsspi";
++		reg = <0x10001000 0x600>;
++
++		interrupts = <29>;
++
++		clocks = <&clkctl 9>, <&hsspi_pll>;
++		clock-names = "hsspi", "pll";
++
++		num-cs = <2>;
++
++		#address-cells = <1>;
++		#size-cells = <0>;
++	};

target/linux/brcm63xx/patches-4.9/001-4.12-06-spi-bcm63xx-hsspi-add-support-for-probing-through-de.patch

@@ -0,0 +1,76 @@
+From 776041498c2b285a7f745c924e10fc11ef720eae Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Thu, 10 Sep 2015 14:53:53 +0200
+Subject: [PATCH 3/3] spi/bcm63xx-hsspi: allow for probing through devicetree
+
+Add required binding support to probe through device tree.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/spi/spi-bcm63xx-hsspi.c | 23 ++++++++++++++++++++---
+ 1 file changed, 20 insertions(+), 3 deletions(-)
+
+--- a/drivers/spi/spi-bcm63xx-hsspi.c
++++ b/drivers/spi/spi-bcm63xx-hsspi.c
+@@ -19,6 +19,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/spi/spi.h>
+ #include <linux/mutex.h>
++#include <linux/of.h>
+ 
+ #define HSSPI_GLOBAL_CTRL_REG			0x0
+ #define GLOBAL_CTRL_CS_POLARITY_SHIFT		0
+@@ -91,6 +92,7 @@
+ 
+ #define HSSPI_MAX_SYNC_CLOCK			30000000
+ 
++#define HSSPI_SPI_MAX_CS			8
+ #define HSSPI_BUS_NUM				1 /* 0 is legacy SPI */
+ 
+ struct bcm63xx_hsspi {
+@@ -332,7 +334,7 @@ static int bcm63xx_hsspi_probe(struct pl
+ 	struct device *dev = &pdev->dev;
+ 	struct clk *clk;
+ 	int irq, ret;
+-	u32 reg, rate;
++	u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS;
+ 
+ 	irq = platform_get_irq(pdev, 0);
+ 	if (irq < 0) {
+@@ -382,8 +384,17 @@ static int bcm63xx_hsspi_probe(struct pl
+ 	mutex_init(&bs->bus_mutex);
+ 	init_completion(&bs->done);
+ 
+-	master->bus_num = HSSPI_BUS_NUM;
+-	master->num_chipselect = 8;
++	master->dev.of_node = dev->of_node;
++	if (!dev->of_node)
++		master->bus_num = HSSPI_BUS_NUM;
++
++	of_property_read_u32(dev->of_node, "num-cs", &num_cs);
++	if (num_cs > 8) {
++		dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
++			 num_cs);
++		num_cs = HSSPI_SPI_MAX_CS;
++	}
++	master->num_chipselect = num_cs;
+ 	master->setup = bcm63xx_hsspi_setup;
+ 	master->transfer_one_message = bcm63xx_hsspi_transfer_one;
+ 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
+@@ -469,10 +480,16 @@ static int bcm63xx_hsspi_resume(struct d
+ static SIMPLE_DEV_PM_OPS(bcm63xx_hsspi_pm_ops, bcm63xx_hsspi_suspend,
+ 			 bcm63xx_hsspi_resume);
+ 
++static const struct of_device_id bcm63xx_hsspi_of_match[] = {
++	{ .compatible = "brcm,bcm6328-hsspi", },
++	{ },
++};
++
+ static struct platform_driver bcm63xx_hsspi_driver = {
+ 	.driver = {
+ 		.name	= "bcm63xx-hsspi",
+ 		.pm	= &bcm63xx_hsspi_pm_ops,
++		.of_match_table = bcm63xx_hsspi_of_match,
+ 	},
+ 	.probe		= bcm63xx_hsspi_probe,
+ 	.remove		= bcm63xx_hsspi_remove,

target/linux/brcm63xx/patches-4.9/001-4.12-07-mdio_bus-Issue-GPIO-RESET-to-PHYs.patch

@@ -0,0 +1,192 @@
+From 69226896ad636b94f6d2e55d75ff21a29c4de83b Mon Sep 17 00:00:00 2001
+From: Roger Quadros <[email protected]>
+Date: Fri, 21 Apr 2017 16:15:38 +0300
+Subject: [PATCH] mdio_bus: Issue GPIO RESET to PHYs.
+
+Some boards [1] leave the PHYs at an invalid state
+during system power-up or reset thus causing unreliability
+issues with the PHY which manifests as PHY not being detected
+or link not functional. To fix this, these PHYs need to be RESET
+via a GPIO connected to the PHY's RESET pin.
+
+Some boards have a single GPIO controlling the PHY RESET pin of all
+PHYs on the bus whereas some others have separate GPIOs controlling
+individual PHY RESETs.
+
+In both cases, the RESET de-assertion cannot be done in the PHY driver
+as the PHY will not probe till its reset is de-asserted.
+So do the RESET de-assertion in the MDIO bus driver.
+
+[1] - am572x-idk, am571x-idk, a437x-idk
+
+Signed-off-by: Roger Quadros <[email protected]>
+Signed-off-by: David S. Miller <[email protected]>
+---
+ Documentation/devicetree/bindings/net/mdio.txt | 33 ++++++++++++++++++
+ drivers/net/phy/mdio_bus.c                     | 47 ++++++++++++++++++++++++++
+ drivers/of/of_mdio.c                           |  7 ++++
+ include/linux/phy.h                            |  7 ++++
+ 4 files changed, 94 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/net/mdio.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/net/mdio.txt
+@@ -0,0 +1,33 @@
++Common MDIO bus properties.
++
++These are generic properties that can apply to any MDIO bus.
++
++Optional properties:
++- reset-gpios: List of one or more GPIOs that control the RESET lines
++  of the PHYs on that MDIO bus.
++- reset-delay-us: RESET pulse width in microseconds as per PHY datasheet.
++
++A list of child nodes, one per device on the bus is expected. These
++should follow the generic phy.txt, or a device specific binding document.
++
++Example :
++This example shows these optional properties, plus other properties
++required for the TI Davinci MDIO driver.
++
++	davinci_mdio: ethernet@0x5c030000 {
++		compatible = "ti,davinci_mdio";
++		reg = <0x5c030000 0x1000>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
++		reset-delay-us = <2>;   /* PHY datasheet states 1us min */
++
++		ethphy0: ethernet-phy@1 {
++			reg = <1>;
++		};
++
++		ethphy1: ethernet-phy@3 {
++			reg = <3>;
++		};
++	};
+--- a/drivers/net/phy/mdio_bus.c
++++ b/drivers/net/phy/mdio_bus.c
+@@ -22,8 +22,11 @@
+ #include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/device.h>
++#include <linux/gpio.h>
++#include <linux/gpio/consumer.h>
+ #include <linux/of_device.h>
+ #include <linux/of_mdio.h>
++#include <linux/of_gpio.h>
+ #include <linux/netdevice.h>
+ #include <linux/etherdevice.h>
+ #include <linux/skbuff.h>
+@@ -304,6 +307,7 @@ int __mdiobus_register(struct mii_bus *b
+ {
+ 	struct mdio_device *mdiodev;
+ 	int i, err;
++	struct gpio_desc *gpiod;
+ 
+ 	if (NULL == bus || NULL == bus->name ||
+ 	    NULL == bus->read || NULL == bus->write)
+@@ -330,6 +334,35 @@ int __mdiobus_register(struct mii_bus *b
+ 	if (bus->reset)
+ 		bus->reset(bus);
+ 
++	/* de-assert bus level PHY GPIO resets */
++	if (bus->num_reset_gpios > 0) {
++		bus->reset_gpiod = devm_kcalloc(&bus->dev,
++						 bus->num_reset_gpios,
++						 sizeof(struct gpio_desc *),
++						 GFP_KERNEL);
++		if (!bus->reset_gpiod)
++			return -ENOMEM;
++	}
++
++	for (i = 0; i < bus->num_reset_gpios; i++) {
++		gpiod = devm_gpiod_get_index(&bus->dev, "reset", i,
++					     GPIOD_OUT_LOW);
++		if (IS_ERR(gpiod)) {
++			err = PTR_ERR(gpiod);
++			if (err != -ENOENT) {
++				dev_err(&bus->dev,
++					"mii_bus %s couldn't get reset GPIO\n",
++					bus->id);
++				return err;
++			}
++		} else {
++			bus->reset_gpiod[i] = gpiod;
++			gpiod_set_value_cansleep(gpiod, 1);
++			udelay(bus->reset_delay_us);
++			gpiod_set_value_cansleep(gpiod, 0);
++		}
++	}
++
+ 	for (i = 0; i < PHY_MAX_ADDR; i++) {
+ 		if ((bus->phy_mask & (1 << i)) == 0) {
+ 			struct phy_device *phydev;
+@@ -355,6 +388,13 @@ error:
+ 		mdiodev->device_remove(mdiodev);
+ 		mdiodev->device_free(mdiodev);
+ 	}
++
++	/* Put PHYs in RESET to save power */
++	for (i = 0; i < bus->num_reset_gpios; i++) {
++		if (bus->reset_gpiod[i])
++			gpiod_set_value_cansleep(bus->reset_gpiod[i], 1);
++	}
++
+ 	device_del(&bus->dev);
+ 	return err;
+ }
+@@ -376,6 +416,13 @@ void mdiobus_unregister(struct mii_bus *
+ 		mdiodev->device_remove(mdiodev);
+ 		mdiodev->device_free(mdiodev);
+ 	}
++
++	/* Put PHYs in RESET to save power */
++	for (i = 0; i < bus->num_reset_gpios; i++) {
++		if (bus->reset_gpiod[i])
++			gpiod_set_value_cansleep(bus->reset_gpiod[i], 1);
++	}
++
+ 	device_del(&bus->dev);
+ }
+ EXPORT_SYMBOL(mdiobus_unregister);
+--- a/drivers/of/of_mdio.c
++++ b/drivers/of/of_mdio.c
+@@ -22,6 +22,8 @@
+ #include <linux/of_net.h>
+ #include <linux/module.h>
+ 
++#define DEFAULT_GPIO_RESET_DELAY	10	/* in microseconds */
++
+ MODULE_AUTHOR("Grant Likely <[email protected]>");
+ MODULE_LICENSE("GPL");
+ 
+@@ -220,6 +222,11 @@ int of_mdiobus_register(struct mii_bus *
+ 
+ 	mdio->dev.of_node = np;
+ 
++	/* Get bus level PHY reset GPIO details */
++	mdio->reset_delay_us = DEFAULT_GPIO_RESET_DELAY;
++	of_property_read_u32(np, "reset-delay-us", &mdio->reset_delay_us);
++	mdio->num_reset_gpios = of_gpio_named_count(np, "reset-gpios");
++
+ 	/* Register the MDIO bus */
+ 	rc = mdiobus_register(mdio);
+ 	if (rc)
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -193,6 +193,13 @@ struct mii_bus {
+ 	 * matching its address
+ 	 */
+ 	int irq[PHY_MAX_ADDR];
++
++	/* GPIO reset pulse width in microseconds */
++	int reset_delay_us;
++	/* Number of reset GPIOs */
++	int num_reset_gpios;
++	/* Array of RESET GPIO descriptors */
++	struct gpio_desc **reset_gpiod;
+ };
+ #define to_mii_bus(d) container_of(d, struct mii_bus, dev)
+ 

target/linux/brcm63xx/patches-4.9/001-4.12-08-net-phy-Call-bus-reset-after-releasing-PHYs-from-res.patch

@@ -0,0 +1,43 @@
+From df0c8d911abf6ba97b2c2fc3c5a12769e0b081a3 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <[email protected]>
+Date: Thu, 11 May 2017 11:24:16 -0700
+Subject: [PATCH] net: phy: Call bus->reset() after releasing PHYs from reset
+
+The API convention makes it that a given MDIO bus reset should be able
+to access PHY devices in its reset() callback and perform additional
+MDIO accesses in order to bring the bus and PHYs in a working state.
+
+Commit 69226896ad63 ("mdio_bus: Issue GPIO RESET to PHYs.") broke that
+contract by first calling bus->reset() and then release all PHYs from
+reset using their shared GPIO line, so restore the expected
+functionality here.
+
+Fixes: 69226896ad63 ("mdio_bus: Issue GPIO RESET to PHYs.")
+Signed-off-by: Florian Fainelli <[email protected]>
+Signed-off-by: David S. Miller <[email protected]>
+---
+ drivers/net/phy/mdio_bus.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/phy/mdio_bus.c
++++ b/drivers/net/phy/mdio_bus.c
+@@ -331,9 +331,6 @@ int __mdiobus_register(struct mii_bus *b
+ 
+ 	mutex_init(&bus->mdio_lock);
+ 
+-	if (bus->reset)
+-		bus->reset(bus);
+-
+ 	/* de-assert bus level PHY GPIO resets */
+ 	if (bus->num_reset_gpios > 0) {
+ 		bus->reset_gpiod = devm_kcalloc(&bus->dev,
+@@ -363,6 +360,9 @@ int __mdiobus_register(struct mii_bus *b
+ 		}
+ 	}
+ 
++	if (bus->reset)
++		bus->reset(bus);
++
+ 	for (i = 0; i < PHY_MAX_ADDR; i++) {
+ 		if ((bus->phy_mask & (1 << i)) == 0) {
+ 			struct phy_device *phydev;

target/linux/brcm63xx/patches-4.9/001-4.13-01-leds-bcm6328-fix-signal-source-assignment-for-high-l.patch

@@ -0,0 +1,34 @@
+From dc90895d776d7b8017bc3b14f588d569d8edbe1f Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Thu, 11 May 2017 13:36:52 +0200
+Subject: [PATCH] leds: bcm6328: fix signal source assignment for high leds
+
+Each nibble represents 4 LEDs, and in case of the higher register, bit 0
+represents LED 4, so we need to use modulus for the LED number as well.
+
+Fixes: fd7b025a238d0a5440bfa26c585eb78097bf48dc ("leds: add BCM6328 LED driver")
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/leds/leds-bcm6328.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/leds/leds-bcm6328.c
++++ b/drivers/leds/leds-bcm6328.c
+@@ -242,7 +242,7 @@ static int bcm6328_hwled(struct device *
+ 
+ 		spin_lock_irqsave(lock, flags);
+ 		val = bcm6328_led_read(addr);
+-		val |= (BIT(reg) << (((sel % 4) * 4) + 16));
++		val |= (BIT(reg % 4) << (((sel % 4) * 4) + 16));
+ 		bcm6328_led_write(addr, val);
+ 		spin_unlock_irqrestore(lock, flags);
+ 	}
+@@ -269,7 +269,7 @@ static int bcm6328_hwled(struct device *
+ 
+ 		spin_lock_irqsave(lock, flags);
+ 		val = bcm6328_led_read(addr);
+-		val |= (BIT(reg) << ((sel % 4) * 4));
++		val |= (BIT(reg % 4) << ((sel % 4) * 4));
+ 		bcm6328_led_write(addr, val);
+ 		spin_unlock_irqrestore(lock, flags);
+ 	}

target/linux/brcm63xx/patches-4.9/001-4.15-01-MIPS-BCM63XX-add-clkdev-lookup-support.patch

@@ -0,0 +1,210 @@
+From e74caf41aec5338b8cbbd0a1483650848f16f532 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 16 Jul 2017 12:23:47 +0200
+Subject: [PATCH V2 1/8] MIPS: BCM63XX: add clkdev lookup support
+
+Enable clkdev lookup support to allow us providing clocks under
+different names to devices more easily, so we don't need to care
+about clock name clashes anymore.
+
+Reviewed-by: Florian Fainelli <[email protected]>
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/Kconfig       |   1 +
+ arch/mips/bcm63xx/clk.c | 150 +++++++++++++++++++++++++++++++++++++-----------
+ 2 files changed, 116 insertions(+), 35 deletions(-)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -271,6 +271,7 @@ config BCM63XX
+ 	select GPIOLIB
+ 	select HAVE_CLK
+ 	select MIPS_L1_CACHE_SHIFT_4
++	select CLKDEV_LOOKUP
+ 	help
+ 	 Support for BCM63XX based boards
+ 
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -10,6 +10,7 @@
+ #include <linux/mutex.h>
+ #include <linux/err.h>
+ #include <linux/clk.h>
++#include <linux/clkdev.h>
+ #include <linux/delay.h>
+ #include <bcm63xx_cpu.h>
+ #include <bcm63xx_io.h>
+@@ -355,44 +356,103 @@ long clk_round_rate(struct clk *clk, uns
+ }
+ EXPORT_SYMBOL_GPL(clk_round_rate);
+ 
+-struct clk *clk_get(struct device *dev, const char *id)
+-{
+-	if (!strcmp(id, "enet0"))
+-		return &clk_enet0;
+-	if (!strcmp(id, "enet1"))
+-		return &clk_enet1;
+-	if (!strcmp(id, "enetsw"))
+-		return &clk_enetsw;
+-	if (!strcmp(id, "ephy"))
+-		return &clk_ephy;
+-	if (!strcmp(id, "usbh"))
+-		return &clk_usbh;
+-	if (!strcmp(id, "usbd"))
+-		return &clk_usbd;
+-	if (!strcmp(id, "spi"))
+-		return &clk_spi;
+-	if (!strcmp(id, "hsspi"))
+-		return &clk_hsspi;
+-	if (!strcmp(id, "xtm"))
+-		return &clk_xtm;
+-	if (!strcmp(id, "periph"))
+-		return &clk_periph;
+-	if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm"))
+-		return &clk_pcm;
+-	if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec"))
+-		return &clk_ipsec;
+-	if ((BCMCPU_IS_6328() || BCMCPU_IS_6362()) && !strcmp(id, "pcie"))
+-		return &clk_pcie;
+-	return ERR_PTR(-ENOENT);
+-}
+-
+-EXPORT_SYMBOL(clk_get);
+-
+-void clk_put(struct clk *clk)
+-{
+-}
+-
+-EXPORT_SYMBOL(clk_put);
++static struct clk_lookup bcm3368_clks[] = {
++	/* fixed rate clocks */
++	CLKDEV_INIT(NULL, "periph", &clk_periph),
++	/* gated clocks */
++	CLKDEV_INIT(NULL, "enet0", &clk_enet0),
++	CLKDEV_INIT(NULL, "enet1", &clk_enet1),
++	CLKDEV_INIT(NULL, "ephy", &clk_ephy),
++	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
++	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
++	CLKDEV_INIT(NULL, "spi", &clk_spi),
++	CLKDEV_INIT(NULL, "pcm", &clk_pcm),
++};
++
++static struct clk_lookup bcm6328_clks[] = {
++	/* fixed rate clocks */
++	CLKDEV_INIT(NULL, "periph", &clk_periph),
++	/* gated clocks */
++	CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
++	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
++	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
++	CLKDEV_INIT(NULL, "hsspi", &clk_hsspi),
++	CLKDEV_INIT(NULL, "pcie", &clk_pcie),
++};
++
++static struct clk_lookup bcm6338_clks[] = {
++	/* fixed rate clocks */
++	CLKDEV_INIT(NULL, "periph", &clk_periph),
++	/* gated clocks */
++	CLKDEV_INIT(NULL, "enet0", &clk_enet0),
++	CLKDEV_INIT(NULL, "enet1", &clk_enet1),
++	CLKDEV_INIT(NULL, "ephy", &clk_ephy),
++	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
++	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
++	CLKDEV_INIT(NULL, "spi", &clk_spi),
++};
++
++static struct clk_lookup bcm6345_clks[] = {
++	/* fixed rate clocks */
++	CLKDEV_INIT(NULL, "periph", &clk_periph),
++	/* gated clocks */
++	CLKDEV_INIT(NULL, "enet0", &clk_enet0),
++	CLKDEV_INIT(NULL, "enet1", &clk_enet1),
++	CLKDEV_INIT(NULL, "ephy", &clk_ephy),
++	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
++	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
++	CLKDEV_INIT(NULL, "spi", &clk_spi),
++};
++
++static struct clk_lookup bcm6348_clks[] = {
++	/* fixed rate clocks */
++	CLKDEV_INIT(NULL, "periph", &clk_periph),
++	/* gated clocks */
++	CLKDEV_INIT(NULL, "enet0", &clk_enet0),
++	CLKDEV_INIT(NULL, "enet1", &clk_enet1),
++	CLKDEV_INIT(NULL, "ephy", &clk_ephy),
++	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
++	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
++	CLKDEV_INIT(NULL, "spi", &clk_spi),
++};
++
++static struct clk_lookup bcm6358_clks[] = {
++	/* fixed rate clocks */
++	CLKDEV_INIT(NULL, "periph", &clk_periph),
++	/* gated clocks */
++	CLKDEV_INIT(NULL, "enet0", &clk_enet0),
++	CLKDEV_INIT(NULL, "enet1", &clk_enet1),
++	CLKDEV_INIT(NULL, "ephy", &clk_ephy),
++	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
++	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
++	CLKDEV_INIT(NULL, "spi", &clk_spi),
++	CLKDEV_INIT(NULL, "pcm", &clk_pcm),
++};
++
++static struct clk_lookup bcm6362_clks[] = {
++	/* fixed rate clocks */
++	CLKDEV_INIT(NULL, "periph", &clk_periph),
++	/* gated clocks */
++	CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
++	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
++	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
++	CLKDEV_INIT(NULL, "spi", &clk_spi),
++	CLKDEV_INIT(NULL, "hsspi", &clk_hsspi),
++	CLKDEV_INIT(NULL, "pcie", &clk_pcie),
++	CLKDEV_INIT(NULL, "ipsec", &clk_ipsec),
++};
++
++static struct clk_lookup bcm6368_clks[] = {
++	/* fixed rate clocks */
++	CLKDEV_INIT(NULL, "periph", &clk_periph),
++	/* gated clocks */
++	CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
++	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
++	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
++	CLKDEV_INIT(NULL, "spi", &clk_spi),
++	CLKDEV_INIT(NULL, "xtm", &clk_xtm),
++	CLKDEV_INIT(NULL, "ipsec", &clk_ipsec),
++};
+ 
+ #define HSSPI_PLL_HZ_6328	133333333
+ #define HSSPI_PLL_HZ_6362	400000000
+@@ -400,11 +460,31 @@ EXPORT_SYMBOL(clk_put);
+ static int __init bcm63xx_clk_init(void)
+ {
+ 	switch (bcm63xx_get_cpu_id()) {
++	case BCM3368_CPU_ID:
++		clkdev_add_table(bcm3368_clks, ARRAY_SIZE(bcm3368_clks));
++		break;
+ 	case BCM6328_CPU_ID:
+ 		clk_hsspi.rate = HSSPI_PLL_HZ_6328;
++		clkdev_add_table(bcm6328_clks, ARRAY_SIZE(bcm6328_clks));
++		break;
++	case BCM6338_CPU_ID:
++		clkdev_add_table(bcm6338_clks, ARRAY_SIZE(bcm6338_clks));
++		break;
++	case BCM6345_CPU_ID:
++		clkdev_add_table(bcm6345_clks, ARRAY_SIZE(bcm6345_clks));
++		break;
++	case BCM6348_CPU_ID:
++		clkdev_add_table(bcm6348_clks, ARRAY_SIZE(bcm6348_clks));
++		break;
++	case BCM6358_CPU_ID:
++		clkdev_add_table(bcm6358_clks, ARRAY_SIZE(bcm6358_clks));
+ 		break;
+ 	case BCM6362_CPU_ID:
+ 		clk_hsspi.rate = HSSPI_PLL_HZ_6362;
++		clkdev_add_table(bcm6362_clks, ARRAY_SIZE(bcm6362_clks));
++		break;
++	case BCM6368_CPU_ID:
++		clkdev_add_table(bcm6368_clks, ARRAY_SIZE(bcm6368_clks));
+ 		break;
+ 	}
+ 

target/linux/brcm63xx/patches-4.9/001-4.15-02-MIPS-BCM63XX-provide-periph-clock-as-refclk-for-uart.patch

@@ -0,0 +1,84 @@
+From d0322bf7bebe87012b4f95c85be6b5ba0cb6f344 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 16 Jul 2017 12:31:44 +0200
+Subject: [PATCH V2 2/8] MIPS: BCM63XX: provide periph clock as refclk for uart
+
+Add a lookup as "refclk" to describe its function for the uarts.
+
+Reviewed-by: Florian Fainelli <[email protected]>
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/clk.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -359,6 +359,8 @@ EXPORT_SYMBOL_GPL(clk_round_rate);
+ static struct clk_lookup bcm3368_clks[] = {
+ 	/* fixed rate clocks */
+ 	CLKDEV_INIT(NULL, "periph", &clk_periph),
++	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
++	CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
+ 	/* gated clocks */
+ 	CLKDEV_INIT(NULL, "enet0", &clk_enet0),
+ 	CLKDEV_INIT(NULL, "enet1", &clk_enet1),
+@@ -372,6 +374,8 @@ static struct clk_lookup bcm3368_clks[]
+ static struct clk_lookup bcm6328_clks[] = {
+ 	/* fixed rate clocks */
+ 	CLKDEV_INIT(NULL, "periph", &clk_periph),
++	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
++	CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
+ 	/* gated clocks */
+ 	CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
+ 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
+@@ -383,6 +387,7 @@ static struct clk_lookup bcm6328_clks[]
+ static struct clk_lookup bcm6338_clks[] = {
+ 	/* fixed rate clocks */
+ 	CLKDEV_INIT(NULL, "periph", &clk_periph),
++	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
+ 	/* gated clocks */
+ 	CLKDEV_INIT(NULL, "enet0", &clk_enet0),
+ 	CLKDEV_INIT(NULL, "enet1", &clk_enet1),
+@@ -395,6 +400,7 @@ static struct clk_lookup bcm6338_clks[]
+ static struct clk_lookup bcm6345_clks[] = {
+ 	/* fixed rate clocks */
+ 	CLKDEV_INIT(NULL, "periph", &clk_periph),
++	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
+ 	/* gated clocks */
+ 	CLKDEV_INIT(NULL, "enet0", &clk_enet0),
+ 	CLKDEV_INIT(NULL, "enet1", &clk_enet1),
+@@ -407,6 +413,7 @@ static struct clk_lookup bcm6345_clks[]
+ static struct clk_lookup bcm6348_clks[] = {
+ 	/* fixed rate clocks */
+ 	CLKDEV_INIT(NULL, "periph", &clk_periph),
++	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
+ 	/* gated clocks */
+ 	CLKDEV_INIT(NULL, "enet0", &clk_enet0),
+ 	CLKDEV_INIT(NULL, "enet1", &clk_enet1),
+@@ -419,6 +426,8 @@ static struct clk_lookup bcm6348_clks[]
+ static struct clk_lookup bcm6358_clks[] = {
+ 	/* fixed rate clocks */
+ 	CLKDEV_INIT(NULL, "periph", &clk_periph),
++	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
++	CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
+ 	/* gated clocks */
+ 	CLKDEV_INIT(NULL, "enet0", &clk_enet0),
+ 	CLKDEV_INIT(NULL, "enet1", &clk_enet1),
+@@ -432,6 +441,8 @@ static struct clk_lookup bcm6358_clks[]
+ static struct clk_lookup bcm6362_clks[] = {
+ 	/* fixed rate clocks */
+ 	CLKDEV_INIT(NULL, "periph", &clk_periph),
++	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
++	CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
+ 	/* gated clocks */
+ 	CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
+ 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
+@@ -445,6 +456,8 @@ static struct clk_lookup bcm6362_clks[]
+ static struct clk_lookup bcm6368_clks[] = {
+ 	/* fixed rate clocks */
+ 	CLKDEV_INIT(NULL, "periph", &clk_periph),
++	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
++	CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
+ 	/* gated clocks */
+ 	CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
+ 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),

target/linux/brcm63xx/patches-4.9/001-4.15-03-tty-bcm63xx_uart-use-refclk-for-the-expected-clock-n.patch

@@ -0,0 +1,26 @@
+From 8124706e6040b1cf0d2dd3a05759df6cec4bddfb Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 16 Jul 2017 12:32:37 +0200
+Subject: [PATCH V2 3/8] tty/bcm63xx_uart: use refclk for the expected clock
+ name
+
+We now have the clock available under refclk, so use that.
+
+Acked-by: Greg Kroah-Hartman <[email protected]>
+Reviewed-by: Florian Fainelli <[email protected]>
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/tty/serial/bcm63xx_uart.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/tty/serial/bcm63xx_uart.c
++++ b/drivers/tty/serial/bcm63xx_uart.c
+@@ -842,7 +842,7 @@ static int bcm_uart_probe(struct platfor
+ 		return -ENODEV;
+ 
+ 	clk = pdev->dev.of_node ? of_clk_get(pdev->dev.of_node, 0) :
+-				  clk_get(&pdev->dev, "periph");
++				  clk_get(&pdev->dev, "refclk");
+ 	if (IS_ERR(clk))
+ 		return -ENODEV;
+ 

target/linux/brcm63xx/patches-4.9/001-4.15-04-tty-bcm63xx_uart-allow-naming-clock-in-device-tree.patch

@@ -0,0 +1,55 @@
+From 317f8659bba01b307cbe4e9902d4e3d333fd7164 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 16 Jul 2017 12:39:17 +0200
+Subject: [PATCH V2 4/8] tty/bcm63xx_uart: allow naming clock in device tree
+
+Codify using a named clock for the refclk of the uart. This makes it
+easier if we might need to add a gating clock (like present on the
+BCM6345).
+
+Acked-by: Rob Herring <[email protected]>
+Acked-by: Greg Kroah-Hartman <[email protected]>
+Reviewed-by: Florian Fainelli <[email protected]>
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ Documentation/devicetree/bindings/serial/brcm,bcm6345-uart.txt | 6 ++++++
+ drivers/tty/serial/bcm63xx_uart.c                              | 6 ++++--
+ 2 files changed, 10 insertions(+), 2 deletions(-)
+
+--- a/Documentation/devicetree/bindings/serial/brcm,bcm6345-uart.txt
++++ b/Documentation/devicetree/bindings/serial/brcm,bcm6345-uart.txt
+@@ -11,6 +11,11 @@ Required properties:
+ - clocks: Clock driving the hardware; used to figure out the baud rate
+   divisor.
+ 
++
++Optional properties:
++
++- clock-names: Should be "refclk".
++
+ Example:
+ 
+ 	uart0: serial@14e00520 {
+@@ -19,6 +24,7 @@ Example:
+ 		interrupt-parent = <&periph_intc>;
+ 		interrupts = <2>;
+ 		clocks = <&periph_clk>;
++		clock-names = "refclk";
+ 	};
+ 
+ 	clocks {
+--- a/drivers/tty/serial/bcm63xx_uart.c
++++ b/drivers/tty/serial/bcm63xx_uart.c
+@@ -841,8 +841,10 @@ static int bcm_uart_probe(struct platfor
+ 	if (!res_irq)
+ 		return -ENODEV;
+ 
+-	clk = pdev->dev.of_node ? of_clk_get(pdev->dev.of_node, 0) :
+-				  clk_get(&pdev->dev, "refclk");
++	clk = clk_get(&pdev->dev, "refclk");
++	if (IS_ERR(clk) && pdev->dev.of_node)
++		clk = of_clk_get(pdev->dev.of_node, 0);
++
+ 	if (IS_ERR(clk))
+ 		return -ENODEV;
+ 

target/linux/brcm63xx/patches-4.9/001-4.15-05-MIPS-BCM63XX-move-the-HSSPI-PLL-HZ-into-its-own-cloc.patch

@@ -0,0 +1,62 @@
+From cb86630379c8f3432c916d62045b5176f17f4123 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 16 Jul 2017 12:57:21 +0200
+Subject: [PATCH V2 6/8] MIPS: BCM63XX: move the HSSPI PLL HZ into its own
+ clock
+
+Split up the HSSPL clock into rate and a gate clock, to more closely
+match the actual hardware.
+
+Reviewed-by: Florian Fainelli <[email protected]>
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/clk.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -247,6 +247,10 @@ static struct clk clk_hsspi = {
+ 	.set	= hsspi_set,
+ };
+ 
++/*
++ * HSSPI PLL
++ */
++static struct clk clk_hsspi_pll;
+ 
+ /*
+  * XTM clock
+@@ -376,6 +380,7 @@ static struct clk_lookup bcm6328_clks[]
+ 	CLKDEV_INIT(NULL, "periph", &clk_periph),
+ 	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
+ 	CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
++	CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
+ 	/* gated clocks */
+ 	CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
+ 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
+@@ -443,6 +448,7 @@ static struct clk_lookup bcm6362_clks[]
+ 	CLKDEV_INIT(NULL, "periph", &clk_periph),
+ 	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
+ 	CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
++	CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
+ 	/* gated clocks */
+ 	CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
+ 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
+@@ -477,7 +483,7 @@ static int __init bcm63xx_clk_init(void)
+ 		clkdev_add_table(bcm3368_clks, ARRAY_SIZE(bcm3368_clks));
+ 		break;
+ 	case BCM6328_CPU_ID:
+-		clk_hsspi.rate = HSSPI_PLL_HZ_6328;
++		clk_hsspi_pll.rate = HSSPI_PLL_HZ_6328;
+ 		clkdev_add_table(bcm6328_clks, ARRAY_SIZE(bcm6328_clks));
+ 		break;
+ 	case BCM6338_CPU_ID:
+@@ -493,7 +499,7 @@ static int __init bcm63xx_clk_init(void)
+ 		clkdev_add_table(bcm6358_clks, ARRAY_SIZE(bcm6358_clks));
+ 		break;
+ 	case BCM6362_CPU_ID:
+-		clk_hsspi.rate = HSSPI_PLL_HZ_6362;
++		clk_hsspi_pll.rate = HSSPI_PLL_HZ_6362;
+ 		clkdev_add_table(bcm6362_clks, ARRAY_SIZE(bcm6362_clks));
+ 		break;
+ 	case BCM6368_CPU_ID:

target/linux/brcm63xx/patches-4.9/001-4.15-06-MIPS-BCM63XX-provide-enet-clocks-as-enet-to-the-ethe.patch

@@ -0,0 +1,60 @@
+From 6d43970a2eb1c7ee88caf7328d201f9c001262e9 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 16 Jul 2017 12:48:41 +0200
+Subject: [PATCH V2 7/8] MIPS: BCM63XX: provide enet clocks as "enet" to the
+ ethernet devices
+
+Add lookups to provide the appropriate enetX clocks as just "enet" to
+the ethernet devices.
+
+Reviewed-by: Florian Fainelli <[email protected]>
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/clk.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -373,6 +373,8 @@ static struct clk_lookup bcm3368_clks[]
+ 	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
+ 	CLKDEV_INIT(NULL, "spi", &clk_spi),
+ 	CLKDEV_INIT(NULL, "pcm", &clk_pcm),
++	CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet0),
++	CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1),
+ };
+ 
+ static struct clk_lookup bcm6328_clks[] = {
+@@ -400,6 +402,7 @@ static struct clk_lookup bcm6338_clks[]
+ 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
+ 	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
+ 	CLKDEV_INIT(NULL, "spi", &clk_spi),
++	CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
+ };
+ 
+ static struct clk_lookup bcm6345_clks[] = {
+@@ -413,6 +416,7 @@ static struct clk_lookup bcm6345_clks[]
+ 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
+ 	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
+ 	CLKDEV_INIT(NULL, "spi", &clk_spi),
++	CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
+ };
+ 
+ static struct clk_lookup bcm6348_clks[] = {
+@@ -426,6 +430,8 @@ static struct clk_lookup bcm6348_clks[]
+ 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
+ 	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
+ 	CLKDEV_INIT(NULL, "spi", &clk_spi),
++	CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
++	CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet_misc),
+ };
+ 
+ static struct clk_lookup bcm6358_clks[] = {
+@@ -441,6 +447,8 @@ static struct clk_lookup bcm6358_clks[]
+ 	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
+ 	CLKDEV_INIT(NULL, "spi", &clk_spi),
+ 	CLKDEV_INIT(NULL, "pcm", &clk_pcm),
++	CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet0),
++	CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1),
+ };
+ 
+ static struct clk_lookup bcm6362_clks[] = {

target/linux/brcm63xx/patches-4.9/001-4.15-07-MIPS-BCM63XX-split-out-swpkt_sar-usb-clocks.patch

@@ -0,0 +1,105 @@
+From b98027285bd1fa95da0645a4234a5fc1f1a83f92 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 26 Feb 2017 11:59:52 +0100
+Subject: [PATCH V2 8/8] MIPS: BCM63XX: split out swpkt_sar/usb clocks
+
+Make the secondary switch clocks their own clocks. This allows proper
+enable reference counting between SAR/XTM and the main switch clocks,
+and controlling them individually from drivers.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/clk.c | 61 +++++++++++++++++++++++++++++++++++++++++--------
+ 1 file changed, 51 insertions(+), 10 deletions(-)
+
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -121,21 +121,56 @@ static struct clk clk_ephy = {
+ };
+ 
+ /*
++ * Ethernet switch SAR clock
++ */
++static void swpkt_sar_set(struct clk *clk, int enable)
++{
++	if (BCMCPU_IS_6368())
++		bcm_hwclock_set(CKCTL_6368_SWPKT_SAR_EN, enable);
++	else
++		return;
++}
++
++static struct clk clk_swpkt_sar = {
++	.set	= swpkt_sar_set,
++};
++
++/*
++ * Ethernet switch USB clock
++ */
++static void swpkt_usb_set(struct clk *clk, int enable)
++{
++	if (BCMCPU_IS_6368())
++		bcm_hwclock_set(CKCTL_6368_SWPKT_USB_EN, enable);
++	else
++		return;
++}
++
++static struct clk clk_swpkt_usb = {
++	.set	= swpkt_usb_set,
++};
++
++/*
+  * Ethernet switch clock
+  */
+ static void enetsw_set(struct clk *clk, int enable)
+ {
+-	if (BCMCPU_IS_6328())
++	if (BCMCPU_IS_6328()) {
+ 		bcm_hwclock_set(CKCTL_6328_ROBOSW_EN, enable);
+-	else if (BCMCPU_IS_6362())
++	} else if (BCMCPU_IS_6362()) {
+ 		bcm_hwclock_set(CKCTL_6362_ROBOSW_EN, enable);
+-	else if (BCMCPU_IS_6368())
+-		bcm_hwclock_set(CKCTL_6368_ROBOSW_EN |
+-				CKCTL_6368_SWPKT_USB_EN |
+-				CKCTL_6368_SWPKT_SAR_EN,
+-				enable);
+-	else
++	} else if (BCMCPU_IS_6368()) {
++		if (enable) {
++			clk_enable_unlocked(&clk_swpkt_sar);
++			clk_enable_unlocked(&clk_swpkt_usb);
++		} else {
++			clk_disable_unlocked(&clk_swpkt_usb);
++			clk_disable_unlocked(&clk_swpkt_sar);
++		}
++		bcm_hwclock_set(CKCTL_6368_ROBOSW_EN, enable);
++	} else {
+ 		return;
++	}
+ 
+ 	if (enable) {
+ 		/* reset switch core afer clock change */
+@@ -260,8 +295,12 @@ static void xtm_set(struct clk *clk, int
+ 	if (!BCMCPU_IS_6368())
+ 		return;
+ 
+-	bcm_hwclock_set(CKCTL_6368_SAR_EN |
+-			CKCTL_6368_SWPKT_SAR_EN, enable);
++	if (enable)
++		clk_enable_unlocked(&clk_swpkt_sar);
++	else
++		clk_disable_unlocked(&clk_swpkt_sar);
++
++	bcm_hwclock_set(CKCTL_6368_SAR_EN, enable);
+ 
+ 	if (enable) {
+ 		/* reset sar core afer clock change */
+@@ -447,6 +486,8 @@ static struct clk_lookup bcm6358_clks[]
+ 	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
+ 	CLKDEV_INIT(NULL, "spi", &clk_spi),
+ 	CLKDEV_INIT(NULL, "pcm", &clk_pcm),
++	CLKDEV_INIT(NULL, "swpkt_sar", &clk_swpkt_sar),
++	CLKDEV_INIT(NULL, "swpkt_usb", &clk_swpkt_usb),
+ 	CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet0),
+ 	CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1),
+ };

target/linux/brcm63xx/patches-4.9/001-4.15-08-bcm63xx_enet-correct-clock-usage.patch

@@ -0,0 +1,101 @@
+From d0423d3e4fa7ae305729cb50369427f075ccb279 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sat, 25 Feb 2017 12:41:28 +0100
+Subject: [PATCH 1/6] bcm63xx_enet: correct clock usage
+
+Check the return code of prepare_enable and change one last instance of
+enable only to prepare_enable. Also properly disable and release the
+clock in error paths and on remove for enetsw.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/net/ethernet/broadcom/bcm63xx_enet.c | 31 +++++++++++++++++++++-------
+ 1 file changed, 23 insertions(+), 8 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+@@ -1790,7 +1790,9 @@ static int bcm_enet_probe(struct platfor
+ 		ret = PTR_ERR(priv->mac_clk);
+ 		goto out;
+ 	}
+-	clk_prepare_enable(priv->mac_clk);
++	ret = clk_prepare_enable(priv->mac_clk);
++	if (ret)
++		goto out_put_clk_mac;
+ 
+ 	/* initialize default and fetch platform data */
+ 	priv->rx_ring_size = BCMENET_DEF_RX_DESC;
+@@ -1822,9 +1824,11 @@ static int bcm_enet_probe(struct platfor
+ 		if (IS_ERR(priv->phy_clk)) {
+ 			ret = PTR_ERR(priv->phy_clk);
+ 			priv->phy_clk = NULL;
+-			goto out_put_clk_mac;
++			goto out_disable_clk_mac;
+ 		}
+-		clk_prepare_enable(priv->phy_clk);
++		ret = clk_prepare_enable(priv->phy_clk);
++		if (ret)
++			goto out_put_clk_phy;
+ 	}
+ 
+ 	/* do minimal hardware init to be able to probe mii bus */
+@@ -1915,13 +1919,16 @@ out_free_mdio:
+ out_uninit_hw:
+ 	/* turn off mdc clock */
+ 	enet_writel(priv, 0, ENET_MIISC_REG);
+-	if (priv->phy_clk) {
++	if (priv->phy_clk)
+ 		clk_disable_unprepare(priv->phy_clk);
++
++out_put_clk_phy:
++	if (priv->phy_clk)
+ 		clk_put(priv->phy_clk);
+-	}
+ 
+-out_put_clk_mac:
++out_disable_clk_mac:
+ 	clk_disable_unprepare(priv->mac_clk);
++out_put_clk_mac:
+ 	clk_put(priv->mac_clk);
+ out:
+ 	free_netdev(dev);
+@@ -2766,7 +2773,9 @@ static int bcm_enetsw_probe(struct platf
+ 		ret = PTR_ERR(priv->mac_clk);
+ 		goto out_unmap;
+ 	}
+-	clk_enable(priv->mac_clk);
++	ret = clk_prepare_enable(priv->mac_clk);
++	if (ret)
++		goto out_put_clk;
+ 
+ 	priv->rx_chan = 0;
+ 	priv->tx_chan = 1;
+@@ -2787,7 +2796,7 @@ static int bcm_enetsw_probe(struct platf
+ 
+ 	ret = register_netdev(dev);
+ 	if (ret)
+-		goto out_put_clk;
++		goto out_disable_clk;
+ 
+ 	netif_carrier_off(dev);
+ 	platform_set_drvdata(pdev, dev);
+@@ -2796,6 +2805,9 @@ static int bcm_enetsw_probe(struct platf
+ 
+ 	return 0;
+ 
++out_disable_clk:
++	clk_disable_unprepare(priv->mac_clk);
++
+ out_put_clk:
+ 	clk_put(priv->mac_clk);
+ 
+@@ -2827,6 +2839,9 @@ static int bcm_enetsw_remove(struct plat
+ 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 	release_mem_region(res->start, resource_size(res));
+ 
++	clk_disable_unprepare(priv->mac_clk);
++	clk_put(priv->mac_clk);
++
+ 	free_netdev(dev);
+ 	return 0;
+ }

target/linux/brcm63xx/patches-4.9/001-4.15-09-bcm63xx_enet-do-not-write-to-random-DMA-channel-on-B.patch

@@ -0,0 +1,29 @@
+From 23d94cb855b6f4f0ee1c01679224472104ac6440 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sat, 30 Sep 2017 14:10:18 +0200
+Subject: [PATCH 2/6] bcm63xx_enet: do not write to random DMA channel on
+ BCM6345
+
+The DMA controller regs actually point to DMA channel 0, so the write to
+ENETDMA_CFG_REG will actually modify a random DMA channel.
+
+Since DMA controller registers do not exist on BCM6345, guard the write
+with the usual check for dma_has_sram.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/net/ethernet/broadcom/bcm63xx_enet.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+@@ -1063,7 +1063,8 @@ static int bcm_enet_open(struct net_devi
+ 	val = enet_readl(priv, ENET_CTL_REG);
+ 	val |= ENET_CTL_ENABLE_MASK;
+ 	enet_writel(priv, val, ENET_CTL_REG);
+-	enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
++	if (priv->dma_has_sram)
++		enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
+ 	enet_dmac_writel(priv, priv->dma_chan_en_mask,
+ 			 ENETDMAC_CHANCFG, priv->rx_chan);
+ 

target/linux/brcm63xx/patches-4.9/001-4.15-10-bcm63xx_enet-do-not-rely-on-probe-order.patch

@@ -0,0 +1,41 @@
+From 71710bb6cbc82f411a4e5faafa0c3178e48e7137 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Tue, 30 May 2017 13:31:45 +0200
+Subject: [PATCH 3/6] bcm63xx_enet: do not rely on probe order
+
+Do not rely on the shared device being probed before the enet(sw)
+devices. This makes it easier to eventually move out the shared
+device as a dma controller driver (what it should be).
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/net/ethernet/broadcom/bcm63xx_enet.c | 9 ++-------
+ 1 file changed, 2 insertions(+), 7 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+@@ -1739,10 +1739,8 @@ static int bcm_enet_probe(struct platfor
+ 	const char *clk_name;
+ 	int i, ret;
+ 
+-	/* stop if shared driver failed, assume driver->probe will be
+-	 * called in the same order we register devices (correct ?) */
+ 	if (!bcm_enet_shared_base[0])
+-		return -ENODEV;
++		return -EPROBE_DEFER;
+ 
+ 	res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ 	res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+@@ -2714,11 +2712,8 @@ static int bcm_enetsw_probe(struct platf
+ 	struct resource *res_mem;
+ 	int ret, irq_rx, irq_tx;
+ 
+-	/* stop if shared driver failed, assume driver->probe will be
+-	 * called in the same order we register devices (correct ?)
+-	 */
+ 	if (!bcm_enet_shared_base[0])
+-		return -ENODEV;
++		return -EPROBE_DEFER;
+ 
+ 	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 	irq_rx = platform_get_irq(pdev, 0);

target/linux/brcm63xx/patches-4.9/001-4.15-11-bcm63xx_enet-use-managed-functions-for-clock-ioremap.patch

@@ -0,0 +1,150 @@
+From 179a445ae4ef36ec44f4aea18e5f42d21334d186 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sat, 25 Feb 2017 12:39:25 +0100
+Subject: [PATCH 4/6] bcm63xx_enet: use managed functions for clock/ioremap
+
+Use managed functions where possible to reduce the amount of resource
+handling on error and remove paths.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/net/ethernet/broadcom/bcm63xx_enet.c | 54 +++++++---------------------
+ 1 file changed, 12 insertions(+), 42 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+@@ -1784,14 +1784,14 @@ static int bcm_enet_probe(struct platfor
+ 		clk_name = "enet1";
+ 	}
+ 
+-	priv->mac_clk = clk_get(&pdev->dev, clk_name);
++	priv->mac_clk = devm_clk_get(&pdev->dev, clk_name);
+ 	if (IS_ERR(priv->mac_clk)) {
+ 		ret = PTR_ERR(priv->mac_clk);
+ 		goto out;
+ 	}
+ 	ret = clk_prepare_enable(priv->mac_clk);
+ 	if (ret)
+-		goto out_put_clk_mac;
++		goto out;
+ 
+ 	/* initialize default and fetch platform data */
+ 	priv->rx_ring_size = BCMENET_DEF_RX_DESC;
+@@ -1819,7 +1819,7 @@ static int bcm_enet_probe(struct platfor
+ 
+ 	if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
+ 		/* using internal PHY, enable clock */
+-		priv->phy_clk = clk_get(&pdev->dev, "ephy");
++		priv->phy_clk = devm_clk_get(&pdev->dev, "ephy");
+ 		if (IS_ERR(priv->phy_clk)) {
+ 			ret = PTR_ERR(priv->phy_clk);
+ 			priv->phy_clk = NULL;
+@@ -1827,7 +1827,7 @@ static int bcm_enet_probe(struct platfor
+ 		}
+ 		ret = clk_prepare_enable(priv->phy_clk);
+ 		if (ret)
+-			goto out_put_clk_phy;
++			goto out_disable_clk_mac;
+ 	}
+ 
+ 	/* do minimal hardware init to be able to probe mii bus */
+@@ -1921,14 +1921,8 @@ out_uninit_hw:
+ 	if (priv->phy_clk)
+ 		clk_disable_unprepare(priv->phy_clk);
+ 
+-out_put_clk_phy:
+-	if (priv->phy_clk)
+-		clk_put(priv->phy_clk);
+-
+ out_disable_clk_mac:
+ 	clk_disable_unprepare(priv->mac_clk);
+-out_put_clk_mac:
+-	clk_put(priv->mac_clk);
+ out:
+ 	free_netdev(dev);
+ 	return ret;
+@@ -1964,12 +1958,10 @@ static int bcm_enet_remove(struct platfo
+ 	}
+ 
+ 	/* disable hw block clocks */
+-	if (priv->phy_clk) {
++	if (priv->phy_clk)
+ 		clk_disable_unprepare(priv->phy_clk);
+-		clk_put(priv->phy_clk);
+-	}
++
+ 	clk_disable_unprepare(priv->mac_clk);
+-	clk_put(priv->mac_clk);
+ 
+ 	free_netdev(dev);
+ 	return 0;
+@@ -2752,26 +2744,20 @@ static int bcm_enetsw_probe(struct platf
+ 	if (ret)
+ 		goto out;
+ 
+-	if (!request_mem_region(res_mem->start, resource_size(res_mem),
+-				"bcm63xx_enetsw")) {
+-		ret = -EBUSY;
++	priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
++	if (IS_ERR(priv->base)) {
++		ret = PTR_ERR(priv->base);
+ 		goto out;
+ 	}
+ 
+-	priv->base = ioremap(res_mem->start, resource_size(res_mem));
+-	if (priv->base == NULL) {
+-		ret = -ENOMEM;
+-		goto out_release_mem;
+-	}
+-
+-	priv->mac_clk = clk_get(&pdev->dev, "enetsw");
++	priv->mac_clk = devm_clk_get(&pdev->dev, "enetsw");
+ 	if (IS_ERR(priv->mac_clk)) {
+ 		ret = PTR_ERR(priv->mac_clk);
+-		goto out_unmap;
++		goto out;
+ 	}
+ 	ret = clk_prepare_enable(priv->mac_clk);
+ 	if (ret)
+-		goto out_put_clk;
++		goto out;
+ 
+ 	priv->rx_chan = 0;
+ 	priv->tx_chan = 1;
+@@ -2803,15 +2789,6 @@ static int bcm_enetsw_probe(struct platf
+ 
+ out_disable_clk:
+ 	clk_disable_unprepare(priv->mac_clk);
+-
+-out_put_clk:
+-	clk_put(priv->mac_clk);
+-
+-out_unmap:
+-	iounmap(priv->base);
+-
+-out_release_mem:
+-	release_mem_region(res_mem->start, resource_size(res_mem));
+ out:
+ 	free_netdev(dev);
+ 	return ret;
+@@ -2823,20 +2800,13 @@ static int bcm_enetsw_remove(struct plat
+ {
+ 	struct bcm_enet_priv *priv;
+ 	struct net_device *dev;
+-	struct resource *res;
+ 
+ 	/* stop netdevice */
+ 	dev = platform_get_drvdata(pdev);
+ 	priv = netdev_priv(dev);
+ 	unregister_netdev(dev);
+ 
+-	/* release device resources */
+-	iounmap(priv->base);
+-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+-	release_mem_region(res->start, resource_size(res));
+-
+ 	clk_disable_unprepare(priv->mac_clk);
+-	clk_put(priv->mac_clk);
+ 
+ 	free_netdev(dev);
+ 	return 0;

target/linux/brcm63xx/patches-4.9/001-4.15-12-bcm63xx_enet-drop-unneeded-NULL-phy_clk-check.patch

@@ -0,0 +1,36 @@
+From 555baec974ede81e616ca88ac6d3fca09239368f Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Tue, 18 Jul 2017 13:18:01 +0200
+Subject: [PATCH 5/6] bcm63xx_enet: drop unneeded NULL phy_clk check
+
+clk_disable and clk_unprepare are NULL-safe, so need to duplicate the
+NULL check of the functions.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/net/ethernet/broadcom/bcm63xx_enet.c | 7 ++-----
+ 1 file changed, 2 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+@@ -1918,8 +1918,7 @@ out_free_mdio:
+ out_uninit_hw:
+ 	/* turn off mdc clock */
+ 	enet_writel(priv, 0, ENET_MIISC_REG);
+-	if (priv->phy_clk)
+-		clk_disable_unprepare(priv->phy_clk);
++	clk_disable_unprepare(priv->phy_clk);
+ 
+ out_disable_clk_mac:
+ 	clk_disable_unprepare(priv->mac_clk);
+@@ -1958,9 +1957,7 @@ static int bcm_enet_remove(struct platfo
+ 	}
+ 
+ 	/* disable hw block clocks */
+-	if (priv->phy_clk)
+-		clk_disable_unprepare(priv->phy_clk);
+-
++	clk_disable_unprepare(priv->phy_clk);
+ 	clk_disable_unprepare(priv->mac_clk);
+ 
+ 	free_netdev(dev);

target/linux/brcm63xx/patches-4.9/001-4.15-13-bcm63xx_enet-remove-unneeded-include.patch

@@ -0,0 +1,22 @@
+From 77364ce98037972fb1c57d0ee0418eb1c2b26521 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Mon, 29 May 2017 13:11:14 +0200
+Subject: [PATCH 6/6] bcm63xx_enet: remove unneeded include
+
+We don't use anyhing from that file, so drop it.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/net/ethernet/broadcom/bcm63xx_enet.h | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h
+@@ -8,7 +8,6 @@
+ #include <linux/platform_device.h>
+ 
+ #include <bcm63xx_regs.h>
+-#include <bcm63xx_irq.h>
+ #include <bcm63xx_io.h>
+ #include <bcm63xx_iudma.h>
+ 

target/linux/brcm63xx/patches-4.9/001-4.16-01-bcm63xx_enet-just-use-enet-as-the-clock-name.patch

@@ -0,0 +1,39 @@
+From 943b0832e0cf3afe5bd40ffb1885d06106122c5d Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 16 Jul 2017 12:49:49 +0200
+Subject: [PATCH 1/4] bcm63xx_enet: just use "enet" as the clock name
+
+Now that we have the individual clocks available as "enet" we
+don't need to rely on the device id for them anymore.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/net/ethernet/broadcom/bcm63xx_enet.c | 5 +----
+ 1 file changed, 1 insertion(+), 4 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+@@ -1736,7 +1736,6 @@ static int bcm_enet_probe(struct platfor
+ 	struct bcm63xx_enet_platform_data *pd;
+ 	struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
+ 	struct mii_bus *bus;
+-	const char *clk_name;
+ 	int i, ret;
+ 
+ 	if (!bcm_enet_shared_base[0])
+@@ -1777,14 +1776,12 @@ static int bcm_enet_probe(struct platfor
+ 	if (priv->mac_id == 0) {
+ 		priv->rx_chan = 0;
+ 		priv->tx_chan = 1;
+-		clk_name = "enet0";
+ 	} else {
+ 		priv->rx_chan = 2;
+ 		priv->tx_chan = 3;
+-		clk_name = "enet1";
+ 	}
+ 
+-	priv->mac_clk = devm_clk_get(&pdev->dev, clk_name);
++	priv->mac_clk = devm_clk_get(&pdev->dev, "enet");
+ 	if (IS_ERR(priv->mac_clk)) {
+ 		ret = PTR_ERR(priv->mac_clk);
+ 		goto out;

target/linux/brcm63xx/patches-4.9/001-4.16-02-bcm63xx_enet-use-platform-data-for-dma-channel-numbe.patch

@@ -0,0 +1,72 @@
+From b7d1d1f345bb3b25c360c1df812d98866e2ee7fb Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sat, 30 Sep 2017 13:50:03 +0200
+Subject: [PATCH 2/4] bcm63xx_enet: use platform data for dma channel numbers
+
+To reduce the reliance on device ids, pass the dma channel numbers to
+the enet devices as platform data.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/dev-enet.c                          |  8 ++++++++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h |  4 ++++
+ drivers/net/ethernet/broadcom/bcm63xx_enet.c          | 11 ++---------
+ 3 files changed, 14 insertions(+), 9 deletions(-)
+
+--- a/arch/mips/bcm63xx/dev-enet.c
++++ b/arch/mips/bcm63xx/dev-enet.c
+@@ -265,6 +265,14 @@ int __init bcm63xx_enet_register(int uni
+ 		dpd->dma_chan_width = ENETDMA_CHAN_WIDTH;
+ 	}
+ 
++	if (unit == 0) {
++		dpd->rx_chan = 0;
++		dpd->tx_chan = 1;
++	} else {
++		dpd->rx_chan = 2;
++		dpd->tx_chan = 3;
++	}
++
+ 	ret = platform_device_register(pdev);
+ 	if (ret)
+ 		return ret;
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
+@@ -54,6 +54,10 @@ struct bcm63xx_enet_platform_data {
+ 
+ 	/* DMA descriptor shift */
+ 	unsigned int dma_desc_shift;
++
++	/* dma channel ids */
++	int rx_chan;
++	int tx_chan;
+ };
+ 
+ /*
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+@@ -1772,15 +1772,6 @@ static int bcm_enet_probe(struct platfor
+ 	priv->irq_tx = res_irq_tx->start;
+ 	priv->mac_id = pdev->id;
+ 
+-	/* get rx & tx dma channel id for this mac */
+-	if (priv->mac_id == 0) {
+-		priv->rx_chan = 0;
+-		priv->tx_chan = 1;
+-	} else {
+-		priv->rx_chan = 2;
+-		priv->tx_chan = 3;
+-	}
+-
+ 	priv->mac_clk = devm_clk_get(&pdev->dev, "enet");
+ 	if (IS_ERR(priv->mac_clk)) {
+ 		ret = PTR_ERR(priv->mac_clk);
+@@ -1812,6 +1803,8 @@ static int bcm_enet_probe(struct platfor
+ 		priv->dma_chan_width = pd->dma_chan_width;
+ 		priv->dma_has_sram = pd->dma_has_sram;
+ 		priv->dma_desc_shift = pd->dma_desc_shift;
++		priv->rx_chan = pd->rx_chan;
++		priv->tx_chan = pd->tx_chan;
+ 	}
+ 
+ 	if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {

target/linux/brcm63xx/patches-4.9/001-4.16-03-bcm63xx_enet-remove-pointless-mac_id-check.patch

@@ -0,0 +1,25 @@
+From 8c61608e5dd2e15575c171ee9cd558ddc3b94962 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 17 Dec 2017 12:54:30 +0100
+Subject: [PATCH 3/4] bcm63xx_enet: remove pointless mac_id check
+
+Enabling the ephy clock for mac 1 is harmless, and the actual usage of
+the ephy is not restricted to mac 0, so we might as well remove the
+check.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/net/ethernet/broadcom/bcm63xx_enet.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+@@ -1807,7 +1807,7 @@ static int bcm_enet_probe(struct platfor
+ 		priv->tx_chan = pd->tx_chan;
+ 	}
+ 
+-	if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
++	if (priv->has_phy && !priv->use_external_mii) {
+ 		/* using internal PHY, enable clock */
+ 		priv->phy_clk = devm_clk_get(&pdev->dev, "ephy");
+ 		if (IS_ERR(priv->phy_clk)) {

target/linux/brcm63xx/patches-4.9/001-4.16-04-bcm63xx_enet-use-platform-device-id-directly-for-mii.patch

@@ -0,0 +1,46 @@
+From faea89cd893a1a7af81185f026a64dad603ef72f Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 17 Dec 2017 12:58:12 +0100
+Subject: [PATCH 4/4] bcm63xx_enet: use platform device id directly for miibus
+ name
+
+Directly use the platform device for generating the miibus name. This removes
+the last user of bcm_enet_priv::mac_id and we can remove the field.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/net/ethernet/broadcom/bcm63xx_enet.c | 3 +--
+ drivers/net/ethernet/broadcom/bcm63xx_enet.h | 3 ---
+ 2 files changed, 1 insertion(+), 5 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+@@ -1770,7 +1770,6 @@ static int bcm_enet_probe(struct platfor
+ 	dev->irq = priv->irq = res_irq->start;
+ 	priv->irq_rx = res_irq_rx->start;
+ 	priv->irq_tx = res_irq_tx->start;
+-	priv->mac_id = pdev->id;
+ 
+ 	priv->mac_clk = devm_clk_get(&pdev->dev, "enet");
+ 	if (IS_ERR(priv->mac_clk)) {
+@@ -1838,7 +1837,7 @@ static int bcm_enet_probe(struct platfor
+ 		bus->priv = priv;
+ 		bus->read = bcm_enet_mdio_read_phylib;
+ 		bus->write = bcm_enet_mdio_write_phylib;
+-		sprintf(bus->id, "%s-%d", pdev->name, priv->mac_id);
++		sprintf(bus->id, "%s-%d", pdev->name, pdev->id);
+ 
+ 		/* only probe bus where we think the PHY is, because
+ 		 * the mdio read operation return 0 instead of 0xffff
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h
+@@ -192,9 +192,6 @@ struct bcm_enet_mib_counters {
+ 
+ struct bcm_enet_priv {
+ 
+-	/* mac id (from platform device id) */
+-	int mac_id;
+-
+ 	/* base remapped address of device */
+ 	void __iomem *base;
+ 

target/linux/brcm63xx/patches-4.9/100-MIPS-BCM63XX-add-USB-host-clock-enable-delay.patch

@@ -0,0 +1,28 @@
+From 80a2f983e9f44dbc3e01ae31c62d877846a7f791 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <[email protected]>
+Date: Mon, 28 Jan 2013 20:06:19 +0100
+Subject: [PATCH 01/11] MIPS: BCM63XX: add USB host clock enable delay
+
+Knowledge of the clock setup delay should remain at the clock level (so
+it can be clock specific and CPU specific). Add the 100 milliseconds
+required clock delay for the USB host clock when it gets enabled.
+
+Signed-off-by: Florian Fainelli <[email protected]>
+---
+ arch/mips/bcm63xx/clk.c |    5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -213,6 +213,11 @@ static void usbh_set(struct clk *clk, in
+ 		bcm_hwclock_set(CKCTL_6362_USBH_EN, enable);
+ 	else if (BCMCPU_IS_6368())
+ 		bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
++	else
++		return;
++
++	if (enable)
++		msleep(100);
+ }
+ 
+ static struct clk clk_usbh = {

target/linux/brcm63xx/patches-4.9/101-MIPS-BCM63XX-add-USB-device-clock-enable-delay-to-cl.patch

@@ -0,0 +1,41 @@
+From 8e9bf528a122741f0171b89c297b63041116d704 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <[email protected]>
+Date: Mon, 28 Jan 2013 20:06:20 +0100
+Subject: [PATCH 02/11] MIPS: BCM63XX: add USB device clock enable delay to
+ clock code
+
+This patch adds the required 10 micro seconds delay to the USB device
+clock enable operation. Put this where the correct clock knowledege is,
+which is in the clock code, and remove this delay from the bcm63xx_udc
+gadget driver where it was before.
+
+Signed-off-by: Florian Fainelli <[email protected]>
+---
+ arch/mips/bcm63xx/clk.c          |    5 +++++
+ drivers/usb/gadget/bcm63xx_udc.c |    1 -
+ 2 files changed, 5 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -235,6 +235,11 @@ static void usbd_set(struct clk *clk, in
+ 		bcm_hwclock_set(CKCTL_6362_USBD_EN, enable);
+ 	else if (BCMCPU_IS_6368())
+ 		bcm_hwclock_set(CKCTL_6368_USBD_EN, enable);
++	else
++		return;
++
++	if (enable)
++		udelay(10);
+ }
+ 
+ static struct clk clk_usbd = {
+--- a/drivers/usb/gadget/udc/bcm63xx_udc.c
++++ b/drivers/usb/gadget/udc/bcm63xx_udc.c
+@@ -410,7 +410,6 @@ static inline void set_clocks(struct bcm
+ 	if (is_enabled) {
+ 		clk_enable(udc->usbh_clk);
+ 		clk_enable(udc->usbd_clk);
+-		udelay(10);
+ 	} else {
+ 		clk_disable(udc->usbd_clk);
+ 		clk_disable(udc->usbh_clk);

target/linux/brcm63xx/patches-4.9/102-MIPS-BCM63XX-move-code-touching-the-USB-private-regi.patch

@@ -0,0 +1,151 @@
+From ac9b0b574d54be28b300bf99ffe092a2c589484f Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <[email protected]>
+Date: Mon, 28 Jan 2013 20:06:21 +0100
+Subject: [PATCH 03/11] MIPS: BCM63XX: move code touching the USB private
+ register
+
+This patch moves the code touching the USB private register in the
+bcm63xx USB gadget driver to arch/mips/bcm63xx/usb-common.c in
+preparation for adding support for OHCI and EHCI host controllers which
+will also touch the USB private register.
+
+Signed-off-by: Florian Fainelli <[email protected]>
+---
+ arch/mips/bcm63xx/Makefile                         |    2 +-
+ arch/mips/bcm63xx/usb-common.c                     |   53 ++++++++++++++++++++
+ .../include/asm/mach-bcm63xx/bcm63xx_usb_priv.h    |    9 ++++
+ drivers/usb/gadget/bcm63xx_udc.c                   |   27 ++--------
+ 4 files changed, 67 insertions(+), 24 deletions(-)
+ create mode 100644 arch/mips/bcm63xx/usb-common.c
+ create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h
+
+--- a/arch/mips/bcm63xx/Makefile
++++ b/arch/mips/bcm63xx/Makefile
+@@ -1,7 +1,7 @@
+ obj-y		+= clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \
+ 		   setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \
+ 		   dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \
+-		   dev-wdt.o dev-usb-usbd.o
++		   dev-wdt.o dev-usb-usbd.o usb-common.o
+ obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
+ 
+ obj-y		+= boards/
+--- /dev/null
++++ b/arch/mips/bcm63xx/usb-common.c
+@@ -0,0 +1,53 @@
++/*
++ * Broadcom BCM63xx common USB device configuration code
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2012 Kevin Cernekee <[email protected]>
++ * Copyright (C) 2012 Broadcom Corporation
++ *
++ */
++#include <linux/export.h>
++
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_regs.h>
++#include <bcm63xx_io.h>
++#include <bcm63xx_usb_priv.h>
++
++void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device)
++{
++	u32 val;
++
++	val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG);
++	if (is_device) {
++		val |= (portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT);
++		val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);
++	} else {
++		val &= ~(portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT);
++		val &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);
++	}
++	bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG);
++
++	val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);
++	if (is_device)
++		val |= USBH_PRIV_SWAP_USBD_MASK;
++	else
++		val &= ~USBH_PRIV_SWAP_USBD_MASK;
++	bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_SWAP_6368_REG);
++}
++EXPORT_SYMBOL(bcm63xx_usb_priv_select_phy_mode);
++
++void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on)
++{
++	u32 val;
++
++	val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG);
++	if (is_on)
++		val &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);
++	else
++		val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);
++	bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG);
++}
++EXPORT_SYMBOL(bcm63xx_usb_priv_select_pullup);
+--- /dev/null
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h
+@@ -0,0 +1,9 @@
++#ifndef BCM63XX_USB_PRIV_H_
++#define BCM63XX_USB_PRIV_H_
++
++#include <linux/types.h>
++
++void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device);
++void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on);
++
++#endif /* BCM63XX_USB_PRIV_H_ */
+--- a/drivers/usb/gadget/udc/bcm63xx_udc.c
++++ b/drivers/usb/gadget/udc/bcm63xx_udc.c
+@@ -39,6 +39,7 @@
+ #include <bcm63xx_dev_usb_usbd.h>
+ #include <bcm63xx_io.h>
+ #include <bcm63xx_regs.h>
++#include <bcm63xx_usb_priv.h>
+ 
+ #define DRV_MODULE_NAME		"bcm63xx_udc"
+ 
+@@ -887,22 +888,7 @@ static void bcm63xx_select_phy_mode(stru
+ 		bcm_gpio_writel(val, GPIO_PINMUX_OTHR_REG);
+ 	}
+ 
+-	val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG);
+-	if (is_device) {
+-		val |= (portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT);
+-		val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);
+-	} else {
+-		val &= ~(portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT);
+-		val &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);
+-	}
+-	bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG);
+-
+-	val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);
+-	if (is_device)
+-		val |= USBH_PRIV_SWAP_USBD_MASK;
+-	else
+-		val &= ~USBH_PRIV_SWAP_USBD_MASK;
+-	bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_SWAP_6368_REG);
++	bcm63xx_usb_priv_select_phy_mode(portmask, is_device);
+ }
+ 
+ /**
+@@ -916,14 +902,9 @@ static void bcm63xx_select_phy_mode(stru
+  */
+ static void bcm63xx_select_pullup(struct bcm63xx_udc *udc, bool is_on)
+ {
+-	u32 val, portmask = BIT(udc->pd->port_no);
++	u32 portmask = BIT(udc->pd->port_no);
+ 
+-	val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG);
+-	if (is_on)
+-		val &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);
+-	else
+-		val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);
+-	bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG);
++	bcm63xx_usb_priv_select_pullup(portmask, is_on);
+ }
+ 
+ /**

target/linux/brcm63xx/patches-4.9/103-MIPS-BCM63XX-add-OHCI-EHCI-configuration-bits-to-com.patch

@@ -0,0 +1,169 @@
+From 28758a9da77954ed323f86123ef448c6a563c037 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <[email protected]>
+Date: Mon, 28 Jan 2013 20:06:22 +0100
+Subject: [PATCH 04/11] MIPS: BCM63XX: add OHCI/EHCI configuration bits to
+ common USB code
+
+This patch updates the common USB code touching the USB private
+registers with the specific bits to properly enable OHCI and EHCI
+controllers on BCM63xx SoCs. As a result we now need to protect access
+to Read Modify Write sequences using a spinlock because we cannot
+guarantee that any of the exposed helper will not be called
+concurrently.
+
+Signed-off-by: Maxime Bizon <[email protected]>
+Signed-off-by: Florian Fainelli <[email protected]>
+---
+ arch/mips/bcm63xx/usb-common.c                     |   97 ++++++++++++++++++++
+ .../include/asm/mach-bcm63xx/bcm63xx_usb_priv.h    |    2 +
+ 2 files changed, 99 insertions(+)
+
+--- a/arch/mips/bcm63xx/usb-common.c
++++ b/arch/mips/bcm63xx/usb-common.c
+@@ -5,10 +5,12 @@
+  * License.  See the file "COPYING" in the main directory of this archive
+  * for more details.
+  *
++ * Copyright (C) 2008 Maxime Bizon <[email protected]>
+  * Copyright (C) 2012 Kevin Cernekee <[email protected]>
+  * Copyright (C) 2012 Broadcom Corporation
+  *
+  */
++#include <linux/spinlock.h>
+ #include <linux/export.h>
+ 
+ #include <bcm63xx_cpu.h>
+@@ -16,9 +18,14 @@
+ #include <bcm63xx_io.h>
+ #include <bcm63xx_usb_priv.h>
+ 
++static DEFINE_SPINLOCK(usb_priv_reg_lock);
++
+ void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device)
+ {
+ 	u32 val;
++	unsigned long flags;
++
++	spin_lock_irqsave(&usb_priv_reg_lock, flags);
+ 
+ 	val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG);
+ 	if (is_device) {
+@@ -36,12 +43,17 @@ void bcm63xx_usb_priv_select_phy_mode(u3
+ 	else
+ 		val &= ~USBH_PRIV_SWAP_USBD_MASK;
+ 	bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_SWAP_6368_REG);
++
++	spin_unlock_irqrestore(&usb_priv_reg_lock, flags);
+ }
+ EXPORT_SYMBOL(bcm63xx_usb_priv_select_phy_mode);
+ 
+ void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on)
+ {
+ 	u32 val;
++	unsigned long flags;
++
++	spin_lock_irqsave(&usb_priv_reg_lock, flags);
+ 
+ 	val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG);
+ 	if (is_on)
+@@ -49,5 +61,90 @@ void bcm63xx_usb_priv_select_pullup(u32
+ 	else
+ 		val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);
+ 	bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG);
++
++	spin_unlock_irqrestore(&usb_priv_reg_lock, flags);
+ }
+ EXPORT_SYMBOL(bcm63xx_usb_priv_select_pullup);
++
++/* The following array represents the meaning of the DESC/DATA
++ * endian swapping with respect to the CPU configured endianness
++ *
++ * DATA	ENDN	mmio	descriptor
++ * 0	0	BE	invalid
++ * 0	1	BE	LE
++ * 1	0	BE	BE
++ * 1	1	BE	invalid
++ *
++ * Since BCM63XX SoCs are configured to be in big-endian mode
++ * we want configuration at line 3.
++ */
++void bcm63xx_usb_priv_ohci_cfg_set(void)
++{
++	u32 reg;
++	unsigned long flags;
++
++	spin_lock_irqsave(&usb_priv_reg_lock, flags);
++
++	if (BCMCPU_IS_6348())
++		bcm_rset_writel(RSET_OHCI_PRIV, 0, OHCI_PRIV_REG);
++	else if (BCMCPU_IS_6358()) {
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6358_REG);
++		reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK;
++		reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK;
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6358_REG);
++		/*
++		 * The magic value comes for the original vendor BSP
++		 * and is needed for USB to work. Datasheet does not
++		 * help, so the magic value is used as-is.
++		 */
++		bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020,
++				USBH_PRIV_TEST_6358_REG);
++
++	} else if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);
++		reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK;
++		reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK;
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG);
++
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
++		reg |= USBH_PRIV_SETUP_IOC_MASK;
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
++	}
++
++	spin_unlock_irqrestore(&usb_priv_reg_lock, flags);
++}
++
++void bcm63xx_usb_priv_ehci_cfg_set(void)
++{
++	u32 reg;
++	unsigned long flags;
++
++	spin_lock_irqsave(&usb_priv_reg_lock, flags);
++
++	if (BCMCPU_IS_6358()) {
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6358_REG);
++		reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK;
++		reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK;
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6358_REG);
++
++		/*
++		 * The magic value comes for the original vendor BSP
++		 * and is needed for USB to work. Datasheet does not
++		 * help, so the magic value is used as-is.
++		 */
++		bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020,
++				USBH_PRIV_TEST_6358_REG);
++
++	} else if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);
++		reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK;
++		reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK;
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG);
++
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
++		reg |= USBH_PRIV_SETUP_IOC_MASK;
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
++	}
++
++	spin_unlock_irqrestore(&usb_priv_reg_lock, flags);
++}
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h
+@@ -5,5 +5,7 @@
+ 
+ void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device);
+ void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on);
++void bcm63xx_usb_priv_ohci_cfg_set(void);
++void bcm63xx_usb_priv_ehci_cfg_set(void);
+ 
+ #endif /* BCM63XX_USB_PRIV_H_ */

target/linux/brcm63xx/patches-4.9/104-MIPS-BCM63XX-introduce-BCM63XX_OHCI-configuration-sy.patch

@@ -0,0 +1,62 @@
+From 94ec618bd1a6b07fafbbfc9bcc54e7f9360ff9a0 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <[email protected]>
+Date: Mon, 28 Jan 2013 20:06:23 +0100
+Subject: [PATCH 05/11] MIPS: BCM63XX: introduce BCM63XX_OHCI configuration
+ symbol
+
+This configuration symbol can be used by CPUs supporting the on-chip
+OHCI controller, and ensures that all relevant OHCI-related
+configuration options are correctly selected. So far, OHCI support is
+available for the 6328, 6348, 6358 and 6358 SoCs.
+
+Signed-off-by: Florian Fainelli <[email protected]>
+---
+ arch/mips/bcm63xx/Kconfig |   15 ++++++++++-----
+ 1 file changed, 10 insertions(+), 5 deletions(-)
+
+--- a/arch/mips/bcm63xx/Kconfig
++++ b/arch/mips/bcm63xx/Kconfig
+@@ -6,10 +6,17 @@ config BCM63XX_CPU_3368
+ 	select SYS_HAS_CPU_BMIPS4350
+ 	select HW_HAS_PCI
+ 
++config BCM63XX_OHCI
++	bool
++	select USB_ARCH_HAS_OHCI
++	select USB_OHCI_BIG_ENDIAN_DESC if USB_OHCI_HCD
++	select USB_OHCI_BIG_ENDIAN_MMIO if USB_OHCI_HCD
++
+ config BCM63XX_CPU_6328
+ 	bool "support 6328 CPU"
+ 	select SYS_HAS_CPU_BMIPS4350
+ 	select HW_HAS_PCI
++	select BCM63XX_OHCI
+ 
+ config BCM63XX_CPU_6338
+ 	bool "support 6338 CPU"
+@@ -24,21 +31,25 @@ config BCM63XX_CPU_6348
+ 	bool "support 6348 CPU"
+ 	select SYS_HAS_CPU_BMIPS32_3300
+ 	select HW_HAS_PCI
++	select BCM63XX_OHCI
+ 
+ config BCM63XX_CPU_6358
+ 	bool "support 6358 CPU"
+ 	select SYS_HAS_CPU_BMIPS4350
+ 	select HW_HAS_PCI
++	select BCM63XX_OHCI
+ 
+ config BCM63XX_CPU_6362
+ 	bool "support 6362 CPU"
+ 	select SYS_HAS_CPU_BMIPS4350
+ 	select HW_HAS_PCI
++	select BCM63XX_OHCI
+ 
+ config BCM63XX_CPU_6368
+ 	bool "support 6368 CPU"
+ 	select SYS_HAS_CPU_BMIPS4350
+ 	select HW_HAS_PCI
++	select BCM63XX_OHCI
+ endmenu
+ 
+ source "arch/mips/bcm63xx/boards/Kconfig"

target/linux/brcm63xx/patches-4.9/105-MIPS-BCM63XX-add-support-for-the-on-chip-OHCI-contro.patch

@@ -0,0 +1,138 @@
+From 30d22baef255c99a12c4858ce4ab0d45f0d8c9ae Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <[email protected]>
+Date: Mon, 28 Jan 2013 20:06:24 +0100
+Subject: [PATCH 06/11] MIPS: BCM63XX: add support for the on-chip OHCI
+ controller
+
+Broadcom BCM63XX SoCs include an on-chip OHCI controller which can be
+driven by the ohci-platform generic driver by using specific power
+on/off/suspend callback to manage clocks and hardware specific
+configuration.
+
+Signed-off-by: Maxime Bizon <[email protected]>
+Signed-off-by: Florian Fainelli <[email protected]>
+---
+ arch/mips/bcm63xx/Makefile                         |    2 +-
+ arch/mips/bcm63xx/dev-usb-ohci.c                   |   94 ++++++++++++++++++++
+ .../asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h        |    6 ++
+ 3 files changed, 101 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/bcm63xx/dev-usb-ohci.c
+ create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h
+
+--- a/arch/mips/bcm63xx/Makefile
++++ b/arch/mips/bcm63xx/Makefile
+@@ -1,7 +1,7 @@
+ obj-y		+= clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \
+ 		   setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \
+ 		   dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \
+-		   dev-wdt.o dev-usb-usbd.o usb-common.o
++		   dev-wdt.o dev-usb-ohci.o dev-usb-usbd.o usb-common.o
+ obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
+ 
+ obj-y		+= boards/
+--- /dev/null
++++ b/arch/mips/bcm63xx/dev-usb-ohci.c
+@@ -0,0 +1,94 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <[email protected]>
++ * Copyright (C) 2013 Florian Fainelli <[email protected]>
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <linux/usb/ohci_pdriver.h>
++#include <linux/dma-mapping.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_regs.h>
++#include <bcm63xx_io.h>
++#include <bcm63xx_usb_priv.h>
++#include <bcm63xx_dev_usb_ohci.h>
++
++static struct resource ohci_resources[] = {
++	{
++		.start		= -1, /* filled at runtime */
++		.end		= -1, /* filled at runtime */
++		.flags		= IORESOURCE_MEM,
++	},
++	{
++		.start		= -1, /* filled at runtime */
++		.flags		= IORESOURCE_IRQ,
++	},
++};
++
++static u64 ohci_dmamask = DMA_BIT_MASK(32);
++
++static struct clk *usb_host_clock;
++
++static int bcm63xx_ohci_power_on(struct platform_device *pdev)
++{
++	usb_host_clock = clk_get(&pdev->dev, "usbh");
++	if (IS_ERR_OR_NULL(usb_host_clock))
++		return -ENODEV;
++
++	clk_prepare_enable(usb_host_clock);
++
++	bcm63xx_usb_priv_ohci_cfg_set();
++
++	return 0;
++}
++
++static void bcm63xx_ohci_power_off(struct platform_device *pdev)
++{
++	if (!IS_ERR_OR_NULL(usb_host_clock)) {
++		clk_disable_unprepare(usb_host_clock);
++		clk_put(usb_host_clock);
++	}
++}
++
++static struct usb_ohci_pdata bcm63xx_ohci_pdata = {
++	.big_endian_desc	= 1,
++	.big_endian_mmio	= 1,
++	.no_big_frame_no	= 1,
++	.num_ports		= 1,
++	.power_on		= bcm63xx_ohci_power_on,
++	.power_off		= bcm63xx_ohci_power_off,
++	.power_suspend		= bcm63xx_ohci_power_off,
++};
++
++static struct platform_device bcm63xx_ohci_device = {
++	.name		= "ohci-platform",
++	.id		= -1,
++	.num_resources	= ARRAY_SIZE(ohci_resources),
++	.resource	= ohci_resources,
++	.dev		= {
++		.platform_data		= &bcm63xx_ohci_pdata,
++		.dma_mask		= &ohci_dmamask,
++		.coherent_dma_mask	= DMA_BIT_MASK(32),
++	},
++};
++
++int __init bcm63xx_ohci_register(void)
++{
++	if (BCMCPU_IS_6345() || BCMCPU_IS_6338())
++		return -ENODEV;
++
++	ohci_resources[0].start = bcm63xx_regset_address(RSET_OHCI0);
++	ohci_resources[0].end = ohci_resources[0].start;
++	ohci_resources[0].end += RSET_OHCI_SIZE - 1;
++	ohci_resources[1].start = bcm63xx_get_irq_number(IRQ_OHCI0);
++
++	return platform_device_register(&bcm63xx_ohci_device);
++}
+--- /dev/null
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h
+@@ -0,0 +1,6 @@
++#ifndef BCM63XX_DEV_USB_OHCI_H_
++#define BCM63XX_DEV_USB_OHCI_H_
++
++int bcm63xx_ohci_register(void);
++
++#endif /* BCM63XX_DEV_USB_OHCI_H_ */

target/linux/brcm63xx/patches-4.9/106-MIPS-BCM63XX-register-OHCI-controller-if-board-enabl.patch

@@ -0,0 +1,36 @@
+From 33ef960aed15f9a98a2c51d8d794cd72418e0be4 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <[email protected]>
+Date: Mon, 28 Jan 2013 20:06:25 +0100
+Subject: [PATCH 07/11] MIPS: BCM63XX: register OHCI controller if board
+ enables it
+
+BCM63XX-based boards can control the registration of the OHCI controller
+by setting their has_ohci0 flag to 1. Handle this in the generic
+code dealing with board registration and call the actual helper to
+register the OHCI controller.
+
+Signed-off-by: Florian Fainelli <[email protected]>
+---
+ arch/mips/bcm63xx/boards/board_bcm963xx.c |    4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -28,6 +28,7 @@
+ #include <bcm63xx_dev_hsspi.h>
+ #include <bcm63xx_dev_pcmcia.h>
+ #include <bcm63xx_dev_spi.h>
++#include <bcm63xx_dev_usb_ohci.h>
+ #include <bcm63xx_dev_usb_usbd.h>
+ #include <board_bcm963xx.h>
+ 
+@@ -898,6 +899,9 @@ int __init board_register_devices(void)
+ 	if (board.has_usbd)
+ 		bcm63xx_usbd_register(&board.usbd);
+ 
++	if (board.has_ohci0)
++		bcm63xx_ohci_register();
++
+ 	if (board.has_dsp)
+ 		bcm63xx_dsp_register(&board.dsp);
+ 

target/linux/brcm63xx/patches-4.9/107-MIPS-BCM63XX-introduce-BCM63XX_EHCI-configuration-sy.patch

@@ -0,0 +1,62 @@
+From 00da1683364e58c6430a4577123d01037f8faddc Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <[email protected]>
+Date: Mon, 28 Jan 2013 20:06:26 +0100
+Subject: [PATCH 08/11] MIPS: BCM63XX: introduce BCM63XX_EHCI configuration
+ symbol
+
+This configuration symbol can be used by CPUs supporting the on-chip
+EHCI controller, and ensures that all relevant EHCI-related
+configuration options are selected. So far BCM6328, BCM6358 and BCM6368
+have an EHCI controller and do select this symbol. Update
+drivers/usb/host/Kconfig with BCM63XX to update direct unmet
+dependencies.
+
+Signed-off-by: Florian Fainelli <[email protected]>
+---
+ arch/mips/bcm63xx/Kconfig |    9 +++++++++
+ drivers/usb/host/Kconfig  |    5 +++--
+ 2 files changed, 12 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/bcm63xx/Kconfig
++++ b/arch/mips/bcm63xx/Kconfig
+@@ -12,11 +12,18 @@ config BCM63XX_OHCI
+ 	select USB_OHCI_BIG_ENDIAN_DESC if USB_OHCI_HCD
+ 	select USB_OHCI_BIG_ENDIAN_MMIO if USB_OHCI_HCD
+ 
++config BCM63XX_EHCI
++	bool
++	select USB_ARCH_HAS_EHCI
++	select USB_EHCI_BIG_ENDIAN_DESC if USB_EHCI_HCD
++	select USB_EHCI_BIG_ENDIAN_MMIO if USB_EHCI_HCD
++
+ config BCM63XX_CPU_6328
+ 	bool "support 6328 CPU"
+ 	select SYS_HAS_CPU_BMIPS4350
+ 	select HW_HAS_PCI
+ 	select BCM63XX_OHCI
++	select BCM63XX_EHCI
+ 
+ config BCM63XX_CPU_6338
+ 	bool "support 6338 CPU"
+@@ -38,18 +45,21 @@ config BCM63XX_CPU_6358
+ 	select SYS_HAS_CPU_BMIPS4350
+ 	select HW_HAS_PCI
+ 	select BCM63XX_OHCI
++	select BCM63XX_EHCI
+ 
+ config BCM63XX_CPU_6362
+ 	bool "support 6362 CPU"
+ 	select SYS_HAS_CPU_BMIPS4350
+ 	select HW_HAS_PCI
+ 	select BCM63XX_OHCI
++	select BCM63XX_EHCI
+ 
+ config BCM63XX_CPU_6368
+ 	bool "support 6368 CPU"
+ 	select SYS_HAS_CPU_BMIPS4350
+ 	select HW_HAS_PCI
+ 	select BCM63XX_OHCI
++	select BCM63XX_EHCI
+ endmenu
+ 
+ source "arch/mips/bcm63xx/boards/Kconfig"

target/linux/brcm63xx/patches-4.9/108-MIPS-BCM63XX-add-support-for-the-on-chip-EHCI-contro.patch

@@ -0,0 +1,137 @@
+From e38f13bd6408769c0b565bb1079024f496eee121 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <[email protected]>
+Date: Mon, 28 Jan 2013 20:06:27 +0100
+Subject: [PATCH 09/11] MIPS: BCM63XX: add support for the on-chip EHCI
+ controller
+
+Broadcom BCM63XX SoCs include an on-chip EHCI controller which can be
+driven by the generic ehci-platform driver by using specific power
+on/off/suspend callbacks to manage clocks and hardware specific
+configuration.
+
+Signed-off-by: Maxime Bizon <[email protected]>
+Signed-off-by: Florian Fainelli <[email protected]>
+---
+ arch/mips/bcm63xx/Makefile                         |    2 +-
+ arch/mips/bcm63xx/dev-usb-ehci.c                   |   92 ++++++++++++++++++++
+ .../asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h        |    6 ++
+ 3 files changed, 99 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/bcm63xx/dev-usb-ehci.c
+ create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h
+
+--- a/arch/mips/bcm63xx/Makefile
++++ b/arch/mips/bcm63xx/Makefile
+@@ -1,7 +1,8 @@
+ obj-y		+= clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \
+ 		   setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \
+ 		   dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \
+-		   dev-wdt.o dev-usb-ohci.o dev-usb-usbd.o usb-common.o
++		   dev-wdt.o dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o \
++		   usb-common.o
+ obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
+ 
+ obj-y		+= boards/
+--- /dev/null
++++ b/arch/mips/bcm63xx/dev-usb-ehci.c
+@@ -0,0 +1,92 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <[email protected]>
++ * Copyright (C) 2013 Florian Fainelli <[email protected]>
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/usb/ehci_pdriver.h>
++#include <linux/dma-mapping.h>
++
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_regs.h>
++#include <bcm63xx_io.h>
++#include <bcm63xx_usb_priv.h>
++#include <bcm63xx_dev_usb_ehci.h>
++
++static struct resource ehci_resources[] = {
++	{
++		.start		= -1, /* filled at runtime */
++		.end		= -1, /* filled at runtime */
++		.flags		= IORESOURCE_MEM,
++	},
++	{
++		.start		= -1, /* filled at runtime */
++		.flags		= IORESOURCE_IRQ,
++	},
++};
++
++static u64 ehci_dmamask = DMA_BIT_MASK(32);
++
++static struct clk *usb_host_clock;
++
++static int bcm63xx_ehci_power_on(struct platform_device *pdev)
++{
++	usb_host_clock = clk_get(&pdev->dev, "usbh");
++	if (IS_ERR_OR_NULL(usb_host_clock))
++		return -ENODEV;
++
++	clk_prepare_enable(usb_host_clock);
++
++	bcm63xx_usb_priv_ehci_cfg_set();
++
++	return 0;
++}
++
++static void bcm63xx_ehci_power_off(struct platform_device *pdev)
++{
++	if (!IS_ERR_OR_NULL(usb_host_clock)) {
++		clk_disable_unprepare(usb_host_clock);
++		clk_put(usb_host_clock);
++	}
++}
++
++static struct usb_ehci_pdata bcm63xx_ehci_pdata = {
++	.big_endian_desc	= 1,
++	.big_endian_mmio	= 1,
++	.power_on		= bcm63xx_ehci_power_on,
++	.power_off		= bcm63xx_ehci_power_off,
++	.power_suspend		= bcm63xx_ehci_power_off,
++};
++
++static struct platform_device bcm63xx_ehci_device = {
++	.name		= "ehci-platform",
++	.id		= -1,
++	.num_resources	= ARRAY_SIZE(ehci_resources),
++	.resource	= ehci_resources,
++	.dev		= {
++		.platform_data		= &bcm63xx_ehci_pdata,
++		.dma_mask		= &ehci_dmamask,
++		.coherent_dma_mask	= DMA_BIT_MASK(32),
++	},
++};
++
++int __init bcm63xx_ehci_register(void)
++{
++	if (!BCMCPU_IS_6328() && !BCMCPU_IS_6358() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
++		return 0;
++
++	ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0);
++	ehci_resources[0].end = ehci_resources[0].start;
++	ehci_resources[0].end += RSET_EHCI_SIZE - 1;
++	ehci_resources[1].start = bcm63xx_get_irq_number(IRQ_EHCI0);
++
++	return platform_device_register(&bcm63xx_ehci_device);
++}
+--- /dev/null
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h
+@@ -0,0 +1,6 @@
++#ifndef BCM63XX_DEV_USB_EHCI_H_
++#define BCM63XX_DEV_USB_EHCI_H_
++
++int bcm63xx_ehci_register(void);
++
++#endif /* BCM63XX_DEV_USB_EHCI_H_ */

target/linux/brcm63xx/patches-4.9/109-MIPS-BCM63XX-register-EHCI-controller-if-board-enabl.patch

@@ -0,0 +1,36 @@
+From 709ef2034f5ba06da35f89856ad7baf2b7a41287 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <[email protected]>
+Date: Mon, 28 Jan 2013 20:06:28 +0100
+Subject: [PATCH 10/11] MIPS: BCM63XX: register EHCI controller if board
+ enables it
+
+BCM63XX-based board can control the registration of the EHCI controller
+by setting their has_ehci0 flag to 1. Handle this in the generic
+code dealing with board registration and call the actual helper to register
+the EHCI controller.
+
+Signed-off-by: Florian Fainelli <[email protected]>
+---
+ arch/mips/bcm63xx/boards/board_bcm963xx.c |    4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -28,6 +28,7 @@
+ #include <bcm63xx_dev_hsspi.h>
+ #include <bcm63xx_dev_pcmcia.h>
+ #include <bcm63xx_dev_spi.h>
++#include <bcm63xx_dev_usb_ehci.h>
+ #include <bcm63xx_dev_usb_ohci.h>
+ #include <bcm63xx_dev_usb_usbd.h>
+ #include <board_bcm963xx.h>
+@@ -899,6 +900,9 @@ int __init board_register_devices(void)
+ 	if (board.has_usbd)
+ 		bcm63xx_usbd_register(&board.usbd);
+ 
++	if (board.has_ehci0)
++		bcm63xx_ehci_register();
++
+ 	if (board.has_ohci0)
+ 		bcm63xx_ohci_register();
+ 

target/linux/brcm63xx/patches-4.9/110-MIPS-BCM63XX-EHCI-controller-does-not-support-overcu.patch

@@ -0,0 +1,24 @@
+From 111bbd770441ab34f9da5bb1d85767a9b75227b4 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <[email protected]>
+Date: Mon, 28 Jan 2013 20:06:30 +0100
+Subject: [PATCH 12/12] MIPS: BCM63XX: EHCI controller does not support
+ overcurrent
+
+This patch sets the ignore_oc flag for the BCM63XX EHCI controller as it
+does not support proper overcurrent reporting.
+
+Signed-off-by: Florian Fainelli <[email protected]>
+---
+ arch/mips/bcm63xx/dev-usb-ehci.c |    1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/mips/bcm63xx/dev-usb-ehci.c
++++ b/arch/mips/bcm63xx/dev-usb-ehci.c
+@@ -61,6 +61,7 @@ static void bcm63xx_ehci_power_off(struc
+ static struct usb_ehci_pdata bcm63xx_ehci_pdata = {
+ 	.big_endian_desc	= 1,
+ 	.big_endian_mmio	= 1,
++	.ignore_oc		= 1,
+ 	.power_on		= bcm63xx_ehci_power_on,
+ 	.power_off		= bcm63xx_ehci_power_off,
+ 	.power_suspend		= bcm63xx_ehci_power_off,

target/linux/brcm63xx/patches-4.9/111-MIPS-BCM63XX-allow-NULL-clock-for-clk_get_rate.patch

@@ -0,0 +1,48 @@
+From patchwork Tue Jul 18 10:17:27 2017
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+Subject: [6/9] MIPS: BCM63XX: allow NULL clock for clk_get_rate
+X-Patchwork-Submitter: Jonas Gorski <[email protected]>
+X-Patchwork-Id: 16776
+Message-Id: <[email protected]>
+To: unlisted-recipients:; (no To-header on input)
+Cc: Ralf Baechle <[email protected]>,
+ Florian Fainelli <[email protected]>,
+ [email protected],
+ James Hogan <[email protected]>,
+ [email protected], [email protected]
+Date: Tue, 18 Jul 2017 12:17:27 +0200
+From: Jonas Gorski <[email protected]>
+List-Id: linux-mips <linux-mips.eddie.linux-mips.org>
+
+Make the behaviour of clk_get_rate consistent with common clk's
+clk_get_rate by accepting NULL clocks as parameter. Some device
+drivers rely on this, and will cause an OOPS otherwise.
+
+Fixes: e7300d04bd08 ("MIPS: BCM63xx: Add support for the Broadcom BCM63xx family of SOCs.")
+Cc: Ralf Baechle <[email protected]>
+Cc: Florian Fainelli <[email protected]>
+Cc: [email protected]
+Cc: James Hogan <[email protected]>
+Cc: [email protected]
+Cc: [email protected]
+Reported-by: Mathias Kresin <[email protected]>
+Signed-off-by: Jonas Gorski <[email protected]>
+Reviewed-by: Florian Fainelli <[email protected]>
+---
+ arch/mips/bcm63xx/clk.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -392,6 +392,9 @@ EXPORT_SYMBOL(clk_disable);
+ 
+ unsigned long clk_get_rate(struct clk *clk)
+ {
++	if (!clk)
++		return 0;
++
+ 	return clk->rate;
+ }
+ 

target/linux/brcm63xx/patches-4.9/120-mtd-add-of_match_table-parsing-for-partition-parsers.patch

@@ -0,0 +1,79 @@
+From 53980645bb12bd8723ac226805ee171780b24196 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Mon, 26 Jun 2017 13:37:11 +0200
+Subject: [PATCH 1/4] mtd: add of_match_table parsing for partition parsers
+
+Allow partition parsers to be matched by attaching compatible strings to
+partitions.
+
+This allows specifying the expected format of flash partitions for
+matching partition parsers.
+
+Example:
+
+flash@foo {
+	...
+	partitions {
+		compatible = "fixed-partitions";
+
+		cfe@0 {
+			reg = <0x0 0x10000>;
+			label = "cfe";
+			read-only;
+		};
+
+		firmware@10000 {
+			reg = <0x10000 0x3e0000>;
+			label = "firmware";
+			compatible = "brcm,bcm63xx-imagetag";
+		};
+
+		nvram@3f0000 {
+			reg = <0x3e0000 0x10000>;
+			label = "nvram";
+		};
+	};
+};
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/mtd/mtdpart.c | 12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+--- a/drivers/mtd/mtdpart.c
++++ b/drivers/mtd/mtdpart.c
+@@ -953,8 +953,7 @@ int add_mtd_partitions(struct mtd_info *
+ 		add_mtd_device(&slave->mtd);
+ 		mtd_partition_split(master, slave);
+ 		mtd_add_partition_attrs(slave);
+-		if (parts[i].types)
+-			mtd_parse_part(slave, parts[i].types);
++		mtd_parse_part(slave, parts[i].types);
+ 
+ 		cur_offset = slave->offset + slave->mtd.size;
+ 	}
+@@ -1164,7 +1163,9 @@ int parse_mtd_partitions(struct mtd_info
+ 			types = types_of;
+ 	}
+ 
+-	np = of_get_child_by_name(mtd_get_of_node(master), "partitions");
++	np = mtd_get_of_node(master);
++	if (!mtd_is_partition(master))
++		np = of_get_child_by_name(np, "partitions");
+ 	of_property_for_each_string(np, "compatible", prop, compat) {
+ 		parser = mtd_part_get_compatible_parser(compat);
+ 		if (!parser)
+@@ -1180,8 +1181,12 @@ int parse_mtd_partitions(struct mtd_info
+ 	}
+ 	of_node_put(np);
+ 
+-	if (!types)
++	if (!types) {
++		if (mtd_is_partition(master))
++			return -ENOENT;
++
+ 		types = default_mtd_part_types;
++	}
+ 
+ 	for ( ; *types; types++) {
+ 		pr_debug("%s: parsing partitions %s\n", master->name, *types);

target/linux/brcm63xx/patches-4.9/121-mtd-bcm63xxpart-move-imagetag-parsing-to-its-own-par.patch

@@ -0,0 +1,481 @@
+From a2b8c7f648e168573905818dbb4cb90ca3957c65 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Wed, 28 Jun 2017 18:29:43 +0200
+Subject: [PATCH] mtd: bcm63xxpart: move imagetag parsing to its own parser
+
+Move the bcm963xx Image Tag parsing into its own partition parser. This
+Allows reusing the parser with different full flash parsers.
+
+While moving it, rename it to bcm963* to better reflect it isn't chip
+but board specific.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+I tried to keep the code as-is, to keep the changes as small as
+possible.
+
+One side effect is that the partitions get renumbered, which means any
+root=/dev/mtdblock* will now point to the wrong mtd device. But since
+bcm963xx boards will require these hardcoded in the kernel commandline
+anyway this should b a non issue, as it can be easily updated.
+
+There is no such thing in the mips/bcm63xx defconfig, so nothing to update
+there.
+
+ drivers/mtd/Kconfig                   |   1 +
+ drivers/mtd/bcm63xxpart.c             | 155 ++----------------------
+ drivers/mtd/parsers/Kconfig           |  11 ++
+ drivers/mtd/parsers/Makefile          |   1 +
+ drivers/mtd/parsers/parser_imagetag.c | 214 ++++++++++++++++++++++++++++++++++
+ 5 files changed, 235 insertions(+), 147 deletions(-)
+ create mode 100644 drivers/mtd/parsers/parser_imagetag.c
+
+--- a/drivers/mtd/Kconfig
++++ b/drivers/mtd/Kconfig
+@@ -163,6 +163,7 @@ config MTD_BCM63XX_PARTS
+ 	tristate "BCM63XX CFE partitioning support"
+ 	depends on BCM63XX || BMIPS_GENERIC || COMPILE_TEST
+ 	select CRC32
++	select MTD_PARSER_IMAGETAG
+ 	help
+ 	  This provides partions parsing for BCM63xx devices with CFE
+ 	  bootloaders.
+--- a/drivers/mtd/bcm63xxpart.c
++++ b/drivers/mtd/bcm63xxpart.c
+@@ -93,51 +93,19 @@ static int bcm63xx_read_nvram(struct mtd
+ 	return 0;
+ }
+ 
+-static int bcm63xx_read_image_tag(struct mtd_info *master, const char *name,
+-	loff_t tag_offset, struct bcm_tag *buf)
+-{
+-	int ret;
+-	size_t retlen;
+-	u32 computed_crc;
+-
+-	ret = mtd_read(master, tag_offset, sizeof(*buf), &retlen, (void *)buf);
+-	if (ret)
+-		return ret;
+-
+-	if (retlen != sizeof(*buf))
+-		return -EIO;
+-
+-	computed_crc = crc32_le(IMAGETAG_CRC_START, (u8 *)buf,
+-				offsetof(struct bcm_tag, header_crc));
+-	if (computed_crc == buf->header_crc) {
+-		STR_NULL_TERMINATE(buf->board_id);
+-		STR_NULL_TERMINATE(buf->tag_version);
+-
+-		pr_info("%s: CFE image tag found at 0x%llx with version %s, board type %s\n",
+-			name, tag_offset, buf->tag_version, buf->board_id);
+-
+-		return 0;
+-	}
+-
+-	pr_warn("%s: CFE image tag at 0x%llx CRC invalid (expected %08x, actual %08x)\n",
+-		name, tag_offset, buf->header_crc, computed_crc);
+-	return 1;
+-}
++static const char * const bcm63xx_cfe_part_types[] = {
++	"bcm963xx-imagetag",
++	NULL,
++};
+ 
+ static int bcm63xx_parse_cfe_nor_partitions(struct mtd_info *master,
+ 	const struct mtd_partition **pparts, struct bcm963xx_nvram *nvram)
+ {
+-	/* CFE, NVRAM and global Linux are always present */
+-	int nrparts = 3, curpart = 0;
+-	struct bcm_tag *buf = NULL;
+ 	struct mtd_partition *parts;
+-	int ret;
+-	unsigned int rootfsaddr, kerneladdr, spareaddr;
+-	unsigned int rootfslen, kernellen, sparelen, totallen;
++	int nrparts = 3, curpart = 0;
+ 	unsigned int cfelen, nvramlen;
+ 	unsigned int cfe_erasesize;
+ 	int i;
+-	bool rootfs_first = false;
+ 
+ 	cfe_erasesize = max_t(uint32_t, master->erasesize,
+ 			      BCM963XX_CFE_BLOCK_SIZE);
+@@ -146,83 +114,9 @@ static int bcm63xx_parse_cfe_nor_partiti
+ 	nvramlen = nvram->psi_size * SZ_1K;
+ 	nvramlen = roundup(nvramlen, cfe_erasesize);
+ 
+-	buf = vmalloc(sizeof(struct bcm_tag));
+-	if (!buf)
+-		return -ENOMEM;
+-
+-	/* Get the tag */
+-	ret = bcm63xx_read_image_tag(master, "rootfs", cfelen, buf);
+-	if (!ret) {
+-		STR_NULL_TERMINATE(buf->flash_image_start);
+-		if (kstrtouint(buf->flash_image_start, 10, &rootfsaddr) ||
+-				rootfsaddr < BCM963XX_EXTENDED_SIZE) {
+-			pr_err("invalid rootfs address: %*ph\n",
+-				(int)sizeof(buf->flash_image_start),
+-				buf->flash_image_start);
+-			goto invalid_tag;
+-		}
+-
+-		STR_NULL_TERMINATE(buf->kernel_address);
+-		if (kstrtouint(buf->kernel_address, 10, &kerneladdr) ||
+-				kerneladdr < BCM963XX_EXTENDED_SIZE) {
+-			pr_err("invalid kernel address: %*ph\n",
+-				(int)sizeof(buf->kernel_address),
+-				buf->kernel_address);
+-			goto invalid_tag;
+-		}
+-
+-		STR_NULL_TERMINATE(buf->kernel_length);
+-		if (kstrtouint(buf->kernel_length, 10, &kernellen)) {
+-			pr_err("invalid kernel length: %*ph\n",
+-				(int)sizeof(buf->kernel_length),
+-				buf->kernel_length);
+-			goto invalid_tag;
+-		}
+-
+-		STR_NULL_TERMINATE(buf->total_length);
+-		if (kstrtouint(buf->total_length, 10, &totallen)) {
+-			pr_err("invalid total length: %*ph\n",
+-				(int)sizeof(buf->total_length),
+-				buf->total_length);
+-			goto invalid_tag;
+-		}
+-
+-		kerneladdr = kerneladdr - BCM963XX_EXTENDED_SIZE;
+-		rootfsaddr = rootfsaddr - BCM963XX_EXTENDED_SIZE;
+-		spareaddr = roundup(totallen, master->erasesize) + cfelen;
+-
+-		if (rootfsaddr < kerneladdr) {
+-			/* default Broadcom layout */
+-			rootfslen = kerneladdr - rootfsaddr;
+-			rootfs_first = true;
+-		} else {
+-			/* OpenWrt layout */
+-			rootfsaddr = kerneladdr + kernellen;
+-			rootfslen = spareaddr - rootfsaddr;
+-		}
+-	} else if (ret > 0) {
+-invalid_tag:
+-		kernellen = 0;
+-		rootfslen = 0;
+-		rootfsaddr = 0;
+-		spareaddr = cfelen;
+-	} else {
+-		goto out;
+-	}
+-	sparelen = master->size - spareaddr - nvramlen;
+-
+-	/* Determine number of partitions */
+-	if (rootfslen > 0)
+-		nrparts++;
+-
+-	if (kernellen > 0)
+-		nrparts++;
+-
+ 	parts = kzalloc(sizeof(*parts) * nrparts + 10 * nrparts, GFP_KERNEL);
+-	if (!parts) {
+-		ret = -ENOMEM;
+-		goto out;
+-	}
++	if (!parts)
++		return -ENOMEM;
+ 
+ 	/* Start building partition list */
+ 	parts[curpart].name = "CFE";
+@@ -230,30 +124,6 @@ invalid_tag:
+ 	parts[curpart].size = cfelen;
+ 	curpart++;
+ 
+-	if (kernellen > 0) {
+-		int kernelpart = curpart;
+-
+-		if (rootfslen > 0 && rootfs_first)
+-			kernelpart++;
+-		parts[kernelpart].name = "kernel";
+-		parts[kernelpart].offset = kerneladdr;
+-		parts[kernelpart].size = kernellen;
+-		curpart++;
+-	}
+-
+-	if (rootfslen > 0) {
+-		int rootfspart = curpart;
+-
+-		if (kernellen > 0 && rootfs_first)
+-			rootfspart--;
+-		parts[rootfspart].name = "rootfs";
+-		parts[rootfspart].offset = rootfsaddr;
+-		parts[rootfspart].size = rootfslen;
+-		if (sparelen > 0  && !rootfs_first)
+-			parts[rootfspart].size += sparelen;
+-		curpart++;
+-	}
+-
+ 	parts[curpart].name = "nvram";
+ 	parts[curpart].offset = master->size - nvramlen;
+ 	parts[curpart].size = nvramlen;
+@@ -263,22 +133,13 @@ invalid_tag:
+ 	parts[curpart].name = "linux";
+ 	parts[curpart].offset = cfelen;
+ 	parts[curpart].size = master->size - cfelen - nvramlen;
++	parts[curpart].types = bcm63xx_cfe_part_types;
+ 
+ 	for (i = 0; i < nrparts; i++)
+ 		pr_info("Partition %d is %s offset %llx and length %llx\n", i,
+ 			parts[i].name, parts[i].offset,	parts[i].size);
+ 
+-	pr_info("Spare partition is offset %x and length %x\n",	spareaddr,
+-		sparelen);
+-
+ 	*pparts = parts;
+-	ret = 0;
+-
+-out:
+-	vfree(buf);
+-
+-	if (ret)
+-		return ret;
+ 
+ 	return nrparts;
+ }
+--- a/drivers/mtd/parsers/Kconfig
++++ b/drivers/mtd/parsers/Kconfig
+@@ -1,3 +1,14 @@
++config MTD_PARSER_IMAGETAG
++	tristate "Parser for BCM963XX Image Tag format partitions"
++	depends on BCM63XX || BMIPS || COMPILE_TEST
++	select CRC32
++	help
++	  Image Tag is the firmware header used by broadcom on their xDSL line
++	  of devices. It is used to describe the offsets and lengths of kernel
++	  and rootfs partitions.
++	  This driver adds support for parsing a partition with an Image Tag
++	  header and creates up to two partitions, kernel and rootfs.
++
+ config MTD_PARSER_TRX
+ 	tristate "Parser for TRX format partitions"
+ 	depends on MTD && (BCM47XX || ARCH_BCM_5301X || COMPILE_TEST)
+--- a/drivers/mtd/parsers/Makefile
++++ b/drivers/mtd/parsers/Makefile
+@@ -1 +1,2 @@
++obj-$(CONFIG_MTD_PARSER_IMAGETAG)	+= parser_imagetag.o
+ obj-$(CONFIG_MTD_PARSER_TRX)		+= parser_trx.o
+--- /dev/null
++++ b/drivers/mtd/parsers/parser_imagetag.c
+@@ -0,0 +1,214 @@
++/*
++ * BCM63XX CFE image tag parser
++ *
++ * Copyright © 2006-2008  Florian Fainelli <[email protected]>
++ *			  Mike Albon <[email protected]>
++ * Copyright © 2009-2010  Daniel Dickinson <[email protected]>
++ * Copyright © 2011-2013  Jonas Gorski <[email protected]>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include <linux/bcm963xx_tag.h>
++#include <linux/crc32.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/sizes.h>
++#include <linux/slab.h>
++#include <linux/vmalloc.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++
++/* Ensure strings read from flash structs are null terminated */
++#define STR_NULL_TERMINATE(x) \
++	do { char *_str = (x); _str[sizeof(x) - 1] = 0; } while (0)
++
++static int bcm963xx_read_imagetag(struct mtd_info *master, const char *name,
++	loff_t tag_offset, struct bcm_tag *buf)
++{
++	int ret;
++	size_t retlen;
++	u32 computed_crc;
++
++	ret = mtd_read(master, tag_offset, sizeof(*buf), &retlen, (void *)buf);
++	if (ret)
++		return ret;
++
++	if (retlen != sizeof(*buf))
++		return -EIO;
++
++	computed_crc = crc32_le(IMAGETAG_CRC_START, (u8 *)buf,
++				offsetof(struct bcm_tag, header_crc));
++	if (computed_crc == buf->header_crc) {
++		STR_NULL_TERMINATE(buf->board_id);
++		STR_NULL_TERMINATE(buf->tag_version);
++
++		pr_info("%s: CFE image tag found at 0x%llx with version %s, board type %s\n",
++			name, tag_offset, buf->tag_version, buf->board_id);
++
++		return 0;
++	}
++
++	pr_warn("%s: CFE image tag at 0x%llx CRC invalid (expected %08x, actual %08x)\n",
++		name, tag_offset, buf->header_crc, computed_crc);
++	return -EINVAL;
++}
++
++static int bcm963xx_parse_imagetag_partitions(struct mtd_info *master,
++					const struct mtd_partition **pparts,
++					struct mtd_part_parser_data *data)
++{
++	/* CFE, NVRAM and global Linux are always present */
++	int nrparts = 0, curpart = 0;
++	struct bcm_tag *buf = NULL;
++	struct mtd_partition *parts;
++	int ret;
++	unsigned int rootfsaddr, kerneladdr, spareaddr, offset;
++	unsigned int rootfslen, kernellen, sparelen, totallen;
++	int i;
++	bool rootfs_first = false;
++
++	buf = vmalloc(sizeof(struct bcm_tag));
++	if (!buf)
++		return -ENOMEM;
++
++	/* Get the tag */
++	ret = bcm963xx_read_imagetag(master, "rootfs", 0, buf);
++	if (!ret) {
++		STR_NULL_TERMINATE(buf->flash_image_start);
++		if (kstrtouint(buf->flash_image_start, 10, &rootfsaddr) ||
++				rootfsaddr < BCM963XX_EXTENDED_SIZE) {
++			pr_err("invalid rootfs address: %*ph\n",
++				(int)sizeof(buf->flash_image_start),
++				buf->flash_image_start);
++			goto out;
++		}
++
++		STR_NULL_TERMINATE(buf->kernel_address);
++		if (kstrtouint(buf->kernel_address, 10, &kerneladdr) ||
++				kerneladdr < BCM963XX_EXTENDED_SIZE) {
++			pr_err("invalid kernel address: %*ph\n",
++				(int)sizeof(buf->kernel_address),
++				buf->kernel_address);
++			goto out;
++		}
++
++		STR_NULL_TERMINATE(buf->kernel_length);
++		if (kstrtouint(buf->kernel_length, 10, &kernellen)) {
++			pr_err("invalid kernel length: %*ph\n",
++				(int)sizeof(buf->kernel_length),
++				buf->kernel_length);
++			goto out;
++		}
++
++		STR_NULL_TERMINATE(buf->total_length);
++		if (kstrtouint(buf->total_length, 10, &totallen)) {
++			pr_err("invalid total length: %*ph\n",
++				(int)sizeof(buf->total_length),
++				buf->total_length);
++			goto out;
++		}
++
++		/*
++		 * Addresses are flash absolute, so convert to partition
++		 * relative addresses. Assume either kernel or rootfs will
++		 * directly follow the image tag.
++		 */
++		if (rootfsaddr < kerneladdr)
++			offset = rootfsaddr - sizeof(struct bcm_tag);
++		else
++			offset = kerneladdr - sizeof(struct bcm_tag);
++
++		kerneladdr = kerneladdr - offset;
++		rootfsaddr = rootfsaddr - offset;
++		spareaddr = roundup(totallen, master->erasesize);
++
++		if (rootfsaddr < kerneladdr) {
++			/* default Broadcom layout */
++			rootfslen = kerneladdr - rootfsaddr;
++			rootfs_first = true;
++		} else {
++			/* OpenWrt layout */
++			rootfsaddr = kerneladdr + kernellen;
++			rootfslen = spareaddr - rootfsaddr;
++		}
++	} else {
++		goto out;
++	}
++	sparelen = master->size - spareaddr;
++
++	/* Determine number of partitions */
++	if (rootfslen > 0)
++		nrparts++;
++
++	if (kernellen > 0)
++		nrparts++;
++
++	parts = kzalloc(sizeof(*parts) * nrparts + 10 * nrparts, GFP_KERNEL);
++	if (!parts) {
++		ret = -ENOMEM;
++		goto out;
++	}
++
++	/* Start building partition list */
++	if (kernellen > 0) {
++		int kernelpart = curpart;
++
++		if (rootfslen > 0 && rootfs_first)
++			kernelpart++;
++		parts[kernelpart].name = "kernel";
++		parts[kernelpart].offset = kerneladdr;
++		parts[kernelpart].size = kernellen;
++		curpart++;
++	}
++
++	if (rootfslen > 0) {
++		int rootfspart = curpart;
++
++		if (kernellen > 0 && rootfs_first)
++			rootfspart--;
++		parts[rootfspart].name = "rootfs";
++		parts[rootfspart].offset = rootfsaddr;
++		parts[rootfspart].size = rootfslen;
++		if (sparelen > 0  && !rootfs_first)
++			parts[rootfspart].size += sparelen;
++		curpart++;
++	}
++
++	for (i = 0; i < nrparts; i++)
++		pr_info("Partition %d is %s offset %llx and length %llx\n", i,
++			parts[i].name, parts[i].offset,	parts[i].size);
++
++	pr_info("Spare partition is offset %x and length %x\n",	spareaddr,
++		sparelen);
++
++	*pparts = parts;
++	ret = 0;
++
++out:
++	vfree(buf);
++
++	if (ret)
++		return ret;
++
++	return nrparts;
++}
++
++static struct mtd_part_parser bcm963xx_imagetag_parser = {
++	.parse_fn = bcm963xx_parse_imagetag_partitions,
++	.name = "bcm963xx-imagetag",
++};
++module_mtd_part_parser(bcm963xx_imagetag_parser);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Daniel Dickinson <[email protected]>");
++MODULE_AUTHOR("Florian Fainelli <[email protected]>");
++MODULE_AUTHOR("Mike Albon <[email protected]>");
++MODULE_AUTHOR("Jonas Gorski <[email protected]");
++MODULE_DESCRIPTION("MTD parser for BCM963XX CFE Image Tag partitions");

target/linux/brcm63xx/patches-4.9/122-mtd-bcm63xxpart-add-of_match_table.patch

@@ -0,0 +1,37 @@
+From 89cd5efa4a0d342b860a726bb1d382e4db4b96a4 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Wed, 28 Jun 2017 18:34:42 +0200
+Subject: [PATCH 1/2] mtd: bcm63xxpart: add of_match_table
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/mtd/bcm63xxpart.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/mtd/bcm63xxpart.c
++++ b/drivers/mtd/bcm63xxpart.c
+@@ -34,6 +34,7 @@
+ #include <linux/vmalloc.h>
+ #include <linux/mtd/mtd.h>
+ #include <linux/mtd/partitions.h>
++#include <linux/of.h>
+ 
+ #define BCM963XX_CFE_BLOCK_SIZE		SZ_64K	/* always at least 64KiB */
+ 
+@@ -172,9 +173,16 @@ out:
+ 	return ret;
+ };
+ 
++static const struct of_device_id parse_bcm63xx_cfe_match_table[] = {
++	{ .compatible = "brcm,bcm963xx-cfe-nor-partitions" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, parse_bcm63xx_cfe_match_table);
++
+ static struct mtd_part_parser bcm63xx_cfe_parser = {
+ 	.parse_fn = bcm63xx_parse_cfe_partitions,
+ 	.name = "bcm63xxpart",
++	.of_match_table = parse_bcm63xx_cfe_match_table,
+ };
+ module_mtd_part_parser(bcm63xx_cfe_parser);
+ 

target/linux/brcm63xx/patches-4.9/123-mtd-parser_bcm63xx_imagetag-add-of_match_table-suppo.patch

@@ -0,0 +1,37 @@
+From 3303dd9f5b197cc2efd9cbd7b9b45fc1e510a393 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Wed, 28 Jun 2017 18:37:12 +0200
+Subject: [PATCH 2/2] mtd: parser_bcm63xx_imagetag: add of_match_table support
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/mtd/parsers/parser_imagetag.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/mtd/parsers/parser_imagetag.c
++++ b/drivers/mtd/parsers/parser_imagetag.c
+@@ -24,6 +24,7 @@
+ #include <linux/vmalloc.h>
+ #include <linux/mtd/mtd.h>
+ #include <linux/mtd/partitions.h>
++#include <linux/of.h>
+ 
+ /* Ensure strings read from flash structs are null terminated */
+ #define STR_NULL_TERMINATE(x) \
+@@ -200,9 +201,16 @@ out:
+ 	return nrparts;
+ }
+ 
++static const struct of_device_id parse_bcm963xx_imagetag_match_table[] = {
++	{ .compatible = "brcm,bcm963xx-imagetag" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, parse_bcm963xx_imagetag_match_table);
++
+ static struct mtd_part_parser bcm963xx_imagetag_parser = {
+ 	.parse_fn = bcm963xx_parse_imagetag_partitions,
+ 	.name = "bcm963xx-imagetag",
++	.of_match_table = parse_bcm963xx_imagetag_match_table,
+ };
+ module_mtd_part_parser(bcm963xx_imagetag_parser);
+ 

target/linux/brcm63xx/patches-4.9/130-pinctrl-add-bcm63xx-base-code.patch

@@ -0,0 +1,226 @@
+From ab2f33e35e35905a76204138143875251f3e1088 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Fri, 24 Jun 2016 22:07:42 +0200
+Subject: [PATCH 01/13] pinctrl: add bcm63xx base code
+
+Setup directory and add a helper for bcm63xx pinctrl support.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/pinctrl/Kconfig                   |   1 +
+ drivers/pinctrl/Makefile                  |   1 +
+ drivers/pinctrl/bcm63xx/Kconfig           |   3 +
+ drivers/pinctrl/bcm63xx/Makefile          |   1 +
+ drivers/pinctrl/bcm63xx/pinctrl-bcm63xx.c | 142 ++++++++++++++++++++++++++++++
+ drivers/pinctrl/bcm63xx/pinctrl-bcm63xx.h |  14 +++
+ 7 files changed, 163 insertions(+)
+ create mode 100644 drivers/pinctrl/bcm63xx/Kconfig
+ create mode 100644 drivers/pinctrl/bcm63xx/Makefile
+ create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm63xx.c
+ create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm63xx.h
+
+--- a/drivers/pinctrl/Kconfig
++++ b/drivers/pinctrl/Kconfig
+@@ -258,6 +258,7 @@ config PINCTRL_ZYNQ
+ 
+ source "drivers/pinctrl/aspeed/Kconfig"
+ source "drivers/pinctrl/bcm/Kconfig"
++source "drivers/pinctrl/bcm63xx/Kconfig"
+ source "drivers/pinctrl/berlin/Kconfig"
+ source "drivers/pinctrl/freescale/Kconfig"
+ source "drivers/pinctrl/intel/Kconfig"
+--- a/drivers/pinctrl/Makefile
++++ b/drivers/pinctrl/Makefile
+@@ -39,6 +39,7 @@ obj-$(CONFIG_PINCTRL_ZYNQ)	+= pinctrl-zy
+ 
+ obj-$(CONFIG_ARCH_ASPEED)	+= aspeed/
+ obj-y				+= bcm/
++obj-y				+= bcm63xx/
+ obj-$(CONFIG_PINCTRL_BERLIN)	+= berlin/
+ obj-y				+= freescale/
+ obj-$(CONFIG_X86)		+= intel/
+--- /dev/null
++++ b/drivers/pinctrl/bcm63xx/Kconfig
+@@ -0,0 +1,3 @@
++config PINCTRL_BCM63XX
++	bool
++	select GPIO_GENERIC
+--- /dev/null
++++ b/drivers/pinctrl/bcm63xx/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_PINCTRL_BCM63XX)	+= pinctrl-bcm63xx.o
+--- /dev/null
++++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm63xx.c
+@@ -0,0 +1,155 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2016 Jonas Gorski <[email protected]>
++ */
++
++#include <linux/bitops.h>
++#include <linux/device.h>
++#include <linux/gpio/driver.h>
++#include <linux/of_irq.h>
++
++#include "pinctrl-bcm63xx.h"
++#include "../core.h"
++
++#define BANK_SIZE	sizeof(u32)
++#define PINS_PER_BANK	(BANK_SIZE * BITS_PER_BYTE)
++
++#ifdef CONFIG_OF
++static int bcm63xx_gpio_of_xlate(struct gpio_chip *gc,
++				 const struct of_phandle_args *gpiospec,
++				 u32 *flags)
++{
++	struct gpio_chip *base = gpiochip_get_data(gc);
++	int pin = gpiospec->args[0];
++
++	if (gc != &base[pin / PINS_PER_BANK])
++		return -EINVAL;
++
++	pin = pin % PINS_PER_BANK;
++
++	if (pin >= gc->ngpio)
++		return -EINVAL;
++
++	if (flags)
++		*flags = gpiospec->args[1];
++
++	return pin;
++}
++#endif
++
++static int bcm63xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
++{
++	struct gpio_chip *base = gpiochip_get_data(chip);
++	char irq_name[7]; /* "gpioXX" */
++
++	/* FIXME: this is ugly */
++	sprintf(irq_name, "gpio%d", gpio + PINS_PER_BANK * (chip - base));
++	return of_irq_get_byname(chip->of_node, irq_name);
++}
++
++static int bcm63xx_setup_gpio(struct device *dev, struct gpio_chip *gc,
++			      void __iomem *dirout, void __iomem *data,
++			      size_t sz, int ngpio)
++
++{
++	int banks, chips, i, ret = -EINVAL;
++
++	chips = DIV_ROUND_UP(ngpio, PINS_PER_BANK);
++	banks = sz / BANK_SIZE;
++
++	for (i = 0; i < chips; i++) {
++		int offset, pins;
++		int reg_offset;
++		char *label;
++
++		label = devm_kasprintf(dev, GFP_KERNEL, "bcm63xx-gpio.%i", i);
++		if (!label)
++			return -ENOMEM;
++
++		offset = i * PINS_PER_BANK;
++		pins = min_t(int, ngpio - offset, PINS_PER_BANK);
++
++		/* the registers are treated like a huge big endian register */
++		reg_offset = (banks - i - 1) * BANK_SIZE;
++
++		ret = bgpio_init(&gc[i], dev, BANK_SIZE, data + reg_offset,
++				 NULL, NULL, dirout + reg_offset, NULL,
++				 BGPIOF_BIG_ENDIAN_BYTE_ORDER);
++		if (ret)
++			return ret;
++
++		gc[i].request = gpiochip_generic_request;
++		gc[i].free = gpiochip_generic_free;
++
++		if (of_get_property(dev->of_node, "interrupt-names", NULL))
++			gc[i].to_irq = bcm63xx_gpio_to_irq;
++
++#ifdef CONFIG_OF
++		gc[i].of_gpio_n_cells = 2;
++		gc[i].of_xlate = bcm63xx_gpio_of_xlate;
++#endif
++
++		gc[i].label = label;
++		gc[i].ngpio = pins;
++
++		devm_gpiochip_add_data(dev, &gc[i], gc);
++	}
++
++	return 0;
++}
++
++static void bcm63xx_setup_pinranges(struct gpio_chip *gc, const char *name,
++				    int ngpio)
++{
++	int i, chips = DIV_ROUND_UP(ngpio, PINS_PER_BANK);
++
++	for (i = 0; i < chips; i++) {
++		int offset, pins;
++
++		offset = i * PINS_PER_BANK;
++		pins = min_t(int, ngpio - offset, PINS_PER_BANK);
++
++		gpiochip_add_pin_range(&gc[i], name, 0, offset, pins);
++	}
++}
++
++struct pinctrl_dev *bcm63xx_pinctrl_register(struct platform_device *pdev,
++					     struct pinctrl_desc *desc,
++					     void *priv, struct gpio_chip *gc,
++					     int ngpio)
++{
++	struct pinctrl_dev *pctldev;
++	struct resource *res;
++	void __iomem *dirout, *data;
++	size_t sz;
++	int ret;
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirout");
++	dirout = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(dirout))
++		return ERR_CAST(dirout);
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
++	data = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(data))
++		return ERR_CAST(data);
++
++	sz = resource_size(res);
++
++	ret = bcm63xx_setup_gpio(&pdev->dev, gc, dirout, data, sz, ngpio);
++	if (ret)
++		return ERR_PTR(ret);
++
++	pctldev = devm_pinctrl_register(&pdev->dev, desc, priv);
++	if (IS_ERR(pctldev))
++		return pctldev;
++
++	bcm63xx_setup_pinranges(gc, pinctrl_dev_get_devname(pctldev), ngpio);
++
++	dev_info(&pdev->dev, "registered at mmio %p\n", dirout);
++
++	return pctldev;
++}
+--- /dev/null
++++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm63xx.h
+@@ -0,0 +1,14 @@
++#ifndef __PINCTRL_BCM63XX
++#define __PINCTRL_BCM63XX
++
++#include <linux/kernel.h>
++#include <linux/gpio.h>
++#include <linux/pinctrl/pinctrl.h>
++#include <linux/platform_device.h>
++
++struct pinctrl_dev *bcm63xx_pinctrl_register(struct platform_device *pdev,
++					     struct pinctrl_desc *desc,
++					     void *priv, struct gpio_chip *gc,
++					     int ngpio);
++
++#endif

target/linux/brcm63xx/patches-4.9/131-Documentation-add-BCM6328-pincontroller-binding-docu.patch

@@ -0,0 +1,78 @@
+From 4bdd40849632608d5cb7d3a64380cd76e7eea07b Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Wed, 27 Jul 2016 11:33:56 +0200
+Subject: [PATCH 02/16] Documentation: add BCM6328 pincontroller binding
+ documentation
+
+Add binding documentation for the pincontrol core found in BCM6328 SoCs.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ .../bindings/pinctrl/brcm,bcm6328-pinctrl.txt      | 61 ++++++++++++++++++++++
+ 1 file changed, 61 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.txt
+@@ -0,0 +1,61 @@
++* Broadcom BCM6328 pin controller
++
++Required properties:
++- compatible: Must be "brcm,bcm6328-pinctrl".
++- reg: Register specifies of dirout, dat, mode, mux registers.
++- reg-names: Must be "dirout", "dat", "mode", "mux".
++- gpio-controller: Identifies this node as a GPIO controller.
++- #gpio-cells: Must be <2>
++
++Example:
++
++pinctrl: pin-controller@10000080 {
++	compatible = "brcm,bcm6328-pinctrl";
++	reg = <0x10000080 0x8>,
++	      <0x10000088 0x8>,
++	      <0x10000098 0x4>,
++	      <0x1000009c 0xc>;
++	reg-names = "dirout", "dat", "mode", "mux";
++
++	gpio-controller;
++	#gpio-cells = <2>;
++};
++
++Available pins/groups and functions:
++
++name		pins	functions
++-----------------------------------------------------------
++gpio0		0	led
++gpio1		1	led
++gpio2		2	led
++gpio3		3	led
++gpio4		4	led
++gpio5		5	led
++gpio6		6	led, serial_led_data
++gpio7		7	led, serial_led_clk
++gpio8		8	led
++gpio9		9	led
++gpio10		10	led
++gpio11		11	led
++gpio12		12	led
++gpio13		13	led
++gpio14		14	led
++gpio15		15	led
++gpio16		16	led, pcie_clkreq
++gpio17		17	led
++gpio18		18	led
++gpio19		19	led
++gpio20		20	led
++gpio21		21	led
++gpio22		22	led
++gpio23		23	led
++gpio24		24	-
++gpio25		25	ephy0_act_led
++gpio26		26	ephy1_act_led
++gpio27		27	ephy2_act_led
++gpio28		28	ephy3_act_led
++gpio29		29	-
++gpio30		30	-
++gpio31		31	-
++hsspi_cs1	-	hsspi_cs1
++usb_port1	-	usb_host_port, usb_device_port

target/linux/brcm63xx/patches-4.9/132-pinctrl-add-a-pincontrol-driver-for-BCM6328.patch

@@ -0,0 +1,495 @@
+From 393e9753f6492c1fdf55891ddee60d955ae8b119 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Fri, 24 Jun 2016 22:12:50 +0200
+Subject: [PATCH 03/16] pinctrl: add a pincontrol driver for BCM6328
+
+Add a pincontrol driver for BCM6328. BCM628 supports muxing 32 pins as
+GPIOs, as LEDs for the integrated LED controller, or various other
+functions. Its pincontrol mux registers also control other aspects, like
+switching the second USB port between host and device mode.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/pinctrl/bcm63xx/Kconfig           |   7 +
+ drivers/pinctrl/bcm63xx/Makefile          |   1 +
+ drivers/pinctrl/bcm63xx/pinctrl-bcm6328.c | 456 ++++++++++++++++++++++++++++++
+ 3 files changed, 464 insertions(+)
+ create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm6328.c
+
+--- a/drivers/pinctrl/bcm63xx/Kconfig
++++ b/drivers/pinctrl/bcm63xx/Kconfig
+@@ -1,3 +1,10 @@
+ config PINCTRL_BCM63XX
+ 	bool
+ 	select GPIO_GENERIC
++
++config PINCTRL_BCM6328
++	bool "BCM6328 pincontrol driver" if COMPILE_TEST
++	select PINMUX
++	select PINCONF
++	select PINCTRL_BCM63XX
++	select GENERIC_PINCONF
+--- a/drivers/pinctrl/bcm63xx/Makefile
++++ b/drivers/pinctrl/bcm63xx/Makefile
+@@ -1 +1,2 @@
+ obj-$(CONFIG_PINCTRL_BCM63XX)	+= pinctrl-bcm63xx.o
++obj-$(CONFIG_PINCTRL_BCM6328)	+= pinctrl-bcm6328.o
+--- /dev/null
++++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm6328.c
+@@ -0,0 +1,456 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2016 Jonas Gorski <[email protected]>
++ */
++
++#include <linux/bitops.h>
++#include <linux/gpio.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++#include <linux/of.h>
++#include <linux/of_gpio.h>
++#include <linux/platform_device.h>
++
++#include <linux/pinctrl/machine.h>
++#include <linux/pinctrl/pinconf.h>
++#include <linux/pinctrl/pinconf-generic.h>
++#include <linux/pinctrl/pinmux.h>
++
++#include "../core.h"
++#include "../pinctrl-utils.h"
++
++#include "pinctrl-bcm63xx.h"
++
++#define BCM6328_MUX_LO_REG	0x4
++#define BCM6328_MUX_HI_REG	0x0
++#define BCM6328_MUX_OTHER_REG	0x8
++
++#define BCM6328_NGPIO		32
++
++struct bcm6328_pingroup {
++	const char *name;
++	const unsigned * const pins;
++	const unsigned num_pins;
++};
++
++struct bcm6328_function {
++	const char *name;
++	const char * const *groups;
++	const unsigned num_groups;
++
++	unsigned mode_val:1;
++	unsigned mux_val:2;
++};
++
++struct bcm6328_pinctrl {
++	struct pinctrl_dev *pctldev;
++	struct pinctrl_desc desc;
++
++	void __iomem *mode;
++	void __iomem *mux[3];
++
++	/* register access lock */
++	spinlock_t lock;
++
++	struct gpio_chip gpio;
++};
++
++static const struct pinctrl_pin_desc bcm6328_pins[] = {
++	PINCTRL_PIN(0, "gpio0"),
++	PINCTRL_PIN(1, "gpio1"),
++	PINCTRL_PIN(2, "gpio2"),
++	PINCTRL_PIN(3, "gpio3"),
++	PINCTRL_PIN(4, "gpio4"),
++	PINCTRL_PIN(5, "gpio5"),
++	PINCTRL_PIN(6, "gpio6"),
++	PINCTRL_PIN(7, "gpio7"),
++	PINCTRL_PIN(8, "gpio8"),
++	PINCTRL_PIN(9, "gpio9"),
++	PINCTRL_PIN(10, "gpio10"),
++	PINCTRL_PIN(11, "gpio11"),
++	PINCTRL_PIN(12, "gpio12"),
++	PINCTRL_PIN(13, "gpio13"),
++	PINCTRL_PIN(14, "gpio14"),
++	PINCTRL_PIN(15, "gpio15"),
++	PINCTRL_PIN(16, "gpio16"),
++	PINCTRL_PIN(17, "gpio17"),
++	PINCTRL_PIN(18, "gpio18"),
++	PINCTRL_PIN(19, "gpio19"),
++	PINCTRL_PIN(20, "gpio20"),
++	PINCTRL_PIN(21, "gpio21"),
++	PINCTRL_PIN(22, "gpio22"),
++	PINCTRL_PIN(23, "gpio23"),
++	PINCTRL_PIN(24, "gpio24"),
++	PINCTRL_PIN(25, "gpio25"),
++	PINCTRL_PIN(26, "gpio26"),
++	PINCTRL_PIN(27, "gpio27"),
++	PINCTRL_PIN(28, "gpio28"),
++	PINCTRL_PIN(29, "gpio29"),
++	PINCTRL_PIN(30, "gpio30"),
++	PINCTRL_PIN(31, "gpio31"),
++
++	/*
++	 * No idea where they really are; so let's put them according
++	 * to their mux offsets.
++	 */
++	PINCTRL_PIN(36, "hsspi_cs1"),
++	PINCTRL_PIN(38, "usb_p2"),
++};
++
++static unsigned gpio0_pins[] = { 0 };
++static unsigned gpio1_pins[] = { 1 };
++static unsigned gpio2_pins[] = { 2 };
++static unsigned gpio3_pins[] = { 3 };
++static unsigned gpio4_pins[] = { 4 };
++static unsigned gpio5_pins[] = { 5 };
++static unsigned gpio6_pins[] = { 6 };
++static unsigned gpio7_pins[] = { 7 };
++static unsigned gpio8_pins[] = { 8 };
++static unsigned gpio9_pins[] = { 9 };
++static unsigned gpio10_pins[] = { 10 };
++static unsigned gpio11_pins[] = { 11 };
++static unsigned gpio12_pins[] = { 12 };
++static unsigned gpio13_pins[] = { 13 };
++static unsigned gpio14_pins[] = { 14 };
++static unsigned gpio15_pins[] = { 15 };
++static unsigned gpio16_pins[] = { 16 };
++static unsigned gpio17_pins[] = { 17 };
++static unsigned gpio18_pins[] = { 18 };
++static unsigned gpio19_pins[] = { 19 };
++static unsigned gpio20_pins[] = { 20 };
++static unsigned gpio21_pins[] = { 21 };
++static unsigned gpio22_pins[] = { 22 };
++static unsigned gpio23_pins[] = { 23 };
++static unsigned gpio24_pins[] = { 24 };
++static unsigned gpio25_pins[] = { 25 };
++static unsigned gpio26_pins[] = { 26 };
++static unsigned gpio27_pins[] = { 27 };
++static unsigned gpio28_pins[] = { 28 };
++static unsigned gpio29_pins[] = { 29 };
++static unsigned gpio30_pins[] = { 30 };
++static unsigned gpio31_pins[] = { 31 };
++
++static unsigned hsspi_cs1_pins[] = { 36 };
++static unsigned usb_port1_pins[] = { 38 };
++
++#define BCM6328_GROUP(n)					\
++	{							\
++		.name = #n,					\
++		.pins = n##_pins,				\
++		.num_pins = ARRAY_SIZE(n##_pins),		\
++	}
++
++static struct bcm6328_pingroup bcm6328_groups[] = {
++	BCM6328_GROUP(gpio0),
++	BCM6328_GROUP(gpio1),
++	BCM6328_GROUP(gpio2),
++	BCM6328_GROUP(gpio3),
++	BCM6328_GROUP(gpio4),
++	BCM6328_GROUP(gpio5),
++	BCM6328_GROUP(gpio6),
++	BCM6328_GROUP(gpio7),
++	BCM6328_GROUP(gpio8),
++	BCM6328_GROUP(gpio9),
++	BCM6328_GROUP(gpio10),
++	BCM6328_GROUP(gpio11),
++	BCM6328_GROUP(gpio12),
++	BCM6328_GROUP(gpio13),
++	BCM6328_GROUP(gpio14),
++	BCM6328_GROUP(gpio15),
++	BCM6328_GROUP(gpio16),
++	BCM6328_GROUP(gpio17),
++	BCM6328_GROUP(gpio18),
++	BCM6328_GROUP(gpio19),
++	BCM6328_GROUP(gpio20),
++	BCM6328_GROUP(gpio21),
++	BCM6328_GROUP(gpio22),
++	BCM6328_GROUP(gpio23),
++	BCM6328_GROUP(gpio24),
++	BCM6328_GROUP(gpio25),
++	BCM6328_GROUP(gpio26),
++	BCM6328_GROUP(gpio27),
++	BCM6328_GROUP(gpio28),
++	BCM6328_GROUP(gpio29),
++	BCM6328_GROUP(gpio30),
++	BCM6328_GROUP(gpio31),
++
++	BCM6328_GROUP(hsspi_cs1),
++	BCM6328_GROUP(usb_port1),
++};
++
++/* GPIO_MODE */
++static const char * const led_groups[] = {
++	"gpio0",
++	"gpio1",
++	"gpio2",
++	"gpio3",
++	"gpio4",
++	"gpio5",
++	"gpio6",
++	"gpio7",
++	"gpio8",
++	"gpio9",
++	"gpio10",
++	"gpio11",
++	"gpio12",
++	"gpio13",
++	"gpio14",
++	"gpio15",
++	"gpio16",
++	"gpio17",
++	"gpio18",
++	"gpio19",
++	"gpio20",
++	"gpio21",
++	"gpio22",
++	"gpio23",
++};
++
++/* PINMUX_SEL */
++static const char * const serial_led_data_groups[] = {
++	"gpio6",
++};
++
++static const char * const serial_led_clk_groups[] = {
++	"gpio7",
++};
++
++static const char * const inet_act_led_groups[] = {
++	"gpio11",
++};
++
++static const char * const pcie_clkreq_groups[] = {
++	"gpio16",
++};
++
++static const char * const ephy0_act_led_groups[] = {
++	"gpio25",
++};
++
++static const char * const ephy1_act_led_groups[] = {
++	"gpio26",
++};
++
++static const char * const ephy2_act_led_groups[] = {
++	"gpio27",
++};
++
++static const char * const ephy3_act_led_groups[] = {
++	"gpio28",
++};
++
++static const char * const hsspi_cs1_groups[] = {
++	"hsspi_cs1"
++};
++
++static const char * const usb_host_port_groups[] = {
++	"usb_port1",
++};
++
++static const char * const usb_device_port_groups[] = {
++	"usb_port1",
++};
++
++#define BCM6328_MODE_FUN(n)				\
++	{						\
++		.name = #n,				\
++		.groups = n##_groups,			\
++		.num_groups = ARRAY_SIZE(n##_groups),	\
++		.mode_val = 1,				\
++	}
++
++#define BCM6328_MUX_FUN(n, mux)				\
++	{						\
++		.name = #n,				\
++		.groups = n##_groups,			\
++		.num_groups = ARRAY_SIZE(n##_groups),	\
++		.mux_val = mux,				\
++	}
++
++static const struct bcm6328_function bcm6328_funcs[] = {
++	BCM6328_MODE_FUN(led),
++	BCM6328_MUX_FUN(serial_led_data, 2),
++	BCM6328_MUX_FUN(serial_led_clk, 2),
++	BCM6328_MUX_FUN(inet_act_led, 1),
++	BCM6328_MUX_FUN(pcie_clkreq, 2),
++	BCM6328_MUX_FUN(ephy0_act_led, 1),
++	BCM6328_MUX_FUN(ephy1_act_led, 1),
++	BCM6328_MUX_FUN(ephy2_act_led, 1),
++	BCM6328_MUX_FUN(ephy3_act_led, 1),
++	BCM6328_MUX_FUN(hsspi_cs1, 2),
++	BCM6328_MUX_FUN(usb_host_port, 1),
++	BCM6328_MUX_FUN(usb_device_port, 2),
++};
++
++static int bcm6328_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
++{
++	return ARRAY_SIZE(bcm6328_groups);
++}
++
++static const char *bcm6328_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
++						  unsigned group)
++{
++	return bcm6328_groups[group].name;
++}
++
++static int bcm6328_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
++					  unsigned group, const unsigned **pins,
++					  unsigned *num_pins)
++{
++	*pins = bcm6328_groups[group].pins;
++	*num_pins = bcm6328_groups[group].num_pins;
++
++	return 0;
++}
++
++static int bcm6328_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
++{
++	return ARRAY_SIZE(bcm6328_funcs);
++}
++
++static const char *bcm6328_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
++						 unsigned selector)
++{
++	return bcm6328_funcs[selector].name;
++}
++
++static int bcm6328_pinctrl_get_groups(struct pinctrl_dev *pctldev,
++				      unsigned selector,
++				      const char * const **groups,
++				      unsigned * const num_groups)
++{
++	*groups = bcm6328_funcs[selector].groups;
++	*num_groups = bcm6328_funcs[selector].num_groups;
++
++	return 0;
++}
++
++static void bcm6328_rmw_mux(struct bcm6328_pinctrl *pctl, unsigned pin,
++			    u32 mode, u32 mux)
++{
++	unsigned long flags;
++	u32 reg;
++
++	spin_lock_irqsave(&pctl->lock, flags);
++	if (pin < 32) {
++		reg = __raw_readl(pctl->mode);
++		reg &= ~BIT(pin);
++		if (mode)
++			reg |= BIT(pin);
++		__raw_writel(reg, pctl->mode);
++	}
++
++	reg = __raw_readl(pctl->mux[pin / 16]);
++	reg &= ~(3UL << ((pin % 16) * 2));
++	reg |= mux << ((pin % 16) * 2);
++	__raw_writel(reg, pctl->mux[pin / 16]);
++
++	spin_unlock_irqrestore(&pctl->lock, flags);
++}
++
++static int bcm6328_pinctrl_set_mux(struct pinctrl_dev *pctldev,
++				   unsigned selector, unsigned group)
++{
++	struct bcm6328_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
++	const struct bcm6328_pingroup *grp = &bcm6328_groups[group];
++	const struct bcm6328_function *f = &bcm6328_funcs[selector];
++
++	bcm6328_rmw_mux(pctl, grp->pins[0], f->mode_val, f->mux_val);
++
++	return 0;
++}
++
++static int bcm6328_gpio_request_enable(struct pinctrl_dev *pctldev,
++				       struct pinctrl_gpio_range *range,
++				       unsigned offset)
++{
++	struct bcm6328_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
++
++	/* disable all functions using this pin */
++	bcm6328_rmw_mux(pctl, offset, 0, 0);
++
++	return 0;
++}
++
++static struct pinctrl_ops bcm6328_pctl_ops = {
++	.get_groups_count	= bcm6328_pinctrl_get_group_count,
++	.get_group_name		= bcm6328_pinctrl_get_group_name,
++	.get_group_pins		= bcm6328_pinctrl_get_group_pins,
++#ifdef CONFIG_OF
++	.dt_node_to_map		= pinconf_generic_dt_node_to_map_pin,
++	.dt_free_map		= pinctrl_utils_free_map,
++#endif
++};
++
++static struct pinmux_ops bcm6328_pmx_ops = {
++	.get_functions_count	= bcm6328_pinctrl_get_func_count,
++	.get_function_name	= bcm6328_pinctrl_get_func_name,
++	.get_function_groups	= bcm6328_pinctrl_get_groups,
++	.set_mux		= bcm6328_pinctrl_set_mux,
++	.gpio_request_enable	= bcm6328_gpio_request_enable,
++	.strict			= true,
++};
++
++static int bcm6328_pinctrl_probe(struct platform_device *pdev)
++{
++	struct bcm6328_pinctrl *pctl;
++	struct resource *res;
++	void __iomem *mode, *mux;
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mode");
++	mode = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(mode))
++		return PTR_ERR(mode);
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mux");
++	mux = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(mux))
++		return PTR_ERR(mux);
++
++	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
++	if (!pctl)
++		return -ENOMEM;
++
++	spin_lock_init(&pctl->lock);
++
++	pctl->mode = mode;
++	pctl->mux[0] = mux + BCM6328_MUX_LO_REG;
++	pctl->mux[1] = mux + BCM6328_MUX_HI_REG;
++	pctl->mux[2] = mux + BCM6328_MUX_OTHER_REG;
++
++	pctl->desc.name = dev_name(&pdev->dev);
++	pctl->desc.owner = THIS_MODULE;
++	pctl->desc.pctlops = &bcm6328_pctl_ops;
++	pctl->desc.pmxops = &bcm6328_pmx_ops;
++
++	pctl->desc.npins = ARRAY_SIZE(bcm6328_pins);
++	pctl->desc.pins = bcm6328_pins;
++
++	platform_set_drvdata(pdev, pctl);
++
++	pctl->pctldev = bcm63xx_pinctrl_register(pdev, &pctl->desc, pctl,
++						 &pctl->gpio, BCM6328_NGPIO);
++	if (IS_ERR(pctl->pctldev))
++		return PTR_ERR(pctl->pctldev);
++
++	return 0;
++}
++
++static const struct of_device_id bcm6328_pinctrl_match[] = {
++	{ .compatible = "brcm,bcm6328-pinctrl", },
++	{ },
++};
++
++static struct platform_driver bcm6328_pinctrl_driver = {
++	.probe = bcm6328_pinctrl_probe,
++	.driver = {
++		.name = "bcm6328-pinctrl",
++		.of_match_table = bcm6328_pinctrl_match,
++	},
++};
++
++builtin_platform_driver(bcm6328_pinctrl_driver);

target/linux/brcm63xx/patches-4.9/133-Documentation-add-BCM6348-pincontroller-binding-docu.patch

@@ -0,0 +1,49 @@
+From 962c46bf7f43df730e2d3698930e77958cc6b191 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Wed, 27 Jul 2016 11:35:45 +0200
+Subject: [PATCH 04/16] Documentation: add BCM6348 pincontroller binding
+ documentation
+
+Add binding documentation for the pincontrol core found in BCM6348 SoCs.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ .../bindings/pinctrl/brcm,bcm6348-pinctrl.txt      | 32 ++++++++++++++++++++++
+ 1 file changed, 32 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6348-pinctrl.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6348-pinctrl.txt
+@@ -0,0 +1,32 @@
++* Broadcom BCM6348 pin controller
++
++Required properties:
++- compatible: Must be "brcm,bcm6348-pinctrl".
++- reg: register Specifiers of dirout, dat, mode registers.
++- reg-names: Must be "dirout", "dat", "mode".
++- gpio-controller: Identifies this node as a GPIO controller.
++- #gpio-cells: Must be <2>.
++
++Example:
++
++pinctrl: pin-controller@fffe0080 {
++	compatible = "brcm,bcm6348-pinctrl";
++	reg = <0xfffe0080 0x8>,
++	      <0xfffe0088 0x8>,
++	      <0xfffe0098 0x4>;
++	reg-names = "dirout", "dat", "mode";
++
++	gpio-controller;
++	#gpio-cells = <2>;
++};
++
++Available pins/groups and functions:
++
++name		pins	functions
++-----------------------------------------------------------
++group0		32-36	ext_mii, utopia, diag
++group1		22-31	ext_ephy, mii_snoop, mii_pccard,
++			spi_master_uart, utopia, diag
++group2		16-21	pci, diag
++group3		8-15	ext_mii, utopia
++group4		0-7	ext_ephy, mii_snoop, legacy_led, diag

target/linux/brcm63xx/patches-4.9/134-pinctrl-add-a-pincontrol-driver-for-BCM6348.patch

@@ -0,0 +1,432 @@
+From 45444cb631555e2dc16b95d779b10aa075c7482e Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Fri, 24 Jun 2016 22:14:13 +0200
+Subject: [PATCH 05/16] pinctrl: add a pincontrol driver for BCM6348
+
+Add a pincotrol driver for BCM6348. BCM6348 allow muxing five groups of
+up to ten gpios into fourteen potential functions. It does not allow
+muxing individual pins. Some functions require more than one group to be
+muxed to the same function.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/pinctrl/bcm63xx/Kconfig           |   7 +
+ drivers/pinctrl/bcm63xx/Makefile          |   1 +
+ drivers/pinctrl/bcm63xx/pinctrl-bcm6348.c | 392 ++++++++++++++++++++++++++++++
+ 3 files changed, 400 insertions(+)
+ create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm6348.c
+
+--- a/drivers/pinctrl/bcm63xx/Kconfig
++++ b/drivers/pinctrl/bcm63xx/Kconfig
+@@ -8,3 +8,10 @@ config PINCTRL_BCM6328
+ 	select PINCONF
+ 	select PINCTRL_BCM63XX
+ 	select GENERIC_PINCONF
++
++config PINCTRL_BCM6348
++	bool "BCM6348 pincontrol driver" if COMPILE_TEST
++	select PINMUX
++	select PINCONF
++	select PINCTRL_BCM63XX
++	select GENERIC_PINCONF
+--- a/drivers/pinctrl/bcm63xx/Makefile
++++ b/drivers/pinctrl/bcm63xx/Makefile
+@@ -1,2 +1,3 @@
+ obj-$(CONFIG_PINCTRL_BCM63XX)	+= pinctrl-bcm63xx.o
+ obj-$(CONFIG_PINCTRL_BCM6328)	+= pinctrl-bcm6328.o
++obj-$(CONFIG_PINCTRL_BCM6348)	+= pinctrl-bcm6348.o
+--- /dev/null
++++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm6348.c
+@@ -0,0 +1,392 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2016 Jonas Gorski <[email protected]>
++ */
++
++#include <linux/kernel.h>
++#include <linux/spinlock.h>
++#include <linux/bitops.h>
++#include <linux/gpio.h>
++#include <linux/of.h>
++#include <linux/of_gpio.h>
++#include <linux/slab.h>
++#include <linux/platform_device.h>
++
++#include <linux/pinctrl/machine.h>
++#include <linux/pinctrl/pinconf.h>
++#include <linux/pinctrl/pinconf-generic.h>
++#include <linux/pinctrl/pinmux.h>
++
++#include "../core.h"
++#include "../pinctrl-utils.h"
++
++#include "pinctrl-bcm63xx.h"
++
++#define BCM6348_NGPIO		37
++
++#define MAX_GROUP		4
++#define PINS_PER_GROUP		8
++#define PIN_TO_GROUP(pin)	(MAX_GROUP - ((pin) / PINS_PER_GROUP))
++#define GROUP_SHIFT(pin)	(PIN_TO_GROUP(pin) * 4)
++#define GROUP_MASK(pin)		(0xf << GROUP_SHIFT(pin))
++
++struct bcm6348_pingroup {
++	const char *name;
++	const unsigned * const pins;
++	const unsigned num_pins;
++};
++
++struct bcm6348_function {
++	const char *name;
++	const char * const *groups;
++	const unsigned num_groups;
++	unsigned int value;
++};
++
++struct bcm6348_pinctrl {
++	struct pinctrl_dev *pctldev;
++	struct pinctrl_desc desc;
++
++	void __iomem *mode;
++
++	/* register access lock */
++	spinlock_t lock;
++
++	struct gpio_chip gpio[2];
++};
++
++#define BCM6348_PIN(a, b, group)		\
++	{					\
++		.number = a,			\
++		.name = b,			\
++		.drv_data = (void *)(group),	\
++	}
++
++static const struct pinctrl_pin_desc bcm6348_pins[] = {
++	BCM6348_PIN(0, "gpio0", 4),
++	BCM6348_PIN(1, "gpio1", 4),
++	BCM6348_PIN(2, "gpio2", 4),
++	BCM6348_PIN(3, "gpio3", 4),
++	BCM6348_PIN(4, "gpio4", 4),
++	BCM6348_PIN(5, "gpio5", 4),
++	BCM6348_PIN(6, "gpio6", 4),
++	BCM6348_PIN(7, "gpio7", 4),
++	BCM6348_PIN(8, "gpio8", 3),
++	BCM6348_PIN(9, "gpio9", 3),
++	BCM6348_PIN(10, "gpio10", 3),
++	BCM6348_PIN(11, "gpio11", 3),
++	BCM6348_PIN(12, "gpio12", 3),
++	BCM6348_PIN(13, "gpio13", 3),
++	BCM6348_PIN(14, "gpio14", 3),
++	BCM6348_PIN(15, "gpio15", 3),
++	BCM6348_PIN(16, "gpio16", 2),
++	BCM6348_PIN(17, "gpio17", 2),
++	BCM6348_PIN(18, "gpio18", 2),
++	BCM6348_PIN(19, "gpio19", 2),
++	BCM6348_PIN(20, "gpio20", 2),
++	BCM6348_PIN(21, "gpio21", 2),
++	BCM6348_PIN(22, "gpio22", 1),
++	BCM6348_PIN(23, "gpio23", 1),
++	BCM6348_PIN(24, "gpio24", 1),
++	BCM6348_PIN(25, "gpio25", 1),
++	BCM6348_PIN(26, "gpio26", 1),
++	BCM6348_PIN(27, "gpio27", 1),
++	BCM6348_PIN(28, "gpio28", 1),
++	BCM6348_PIN(29, "gpio29", 1),
++	BCM6348_PIN(30, "gpio30", 1),
++	BCM6348_PIN(31, "gpio31", 1),
++	BCM6348_PIN(32, "gpio32", 0),
++	BCM6348_PIN(33, "gpio33", 0),
++	BCM6348_PIN(34, "gpio34", 0),
++	BCM6348_PIN(35, "gpio35", 0),
++	BCM6348_PIN(36, "gpio36", 0),
++};
++
++enum bcm6348_muxes {
++	BCM6348_MUX_GPIO = 0,
++	BCM6348_MUX_EXT_EPHY,
++	BCM6348_MUX_MII_SNOOP,
++	BCM6348_MUX_LEGACY_LED,
++	BCM6348_MUX_MII_PCCARD,
++	BCM6348_MUX_PCI,
++	BCM6348_MUX_SPI_MASTER_UART,
++	BCM6348_MUX_EXT_MII,
++	BCM6348_MUX_UTOPIA,
++	BCM6348_MUX_DIAG,
++};
++
++static unsigned group0_pins[] = {
++	32, 33, 34, 35, 36,
++};
++
++static unsigned group1_pins[] = {
++	22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
++};
++
++static unsigned group2_pins[] = {
++	16, 17, 18, 19, 20, 21,
++};
++
++static unsigned group3_pins[] = {
++	8, 9, 10, 11, 12, 13, 14, 15,
++};
++
++static unsigned group4_pins[] = {
++	0, 1, 2, 3, 4, 5, 6, 7,
++};
++
++#define BCM6348_GROUP(n)				\
++	{						\
++		.name = #n,				\
++		.pins = n##_pins,			\
++		.num_pins = ARRAY_SIZE(n##_pins),	\
++	} \
++
++static struct bcm6348_pingroup bcm6348_groups[] = {
++	BCM6348_GROUP(group0),
++	BCM6348_GROUP(group1),
++	BCM6348_GROUP(group2),
++	BCM6348_GROUP(group3),
++	BCM6348_GROUP(group4),
++};
++
++static const char * const ext_mii_groups[] = {
++	"group0",
++	"group3",
++};
++
++static const char * const ext_ephy_groups[] = {
++	"group1",
++	"group4"
++};
++
++static const char * const mii_snoop_groups[] = {
++	"group1",
++	"group4",
++};
++
++static const char * const legacy_led_groups[] = {
++	"group4",
++};
++
++static const char * const mii_pccard_groups[] = {
++	"group1",
++};
++
++static const char * const pci_groups[] = {
++	"group2",
++};
++
++static const char * const spi_master_uart_groups[] = {
++	"group1",
++};
++
++static const char * const utopia_groups[] = {
++	"group0",
++	"group1",
++	"group3",
++};
++
++static const char * const diag_groups[] = {
++	"group0",
++	"group1",
++	"group2",
++	"group4",
++};
++
++#define BCM6348_FUN(n, f)				\
++	{						\
++		.name = #n,				\
++		.groups = n##_groups,			\
++		.num_groups = ARRAY_SIZE(n##_groups),	\
++		.value = BCM6348_MUX_##f,		\
++	}
++
++static const struct bcm6348_function bcm6348_funcs[] = {
++	BCM6348_FUN(ext_mii, EXT_MII),
++	BCM6348_FUN(ext_ephy, EXT_EPHY),
++	BCM6348_FUN(mii_snoop, MII_SNOOP),
++	BCM6348_FUN(legacy_led, LEGACY_LED),
++	BCM6348_FUN(mii_pccard, MII_PCCARD),
++	BCM6348_FUN(pci, PCI),
++	BCM6348_FUN(spi_master_uart, SPI_MASTER_UART),
++	BCM6348_FUN(utopia, UTOPIA),
++	BCM6348_FUN(diag, DIAG),
++};
++
++static int bcm6348_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
++{
++	return ARRAY_SIZE(bcm6348_groups);
++}
++
++static const char *bcm6348_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
++						  unsigned group)
++{
++	return bcm6348_groups[group].name;
++}
++
++static int bcm6348_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
++					  unsigned group, const unsigned **pins,
++					  unsigned *num_pins)
++{
++	*pins = bcm6348_groups[group].pins;
++	*num_pins = bcm6348_groups[group].num_pins;
++
++	return 0;
++}
++
++static int bcm6348_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
++{
++	return ARRAY_SIZE(bcm6348_funcs);
++}
++
++static const char *bcm6348_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
++						 unsigned selector)
++{
++	return bcm6348_funcs[selector].name;
++}
++
++static int bcm6348_pinctrl_get_groups(struct pinctrl_dev *pctldev,
++				      unsigned selector,
++				      const char * const **groups,
++				      unsigned * const num_groups)
++{
++	*groups = bcm6348_funcs[selector].groups;
++	*num_groups = bcm6348_funcs[selector].num_groups;
++
++	return 0;
++}
++
++static void bcm6348_rmw_mux(struct bcm6348_pinctrl *pctl, u32 mask, u32 val)
++{
++	unsigned long flags;
++	u32 reg;
++
++	spin_lock_irqsave(&pctl->lock, flags);
++
++	reg = __raw_readl(pctl->mode);
++	reg &= ~mask;
++	reg |= val & mask;
++	__raw_writel(reg, pctl->mode);
++
++	spin_unlock_irqrestore(&pctl->lock, flags);
++}
++
++static int bcm6348_pinctrl_set_mux(struct pinctrl_dev *pctldev,
++				   unsigned selector, unsigned group)
++{
++	struct bcm6348_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
++	const struct bcm6348_pingroup *grp = &bcm6348_groups[group];
++	const struct bcm6348_function *f = &bcm6348_funcs[selector];
++	u32 group_num, mask, val;
++
++	/*
++	 * pins n..(n+7) share the same group, so we only need to look at
++	 * the first pin.
++	 */
++	group_num = (unsigned long)bcm6348_pins[grp->pins[0]].drv_data;
++	mask = GROUP_MASK(group_num);
++	val = f->value << GROUP_SHIFT(group_num);
++
++	bcm6348_rmw_mux(pctl, mask, val);
++
++	return 0;
++}
++
++static int bcm6348_gpio_request_enable(struct pinctrl_dev *pctldev,
++				       struct pinctrl_gpio_range *range,
++				       unsigned offset)
++{
++	struct bcm6348_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
++	struct pin_desc *desc;
++	u32 mask;
++
++	/* don't reconfigure if already muxed */
++	desc = pin_desc_get(pctldev, offset);
++	if (desc->mux_usecount)
++		return 0;
++
++	mask = GROUP_MASK(offset);
++
++	/* disable all functions using this pin */
++	bcm6348_rmw_mux(pctl, mask, 0);
++
++	return 0;
++}
++
++static struct pinctrl_ops bcm6348_pctl_ops = {
++	.get_groups_count	= bcm6348_pinctrl_get_group_count,
++	.get_group_name		= bcm6348_pinctrl_get_group_name,
++	.get_group_pins		= bcm6348_pinctrl_get_group_pins,
++#ifdef CONFIG_OF
++	.dt_node_to_map		= pinconf_generic_dt_node_to_map_pin,
++	.dt_free_map		= pinctrl_utils_free_map,
++#endif
++};
++
++static struct pinmux_ops bcm6348_pmx_ops = {
++	.get_functions_count	= bcm6348_pinctrl_get_func_count,
++	.get_function_name	= bcm6348_pinctrl_get_func_name,
++	.get_function_groups	= bcm6348_pinctrl_get_groups,
++	.set_mux		= bcm6348_pinctrl_set_mux,
++	.gpio_request_enable	= bcm6348_gpio_request_enable,
++	.strict			= true,
++};
++
++static int bcm6348_pinctrl_probe(struct platform_device *pdev)
++{
++	struct bcm6348_pinctrl *pctl;
++	struct resource *res;
++	void __iomem *mode;
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mode");
++	mode = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(mode))
++		return PTR_ERR(mode);
++
++	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
++	if (!pctl)
++		return -ENOMEM;
++
++	spin_lock_init(&pctl->lock);
++
++	pctl->mode = mode;
++
++	/* disable all muxes by default */
++	__raw_writel(0, pctl->mode);
++
++	pctl->desc.name = dev_name(&pdev->dev);
++	pctl->desc.owner = THIS_MODULE;
++	pctl->desc.pctlops = &bcm6348_pctl_ops;
++	pctl->desc.pmxops = &bcm6348_pmx_ops;
++
++	pctl->desc.npins = ARRAY_SIZE(bcm6348_pins);
++	pctl->desc.pins = bcm6348_pins;
++
++	platform_set_drvdata(pdev, pctl);
++
++	pctl->pctldev = bcm63xx_pinctrl_register(pdev, &pctl->desc, pctl,
++						 pctl->gpio, BCM6348_NGPIO);
++	if (IS_ERR(pctl->pctldev))
++		return PTR_ERR(pctl->pctldev);
++
++	return 0;
++}
++
++static const struct of_device_id bcm6348_pinctrl_match[] = {
++	{ .compatible = "brcm,bcm6348-pinctrl", },
++	{ },
++};
++
++static struct platform_driver bcm6348_pinctrl_driver = {
++	.probe = bcm6348_pinctrl_probe,
++	.driver = {
++		.name = "bcm6348-pinctrl",
++		.of_match_table = bcm6348_pinctrl_match,
++	},
++};
++
++builtin_platform_driver(bcm6348_pinctrl_driver);

target/linux/brcm63xx/patches-4.9/135-Documentation-add-BCM6358-pincontroller-binding-docu.patch

@@ -0,0 +1,61 @@
+From c7c8fa7f5b5ee9bea751fa7bdae8ff4acde8f26e Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Wed, 27 Jul 2016 11:36:00 +0200
+Subject: [PATCH 06/16] Documentation: add BCM6358 pincontroller binding
+ documentation
+
+Add binding documentation for the pincontrol core found in BCM6358 SoCs.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ .../bindings/pinctrl/brcm,bcm6358-pinctrl.txt      | 44 ++++++++++++++++++++++
+ 1 file changed, 44 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.txt
+@@ -0,0 +1,44 @@
++* Broadcom BCM6358 pin controller
++
++Required properties:
++- compatible: Must be "brcm,bcm6358-pinctrl".
++- reg: Register specifiers of dirout, dat registers.
++- reg-names: Must be "dirout", "dat".
++- brcm,gpiomode: Phandle to the shared gpiomode register.
++- gpio-controller: Identifies this node as a gpio-controller.
++- #gpio-cells: Must be <2>.
++
++Example:
++
++pinctrl: pin-controller@fffe0080 {
++	compatible = "brcm,bcm6358-pinctrl";
++	reg = <0xfffe0080 0x8>,
++	      <0xfffe0088 0x8>,
++	      <0xfffe0098 0x4>;
++	reg-names = "dirout", "dat";
++	brcm,gpiomode = <&gpiomode>;
++
++	gpio-controller;
++	#gpio-cells = <2>;
++};
++
++gpiomode: syscon@fffe0098 {
++	compatible = "brcm,bcm6358-gpiomode", "syscon";
++	reg = <0xfffe0098 0x4>;
++	native-endian;
++};
++
++Available pins/groups and functions:
++
++name		pins		functions
++-----------------------------------------------------------
++ebi_cs_grp	30-31		ebi_cs
++uart1_grp	28-31		uart1
++spi_cs_grp	32-33		spi_cs
++async_modem_grp	12-15		async_modem
++legacy_led_grp	9-15		legacy_led
++serial_led_grp	6-7		serial_led
++led_grp		0-3		led
++utopia_grp	12-15, 22-31	utopia
++pwm_syn_clk_grp	8		pwm_syn_clk
++sys_irq_grp	5		sys_irq

target/linux/brcm63xx/patches-4.9/136-pinctrl-add-a-pincontrol-driver-for-BCM6358.patch

@@ -0,0 +1,436 @@
+From fb00ef462f3f8b70ea8902151cc72810fe90b999 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Fri, 24 Jun 2016 22:16:01 +0200
+Subject: [PATCH 07/16] pinctrl: add a pincontrol driver for BCM6358
+
+Add a pincotrol driver for BCM6358. BCM6358 allow overlaying different
+functions onto the GPIO pins. It does not support configuring individual
+pins but only whole groups. These groups may overlap, and still require
+the directions to be set correctly in the GPIO register. In addition the
+functions register controls other, not directly mux related functions.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/pinctrl/bcm63xx/Kconfig           |   8 +
+ drivers/pinctrl/bcm63xx/Makefile          |   1 +
+ drivers/pinctrl/bcm63xx/pinctrl-bcm6358.c | 393 ++++++++++++++++++++++++++++++
+ 3 files changed, 402 insertions(+)
+ create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm6358.c
+
+--- a/drivers/pinctrl/bcm63xx/Kconfig
++++ b/drivers/pinctrl/bcm63xx/Kconfig
+@@ -15,3 +15,11 @@ config PINCTRL_BCM6348
+ 	select PINCONF
+ 	select PINCTRL_BCM63XX
+ 	select GENERIC_PINCONF
++
++config PINCTRL_BCM6358
++	bool "BCM6358 pincontrol driver" if COMPILE_TEST
++	select PINMUX
++	select PINCONF
++	select PINCTRL_BCM63XX
++	select GENERIC_PINCONF
++	select MFD_SYSCON
+--- a/drivers/pinctrl/bcm63xx/Makefile
++++ b/drivers/pinctrl/bcm63xx/Makefile
+@@ -1,3 +1,4 @@
+ obj-$(CONFIG_PINCTRL_BCM63XX)	+= pinctrl-bcm63xx.o
+ obj-$(CONFIG_PINCTRL_BCM6328)	+= pinctrl-bcm6328.o
+ obj-$(CONFIG_PINCTRL_BCM6348)	+= pinctrl-bcm6348.o
++obj-$(CONFIG_PINCTRL_BCM6358)	+= pinctrl-bcm6358.o
+--- /dev/null
++++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm6358.c
+@@ -0,0 +1,393 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2016 Jonas Gorski <[email protected]>
++ */
++
++#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/gpio.h>
++#include <linux/gpio/driver.h>
++#include <linux/mfd/syscon.h>
++#include <linux/of.h>
++#include <linux/of_gpio.h>
++#include <linux/of_address.h>
++#include <linux/slab.h>
++#include <linux/regmap.h>
++#include <linux/platform_device.h>
++
++#include <linux/pinctrl/pinconf.h>
++#include <linux/pinctrl/pinconf-generic.h>
++#include <linux/pinctrl/pinmux.h>
++#include <linux/pinctrl/machine.h>
++
++#include "../core.h"
++#include "../pinctrl-utils.h"
++
++#include "pinctrl-bcm63xx.h"
++
++/* GPIO_MODE register */
++#define BCM6358_MODE_MUX_NONE		0
++
++/* overlays on gpio pins */
++#define BCM6358_MODE_MUX_EBI_CS		BIT(5)
++#define BCM6358_MODE_MUX_UART1		BIT(6)
++#define BCM6358_MODE_MUX_SPI_CS		BIT(7)
++#define BCM6358_MODE_MUX_ASYNC_MODEM	BIT(8)
++#define BCM6358_MODE_MUX_LEGACY_LED	BIT(9)
++#define BCM6358_MODE_MUX_SERIAL_LED	BIT(10)
++#define BCM6358_MODE_MUX_LED		BIT(11)
++#define BCM6358_MODE_MUX_UTOPIA		BIT(12)
++#define BCM6358_MODE_MUX_CLKRST		BIT(13)
++#define BCM6358_MODE_MUX_PWM_SYN_CLK	BIT(14)
++#define BCM6358_MODE_MUX_SYS_IRQ	BIT(15)
++
++#define BCM6358_NGPIO			40
++
++struct bcm6358_pingroup {
++	const char *name;
++	const unsigned * const pins;
++	const unsigned num_pins;
++
++	const u16 mode_val;
++
++	/* non-GPIO function muxes require the gpio direction to be set */
++	const u16 direction;
++};
++
++struct bcm6358_function {
++	const char *name;
++	const char * const *groups;
++	const unsigned num_groups;
++};
++
++struct bcm6358_pinctrl {
++	struct device *dev;
++	struct pinctrl_dev *pctldev;
++	struct pinctrl_desc desc;
++
++	struct regmap_field *overlays;
++
++	struct gpio_chip gpio[2];
++};
++
++#define BCM6358_GPIO_PIN(a, b, bit1, bit2, bit3)		\
++	{							\
++		.number = a,					\
++		.name = b,					\
++		.drv_data = (void *)(BCM6358_MODE_MUX_##bit1 |	\
++				     BCM6358_MODE_MUX_##bit2 |	\
++				     BCM6358_MODE_MUX_##bit3),	\
++	}
++
++static const struct pinctrl_pin_desc bcm6358_pins[] = {
++	BCM6358_GPIO_PIN(0, "gpio0", LED, NONE, NONE),
++	BCM6358_GPIO_PIN(1, "gpio1", LED, NONE, NONE),
++	BCM6358_GPIO_PIN(2, "gpio2", LED, NONE, NONE),
++	BCM6358_GPIO_PIN(3, "gpio3", LED, NONE, NONE),
++	PINCTRL_PIN(4, "gpio4"),
++	BCM6358_GPIO_PIN(5, "gpio5", SYS_IRQ, NONE, NONE),
++	BCM6358_GPIO_PIN(6, "gpio6", SERIAL_LED, NONE, NONE),
++	BCM6358_GPIO_PIN(7, "gpio7", SERIAL_LED, NONE, NONE),
++	BCM6358_GPIO_PIN(8, "gpio8", PWM_SYN_CLK, NONE, NONE),
++	BCM6358_GPIO_PIN(9, "gpio09", LEGACY_LED, NONE, NONE),
++	BCM6358_GPIO_PIN(10, "gpio10", LEGACY_LED, NONE, NONE),
++	BCM6358_GPIO_PIN(11, "gpio11", LEGACY_LED, NONE, NONE),
++	BCM6358_GPIO_PIN(12, "gpio12", LEGACY_LED, ASYNC_MODEM, UTOPIA),
++	BCM6358_GPIO_PIN(13, "gpio13", LEGACY_LED, ASYNC_MODEM, UTOPIA),
++	BCM6358_GPIO_PIN(14, "gpio14", LEGACY_LED, ASYNC_MODEM, UTOPIA),
++	BCM6358_GPIO_PIN(15, "gpio15", LEGACY_LED, ASYNC_MODEM, UTOPIA),
++	PINCTRL_PIN(16, "gpio16"),
++	PINCTRL_PIN(17, "gpio17"),
++	PINCTRL_PIN(18, "gpio18"),
++	PINCTRL_PIN(19, "gpio19"),
++	PINCTRL_PIN(20, "gpio20"),
++	PINCTRL_PIN(21, "gpio21"),
++	BCM6358_GPIO_PIN(22, "gpio22", UTOPIA, NONE, NONE),
++	BCM6358_GPIO_PIN(23, "gpio23", UTOPIA, NONE, NONE),
++	BCM6358_GPIO_PIN(24, "gpio24", UTOPIA, NONE, NONE),
++	BCM6358_GPIO_PIN(25, "gpio25", UTOPIA, NONE, NONE),
++	BCM6358_GPIO_PIN(26, "gpio26", UTOPIA, NONE, NONE),
++	BCM6358_GPIO_PIN(27, "gpio27", UTOPIA, NONE, NONE),
++	BCM6358_GPIO_PIN(28, "gpio28", UTOPIA, UART1, NONE),
++	BCM6358_GPIO_PIN(29, "gpio29", UTOPIA, UART1, NONE),
++	BCM6358_GPIO_PIN(30, "gpio30", UTOPIA, UART1, EBI_CS),
++	BCM6358_GPIO_PIN(31, "gpio31", UTOPIA, UART1, EBI_CS),
++	BCM6358_GPIO_PIN(32, "gpio32", SPI_CS, NONE, NONE),
++	BCM6358_GPIO_PIN(33, "gpio33", SPI_CS, NONE, NONE),
++	PINCTRL_PIN(34, "gpio34"),
++	PINCTRL_PIN(35, "gpio35"),
++	PINCTRL_PIN(36, "gpio36"),
++	PINCTRL_PIN(37, "gpio37"),
++	PINCTRL_PIN(38, "gpio38"),
++	PINCTRL_PIN(39, "gpio39"),
++};
++
++static unsigned ebi_cs_grp_pins[] = { 30, 31 };
++
++static unsigned uart1_grp_pins[] = { 28, 29, 30, 31 };
++
++static unsigned spi_cs_grp_pins[] = { 32, 33 };
++
++static unsigned async_modem_grp_pins[] = { 12, 13, 14, 15 };
++
++static unsigned serial_led_grp_pins[] = { 6, 7 };
++
++static unsigned legacy_led_grp_pins[] = { 9, 10, 11, 12, 13, 14, 15 };
++
++static unsigned led_grp_pins[] = { 0, 1, 2, 3 };
++
++static unsigned utopia_grp_pins[] = {
++	12, 13, 14, 15, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
++};
++
++static unsigned pwm_syn_clk_grp_pins[] = { 8 };
++
++static unsigned sys_irq_grp_pins[] = { 5 };
++
++#define BCM6358_GPIO_MUX_GROUP(n, bit, dir)			\
++	{							\
++		.name = #n,					\
++		.pins = n##_pins,				\
++		.num_pins = ARRAY_SIZE(n##_pins),		\
++		.mode_val = BCM6358_MODE_MUX_##bit,		\
++		.direction = dir,				\
++	}
++
++static const struct bcm6358_pingroup bcm6358_groups[] = {
++	BCM6358_GPIO_MUX_GROUP(ebi_cs_grp, EBI_CS, 0x3),
++	BCM6358_GPIO_MUX_GROUP(uart1_grp, UART1, 0x2),
++	BCM6358_GPIO_MUX_GROUP(spi_cs_grp, SPI_CS, 0x6),
++	BCM6358_GPIO_MUX_GROUP(async_modem_grp, ASYNC_MODEM, 0x6),
++	BCM6358_GPIO_MUX_GROUP(legacy_led_grp, LEGACY_LED, 0x7f),
++	BCM6358_GPIO_MUX_GROUP(serial_led_grp, SERIAL_LED, 0x3),
++	BCM6358_GPIO_MUX_GROUP(led_grp, LED, 0xf),
++	BCM6358_GPIO_MUX_GROUP(utopia_grp, UTOPIA, 0x000f),
++	BCM6358_GPIO_MUX_GROUP(pwm_syn_clk_grp, PWM_SYN_CLK, 0x1),
++	BCM6358_GPIO_MUX_GROUP(sys_irq_grp, SYS_IRQ, 0x1),
++};
++
++static const char * const ebi_cs_groups[] = {
++	"ebi_cs_grp"
++};
++
++static const char * const uart1_groups[] = {
++	"uart1_grp"
++};
++
++static const char * const spi_cs_2_3_groups[] = {
++	"spi_cs_2_3_grp"
++};
++
++static const char * const async_modem_groups[] = {
++	"async_modem_grp"
++};
++
++static const char * const legacy_led_groups[] = {
++	"legacy_led_grp",
++};
++
++static const char * const serial_led_groups[] = {
++	"serial_led_grp",
++};
++
++static const char * const led_groups[] = {
++	"led_grp",
++};
++
++static const char * const clkrst_groups[] = {
++	"clkrst_grp",
++};
++
++static const char * const pwm_syn_clk_groups[] = {
++	"pwm_syn_clk_grp",
++};
++
++static const char * const sys_irq_groups[] = {
++	"sys_irq_grp",
++};
++
++#define BCM6358_FUN(n)					\
++	{						\
++		.name = #n,				\
++		.groups = n##_groups,			\
++		.num_groups = ARRAY_SIZE(n##_groups),	\
++	}
++
++static const struct bcm6358_function bcm6358_funcs[] = {
++	BCM6358_FUN(ebi_cs),
++	BCM6358_FUN(uart1),
++	BCM6358_FUN(spi_cs_2_3),
++	BCM6358_FUN(async_modem),
++	BCM6358_FUN(legacy_led),
++	BCM6358_FUN(serial_led),
++	BCM6358_FUN(led),
++	BCM6358_FUN(clkrst),
++	BCM6358_FUN(pwm_syn_clk),
++	BCM6358_FUN(sys_irq),
++};
++
++static int bcm6358_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
++{
++	return ARRAY_SIZE(bcm6358_groups);
++}
++
++static const char *bcm6358_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
++						  unsigned group)
++{
++	return bcm6358_groups[group].name;
++}
++
++static int bcm6358_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
++					  unsigned group, const unsigned **pins,
++					  unsigned *num_pins)
++{
++	*pins = bcm6358_groups[group].pins;
++	*num_pins = bcm6358_groups[group].num_pins;
++
++	return 0;
++}
++
++static int bcm6358_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
++{
++	return ARRAY_SIZE(bcm6358_funcs);
++}
++
++static const char *bcm6358_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
++						 unsigned selector)
++{
++	return bcm6358_funcs[selector].name;
++}
++
++static int bcm6358_pinctrl_get_groups(struct pinctrl_dev *pctldev,
++				      unsigned selector,
++				      const char * const **groups,
++				      unsigned * const num_groups)
++{
++	*groups = bcm6358_funcs[selector].groups;
++	*num_groups = bcm6358_funcs[selector].num_groups;
++
++	return 0;
++}
++
++static int bcm6358_pinctrl_set_mux(struct pinctrl_dev *pctldev,
++				   unsigned selector, unsigned group)
++{
++	struct bcm6358_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
++	const struct bcm6358_pingroup *grp = &bcm6358_groups[group];
++	u32 val = grp->mode_val;
++	u32 mask = val;
++	unsigned pin;
++
++	for (pin = 0; pin < grp->num_pins; pin++)
++		mask |= (unsigned long)bcm6358_pins[pin].drv_data;
++
++	regmap_field_update_bits(pctl->overlays, mask, val);
++
++	for (pin = 0; pin < grp->num_pins; pin++) {
++		int hw_gpio = bcm6358_pins[pin].number;
++		struct gpio_chip *gc = &pctl->gpio[hw_gpio / 32];
++
++		if (grp->direction & BIT(pin))
++			gc->direction_output(gc, hw_gpio % 32, 0);
++		else
++			gc->direction_input(gc, hw_gpio % 32);
++	}
++
++	return 0;
++}
++
++static int bcm6358_gpio_request_enable(struct pinctrl_dev *pctldev,
++				       struct pinctrl_gpio_range *range,
++				       unsigned offset)
++{
++	struct bcm6358_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
++	u32 mask;
++
++	mask = (unsigned long)bcm6358_pins[offset].drv_data;
++	if (!mask)
++		return 0;
++
++	/* disable all functions using this pin */
++	return regmap_field_update_bits(pctl->overlays, mask, 0);
++}
++
++static struct pinctrl_ops bcm6358_pctl_ops = {
++	.get_groups_count	= bcm6358_pinctrl_get_group_count,
++	.get_group_name		= bcm6358_pinctrl_get_group_name,
++	.get_group_pins		= bcm6358_pinctrl_get_group_pins,
++#ifdef CONFIG_OF
++	.dt_node_to_map		= pinconf_generic_dt_node_to_map_pin,
++	.dt_free_map		= pinctrl_utils_free_map,
++#endif
++};
++
++static struct pinmux_ops bcm6358_pmx_ops = {
++	.get_functions_count	= bcm6358_pinctrl_get_func_count,
++	.get_function_name	= bcm6358_pinctrl_get_func_name,
++	.get_function_groups	= bcm6358_pinctrl_get_groups,
++	.set_mux		= bcm6358_pinctrl_set_mux,
++	.gpio_request_enable	= bcm6358_gpio_request_enable,
++	.strict			= true,
++};
++
++static int bcm6358_pinctrl_probe(struct platform_device *pdev)
++{
++	struct bcm6358_pinctrl *pctl;
++	struct regmap *mode;
++	struct reg_field overlays = REG_FIELD(0, 0, 15);
++
++	if (pdev->dev.of_node)
++		mode = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
++						       "brcm,gpiomode");
++	else
++		mode = syscon_regmap_lookup_by_pdevname("syscon.fffe0098");
++
++	if (IS_ERR(mode))
++		return PTR_ERR(mode);
++
++	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
++	if (!pctl)
++		return -ENOMEM;
++
++	pctl->overlays = devm_regmap_field_alloc(&pdev->dev, mode, overlays);
++	if (IS_ERR(pctl->overlays))
++		return PTR_ERR(pctl->overlays);
++
++	/* disable all muxes by default */
++	regmap_field_write(pctl->overlays, 0);
++
++	pctl->desc.name = dev_name(&pdev->dev);
++	pctl->desc.owner = THIS_MODULE;
++	pctl->desc.pctlops = &bcm6358_pctl_ops;
++	pctl->desc.pmxops = &bcm6358_pmx_ops;
++
++	pctl->desc.npins = ARRAY_SIZE(bcm6358_pins);
++	pctl->desc.pins = bcm6358_pins;
++
++	platform_set_drvdata(pdev, pctl);
++
++	pctl->pctldev = bcm63xx_pinctrl_register(pdev, &pctl->desc, pctl,
++						 pctl->gpio, BCM6358_NGPIO);
++	if (IS_ERR(pctl->pctldev))
++		return PTR_ERR(pctl->pctldev);
++
++	return 0;
++}
++
++static const struct of_device_id bcm6358_pinctrl_match[] = {
++	{ .compatible = "brcm,bcm6358-pinctrl", },
++	{ },
++};
++
++static struct platform_driver bcm6358_pinctrl_driver = {
++	.probe = bcm6358_pinctrl_probe,
++	.driver = {
++		.name = "bcm6358-pinctrl",
++		.of_match_table = bcm6358_pinctrl_match,
++	},
++};
++
++builtin_platform_driver(bcm6358_pinctrl_driver);

target/linux/brcm63xx/patches-4.9/137-Documentation-add-BCM6362-pincontroller-binding-docu.patch

@@ -0,0 +1,96 @@
+From ba03ea8ada2ca71c9095d96a1e4085c2c5cf0e69 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Wed, 27 Jul 2016 11:36:18 +0200
+Subject: [PATCH 08/16] Documentation: add BCM6362 pincontroller binding
+ documentation
+
+Add binding documentation for the pincontrol core found in BCM6362 SoCs.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ .../bindings/pinctrl/brcm,bcm6362-pinctrl.txt      | 79 ++++++++++++++++++++++
+ 1 file changed, 79 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.txt
+@@ -0,0 +1,79 @@
++* Broadcom BCM6362 pin controller
++
++Required properties:
++- compatible: Must be "brcm,bcm6362-pinctrl"
++- reg: Register specifiers of dirout, dat, led, mode, ctrl, basemode registers.
++- reg-names: Must be "dirout", "dat", "led", "mode", "ctrl", "basemode".
++- gpio-controller: Identifies this node as a GPIO controller.
++- #gpio-cells: Must be <2>.
++
++Example:
++
++pinctrl: pin-controller@10000080 {
++	compatible = "brcm,bcm6362-pinctrl";
++	reg = <0x10000080 0x8>,
++	      <0x10000088 0x8>,
++	      <0x10000090 0x4>,
++	      <0x10000098 0x4>,
++	      <0x1000009c 0x4>,
++	      <0x100000b8 0x4>;
++	reg-names = "dirout", "dat", "led",
++		    "mode", "ctrl", "basemode";
++
++	gpio-controller;
++	#gpio-cells = <2>;
++};
++
++Available pins/groups and functions:
++
++name		pins		functions
++-----------------------------------------------------------
++gpio0		0		led, usb_device_led
++gpio1		1		led, sys_irq
++gpio2		2		led, serial_led_clk
++gpio3		3		led, serial_led_data
++gpio4		4		led, robosw_led_data
++gpio5		5		led, robosw_led_clk
++gpio6		6		led, robosw_led0
++gpio7		7		led, robosw_led1
++gpio8		8		led, inet_led
++gpio9		9		led, spi_cs2
++gpio10		10		led, spi_cs3
++gpio11		11		led, ntr_pulse
++gpio12		12		led, uart1_scts
++gpio13		13		led, uart1_srts
++gpio14		14		led, uart1_sdin
++gpio15		15		led, uart1_sdout
++gpio16		16		led, adsl_spi_miso
++gpio17		17		led, adsl_spi_mosi
++gpio18		18		led, adsl_spi_clk
++gpio19		19		led, adsl_spi_cs
++gpio20		20		led, ephy0_led
++gpio21		21		led, ephy1_led
++gpio22		22		led, ephy2_led
++gpio23		23		led, ephy3_led
++gpio24		24		ext_irq0
++gpio25		25		ext_irq1
++gpio26		26		ext_irq2
++gpio27		27		ext_irq3
++gpio28		28		-
++gpio29		29		-
++gpio30		30		-
++gpio31		31		-
++gpio32		32		wifi
++gpio33		33		wifi
++gpio34		34		wifi
++gpio35		35		wifi
++gpio36		36		wifi
++gpio37		37		wifi
++gpio38		38		wifi
++gpio39		39		wifi
++gpio40		40		wifi
++gpio41		41		wifi
++gpio42		42		wifi
++gpio43		43		wifi
++gpio44		44		wifi
++gpio45		45		wifi
++gpio46		46		wifi
++gpio47		47		wifi
++nand_grp	8, 12-23, 27	nand

target/linux/brcm63xx/patches-4.9/138-pinctrl-add-a-pincontrol-driver-for-BCM6362.patch

@@ -0,0 +1,733 @@
+From eea6b96701d734095e2f823f3a82d9b063f553ae Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Fri, 24 Jun 2016 22:17:20 +0200
+Subject: [PATCH 09/16] pinctrl: add a pincontrol driver for BCM6362
+
+Add a pincotrol driver for BCM6362. BCM6362 allows muxing individual
+GPIO pins to the LED controller, to be available by the integrated
+wifi, or other functions. It also supports overlay groups, of which
+only NAND is documented.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/pinctrl/bcm63xx/Kconfig           |   7 +
+ drivers/pinctrl/bcm63xx/Makefile          |   1 +
+ drivers/pinctrl/bcm63xx/pinctrl-bcm6362.c | 692 ++++++++++++++++++++++++++++++
+ 3 files changed, 700 insertions(+)
+ create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm6362.c
+
+--- a/drivers/pinctrl/bcm63xx/Kconfig
++++ b/drivers/pinctrl/bcm63xx/Kconfig
+@@ -23,3 +23,10 @@ config PINCTRL_BCM6358
+ 	select PINCTRL_BCM63XX
+ 	select GENERIC_PINCONF
+ 	select MFD_SYSCON
++
++config PINCTRL_BCM6362
++	bool "BCM6362 pincontrol driver" if COMPILE_TEST
++	select PINMUX
++	select PINCONF
++	select PINCTRL_BCM63XX
++	select GENERIC_PINCONF
+--- a/drivers/pinctrl/bcm63xx/Makefile
++++ b/drivers/pinctrl/bcm63xx/Makefile
+@@ -2,3 +2,4 @@ obj-$(CONFIG_PINCTRL_BCM63XX)	+= pinctrl
+ obj-$(CONFIG_PINCTRL_BCM6328)	+= pinctrl-bcm6328.o
+ obj-$(CONFIG_PINCTRL_BCM6348)	+= pinctrl-bcm6348.o
+ obj-$(CONFIG_PINCTRL_BCM6358)	+= pinctrl-bcm6358.o
++obj-$(CONFIG_PINCTRL_BCM6362)	+= pinctrl-bcm6362.o
+--- /dev/null
++++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm6362.c
+@@ -0,0 +1,692 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2016 Jonas Gorski <[email protected]>
++ */
++
++#include <linux/kernel.h>
++#include <linux/spinlock.h>
++#include <linux/bitops.h>
++#include <linux/gpio.h>
++#include <linux/of.h>
++#include <linux/of_gpio.h>
++#include <linux/slab.h>
++#include <linux/platform_device.h>
++
++#include <linux/pinctrl/pinconf.h>
++#include <linux/pinctrl/pinconf-generic.h>
++#include <linux/pinctrl/pinmux.h>
++#include <linux/pinctrl/machine.h>
++
++#include "../core.h"
++#include "../pinctrl-utils.h"
++
++#include "pinctrl-bcm63xx.h"
++
++#define BCM6362_NGPIO	48
++
++/* GPIO_BASEMODE register */
++#define BASEMODE_NAND	BIT(2)
++
++enum bcm6362_pinctrl_reg {
++	BCM6362_LEDCTRL,
++	BCM6362_MODE,
++	BCM6362_CTRL,
++	BCM6362_BASEMODE,
++};
++
++struct bcm6362_pingroup {
++	const char *name;
++	const unsigned * const pins;
++	const unsigned num_pins;
++};
++
++struct bcm6362_function {
++	const char *name;
++	const char * const *groups;
++	const unsigned num_groups;
++
++	enum bcm6362_pinctrl_reg reg;
++	u32 basemode_mask;
++};
++
++struct bcm6362_pinctrl {
++	struct pinctrl_dev *pctldev;
++	struct pinctrl_desc desc;
++
++	void __iomem *led;
++	void __iomem *mode;
++	void __iomem *ctrl;
++	void __iomem *basemode;
++
++	/* register access lock */
++	spinlock_t lock;
++
++	struct gpio_chip gpio[2];
++};
++
++#define BCM6362_PIN(a, b, mask)			\
++	{					\
++		.number = a,			\
++		.name = b,			\
++		.drv_data = (void *)(mask),	\
++	}
++
++static const struct pinctrl_pin_desc bcm6362_pins[] = {
++	PINCTRL_PIN(0, "gpio0"),
++	PINCTRL_PIN(1, "gpio1"),
++	PINCTRL_PIN(2, "gpio2"),
++	PINCTRL_PIN(3, "gpio3"),
++	PINCTRL_PIN(4, "gpio4"),
++	PINCTRL_PIN(5, "gpio5"),
++	PINCTRL_PIN(6, "gpio6"),
++	PINCTRL_PIN(7, "gpio7"),
++	BCM6362_PIN(8, "gpio8", BASEMODE_NAND),
++	PINCTRL_PIN(9, "gpio9"),
++	PINCTRL_PIN(10, "gpio10"),
++	PINCTRL_PIN(11, "gpio11"),
++	BCM6362_PIN(12, "gpio12", BASEMODE_NAND),
++	BCM6362_PIN(13, "gpio13", BASEMODE_NAND),
++	BCM6362_PIN(14, "gpio14", BASEMODE_NAND),
++	BCM6362_PIN(15, "gpio15", BASEMODE_NAND),
++	BCM6362_PIN(16, "gpio16", BASEMODE_NAND),
++	BCM6362_PIN(17, "gpio17", BASEMODE_NAND),
++	BCM6362_PIN(18, "gpio18", BASEMODE_NAND),
++	BCM6362_PIN(19, "gpio19", BASEMODE_NAND),
++	BCM6362_PIN(20, "gpio20", BASEMODE_NAND),
++	BCM6362_PIN(21, "gpio21", BASEMODE_NAND),
++	BCM6362_PIN(22, "gpio22", BASEMODE_NAND),
++	BCM6362_PIN(23, "gpio23", BASEMODE_NAND),
++	PINCTRL_PIN(24, "gpio24"),
++	PINCTRL_PIN(25, "gpio25"),
++	PINCTRL_PIN(26, "gpio26"),
++	BCM6362_PIN(27, "gpio27", BASEMODE_NAND),
++	PINCTRL_PIN(28, "gpio28"),
++	PINCTRL_PIN(29, "gpio29"),
++	PINCTRL_PIN(30, "gpio30"),
++	PINCTRL_PIN(31, "gpio31"),
++	PINCTRL_PIN(32, "gpio32"),
++	PINCTRL_PIN(33, "gpio33"),
++	PINCTRL_PIN(34, "gpio34"),
++	PINCTRL_PIN(35, "gpio35"),
++	PINCTRL_PIN(36, "gpio36"),
++	PINCTRL_PIN(37, "gpio37"),
++	PINCTRL_PIN(38, "gpio38"),
++	PINCTRL_PIN(39, "gpio39"),
++	PINCTRL_PIN(40, "gpio40"),
++	PINCTRL_PIN(41, "gpio41"),
++	PINCTRL_PIN(42, "gpio42"),
++	PINCTRL_PIN(43, "gpio43"),
++	PINCTRL_PIN(44, "gpio44"),
++	PINCTRL_PIN(45, "gpio45"),
++	PINCTRL_PIN(46, "gpio46"),
++	PINCTRL_PIN(47, "gpio47"),
++};
++
++static unsigned gpio0_pins[] = { 0 };
++static unsigned gpio1_pins[] = { 1 };
++static unsigned gpio2_pins[] = { 2 };
++static unsigned gpio3_pins[] = { 3 };
++static unsigned gpio4_pins[] = { 4 };
++static unsigned gpio5_pins[] = { 5 };
++static unsigned gpio6_pins[] = { 6 };
++static unsigned gpio7_pins[] = { 7 };
++static unsigned gpio8_pins[] = { 8 };
++static unsigned gpio9_pins[] = { 9 };
++static unsigned gpio10_pins[] = { 10 };
++static unsigned gpio11_pins[] = { 11 };
++static unsigned gpio12_pins[] = { 12 };
++static unsigned gpio13_pins[] = { 13 };
++static unsigned gpio14_pins[] = { 14 };
++static unsigned gpio15_pins[] = { 15 };
++static unsigned gpio16_pins[] = { 16 };
++static unsigned gpio17_pins[] = { 17 };
++static unsigned gpio18_pins[] = { 18 };
++static unsigned gpio19_pins[] = { 19 };
++static unsigned gpio20_pins[] = { 20 };
++static unsigned gpio21_pins[] = { 21 };
++static unsigned gpio22_pins[] = { 22 };
++static unsigned gpio23_pins[] = { 23 };
++static unsigned gpio24_pins[] = { 24 };
++static unsigned gpio25_pins[] = { 25 };
++static unsigned gpio26_pins[] = { 26 };
++static unsigned gpio27_pins[] = { 27 };
++static unsigned gpio28_pins[] = { 28 };
++static unsigned gpio29_pins[] = { 29 };
++static unsigned gpio30_pins[] = { 30 };
++static unsigned gpio31_pins[] = { 31 };
++static unsigned gpio32_pins[] = { 32 };
++static unsigned gpio33_pins[] = { 33 };
++static unsigned gpio34_pins[] = { 34 };
++static unsigned gpio35_pins[] = { 35 };
++static unsigned gpio36_pins[] = { 36 };
++static unsigned gpio37_pins[] = { 37 };
++static unsigned gpio38_pins[] = { 38 };
++static unsigned gpio39_pins[] = { 39 };
++static unsigned gpio40_pins[] = { 40 };
++static unsigned gpio41_pins[] = { 41 };
++static unsigned gpio42_pins[] = { 42 };
++static unsigned gpio43_pins[] = { 43 };
++static unsigned gpio44_pins[] = { 44 };
++static unsigned gpio45_pins[] = { 45 };
++static unsigned gpio46_pins[] = { 46 };
++static unsigned gpio47_pins[] = { 47 };
++
++static unsigned nand_grp_pins[] = {
++	8, 12, 13, 14, 15, 16, 17,
++	18, 19, 20, 21, 22, 23, 27,
++};
++
++#define BCM6362_GROUP(n)				\
++	{						\
++		.name = #n,				\
++		.pins = n##_pins,			\
++		.num_pins = ARRAY_SIZE(n##_pins),	\
++	}
++
++static struct bcm6362_pingroup bcm6362_groups[] = {
++	BCM6362_GROUP(gpio0),
++	BCM6362_GROUP(gpio1),
++	BCM6362_GROUP(gpio2),
++	BCM6362_GROUP(gpio3),
++	BCM6362_GROUP(gpio4),
++	BCM6362_GROUP(gpio5),
++	BCM6362_GROUP(gpio6),
++	BCM6362_GROUP(gpio7),
++	BCM6362_GROUP(gpio8),
++	BCM6362_GROUP(gpio9),
++	BCM6362_GROUP(gpio10),
++	BCM6362_GROUP(gpio11),
++	BCM6362_GROUP(gpio12),
++	BCM6362_GROUP(gpio13),
++	BCM6362_GROUP(gpio14),
++	BCM6362_GROUP(gpio15),
++	BCM6362_GROUP(gpio16),
++	BCM6362_GROUP(gpio17),
++	BCM6362_GROUP(gpio18),
++	BCM6362_GROUP(gpio19),
++	BCM6362_GROUP(gpio20),
++	BCM6362_GROUP(gpio21),
++	BCM6362_GROUP(gpio22),
++	BCM6362_GROUP(gpio23),
++	BCM6362_GROUP(gpio24),
++	BCM6362_GROUP(gpio25),
++	BCM6362_GROUP(gpio26),
++	BCM6362_GROUP(gpio27),
++	BCM6362_GROUP(gpio28),
++	BCM6362_GROUP(gpio29),
++	BCM6362_GROUP(gpio30),
++	BCM6362_GROUP(gpio31),
++	BCM6362_GROUP(gpio32),
++	BCM6362_GROUP(gpio33),
++	BCM6362_GROUP(gpio34),
++	BCM6362_GROUP(gpio35),
++	BCM6362_GROUP(gpio36),
++	BCM6362_GROUP(gpio37),
++	BCM6362_GROUP(gpio38),
++	BCM6362_GROUP(gpio39),
++	BCM6362_GROUP(gpio40),
++	BCM6362_GROUP(gpio41),
++	BCM6362_GROUP(gpio42),
++	BCM6362_GROUP(gpio43),
++	BCM6362_GROUP(gpio44),
++	BCM6362_GROUP(gpio45),
++	BCM6362_GROUP(gpio46),
++	BCM6362_GROUP(gpio47),
++	BCM6362_GROUP(nand_grp),
++};
++
++static const char * const led_groups[] = {
++	"gpio0",
++	"gpio1",
++	"gpio2",
++	"gpio3",
++	"gpio4",
++	"gpio5",
++	"gpio6",
++	"gpio7",
++	"gpio8",
++	"gpio9",
++	"gpio10",
++	"gpio11",
++	"gpio12",
++	"gpio13",
++	"gpio14",
++	"gpio15",
++	"gpio16",
++	"gpio17",
++	"gpio18",
++	"gpio19",
++	"gpio20",
++	"gpio21",
++	"gpio22",
++	"gpio23",
++};
++
++static const char * const usb_device_led_groups[] = {
++	"gpio0",
++};
++
++static const char * const sys_irq_groups[] = {
++	"gpio1",
++};
++
++static const char * const serial_led_clk_groups[] = {
++	"gpio2",
++};
++
++static const char * const serial_led_data_groups[] = {
++	"gpio3",
++};
++
++static const char * const robosw_led_data_groups[] = {
++	"gpio4",
++};
++
++static const char * const robosw_led_clk_groups[] = {
++	"gpio5",
++};
++
++static const char * const robosw_led0_groups[] = {
++	"gpio6",
++};
++
++static const char * const robosw_led1_groups[] = {
++	"gpio7",
++};
++
++static const char * const inet_led_groups[] = {
++	"gpio8",
++};
++
++static const char * const spi_cs2_groups[] = {
++	"gpio9",
++};
++
++static const char * const spi_cs3_groups[] = {
++	"gpio10",
++};
++
++static const char * const ntr_pulse_groups[] = {
++	"gpio11",
++};
++
++static const char * const uart1_scts_groups[] = {
++	"gpio12",
++};
++
++static const char * const uart1_srts_groups[] = {
++	"gpio13",
++};
++
++static const char * const uart1_sdin_groups[] = {
++	"gpio14",
++};
++
++static const char * const uart1_sdout_groups[] = {
++	"gpio15",
++};
++
++static const char * const adsl_spi_miso_groups[] = {
++	"gpio16",
++};
++
++static const char * const adsl_spi_mosi_groups[] = {
++	"gpio17",
++};
++
++static const char * const adsl_spi_clk_groups[] = {
++	"gpio18",
++};
++
++static const char * const adsl_spi_cs_groups[] = {
++	"gpio19",
++};
++
++static const char * const ephy0_led_groups[] = {
++	"gpio20",
++};
++
++static const char * const ephy1_led_groups[] = {
++	"gpio21",
++};
++
++static const char * const ephy2_led_groups[] = {
++	"gpio22",
++};
++
++static const char * const ephy3_led_groups[] = {
++	"gpio23",
++};
++
++static const char * const ext_irq0_groups[] = {
++	"gpio24",
++};
++
++static const char * const ext_irq1_groups[] = {
++	"gpio25",
++};
++
++static const char * const ext_irq2_groups[] = {
++	"gpio26",
++};
++
++static const char * const ext_irq3_groups[] = {
++	"gpio27",
++};
++
++static const char * const wifi_groups[] = {
++	"gpio32",
++	"gpio33",
++	"gpio34",
++	"gpio35",
++	"gpio36",
++	"gpio37",
++	"gpio38",
++	"gpio39",
++	"gpio40",
++	"gpio41",
++	"gpio42",
++	"gpio43",
++	"gpio44",
++	"gpio45",
++	"gpio46",
++	"gpio47",
++};
++
++static const char * const nand_groups[] = {
++	"nand_grp",
++};
++
++#define BCM6362_LED_FUN(n)				\
++	{						\
++		.name = #n,				\
++		.groups = n##_groups,			\
++		.num_groups = ARRAY_SIZE(n##_groups),	\
++		.reg = BCM6362_LEDCTRL,			\
++	}
++
++#define BCM6362_MODE_FUN(n)				\
++	{						\
++		.name = #n,				\
++		.groups = n##_groups,			\
++		.num_groups = ARRAY_SIZE(n##_groups),	\
++		.reg = BCM6362_MODE,			\
++	}
++
++#define BCM6362_CTRL_FUN(n)				\
++	{						\
++		.name = #n,				\
++		.groups = n##_groups,			\
++		.num_groups = ARRAY_SIZE(n##_groups),	\
++		.reg = BCM6362_CTRL,			\
++	}
++
++#define BCM6362_BASEMODE_FUN(n, mask)			\
++	{						\
++		.name = #n,				\
++		.groups = n##_groups,			\
++		.num_groups = ARRAY_SIZE(n##_groups),	\
++		.reg = BCM6362_BASEMODE,		\
++		.basemode_mask = (mask),		\
++	}
++
++static const struct bcm6362_function bcm6362_funcs[] = {
++	BCM6362_LED_FUN(led),
++	BCM6362_MODE_FUN(usb_device_led),
++	BCM6362_MODE_FUN(sys_irq),
++	BCM6362_MODE_FUN(serial_led_clk),
++	BCM6362_MODE_FUN(serial_led_data),
++	BCM6362_MODE_FUN(robosw_led_data),
++	BCM6362_MODE_FUN(robosw_led_clk),
++	BCM6362_MODE_FUN(robosw_led0),
++	BCM6362_MODE_FUN(robosw_led1),
++	BCM6362_MODE_FUN(inet_led),
++	BCM6362_MODE_FUN(spi_cs2),
++	BCM6362_MODE_FUN(spi_cs3),
++	BCM6362_MODE_FUN(ntr_pulse),
++	BCM6362_MODE_FUN(uart1_scts),
++	BCM6362_MODE_FUN(uart1_srts),
++	BCM6362_MODE_FUN(uart1_sdin),
++	BCM6362_MODE_FUN(uart1_sdout),
++	BCM6362_MODE_FUN(adsl_spi_miso),
++	BCM6362_MODE_FUN(adsl_spi_mosi),
++	BCM6362_MODE_FUN(adsl_spi_clk),
++	BCM6362_MODE_FUN(adsl_spi_cs),
++	BCM6362_MODE_FUN(ephy0_led),
++	BCM6362_MODE_FUN(ephy1_led),
++	BCM6362_MODE_FUN(ephy2_led),
++	BCM6362_MODE_FUN(ephy3_led),
++	BCM6362_MODE_FUN(ext_irq0),
++	BCM6362_MODE_FUN(ext_irq1),
++	BCM6362_MODE_FUN(ext_irq2),
++	BCM6362_MODE_FUN(ext_irq3),
++	BCM6362_CTRL_FUN(wifi),
++	BCM6362_BASEMODE_FUN(nand, BASEMODE_NAND),
++};
++
++static int bcm6362_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
++{
++	return ARRAY_SIZE(bcm6362_groups);
++}
++
++static const char *bcm6362_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
++						  unsigned group)
++{
++	return bcm6362_groups[group].name;
++}
++
++static int bcm6362_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
++					  unsigned group, const unsigned **pins,
++					  unsigned *num_pins)
++{
++	*pins = bcm6362_groups[group].pins;
++	*num_pins = bcm6362_groups[group].num_pins;
++
++	return 0;
++}
++
++static int bcm6362_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
++{
++	return ARRAY_SIZE(bcm6362_funcs);
++}
++
++static const char *bcm6362_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
++						 unsigned selector)
++{
++	return bcm6362_funcs[selector].name;
++}
++
++static int bcm6362_pinctrl_get_groups(struct pinctrl_dev *pctldev,
++				      unsigned selector,
++				      const char * const **groups,
++				      unsigned * const num_groups)
++{
++	*groups = bcm6362_funcs[selector].groups;
++	*num_groups = bcm6362_funcs[selector].num_groups;
++
++	return 0;
++}
++
++static void bcm6362_rmw_mux(struct bcm6362_pinctrl *pctl, void __iomem *reg,
++			    u32 mask, u32 val)
++{
++	unsigned long flags;
++	u32 tmp;
++
++	spin_lock_irqsave(&pctl->lock, flags);
++	tmp = __raw_readl(reg);
++	tmp &= ~mask;
++	tmp |= val & mask;
++	__raw_writel(tmp, reg);
++
++	spin_unlock_irqrestore(&pctl->lock, flags);
++}
++
++static void bcm6362_set_gpio(struct bcm6362_pinctrl *pctl, unsigned pin)
++{
++	const struct pinctrl_pin_desc *desc = &bcm6362_pins[pin];
++	u32 mask = BIT(pin % 32);
++
++	if (desc->drv_data)
++		bcm6362_rmw_mux(pctl, pctl->basemode, (u32)desc->drv_data, 0);
++
++	if (pin < 32) {
++		/* base mode 0 => gpio 1 => mux function */
++		bcm6362_rmw_mux(pctl, pctl->mode, mask, 0);
++
++		/* pins 0-23 might be muxed to led */
++		if (pin < 24)
++			bcm6362_rmw_mux(pctl, pctl->led, mask, 0);
++	} else {
++		/* ctrl reg 0 => wifi function 1 => gpio */
++		bcm6362_rmw_mux(pctl, pctl->ctrl, mask, mask);
++	}
++}
++
++static int bcm6362_pinctrl_set_mux(struct pinctrl_dev *pctldev,
++				   unsigned selector, unsigned group)
++{
++	struct bcm6362_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
++	const struct bcm6362_pingroup *grp = &bcm6362_groups[group];
++	const struct bcm6362_function *f = &bcm6362_funcs[selector];
++	unsigned i;
++	void __iomem *reg;
++	u32 val, mask;
++
++	for (i = 0; i < grp->num_pins; i++)
++		bcm6362_set_gpio(pctl, grp->pins[i]);
++
++	switch (f->reg) {
++	case BCM6362_LEDCTRL:
++		reg = pctl->led;
++		mask = BIT(grp->pins[0]);
++		val = BIT(grp->pins[0]);
++		break;
++	case BCM6362_MODE:
++		reg = pctl->ctrl;
++		mask = BIT(grp->pins[0]);
++		val = BIT(grp->pins[0]);
++		break;
++	case BCM6362_CTRL:
++		reg = pctl->ctrl;
++		mask = BIT(grp->pins[0]);
++		val = 0;
++		break;
++	case BCM6362_BASEMODE:
++		reg = pctl->basemode;
++		mask = f->basemode_mask;
++		val = f->basemode_mask;
++		break;
++	default:
++		WARN_ON(1);
++		return -EINVAL;
++	}
++
++	bcm6362_rmw_mux(pctl, reg, mask, val);
++
++	return 0;
++}
++
++static int bcm6362_gpio_request_enable(struct pinctrl_dev *pctldev,
++				       struct pinctrl_gpio_range *range,
++				       unsigned offset)
++{
++	struct bcm6362_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
++
++	/* disable all functions using this pin */
++	bcm6362_set_gpio(pctl, offset);
++
++	return 0;
++}
++
++static struct pinctrl_ops bcm6362_pctl_ops = {
++	.get_groups_count	= bcm6362_pinctrl_get_group_count,
++	.get_group_name		= bcm6362_pinctrl_get_group_name,
++	.get_group_pins		= bcm6362_pinctrl_get_group_pins,
++#ifdef CONFIG_OF
++	.dt_node_to_map		= pinconf_generic_dt_node_to_map_pin,
++	.dt_free_map		= pinctrl_utils_free_map,
++#endif
++};
++
++static struct pinmux_ops bcm6362_pmx_ops = {
++	.get_functions_count	= bcm6362_pinctrl_get_func_count,
++	.get_function_name	= bcm6362_pinctrl_get_func_name,
++	.get_function_groups	= bcm6362_pinctrl_get_groups,
++	.set_mux		= bcm6362_pinctrl_set_mux,
++	.gpio_request_enable	= bcm6362_gpio_request_enable,
++	.strict			= true,
++};
++
++static int bcm6362_pinctrl_probe(struct platform_device *pdev)
++{
++	struct bcm6362_pinctrl *pctl;
++	struct resource *res;
++	void __iomem *led, *mode, *ctrl, *basemode;
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "led");
++	led = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(led))
++		return PTR_ERR(led);
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mode");
++	mode = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(mode))
++		return PTR_ERR(mode);
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
++	ctrl = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(ctrl))
++		return PTR_ERR(ctrl);
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "basemode");
++	basemode = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(basemode))
++		return PTR_ERR(basemode);
++
++	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
++	if (!pctl)
++		return -ENOMEM;
++
++	spin_lock_init(&pctl->lock);
++
++	pctl->led = led;
++	pctl->mode = mode;
++	pctl->ctrl = ctrl;
++	pctl->basemode = basemode;
++
++	pctl->desc.name = dev_name(&pdev->dev);
++	pctl->desc.owner = THIS_MODULE;
++	pctl->desc.pctlops = &bcm6362_pctl_ops;
++	pctl->desc.pmxops = &bcm6362_pmx_ops;
++
++	pctl->desc.npins = ARRAY_SIZE(bcm6362_pins);
++	pctl->desc.pins = bcm6362_pins;
++
++	platform_set_drvdata(pdev, pctl);
++
++	pctl->pctldev = bcm63xx_pinctrl_register(pdev, &pctl->desc, pctl,
++						 pctl->gpio, BCM6362_NGPIO);
++	if (IS_ERR(pctl->pctldev))
++		return PTR_ERR(pctl->pctldev);
++
++	return 0;
++}
++
++static const struct of_device_id bcm6362_pinctrl_match[] = {
++	{ .compatible = "brcm,bcm6362-pinctrl", },
++	{ },
++};
++
++static struct platform_driver bcm6362_pinctrl_driver = {
++	.probe = bcm6362_pinctrl_probe,
++	.driver = {
++		.name = "bcm6362-pinctrl",
++		.of_match_table = bcm6362_pinctrl_match,
++	},
++};
++
++builtin_platform_driver(bcm6362_pinctrl_driver);

target/linux/brcm63xx/patches-4.9/139-Documentation-add-BCM6368-pincontroller-binding-docu.patch

@@ -0,0 +1,84 @@
+From 30594cf9bfff176a9e4b14c50dcd8b9d0cc3edec Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Wed, 27 Jul 2016 11:36:51 +0200
+Subject: [PATCH 10/16] Documentation: add BCM6368 pincontroller binding
+ documentation
+
+Add binding documentation for the pincontrol core found in BCM6368 SoCs.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ .../bindings/pinctrl/brcm,bcm6368-pinctrl.txt      | 67 ++++++++++++++++++++++
+ 1 file changed, 67 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.txt
+@@ -0,0 +1,67 @@
++* Broadcom BCM6368 pin controller
++
++Required properties:
++- compatible: Must be "brcm,bcm6368-pinctrl".
++- reg: Register specifiers of dirout, dat, mode registers.
++- reg-names: Must be "dirout", "dat", "mode".
++- brcm,gpiobasemode: Phandle to the gpio basemode register.
++- gpio-controller: Identifies this node as a GPIO controller.
++- #gpio-cells: Must be <2>.
++
++Example:
++
++pinctrl: pin-controller@10000080 {
++	compatible = "brcm,bcm6368-pinctrl";
++	reg = <0x10000080 0x08>,
++	      <0x10000088 0x08>,
++	      <0x10000098 0x04>;
++	reg-names = "dirout", "dat", "mode";
++	brcm,gpiobasemode = <&gpiobasemode>;
++
++	gpio-controller;
++	#gpio-cells = <2>;
++};
++
++gpiobasemode: syscon@100000b8 {
++	compatible = "brcm,bcm6368-gpiobasemode", "syscon";
++	reg = <0x100000b8 4>;
++	native-endian;
++};
++
++Available pins/groups and functions:
++
++name		pins	functions
++-----------------------------------------------------------
++gpio0		0	analog_afe0
++gpio1		1	analog_afe1
++gpio2		2	sys_irq
++gpio3		3	serial_led_data
++gpio4		4	serial_led_clk
++gpio5		5	inet_led
++gpio6		6	ephy0_led
++gpio7		7	ephy1_led
++gpio8		8	ephy2_led
++gpio9		9	ephy3_led
++gpio10		10	robosw_led_data
++gpio11		11	robosw_led_clk
++gpio12		12	robosw_led0
++gpio13		13	robosw_led1
++gpio14		14	usb_device_led
++gpio15		15	-
++gpio16		16	pci_req1
++gpio17		17	pci_gnt1
++gpio18		18	pci_intb
++gpio19		19	pci_req0
++gpio20		20	pci_gnt0
++gpio21		21	-
++gpio22		22	pcmcia_cd1
++gpio23		23	pcmcia_cd2
++gpio24		24	pcmcia_vs1
++gpio25		25	pcmcia_vs2
++gpio26		26	ebi_cs2
++gpio27		27	ebi_cs3
++gpio28		28	spi_cs2
++gpio29		29	spi_cs3
++gpio30		30	spi_cs4
++gpio31		31	spi_cs5
++uart1_grp	30-33	uart1

target/linux/brcm63xx/patches-4.9/140-pinctrl-add-a-pincontrol-driver-for-BCM6368.patch

@@ -0,0 +1,620 @@
+From 90be3cb4f1a45b8be4a4ec264cd66c2f8e893fcb Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Fri, 24 Jun 2016 22:18:25 +0200
+Subject: [PATCH 11/16] pinctrl: add a pincontrol driver for BCM6368
+
+Add a pincontrol driver for BCM6368. BCM6368 allows muxing the first 32
+GPIOs onto alternative functions. Not all are documented.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/pinctrl/bcm63xx/Kconfig           |  15 +
+ drivers/pinctrl/bcm63xx/Makefile          |   1 +
+ drivers/pinctrl/bcm63xx/pinctrl-bcm6368.c | 573 ++++++++++++++++++++++++++++++
+ 3 files changed, 589 insertions(+)
+ create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm6368.c
+
+--- a/drivers/pinctrl/bcm63xx/Kconfig
++++ b/drivers/pinctrl/bcm63xx/Kconfig
+@@ -30,3 +30,18 @@ config PINCTRL_BCM6362
+ 	select PINCONF
+ 	select PINCTRL_BCM63XX
+ 	select GENERIC_PINCONF
++
++config PINCTRL_BCM6368
++	bool "BCM6368 pincontrol driver" if COMPILE_TEST
++	select PINMUX
++	select PINCONF
++	select PINCTRL_BCM63XX
++	select GENERIC_PINCONF
++	select MFD_SYSCON
++
++config PINCTRL_BCM63268
++	bool "BCM63268 pincontrol driver" if COMPILE_TEST
++	select PINMUX
++	select PINCONF
++	select PINCTRL_BCM63XX
++	select GENERIC_PINCONF
+--- a/drivers/pinctrl/bcm63xx/Makefile
++++ b/drivers/pinctrl/bcm63xx/Makefile
+@@ -3,3 +3,4 @@ obj-$(CONFIG_PINCTRL_BCM6328)	+= pinctrl
+ obj-$(CONFIG_PINCTRL_BCM6348)	+= pinctrl-bcm6348.o
+ obj-$(CONFIG_PINCTRL_BCM6358)	+= pinctrl-bcm6358.o
+ obj-$(CONFIG_PINCTRL_BCM6362)	+= pinctrl-bcm6362.o
++obj-$(CONFIG_PINCTRL_BCM6368)	+= pinctrl-bcm6368.o
+--- /dev/null
++++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm6368.c
+@@ -0,0 +1,573 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2016 Jonas Gorski <[email protected]>
++ */
++
++#include <linux/bitops.h>
++#include <linux/kernel.h>
++#include <linux/gpio.h>
++#include <linux/mfd/syscon.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_gpio.h>
++#include <linux/pinctrl/pinconf.h>
++#include <linux/pinctrl/pinconf-generic.h>
++#include <linux/pinctrl/pinmux.h>
++#include <linux/pinctrl/machine.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++
++#include "../core.h"
++#include "../pinctrl-utils.h"
++
++#include "pinctrl-bcm63xx.h"
++
++#define BCM6368_NGPIO	38
++
++#define BCM6368_BASEMODE_MASK	0x7
++#define BCM6368_BASEMODE_GPIO	0x0
++#define BCM6368_BASEMODE_UART1	0x1
++
++struct bcm6368_pingroup {
++	const char *name;
++	const unsigned * const pins;
++	const unsigned num_pins;
++};
++
++struct bcm6368_function {
++	const char *name;
++	const char * const *groups;
++	const unsigned num_groups;
++
++	unsigned dir_out:16;
++	unsigned basemode:3;
++};
++
++struct bcm6368_pinctrl {
++	struct pinctrl_dev *pctldev;
++	struct pinctrl_desc desc;
++
++	void __iomem *mode;
++	struct regmap_field *overlay;
++
++	/* register access lock */
++	spinlock_t lock;
++
++	struct gpio_chip gpio[2];
++};
++
++#define BCM6368_BASEMODE_PIN(a, b)		\
++	{					\
++		.number = a,			\
++		.name = b,			\
++		.drv_data = (void *)true	\
++	}
++
++static const struct pinctrl_pin_desc bcm6368_pins[] = {
++	PINCTRL_PIN(0, "gpio0"),
++	PINCTRL_PIN(1, "gpio1"),
++	PINCTRL_PIN(2, "gpio2"),
++	PINCTRL_PIN(3, "gpio3"),
++	PINCTRL_PIN(4, "gpio4"),
++	PINCTRL_PIN(5, "gpio5"),
++	PINCTRL_PIN(6, "gpio6"),
++	PINCTRL_PIN(7, "gpio7"),
++	PINCTRL_PIN(8, "gpio8"),
++	PINCTRL_PIN(9, "gpio9"),
++	PINCTRL_PIN(10, "gpio10"),
++	PINCTRL_PIN(11, "gpio11"),
++	PINCTRL_PIN(12, "gpio12"),
++	PINCTRL_PIN(13, "gpio13"),
++	PINCTRL_PIN(14, "gpio14"),
++	PINCTRL_PIN(15, "gpio15"),
++	PINCTRL_PIN(16, "gpio16"),
++	PINCTRL_PIN(17, "gpio17"),
++	PINCTRL_PIN(18, "gpio18"),
++	PINCTRL_PIN(19, "gpio19"),
++	PINCTRL_PIN(20, "gpio20"),
++	PINCTRL_PIN(21, "gpio21"),
++	PINCTRL_PIN(22, "gpio22"),
++	PINCTRL_PIN(23, "gpio23"),
++	PINCTRL_PIN(24, "gpio24"),
++	PINCTRL_PIN(25, "gpio25"),
++	PINCTRL_PIN(26, "gpio26"),
++	PINCTRL_PIN(27, "gpio27"),
++	PINCTRL_PIN(28, "gpio28"),
++	PINCTRL_PIN(29, "gpio29"),
++	BCM6368_BASEMODE_PIN(30, "gpio30"),
++	BCM6368_BASEMODE_PIN(31, "gpio31"),
++	BCM6368_BASEMODE_PIN(32, "gpio32"),
++	BCM6368_BASEMODE_PIN(33, "gpio33"),
++	PINCTRL_PIN(34, "gpio34"),
++	PINCTRL_PIN(35, "gpio35"),
++	PINCTRL_PIN(36, "gpio36"),
++	PINCTRL_PIN(37, "gpio37"),
++};
++
++static unsigned gpio0_pins[] = { 0 };
++static unsigned gpio1_pins[] = { 1 };
++static unsigned gpio2_pins[] = { 2 };
++static unsigned gpio3_pins[] = { 3 };
++static unsigned gpio4_pins[] = { 4 };
++static unsigned gpio5_pins[] = { 5 };
++static unsigned gpio6_pins[] = { 6 };
++static unsigned gpio7_pins[] = { 7 };
++static unsigned gpio8_pins[] = { 8 };
++static unsigned gpio9_pins[] = { 9 };
++static unsigned gpio10_pins[] = { 10 };
++static unsigned gpio11_pins[] = { 11 };
++static unsigned gpio12_pins[] = { 12 };
++static unsigned gpio13_pins[] = { 13 };
++static unsigned gpio14_pins[] = { 14 };
++static unsigned gpio15_pins[] = { 15 };
++static unsigned gpio16_pins[] = { 16 };
++static unsigned gpio17_pins[] = { 17 };
++static unsigned gpio18_pins[] = { 18 };
++static unsigned gpio19_pins[] = { 19 };
++static unsigned gpio20_pins[] = { 20 };
++static unsigned gpio21_pins[] = { 21 };
++static unsigned gpio22_pins[] = { 22 };
++static unsigned gpio23_pins[] = { 23 };
++static unsigned gpio24_pins[] = { 24 };
++static unsigned gpio25_pins[] = { 25 };
++static unsigned gpio26_pins[] = { 26 };
++static unsigned gpio27_pins[] = { 27 };
++static unsigned gpio28_pins[] = { 28 };
++static unsigned gpio29_pins[] = { 29 };
++static unsigned gpio30_pins[] = { 30 };
++static unsigned gpio31_pins[] = { 31 };
++static unsigned uart1_grp_pins[] = { 30, 31, 32, 33 };
++
++#define BCM6368_GROUP(n)				\
++	{						\
++		.name = #n,				\
++		.pins = n##_pins,			\
++		.num_pins = ARRAY_SIZE(n##_pins),	\
++	}
++
++static struct bcm6368_pingroup bcm6368_groups[] = {
++	BCM6368_GROUP(gpio0),
++	BCM6368_GROUP(gpio1),
++	BCM6368_GROUP(gpio2),
++	BCM6368_GROUP(gpio3),
++	BCM6368_GROUP(gpio4),
++	BCM6368_GROUP(gpio5),
++	BCM6368_GROUP(gpio6),
++	BCM6368_GROUP(gpio7),
++	BCM6368_GROUP(gpio8),
++	BCM6368_GROUP(gpio9),
++	BCM6368_GROUP(gpio10),
++	BCM6368_GROUP(gpio11),
++	BCM6368_GROUP(gpio12),
++	BCM6368_GROUP(gpio13),
++	BCM6368_GROUP(gpio14),
++	BCM6368_GROUP(gpio15),
++	BCM6368_GROUP(gpio16),
++	BCM6368_GROUP(gpio17),
++	BCM6368_GROUP(gpio18),
++	BCM6368_GROUP(gpio19),
++	BCM6368_GROUP(gpio20),
++	BCM6368_GROUP(gpio21),
++	BCM6368_GROUP(gpio22),
++	BCM6368_GROUP(gpio23),
++	BCM6368_GROUP(gpio24),
++	BCM6368_GROUP(gpio25),
++	BCM6368_GROUP(gpio26),
++	BCM6368_GROUP(gpio27),
++	BCM6368_GROUP(gpio28),
++	BCM6368_GROUP(gpio29),
++	BCM6368_GROUP(gpio30),
++	BCM6368_GROUP(gpio31),
++	BCM6368_GROUP(uart1_grp),
++};
++
++static const char * const analog_afe_0_groups[] = {
++	"gpio0",
++};
++
++static const char * const analog_afe_1_groups[] = {
++	"gpio1",
++};
++
++static const char * const sys_irq_groups[] = {
++	"gpio2",
++};
++
++static const char * const serial_led_data_groups[] = {
++	"gpio3",
++};
++
++static const char * const serial_led_clk_groups[] = {
++	"gpio4",
++};
++
++static const char * const inet_led_groups[] = {
++	"gpio5",
++};
++
++static const char * const ephy0_led_groups[] = {
++	"gpio6",
++};
++
++static const char * const ephy1_led_groups[] = {
++	"gpio7",
++};
++
++static const char * const ephy2_led_groups[] = {
++	"gpio8",
++};
++
++static const char * const ephy3_led_groups[] = {
++	"gpio9",
++};
++
++static const char * const robosw_led_data_groups[] = {
++	"gpio10",
++};
++
++static const char * const robosw_led_clk_groups[] = {
++	"gpio11",
++};
++
++static const char * const robosw_led0_groups[] = {
++	"gpio12",
++};
++
++static const char * const robosw_led1_groups[] = {
++	"gpio13",
++};
++
++static const char * const usb_device_led_groups[] = {
++	"gpio14",
++};
++
++static const char * const pci_req1_groups[] = {
++	"gpio16",
++};
++
++static const char * const pci_gnt1_groups[] = {
++	"gpio17",
++};
++
++static const char * const pci_intb_groups[] = {
++	"gpio18",
++};
++
++static const char * const pci_req0_groups[] = {
++	"gpio19",
++};
++
++static const char * const pci_gnt0_groups[] = {
++	"gpio20",
++};
++
++static const char * const pcmcia_cd1_groups[] = {
++	"gpio22",
++};
++
++static const char * const pcmcia_cd2_groups[] = {
++	"gpio23",
++};
++
++static const char * const pcmcia_vs1_groups[] = {
++	"gpio24",
++};
++
++static const char * const pcmcia_vs2_groups[] = {
++	"gpio25",
++};
++
++static const char * const ebi_cs2_groups[] = {
++	"gpio26",
++};
++
++static const char * const ebi_cs3_groups[] = {
++	"gpio27",
++};
++
++static const char * const spi_cs2_groups[] = {
++	"gpio28",
++};
++
++static const char * const spi_cs3_groups[] = {
++	"gpio29",
++};
++
++static const char * const spi_cs4_groups[] = {
++	"gpio30",
++};
++
++static const char * const spi_cs5_groups[] = {
++	"gpio31",
++};
++
++static const char * const uart1_groups[] = {
++	"uart1_grp",
++};
++
++#define BCM6368_FUN(n, out)				\
++	{						\
++		.name = #n,				\
++		.groups = n##_groups,			\
++		.num_groups = ARRAY_SIZE(n##_groups),	\
++		.dir_out = out,				\
++	}
++
++#define BCM6368_BASEMODE_FUN(n, val, out)		\
++	{						\
++		.name = #n,				\
++		.groups = n##_groups,			\
++		.num_groups = ARRAY_SIZE(n##_groups),	\
++		.basemode = BCM6368_BASEMODE_##val,	\
++		.dir_out = out,				\
++	}
++
++static const struct bcm6368_function bcm6368_funcs[] = {
++	BCM6368_FUN(analog_afe_0, 1),
++	BCM6368_FUN(analog_afe_1, 1),
++	BCM6368_FUN(sys_irq, 1),
++	BCM6368_FUN(serial_led_data, 1),
++	BCM6368_FUN(serial_led_clk, 1),
++	BCM6368_FUN(inet_led, 1),
++	BCM6368_FUN(ephy0_led, 1),
++	BCM6368_FUN(ephy1_led, 1),
++	BCM6368_FUN(ephy2_led, 1),
++	BCM6368_FUN(ephy3_led, 1),
++	BCM6368_FUN(robosw_led_data, 1),
++	BCM6368_FUN(robosw_led_clk, 1),
++	BCM6368_FUN(robosw_led0, 1),
++	BCM6368_FUN(robosw_led1, 1),
++	BCM6368_FUN(usb_device_led, 1),
++	BCM6368_FUN(pci_req1, 0),
++	BCM6368_FUN(pci_gnt1, 0),
++	BCM6368_FUN(pci_intb, 0),
++	BCM6368_FUN(pci_req0, 0),
++	BCM6368_FUN(pci_gnt0, 0),
++	BCM6368_FUN(pcmcia_cd1, 0),
++	BCM6368_FUN(pcmcia_cd2, 0),
++	BCM6368_FUN(pcmcia_vs1, 0),
++	BCM6368_FUN(pcmcia_vs2, 0),
++	BCM6368_FUN(ebi_cs2, 1),
++	BCM6368_FUN(ebi_cs3, 1),
++	BCM6368_FUN(spi_cs2, 1),
++	BCM6368_FUN(spi_cs3, 1),
++	BCM6368_FUN(spi_cs4, 1),
++	BCM6368_FUN(spi_cs5, 1),
++	BCM6368_BASEMODE_FUN(uart1, UART1, 0x6),
++};
++
++static int bcm6368_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
++{
++	return ARRAY_SIZE(bcm6368_groups);
++}
++
++static const char *bcm6368_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
++						  unsigned group)
++{
++	return bcm6368_groups[group].name;
++}
++
++static int bcm6368_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
++					  unsigned group, const unsigned **pins,
++					  unsigned *num_pins)
++{
++	*pins = bcm6368_groups[group].pins;
++	*num_pins = bcm6368_groups[group].num_pins;
++
++	return 0;
++}
++
++static int bcm6368_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
++{
++	return ARRAY_SIZE(bcm6368_funcs);
++}
++
++static const char *bcm6368_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
++						 unsigned selector)
++{
++	return bcm6368_funcs[selector].name;
++}
++
++static int bcm6368_pinctrl_get_groups(struct pinctrl_dev *pctldev,
++				      unsigned selector,
++				      const char * const **groups,
++				      unsigned * const num_groups)
++{
++	*groups = bcm6368_funcs[selector].groups;
++	*num_groups = bcm6368_funcs[selector].num_groups;
++
++	return 0;
++}
++
++static void bcm6368_rmw_mux(struct bcm6368_pinctrl *pctl, void __iomem *reg,
++			    u32 mask, u32 val)
++{
++	u32 tmp;
++
++	tmp = __raw_readl(reg);
++	tmp &= ~mask;
++	tmp |= (val & mask);
++	__raw_writel(tmp, reg);
++}
++
++static int bcm6368_pinctrl_set_mux(struct pinctrl_dev *pctldev,
++				   unsigned selector, unsigned group)
++{
++	struct bcm6368_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
++	const struct bcm6368_pingroup *grp = &bcm6368_groups[group];
++	const struct bcm6368_function *fun = &bcm6368_funcs[selector];
++	unsigned long flags;
++	int i, pin;
++
++	spin_lock_irqsave(&pctl->lock, flags);
++	if (fun->basemode) {
++		u32 mask = 0;
++
++		for (i = 0; i < grp->num_pins; i++) {
++			pin = grp->pins[i];
++			if (pin < 32)
++				mask |= BIT(pin);
++		}
++
++		bcm6368_rmw_mux(pctl, pctl->mode, mask, 0);
++		regmap_field_write(pctl->overlay, fun->basemode);
++	} else {
++		pin = grp->pins[0];
++
++		if (bcm6368_pins[pin].drv_data)
++			regmap_field_write(pctl->overlay,
++					   BCM6368_BASEMODE_GPIO);
++
++		bcm6368_rmw_mux(pctl, pctl->mode, BIT(pin), BIT(pin));
++	}
++	spin_unlock_irqrestore(&pctl->lock, flags);
++
++	for (pin = 0; pin < grp->num_pins; pin++) {
++		int hw_gpio = bcm6368_pins[pin].number;
++		struct gpio_chip *gc = &pctl->gpio[hw_gpio / 32];
++
++		if (fun->dir_out & BIT(pin))
++			gc->direction_output(gc, hw_gpio % 32, 0);
++		else
++			gc->direction_input(gc, hw_gpio % 32);
++	}
++
++	return 0;
++}
++
++static int bcm6368_gpio_request_enable(struct pinctrl_dev *pctldev,
++				       struct pinctrl_gpio_range *range,
++				       unsigned offset)
++{
++	struct bcm6368_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
++	unsigned long flags;
++
++	if (offset >= 32 && !bcm6368_pins[offset].drv_data)
++		return 0;
++
++	spin_lock_irqsave(&pctl->lock, flags);
++	/* disable all functions using this pin */
++	if (offset < 32)
++		bcm6368_rmw_mux(pctl, pctl->mode, BIT(offset), 0);
++
++	if (bcm6368_pins[offset].drv_data)
++		regmap_field_write(pctl->overlay, BCM6368_BASEMODE_GPIO);
++
++	spin_unlock_irqrestore(&pctl->lock, flags);
++
++	return 0;
++}
++
++static struct pinctrl_ops bcm6368_pctl_ops = {
++	.get_groups_count	= bcm6368_pinctrl_get_group_count,
++	.get_group_name		= bcm6368_pinctrl_get_group_name,
++	.get_group_pins		= bcm6368_pinctrl_get_group_pins,
++#ifdef CONFIG_OF
++	.dt_node_to_map		= pinconf_generic_dt_node_to_map_pin,
++	.dt_free_map		= pinctrl_utils_free_map,
++#endif
++};
++
++static struct pinmux_ops bcm6368_pmx_ops = {
++	.get_functions_count	= bcm6368_pinctrl_get_func_count,
++	.get_function_name	= bcm6368_pinctrl_get_func_name,
++	.get_function_groups	= bcm6368_pinctrl_get_groups,
++	.set_mux		= bcm6368_pinctrl_set_mux,
++	.gpio_request_enable	= bcm6368_gpio_request_enable,
++	.strict			= true,
++};
++
++static int bcm6368_pinctrl_probe(struct platform_device *pdev)
++{
++	struct bcm6368_pinctrl *pctl;
++	struct resource *res;
++	void __iomem *mode;
++	struct regmap *basemode;
++	struct reg_field overlay = REG_FIELD(0, 0, 3);
++
++	if (pdev->dev.of_node)
++		basemode = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
++							   "brcm,gpiobasemode");
++	else
++		basemode = syscon_regmap_lookup_by_pdevname("syscon.b00000b8");
++
++	if (IS_ERR(basemode))
++		return PTR_ERR(basemode);
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mode");
++	mode = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(mode))
++		return PTR_ERR(mode);
++
++	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
++	if (!pctl)
++		return -ENOMEM;
++
++	pctl->overlay = devm_regmap_field_alloc(&pdev->dev, basemode, overlay);
++	if (IS_ERR(pctl->overlay))
++		return PTR_ERR(pctl->overlay);
++
++	spin_lock_init(&pctl->lock);
++
++	pctl->mode = mode;
++
++	/* disable all muxes by default */
++	__raw_writel(0, pctl->mode);
++
++	pctl->desc.name = dev_name(&pdev->dev);
++	pctl->desc.owner = THIS_MODULE;
++	pctl->desc.pctlops = &bcm6368_pctl_ops;
++	pctl->desc.pmxops = &bcm6368_pmx_ops;
++
++	pctl->desc.npins = ARRAY_SIZE(bcm6368_pins);
++	pctl->desc.pins = bcm6368_pins;
++
++	platform_set_drvdata(pdev, pctl);
++
++	pctl->pctldev = bcm63xx_pinctrl_register(pdev, &pctl->desc, pctl,
++						 pctl->gpio, BCM6368_NGPIO);
++	if (IS_ERR(pctl->pctldev))
++		return PTR_ERR(pctl->pctldev);
++
++	return 0;
++}
++
++static const struct of_device_id bcm6368_pinctrl_match[] = {
++	{ .compatible = "brcm,bcm6368-pinctrl", },
++	{ },
++};
++
++static struct platform_driver bcm6368_pinctrl_driver = {
++	.probe = bcm6368_pinctrl_probe,
++	.driver = {
++		.name = "bcm6368-pinctrl",
++		.of_match_table = bcm6368_pinctrl_match,
++	},
++};
++
++builtin_platform_driver(bcm6368_pinctrl_driver);

target/linux/brcm63xx/patches-4.9/141-Documentation-add-BCM63268-pincontroller-binding-doc.patch

@@ -0,0 +1,106 @@
+From 28cc80e4ada5d73d5305fd268297825cd8d01936 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Wed, 27 Jul 2016 11:37:08 +0200
+Subject: [PATCH 12/16] Documentation: add BCM63268 pincontroller binding
+ documentation
+
+Add binding documentation for the pincontrol core found in the BCM63268
+family SoCs.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ .../bindings/pinctrl/brcm,bcm63268-pinctrl.txt     | 88 ++++++++++++++++++++++
+ 1 file changed, 88 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.txt
+@@ -0,0 +1,88 @@
++* Broadcom BCM63268 pin controller
++
++Required properties:
++- compatible: Must be "brcm,bcm6362-pinctrl".
++- reg: Register specifiers of dirout, dat, led, mode, ctrl, basemode registers.
++- reg-names: Must be "dirout", "dat", "led", "mode", "ctrl", "basemode".
++- gpio-controller: Identifies this node as a GPIO controller.
++- #gpio-cells: Must be <2>.
++
++Example:
++
++pinctrl: pin-controller@100000c0 {
++	compatible = "brcm,bcm63268-pinctrl";
++	reg = <0x100000c0 0x8>,
++	      <0x100000c8 0x8>,
++	      <0x100000d0 0x4>,
++	      <0x100000d8 0x4>,
++	      <0x100000dc 0x4>,
++	      <0x100000f8 0x4>;
++	reg-names = "dirout", "dat", "led", "mode",
++		    "ctrl", "basemode";
++
++	gpio-controller;
++	#gpio-cells = <2>;
++};
++
++Available pins/groups and functions:
++
++name		pins		functions
++-----------------------------------------------------------
++gpio0		0		led, serial_led_clk
++gpio1		1		led, serial_led_data
++gpio2		2		led,
++gpio3		3		led,
++gpio4		4		led,
++gpio5		5		led,
++gpio6		6		led,
++gpio7		7		led,
++gpio8		8		led, hsspi_cs6
++gpio9		9		led, hsspi_cs7
++gpio10		10		led, uart1_scts
++gpio11		11		led, uart1_srts
++gpio12		12		led, uart1_sdin
++gpio13		13		led, uart1_sdout
++gpio14		14		led, ntr_pulse_in
++gpio15		15		led, dsl_ntr_pulse_out
++gpio16		16		led, hsspi_cs4
++gpio17		17		led, hsspi_cs5
++gpio18		18		led, adsl_spi_miso
++gpio19		19		led, adsl_spi_mosi
++gpio20		20		led,
++gpio21		21		led,
++gpio22		22		led, vreg_clk
++gpio23		23		led, pcie_clkreq_b
++gpio24		24		uart1_scts
++gpio25		25		uart1_srts
++gpio26		26		uart1_sdin
++gpio27		27		uart1_sdout
++gpio28		28		ntr_pulse_in
++gpio29		29		dsl_ntr_pulse_out
++gpio30		30		switch_led_clk
++gpio31		31		switch_led_data
++gpio32		32		wifi
++gpio33		33		wifi
++gpio34		34		wifi
++gpio35		35		wifi
++gpio36		36		wifi
++gpio37		37		wifi
++gpio38		38		wifi
++gpio39		39		wifi
++gpio40		40		wifi
++gpio41		41		wifi
++gpio42		42		wifi
++gpio43		43		wifi
++gpio44		44		wifi
++gpio45		45		wifi
++gpio46		46		wifi
++gpio47		47		wifi
++gpio48		48		wifi
++gpio49		49		wifi
++gpio50		50		wifi
++gpio51		51		wifi
++nand_grp	2-7,24-31	nand
++dect_pd_grp	8-9		dect_pd
++vdsl_phy0_grp	10-11		vdsl_phy0
++vdsl_phy1_grp	12-13		vdsl_phy1
++vdsl_phy2_grp	24-25		vdsl_phy2
++vdsl_phy3_grp	26-27		vdsl_phy3

target/linux/brcm63xx/patches-4.9/142-pinctrl-add-a-pincontrol-driver-for-BCM63268.patch

@@ -0,0 +1,736 @@
+From 8665d3ea63649cc155286c75f83f694a930580e5 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Fri, 24 Jun 2016 22:19:12 +0200
+Subject: [PATCH 13/16] pinctrl: add a pincontrol driver for BCM63268
+
+Add a pincontrol driver for BCM63268. BCM63268 allows muxing GPIOs
+to different functions. Depending on the mux, these are either single
+pin configurations or whole pin groups.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/pinctrl/bcm63xx/Makefile           |   1 +
+ drivers/pinctrl/bcm63xx/pinctrl-bcm63268.c | 710 +++++++++++++++++++++++++++++
+ 2 files changed, 711 insertions(+)
+ create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm63268.c
+
+--- a/drivers/pinctrl/bcm63xx/Makefile
++++ b/drivers/pinctrl/bcm63xx/Makefile
+@@ -4,3 +4,4 @@ obj-$(CONFIG_PINCTRL_BCM6348)	+= pinctrl
+ obj-$(CONFIG_PINCTRL_BCM6358)	+= pinctrl-bcm6358.o
+ obj-$(CONFIG_PINCTRL_BCM6362)	+= pinctrl-bcm6362.o
+ obj-$(CONFIG_PINCTRL_BCM6368)	+= pinctrl-bcm6368.o
++obj-$(CONFIG_PINCTRL_BCM63268)	+= pinctrl-bcm63268.o
+--- /dev/null
++++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm63268.c
+@@ -0,0 +1,710 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2016 Jonas Gorski <[email protected]>
++ */
++
++#include <linux/kernel.h>
++#include <linux/spinlock.h>
++#include <linux/bitops.h>
++#include <linux/gpio.h>
++#include <linux/of.h>
++#include <linux/of_gpio.h>
++#include <linux/slab.h>
++#include <linux/platform_device.h>
++
++#include <linux/pinctrl/pinconf.h>
++#include <linux/pinctrl/pinconf-generic.h>
++#include <linux/pinctrl/pinmux.h>
++#include <linux/pinctrl/machine.h>
++
++#include "../core.h"
++#include "../pinctrl-utils.h"
++
++#include "pinctrl-bcm63xx.h"
++
++#define BCM63268_NGPIO			52
++
++/* GPIO_BASEMODE register */
++#define BASEMODE_NAND			BIT(2) /* GPIOs 2-7, 24-31 */
++#define BASEMODE_GPIO35			BIT(4) /* GPIO 35 */
++#define BASEMODE_DECTPD			BIT(5) /* GPIOs 8/9 */
++#define BASEMODE_VDSL_PHY_0		BIT(6) /* GPIOs 10/11 */
++#define BASEMODE_VDSL_PHY_1		BIT(7) /* GPIOs 12/13 */
++#define BASEMODE_VDSL_PHY_2		BIT(8) /* GPIOs 24/25 */
++#define BASEMODE_VDSL_PHY_3		BIT(9) /* GPIOs 26/27 */
++
++enum bcm63268_pinctrl_reg {
++	BCM63268_LEDCTRL,
++	BCM63268_MODE,
++	BCM63268_CTRL,
++	BCM63268_BASEMODE,
++};
++
++struct bcm63268_pingroup {
++	const char *name;
++	const unsigned * const pins;
++	const unsigned num_pins;
++};
++
++struct bcm63268_function {
++	const char *name;
++	const char * const *groups;
++	const unsigned num_groups;
++
++	enum bcm63268_pinctrl_reg reg;
++	u32 mask;
++};
++
++struct bcm63268_pinctrl {
++	struct pinctrl_dev *pctldev;
++	struct pinctrl_desc desc;
++
++	void __iomem *led;
++	void __iomem *mode;
++	void __iomem *ctrl;
++	void __iomem *basemode;
++
++	/* register access lock */
++	spinlock_t lock;
++
++	struct gpio_chip gpio[2];
++};
++
++#define BCM63268_PIN(a, b, basemode)			\
++	{						\
++		.number = a,				\
++		.name = b,				\
++		.drv_data = (void *)(basemode)		\
++	}
++
++static const struct pinctrl_pin_desc bcm63268_pins[] = {
++	PINCTRL_PIN(0, "gpio0"),
++	PINCTRL_PIN(1, "gpio1"),
++	BCM63268_PIN(2, "gpio2", BASEMODE_NAND),
++	BCM63268_PIN(3, "gpio3", BASEMODE_NAND),
++	BCM63268_PIN(4, "gpio4", BASEMODE_NAND),
++	BCM63268_PIN(5, "gpio5", BASEMODE_NAND),
++	BCM63268_PIN(6, "gpio6", BASEMODE_NAND),
++	BCM63268_PIN(7, "gpio7", BASEMODE_NAND),
++	BCM63268_PIN(8, "gpio8", BASEMODE_DECTPD),
++	BCM63268_PIN(9, "gpio9", BASEMODE_DECTPD),
++	BCM63268_PIN(10, "gpio10", BASEMODE_VDSL_PHY_0),
++	BCM63268_PIN(11, "gpio11", BASEMODE_VDSL_PHY_0),
++	BCM63268_PIN(12, "gpio12", BASEMODE_VDSL_PHY_1),
++	BCM63268_PIN(13, "gpio13", BASEMODE_VDSL_PHY_1),
++	PINCTRL_PIN(14, "gpio14"),
++	PINCTRL_PIN(15, "gpio15"),
++	PINCTRL_PIN(16, "gpio16"),
++	PINCTRL_PIN(17, "gpio17"),
++	PINCTRL_PIN(18, "gpio18"),
++	PINCTRL_PIN(19, "gpio19"),
++	PINCTRL_PIN(20, "gpio20"),
++	PINCTRL_PIN(21, "gpio21"),
++	PINCTRL_PIN(22, "gpio22"),
++	PINCTRL_PIN(23, "gpio23"),
++	BCM63268_PIN(24, "gpio24", BASEMODE_NAND | BASEMODE_VDSL_PHY_2),
++	BCM63268_PIN(25, "gpio25", BASEMODE_NAND | BASEMODE_VDSL_PHY_2),
++	BCM63268_PIN(26, "gpio26", BASEMODE_NAND | BASEMODE_VDSL_PHY_3),
++	BCM63268_PIN(27, "gpio27", BASEMODE_NAND | BASEMODE_VDSL_PHY_3),
++	BCM63268_PIN(28, "gpio28", BASEMODE_NAND),
++	BCM63268_PIN(29, "gpio29", BASEMODE_NAND),
++	BCM63268_PIN(30, "gpio30", BASEMODE_NAND),
++	BCM63268_PIN(31, "gpio31", BASEMODE_NAND),
++	PINCTRL_PIN(32, "gpio32"),
++	PINCTRL_PIN(33, "gpio33"),
++	PINCTRL_PIN(34, "gpio34"),
++	PINCTRL_PIN(35, "gpio35"),
++	PINCTRL_PIN(36, "gpio36"),
++	PINCTRL_PIN(37, "gpio37"),
++	PINCTRL_PIN(38, "gpio38"),
++	PINCTRL_PIN(39, "gpio39"),
++	PINCTRL_PIN(40, "gpio40"),
++	PINCTRL_PIN(41, "gpio41"),
++	PINCTRL_PIN(42, "gpio42"),
++	PINCTRL_PIN(43, "gpio43"),
++	PINCTRL_PIN(44, "gpio44"),
++	PINCTRL_PIN(45, "gpio45"),
++	PINCTRL_PIN(46, "gpio46"),
++	PINCTRL_PIN(47, "gpio47"),
++	PINCTRL_PIN(48, "gpio48"),
++	PINCTRL_PIN(49, "gpio49"),
++	PINCTRL_PIN(50, "gpio50"),
++	PINCTRL_PIN(51, "gpio51"),
++};
++
++static unsigned gpio0_pins[] = { 0 };
++static unsigned gpio1_pins[] = { 1 };
++static unsigned gpio2_pins[] = { 2 };
++static unsigned gpio3_pins[] = { 3 };
++static unsigned gpio4_pins[] = { 4 };
++static unsigned gpio5_pins[] = { 5 };
++static unsigned gpio6_pins[] = { 6 };
++static unsigned gpio7_pins[] = { 7 };
++static unsigned gpio8_pins[] = { 8 };
++static unsigned gpio9_pins[] = { 9 };
++static unsigned gpio10_pins[] = { 10 };
++static unsigned gpio11_pins[] = { 11 };
++static unsigned gpio12_pins[] = { 12 };
++static unsigned gpio13_pins[] = { 13 };
++static unsigned gpio14_pins[] = { 14 };
++static unsigned gpio15_pins[] = { 15 };
++static unsigned gpio16_pins[] = { 16 };
++static unsigned gpio17_pins[] = { 17 };
++static unsigned gpio18_pins[] = { 18 };
++static unsigned gpio19_pins[] = { 19 };
++static unsigned gpio20_pins[] = { 20 };
++static unsigned gpio21_pins[] = { 21 };
++static unsigned gpio22_pins[] = { 22 };
++static unsigned gpio23_pins[] = { 23 };
++static unsigned gpio24_pins[] = { 24 };
++static unsigned gpio25_pins[] = { 25 };
++static unsigned gpio26_pins[] = { 26 };
++static unsigned gpio27_pins[] = { 27 };
++static unsigned gpio28_pins[] = { 28 };
++static unsigned gpio29_pins[] = { 29 };
++static unsigned gpio30_pins[] = { 30 };
++static unsigned gpio31_pins[] = { 31 };
++static unsigned gpio32_pins[] = { 32 };
++static unsigned gpio33_pins[] = { 33 };
++static unsigned gpio34_pins[] = { 34 };
++static unsigned gpio35_pins[] = { 35 };
++static unsigned gpio36_pins[] = { 36 };
++static unsigned gpio37_pins[] = { 37 };
++static unsigned gpio38_pins[] = { 38 };
++static unsigned gpio39_pins[] = { 39 };
++static unsigned gpio40_pins[] = { 40 };
++static unsigned gpio41_pins[] = { 41 };
++static unsigned gpio42_pins[] = { 42 };
++static unsigned gpio43_pins[] = { 43 };
++static unsigned gpio44_pins[] = { 44 };
++static unsigned gpio45_pins[] = { 45 };
++static unsigned gpio46_pins[] = { 46 };
++static unsigned gpio47_pins[] = { 47 };
++static unsigned gpio48_pins[] = { 48 };
++static unsigned gpio49_pins[] = { 49 };
++static unsigned gpio50_pins[] = { 50 };
++static unsigned gpio51_pins[] = { 51 };
++
++static unsigned nand_grp_pins[] = {
++	2, 3, 4, 5, 6, 7, 24,
++	25, 26, 27, 28, 29, 30, 31,
++};
++
++static unsigned dectpd_grp_pins[] = { 8, 9 };
++static unsigned vdsl_phy0_grp_pins[] = { 10, 11 };
++static unsigned vdsl_phy1_grp_pins[] = { 12, 13 };
++static unsigned vdsl_phy2_grp_pins[] = { 24, 25 };
++static unsigned vdsl_phy3_grp_pins[] = { 26, 27 };
++
++#define BCM63268_GROUP(n)					\
++	{							\
++		.name = #n,					\
++		.pins = n##_pins,				\
++		.num_pins = ARRAY_SIZE(n##_pins),		\
++	}
++
++static struct bcm63268_pingroup bcm63268_groups[] = {
++	BCM63268_GROUP(gpio0),
++	BCM63268_GROUP(gpio1),
++	BCM63268_GROUP(gpio2),
++	BCM63268_GROUP(gpio3),
++	BCM63268_GROUP(gpio4),
++	BCM63268_GROUP(gpio5),
++	BCM63268_GROUP(gpio6),
++	BCM63268_GROUP(gpio7),
++	BCM63268_GROUP(gpio8),
++	BCM63268_GROUP(gpio9),
++	BCM63268_GROUP(gpio10),
++	BCM63268_GROUP(gpio11),
++	BCM63268_GROUP(gpio12),
++	BCM63268_GROUP(gpio13),
++	BCM63268_GROUP(gpio14),
++	BCM63268_GROUP(gpio15),
++	BCM63268_GROUP(gpio16),
++	BCM63268_GROUP(gpio17),
++	BCM63268_GROUP(gpio18),
++	BCM63268_GROUP(gpio19),
++	BCM63268_GROUP(gpio20),
++	BCM63268_GROUP(gpio21),
++	BCM63268_GROUP(gpio22),
++	BCM63268_GROUP(gpio23),
++	BCM63268_GROUP(gpio24),
++	BCM63268_GROUP(gpio25),
++	BCM63268_GROUP(gpio26),
++	BCM63268_GROUP(gpio27),
++	BCM63268_GROUP(gpio28),
++	BCM63268_GROUP(gpio29),
++	BCM63268_GROUP(gpio30),
++	BCM63268_GROUP(gpio31),
++	BCM63268_GROUP(gpio32),
++	BCM63268_GROUP(gpio33),
++	BCM63268_GROUP(gpio34),
++	BCM63268_GROUP(gpio35),
++	BCM63268_GROUP(gpio36),
++	BCM63268_GROUP(gpio37),
++	BCM63268_GROUP(gpio38),
++	BCM63268_GROUP(gpio39),
++	BCM63268_GROUP(gpio40),
++	BCM63268_GROUP(gpio41),
++	BCM63268_GROUP(gpio42),
++	BCM63268_GROUP(gpio43),
++	BCM63268_GROUP(gpio44),
++	BCM63268_GROUP(gpio45),
++	BCM63268_GROUP(gpio46),
++	BCM63268_GROUP(gpio47),
++	BCM63268_GROUP(gpio48),
++	BCM63268_GROUP(gpio49),
++	BCM63268_GROUP(gpio50),
++	BCM63268_GROUP(gpio51),
++
++	/* multi pin groups */
++	BCM63268_GROUP(nand_grp),
++	BCM63268_GROUP(dectpd_grp),
++	BCM63268_GROUP(vdsl_phy0_grp),
++	BCM63268_GROUP(vdsl_phy1_grp),
++	BCM63268_GROUP(vdsl_phy2_grp),
++	BCM63268_GROUP(vdsl_phy3_grp),
++};
++
++static const char * const led_groups[] = {
++	"gpio0",
++	"gpio1",
++	"gpio2",
++	"gpio3",
++	"gpio4",
++	"gpio5",
++	"gpio6",
++	"gpio7",
++	"gpio8",
++	"gpio9",
++	"gpio10",
++	"gpio11",
++	"gpio12",
++	"gpio13",
++	"gpio14",
++	"gpio15",
++	"gpio16",
++	"gpio17",
++	"gpio18",
++	"gpio19",
++	"gpio20",
++	"gpio21",
++	"gpio22",
++	"gpio23",
++};
++
++static const char * const serial_led_clk_groups[] = {
++	"gpio0",
++};
++
++static const char * const serial_led_data_groups[] = {
++	"gpio1",
++};
++
++static const char * const hsspi_cs4_groups[] = {
++	"gpio16",
++};
++
++static const char * const hsspi_cs5_groups[] = {
++	"gpio17",
++};
++
++static const char * const hsspi_cs6_groups[] = {
++	"gpio8",
++};
++
++static const char * const hsspi_cs7_groups[] = {
++	"gpio9",
++};
++
++static const char * const uart1_scts_groups[] = {
++	"gpio10",
++	"gpio24",
++};
++
++static const char * const uart1_srts_groups[] = {
++	"gpio11",
++	"gpio25",
++};
++
++static const char * const uart1_sdin_groups[] = {
++	"gpio12",
++	"gpio26",
++};
++
++static const char * const uart1_sdout_groups[] = {
++	"gpio13",
++	"gpio27",
++};
++
++static const char * const ntr_pulse_in_groups[] = {
++	"gpio14",
++	"gpio28",
++};
++
++static const char * const dsl_ntr_pulse_out_groups[] = {
++	"gpio15",
++	"gpio29",
++};
++
++static const char * const adsl_spi_miso_groups[] = {
++	"gpio18",
++};
++
++static const char * const adsl_spi_mosi_groups[] = {
++	"gpio19",
++};
++
++static const char * const vreg_clk_groups[] = {
++	"gpio22",
++};
++
++static const char * const pcie_clkreq_b_groups[] = {
++	"gpio23",
++};
++
++static const char * const switch_led_clk_groups[] = {
++	"gpio30",
++};
++
++static const char * const switch_led_data_groups[] = {
++	"gpio31",
++};
++
++static const char * const wifi_groups[] = {
++	"gpio32",
++	"gpio33",
++	"gpio34",
++	"gpio35",
++	"gpio36",
++	"gpio37",
++	"gpio38",
++	"gpio39",
++	"gpio40",
++	"gpio41",
++	"gpio42",
++	"gpio43",
++	"gpio44",
++	"gpio45",
++	"gpio46",
++	"gpio47",
++	"gpio48",
++	"gpio49",
++	"gpio50",
++	"gpio51",
++};
++
++static const char * const nand_groups[] = {
++	"nand_grp",
++};
++
++static const char * const dectpd_groups[] = {
++	"dectpd_grp",
++};
++
++static const char * const vdsl_phy_override_0_groups[] = {
++	"vdsl_phy_override_0_grp",
++};
++
++static const char * const vdsl_phy_override_1_groups[] = {
++	"vdsl_phy_override_1_grp",
++};
++
++static const char * const vdsl_phy_override_2_groups[] = {
++	"vdsl_phy_override_2_grp",
++};
++
++static const char * const vdsl_phy_override_3_groups[] = {
++	"vdsl_phy_override_3_grp",
++};
++
++#define BCM63268_LED_FUN(n)				\
++	{						\
++		.name = #n,				\
++		.groups = n##_groups,			\
++		.num_groups = ARRAY_SIZE(n##_groups),	\
++		.reg = BCM63268_LEDCTRL,		\
++	}
++
++#define BCM63268_MODE_FUN(n)				\
++	{						\
++		.name = #n,				\
++		.groups = n##_groups,			\
++		.num_groups = ARRAY_SIZE(n##_groups),	\
++		.reg = BCM63268_MODE,			\
++	}
++
++#define BCM63268_CTRL_FUN(n)				\
++	{						\
++		.name = #n,				\
++		.groups = n##_groups,			\
++		.num_groups = ARRAY_SIZE(n##_groups),	\
++		.reg = BCM63268_CTRL,			\
++	}
++
++#define BCM63268_BASEMODE_FUN(n, val)			\
++	{						\
++		.name = #n,				\
++		.groups = n##_groups,			\
++		.num_groups = ARRAY_SIZE(n##_groups),	\
++		.reg = BCM63268_BASEMODE,		\
++		.mask = val,				\
++	}
++
++static const struct bcm63268_function bcm63268_funcs[] = {
++	BCM63268_LED_FUN(led),
++	BCM63268_MODE_FUN(serial_led_clk),
++	BCM63268_MODE_FUN(serial_led_data),
++	BCM63268_MODE_FUN(hsspi_cs6),
++	BCM63268_MODE_FUN(hsspi_cs7),
++	BCM63268_MODE_FUN(uart1_scts),
++	BCM63268_MODE_FUN(uart1_srts),
++	BCM63268_MODE_FUN(uart1_sdin),
++	BCM63268_MODE_FUN(uart1_sdout),
++	BCM63268_MODE_FUN(ntr_pulse_in),
++	BCM63268_MODE_FUN(dsl_ntr_pulse_out),
++	BCM63268_MODE_FUN(hsspi_cs4),
++	BCM63268_MODE_FUN(hsspi_cs5),
++	BCM63268_MODE_FUN(adsl_spi_miso),
++	BCM63268_MODE_FUN(adsl_spi_mosi),
++	BCM63268_MODE_FUN(vreg_clk),
++	BCM63268_MODE_FUN(pcie_clkreq_b),
++	BCM63268_MODE_FUN(switch_led_clk),
++	BCM63268_MODE_FUN(switch_led_data),
++	BCM63268_CTRL_FUN(wifi),
++	BCM63268_BASEMODE_FUN(nand, BASEMODE_NAND),
++	BCM63268_BASEMODE_FUN(dectpd, BASEMODE_DECTPD),
++	BCM63268_BASEMODE_FUN(vdsl_phy_override_0, BASEMODE_VDSL_PHY_0),
++	BCM63268_BASEMODE_FUN(vdsl_phy_override_1, BASEMODE_VDSL_PHY_1),
++	BCM63268_BASEMODE_FUN(vdsl_phy_override_2, BASEMODE_VDSL_PHY_2),
++	BCM63268_BASEMODE_FUN(vdsl_phy_override_3, BASEMODE_VDSL_PHY_3),
++};
++
++static int bcm63268_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
++{
++	return ARRAY_SIZE(bcm63268_groups);
++}
++
++static const char *bcm63268_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
++						   unsigned group)
++{
++	return bcm63268_groups[group].name;
++}
++
++static int bcm63268_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
++					   unsigned group,
++					   const unsigned **pins,
++					   unsigned *num_pins)
++{
++	*pins = bcm63268_groups[group].pins;
++	*num_pins = bcm63268_groups[group].num_pins;
++
++	return 0;
++}
++
++static int bcm63268_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
++{
++	return ARRAY_SIZE(bcm63268_funcs);
++}
++
++static const char *bcm63268_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
++						  unsigned selector)
++{
++	return bcm63268_funcs[selector].name;
++}
++
++static int bcm63268_pinctrl_get_groups(struct pinctrl_dev *pctldev,
++				       unsigned selector,
++				       const char * const **groups,
++				       unsigned * const num_groups)
++{
++	*groups = bcm63268_funcs[selector].groups;
++	*num_groups = bcm63268_funcs[selector].num_groups;
++
++	return 0;
++}
++
++static void bcm63268_rmw_mux(struct bcm63268_pinctrl *pctl, void __iomem *reg,
++			     u32 mask, u32 val)
++{
++	unsigned long flags;
++	u32 tmp;
++
++	spin_lock_irqsave(&pctl->lock, flags);
++	tmp = __raw_readl(reg);
++	tmp &= ~mask;
++	tmp |= val;
++	__raw_writel(tmp, reg);
++
++	spin_unlock_irqrestore(&pctl->lock, flags);
++}
++
++static void bcm63268_set_gpio(struct bcm63268_pinctrl *pctl, unsigned pin)
++{
++	const struct pinctrl_pin_desc *desc = &bcm63268_pins[pin];
++	u32 basemode = (unsigned long)desc->drv_data;
++	u32 mask = BIT(pin % 32);
++
++	if (basemode)
++		bcm63268_rmw_mux(pctl, pctl->basemode, basemode, 0);
++
++	if (pin < 32) {
++		/* base mode: 0 => gpio, 1 => mux function */
++		bcm63268_rmw_mux(pctl, pctl->mode, mask, 0);
++
++		/* pins 0-23 might be muxed to led */
++		if (pin < 24)
++			bcm63268_rmw_mux(pctl, pctl->led, mask, 0);
++	} else if (pin < 52) {
++		/* ctrl reg: 0 => wifi function, 1 => gpio */
++		bcm63268_rmw_mux(pctl, pctl->ctrl, mask, mask);
++	}
++}
++
++static int bcm63268_pinctrl_set_mux(struct pinctrl_dev *pctldev,
++				    unsigned selector, unsigned group)
++{
++	struct bcm63268_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
++	const struct bcm63268_pingroup *grp = &bcm63268_groups[group];
++	const struct bcm63268_function *f = &bcm63268_funcs[selector];
++	unsigned i;
++	void __iomem *reg;
++	u32 val, mask;
++
++	for (i = 0; i < grp->num_pins; i++)
++		bcm63268_set_gpio(pctl, grp->pins[i]);
++
++	switch (f->reg) {
++	case BCM63268_LEDCTRL:
++		reg = pctl->led;
++		mask = BIT(grp->pins[0]);
++		val = BIT(grp->pins[0]);
++		break;
++	case BCM63268_MODE:
++		reg = pctl->mode;
++		mask = BIT(grp->pins[0]);
++		val = BIT(grp->pins[0]);
++		break;
++	case BCM63268_CTRL:
++		reg = pctl->ctrl;
++		mask = BIT(grp->pins[0]);
++		val = 0;
++		break;
++	case BCM63268_BASEMODE:
++		reg = pctl->basemode;
++		mask = f->mask;
++		val = f->mask;
++		break;
++	default:
++		WARN_ON(1);
++		return -EINVAL;
++	}
++
++	bcm63268_rmw_mux(pctl, reg, mask, val);
++
++	return 0;
++}
++
++static int bcm63268_gpio_request_enable(struct pinctrl_dev *pctldev,
++					struct pinctrl_gpio_range *range,
++					unsigned offset)
++{
++	struct bcm63268_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
++
++	/* disable all functions using this pin */
++	bcm63268_set_gpio(pctl, offset);
++
++	return 0;
++}
++
++static struct pinctrl_ops bcm63268_pctl_ops = {
++	.get_groups_count	= bcm63268_pinctrl_get_group_count,
++	.get_group_name		= bcm63268_pinctrl_get_group_name,
++	.get_group_pins		= bcm63268_pinctrl_get_group_pins,
++#ifdef CONFIG_OF
++	.dt_node_to_map		= pinconf_generic_dt_node_to_map_pin,
++	.dt_free_map		= pinctrl_utils_free_map,
++#endif
++};
++
++static struct pinmux_ops bcm63268_pmx_ops = {
++	.get_functions_count	= bcm63268_pinctrl_get_func_count,
++	.get_function_name	= bcm63268_pinctrl_get_func_name,
++	.get_function_groups	= bcm63268_pinctrl_get_groups,
++	.set_mux		= bcm63268_pinctrl_set_mux,
++	.gpio_request_enable	= bcm63268_gpio_request_enable,
++	.strict			= true,
++};
++
++static int bcm63268_pinctrl_probe(struct platform_device *pdev)
++{
++	struct bcm63268_pinctrl *pctl;
++	struct resource *res;
++	void __iomem *led, *mode, *ctrl, *basemode;
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "led");
++	led = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(led))
++		return PTR_ERR(led);
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mode");
++	mode = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(mode))
++		return PTR_ERR(mode);
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
++	ctrl = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(ctrl))
++		return PTR_ERR(ctrl);
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "basemode");
++	basemode = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(basemode))
++		return PTR_ERR(basemode);
++
++	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
++	if (!pctl)
++		return -ENOMEM;
++
++	spin_lock_init(&pctl->lock);
++
++	pctl->led = led;
++	pctl->mode = mode;
++	pctl->ctrl = ctrl;
++	pctl->basemode = basemode;
++
++	pctl->desc.name = dev_name(&pdev->dev);
++	pctl->desc.owner = THIS_MODULE;
++	pctl->desc.pctlops = &bcm63268_pctl_ops;
++	pctl->desc.pmxops = &bcm63268_pmx_ops;
++
++	pctl->desc.npins = ARRAY_SIZE(bcm63268_pins);
++	pctl->desc.pins = bcm63268_pins;
++
++	platform_set_drvdata(pdev, pctl);
++
++	pctl->pctldev = bcm63xx_pinctrl_register(pdev, &pctl->desc, pctl,
++						 pctl->gpio, BCM63268_NGPIO);
++	if (IS_ERR(pctl->pctldev))
++		return PTR_ERR(pctl->pctldev);
++
++	return 0;
++}
++
++static const struct of_device_id bcm63268_pinctrl_match[] = {
++	{ .compatible = "brcm,bcm63268-pinctrl", },
++	{ },
++};
++
++static struct platform_driver bcm63268_pinctrl_driver = {
++	.probe = bcm63268_pinctrl_probe,
++	.driver = {
++		.name = "bcm63268-pinctrl",
++		.of_match_table = bcm63268_pinctrl_match,
++	},
++};
++
++builtin_platform_driver(bcm63268_pinctrl_driver);

target/linux/brcm63xx/patches-4.9/206-USB-EHCI-allow-limiting-ports-for-ehci-platform.patch

@@ -0,0 +1,66 @@
+From 6ac09efa8f0e189ffe7dd7b0889289de56ee44cc Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 19 Jan 2014 12:18:03 +0100
+Subject: [PATCH] USB: EHCI: allow limiting ports for ehci-platform
+
+In the same way as the ohci platform driver allows limiting ports,
+enable the same for ehci. This prevents a mismatch in the available
+ports between ehci/ohci on USB 2.0 controllers.
+
+This is needed if the USB host controller always reports the maximum
+number of ports regardless of the number of available ports (because
+one might be set to be usb device).
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ drivers/usb/host/ehci-hcd.c      | 4 ++++
+ drivers/usb/host/ehci-platform.c | 2 ++
+ drivers/usb/host/ehci.h          | 1 +
+ include/linux/usb/ehci_pdriver.h | 1 +
+ 4 files changed, 8 insertions(+)
+
+--- a/drivers/usb/host/ehci-hcd.c
++++ b/drivers/usb/host/ehci-hcd.c
+@@ -678,6 +678,10 @@ int ehci_setup(struct usb_hcd *hcd)
+ 
+ 	/* cache this readonly data; minimize chip reads */
+ 	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
++	if (ehci->num_ports) {
++		ehci->hcs_params &= ~0xf; /* bits 3:0, ports on HC */
++		ehci->hcs_params |= ehci->num_ports;
++	}
+ 
+ 	ehci->sbrn = HCD_USB2;
+ 
+--- a/drivers/usb/host/ehci-platform.c
++++ b/drivers/usb/host/ehci-platform.c
+@@ -61,6 +61,9 @@ static int ehci_platform_reset(struct us
+ 
+ 	ehci->has_synopsys_hc_bug = pdata->has_synopsys_hc_bug;
+ 
++	if (pdata->num_ports && pdata->num_ports <= 15)
++		ehci->num_ports = pdata->num_ports;
++
+ 	if (pdata->pre_setup) {
+ 		retval = pdata->pre_setup(hcd);
+ 		if (retval < 0)
+--- a/drivers/usb/host/ehci.h
++++ b/drivers/usb/host/ehci.h
+@@ -216,6 +216,7 @@ struct ehci_hcd {			/* one per controlle
+ 	u32			command;
+ 
+ 	/* SILICON QUIRKS */
++	unsigned int		num_ports;
+ 	unsigned		no_selective_suspend:1;
+ 	unsigned		has_fsl_port_bug:1; /* FreeScale */
+ 	unsigned		has_fsl_hs_errata:1;	/* Freescale HS quirk */
+--- a/include/linux/usb/ehci_pdriver.h
++++ b/include/linux/usb/ehci_pdriver.h
+@@ -42,6 +42,7 @@ struct usb_hcd;
+  */
+ struct usb_ehci_pdata {
+ 	int		caps_offset;
++	unsigned int	num_ports;
+ 	unsigned	has_tt:1;
+ 	unsigned	has_synopsys_hc_bug:1;
+ 	unsigned	big_endian_desc:1;

target/linux/brcm63xx/patches-4.9/207-MIPS-BCM63XX-move-device-registration-code-into-its-.patch

@@ -0,0 +1,492 @@
+From 5a50cb0d53344a2429831b00925d6183d4d332e1 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 9 Mar 2014 03:54:05 +0100
+Subject: [PATCH 40/44] MIPS: BCM63XX: move device registration code into its
+ own file
+
+Move device registration code into its own file to allow sharing it
+between board implementations.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/boards/Makefile         |   1 +
+ arch/mips/bcm63xx/boards/board_bcm963xx.c | 188 +-------------------------
+ arch/mips/bcm63xx/boards/board_common.c   | 215 ++++++++++++++++++++++++++++++
+ arch/mips/bcm63xx/boards/board_common.h   |   8 ++
+ 4 files changed, 223 insertions(+), 183 deletions(-)
+ create mode 100644 arch/mips/bcm63xx/boards/board_common.c
+ create mode 100644 arch/mips/bcm63xx/boards/board_common.h
+
+--- a/arch/mips/bcm63xx/boards/Makefile
++++ b/arch/mips/bcm63xx/boards/Makefile
+@@ -1 +1,2 @@
++obj-y					+= board_common.o
+ obj-$(CONFIG_BOARD_BCM963XX)		+= board_bcm963xx.o
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -12,34 +12,21 @@
+ #include <linux/init.h>
+ #include <linux/kernel.h>
+ #include <linux/string.h>
+-#include <linux/platform_device.h>
+-#include <linux/ssb/ssb.h>
+ #include <asm/addrspace.h>
+ #include <bcm63xx_board.h>
+ #include <bcm63xx_cpu.h>
+-#include <bcm63xx_dev_uart.h>
+ #include <bcm63xx_regs.h>
+ #include <bcm63xx_io.h>
+ #include <bcm63xx_nvram.h>
+-#include <bcm63xx_dev_pci.h>
+-#include <bcm63xx_dev_enet.h>
+-#include <bcm63xx_dev_dsp.h>
+-#include <bcm63xx_dev_flash.h>
+-#include <bcm63xx_dev_hsspi.h>
+-#include <bcm63xx_dev_pcmcia.h>
+-#include <bcm63xx_dev_spi.h>
+-#include <bcm63xx_dev_usb_ehci.h>
+-#include <bcm63xx_dev_usb_ohci.h>
+-#include <bcm63xx_dev_usb_usbd.h>
+ #include <board_bcm963xx.h>
+ 
++#include "board_common.h"
++
+ #include <uapi/linux/bcm933xx_hcs.h>
+ 
+ 
+ #define HCS_OFFSET_128K			0x20000
+ 
+-static struct board_info board;
+-
+ /*
+  * known 3368 boards
+  */
+@@ -712,52 +699,6 @@ static const struct board_info __initcon
+ };
+ 
+ /*
+- * Register a sane SPROMv2 to make the on-board
+- * bcm4318 WLAN work
+- */
+-#ifdef CONFIG_SSB_PCIHOST
+-static struct ssb_sprom bcm63xx_sprom = {
+-	.revision		= 0x02,
+-	.board_rev		= 0x17,
+-	.country_code		= 0x0,
+-	.ant_available_bg	= 0x3,
+-	.pa0b0			= 0x15ae,
+-	.pa0b1			= 0xfa85,
+-	.pa0b2			= 0xfe8d,
+-	.pa1b0			= 0xffff,
+-	.pa1b1			= 0xffff,
+-	.pa1b2			= 0xffff,
+-	.gpio0			= 0xff,
+-	.gpio1			= 0xff,
+-	.gpio2			= 0xff,
+-	.gpio3			= 0xff,
+-	.maxpwr_bg		= 0x004c,
+-	.itssi_bg		= 0x00,
+-	.boardflags_lo		= 0x2848,
+-	.boardflags_hi		= 0x0000,
+-};
+-
+-int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)
+-{
+-	if (bus->bustype == SSB_BUSTYPE_PCI) {
+-		memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom));
+-		return 0;
+-	} else {
+-		pr_err("unable to fill SPROM for given bustype\n");
+-		return -EINVAL;
+-	}
+-}
+-#endif
+-
+-/*
+- * return board name for /proc/cpuinfo
+- */
+-const char *board_get_name(void)
+-{
+-	return board.name;
+-}
+-
+-/*
+  * early init callback, read nvram data from flash and checksum it
+  */
+ void __init board_prom_init(void)
+@@ -802,140 +743,15 @@ void __init board_prom_init(void)
+ 		if (strncmp(board_name, bcm963xx_boards[i]->name, 16))
+ 			continue;
+ 		/* copy, board desc array is marked initdata */
+-		memcpy(&board, bcm963xx_boards[i], sizeof(board));
++		board_early_setup(bcm963xx_boards[i]);
+ 		break;
+ 	}
+ 
+-	/* bail out if board is not found, will complain later */
+-	if (!board.name[0]) {
++	/* warn if board is not found, will complain later */
++	if (i == ARRAY_SIZE(bcm963xx_boards)) {
+ 		char name[17];
+ 		memcpy(name, board_name, 16);
+ 		name[16] = 0;
+ 		pr_err("unknown bcm963xx board: %s\n", name);
+-		return;
+-	}
+-
+-	/* setup pin multiplexing depending on board enabled device,
+-	 * this has to be done this early since PCI init is done
+-	 * inside arch_initcall */
+-	val = 0;
+-
+-#ifdef CONFIG_PCI
+-	if (board.has_pci) {
+-		bcm63xx_pci_enabled = 1;
+-		if (BCMCPU_IS_6348())
+-			val |= GPIO_MODE_6348_G2_PCI;
+-	}
+-#endif
+-
+-	if (board.has_pccard) {
+-		if (BCMCPU_IS_6348())
+-			val |= GPIO_MODE_6348_G1_MII_PCCARD;
+-	}
+-
+-	if (board.has_enet0 && !board.enet0.use_internal_phy) {
+-		if (BCMCPU_IS_6348())
+-			val |= GPIO_MODE_6348_G3_EXT_MII |
+-				GPIO_MODE_6348_G0_EXT_MII;
+-	}
+-
+-	if (board.has_enet1 && !board.enet1.use_internal_phy) {
+-		if (BCMCPU_IS_6348())
+-			val |= GPIO_MODE_6348_G3_EXT_MII |
+-				GPIO_MODE_6348_G0_EXT_MII;
+-	}
+-
+-	bcm_gpio_writel(val, GPIO_MODE_REG);
+-}
+-
+-/*
+- * second stage init callback, good time to panic if we couldn't
+- * identify on which board we're running since early printk is working
+- */
+-void __init board_setup(void)
+-{
+-	if (!board.name[0])
+-		panic("unable to detect bcm963xx board");
+-	pr_info("board name: %s\n", board.name);
+-
+-	/* make sure we're running on expected cpu */
+-	if (bcm63xx_get_cpu_id() != board.expected_cpu_id)
+-		panic("unexpected CPU for bcm963xx board");
+-}
+-
+-static struct gpio_led_platform_data bcm63xx_led_data;
+-
+-static struct platform_device bcm63xx_gpio_leds = {
+-	.name			= "leds-gpio",
+-	.id			= 0,
+-	.dev.platform_data	= &bcm63xx_led_data,
+-};
+-
+-/*
+- * third stage init callback, register all board devices.
+- */
+-int __init board_register_devices(void)
+-{
+-	if (board.has_uart0)
+-		bcm63xx_uart_register(0);
+-
+-	if (board.has_uart1)
+-		bcm63xx_uart_register(1);
+-
+-	if (board.has_pccard)
+-		bcm63xx_pcmcia_register();
+-
+-	if (board.has_enet0 &&
+-	    !bcm63xx_nvram_get_mac_address(board.enet0.mac_addr))
+-		bcm63xx_enet_register(0, &board.enet0);
+-
+-	if (board.has_enet1 &&
+-	    !bcm63xx_nvram_get_mac_address(board.enet1.mac_addr))
+-		bcm63xx_enet_register(1, &board.enet1);
+-
+-	if (board.has_enetsw &&
+-	    !bcm63xx_nvram_get_mac_address(board.enetsw.mac_addr))
+-		bcm63xx_enetsw_register(&board.enetsw);
+-
+-	if (board.has_usbd)
+-		bcm63xx_usbd_register(&board.usbd);
+-
+-	if (board.has_ehci0)
+-		bcm63xx_ehci_register();
+-
+-	if (board.has_ohci0)
+-		bcm63xx_ohci_register();
+-
+-	if (board.has_dsp)
+-		bcm63xx_dsp_register(&board.dsp);
+-
+-	/* Generate MAC address for WLAN and register our SPROM,
+-	 * do this after registering enet devices
+-	 */
+-#ifdef CONFIG_SSB_PCIHOST
+-	if (!bcm63xx_nvram_get_mac_address(bcm63xx_sprom.il0mac)) {
+-		memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
+-		memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
+-		if (ssb_arch_register_fallback_sprom(
+-				&bcm63xx_get_fallback_sprom) < 0)
+-			pr_err("failed to register fallback SPROM\n");
+ 	}
+-#endif
+-
+-	bcm63xx_spi_register();
+-
+-	bcm63xx_hsspi_register();
+-
+-	bcm63xx_flash_register();
+-
+-	bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds);
+-	bcm63xx_led_data.leds = board.leds;
+-
+-	platform_device_register(&bcm63xx_gpio_leds);
+-
+-	if (board.ephy_reset_gpio && board.ephy_reset_gpio_flags)
+-		gpio_request_one(board.ephy_reset_gpio,
+-				board.ephy_reset_gpio_flags, "ephy-reset");
+-
+-	return 0;
+ }
+--- /dev/null
++++ b/arch/mips/bcm63xx/boards/board_common.c
+@@ -0,0 +1,218 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <[email protected]>
++ * Copyright (C) 2008 Florian Fainelli <[email protected]>
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/string.h>
++#include <linux/platform_device.h>
++#include <linux/ssb/ssb.h>
++#include <asm/addrspace.h>
++#include <bcm63xx_board.h>
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_dev_uart.h>
++#include <bcm63xx_regs.h>
++#include <bcm63xx_io.h>
++#include <bcm63xx_nvram.h>
++#include <bcm63xx_gpio.h>
++#include <bcm63xx_dev_pci.h>
++#include <bcm63xx_dev_enet.h>
++#include <bcm63xx_dev_dsp.h>
++#include <bcm63xx_dev_flash.h>
++#include <bcm63xx_dev_hsspi.h>
++#include <bcm63xx_dev_pcmcia.h>
++#include <bcm63xx_dev_spi.h>
++#include <bcm63xx_dev_usb_ehci.h>
++#include <bcm63xx_dev_usb_ohci.h>
++#include <bcm63xx_dev_usb_usbd.h>
++#include <board_bcm963xx.h>
++
++#define PFX	"board: "
++
++static struct board_info board;
++
++/*
++ * Register a sane SPROMv2 to make the on-board
++ * bcm4318 WLAN work
++ */
++#ifdef CONFIG_SSB_PCIHOST
++static struct ssb_sprom bcm63xx_sprom = {
++	.revision		= 0x02,
++	.board_rev		= 0x17,
++	.country_code		= 0x0,
++	.ant_available_bg	= 0x3,
++	.pa0b0			= 0x15ae,
++	.pa0b1			= 0xfa85,
++	.pa0b2			= 0xfe8d,
++	.pa1b0			= 0xffff,
++	.pa1b1			= 0xffff,
++	.pa1b2			= 0xffff,
++	.gpio0			= 0xff,
++	.gpio1			= 0xff,
++	.gpio2			= 0xff,
++	.gpio3			= 0xff,
++	.maxpwr_bg		= 0x004c,
++	.itssi_bg		= 0x00,
++	.boardflags_lo		= 0x2848,
++	.boardflags_hi		= 0x0000,
++};
++
++int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)
++{
++	if (bus->bustype == SSB_BUSTYPE_PCI) {
++		memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom));
++		return 0;
++	} else {
++		printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n");
++		return -EINVAL;
++	}
++}
++#endif
++
++/*
++ * return board name for /proc/cpuinfo
++ */
++const char *board_get_name(void)
++{
++	return board.name;
++}
++
++/*
++ * setup board for device registration
++ */
++void __init board_early_setup(const struct board_info *target)
++{
++	u32 val;
++
++	memcpy(&board, target, sizeof(board));
++
++	/* setup pin multiplexing depending on board enabled device,
++	 * this has to be done this early since PCI init is done
++	 * inside arch_initcall */
++	val = 0;
++
++#ifdef CONFIG_PCI
++	if (board.has_pci) {
++		bcm63xx_pci_enabled = 1;
++		if (BCMCPU_IS_6348())
++			val |= GPIO_MODE_6348_G2_PCI;
++	}
++#endif
++
++	if (board.has_pccard) {
++		if (BCMCPU_IS_6348())
++			val |= GPIO_MODE_6348_G1_MII_PCCARD;
++	}
++
++	if (board.has_enet0 && !board.enet0.use_internal_phy) {
++		if (BCMCPU_IS_6348())
++			val |= GPIO_MODE_6348_G3_EXT_MII |
++				GPIO_MODE_6348_G0_EXT_MII;
++	}
++
++	if (board.has_enet1 && !board.enet1.use_internal_phy) {
++		if (BCMCPU_IS_6348())
++			val |= GPIO_MODE_6348_G3_EXT_MII |
++				GPIO_MODE_6348_G0_EXT_MII;
++	}
++
++	bcm_gpio_writel(val, GPIO_MODE_REG);
++}
++
++
++/*
++ * second stage init callback, good time to panic if we couldn't
++ * identify on which board we're running since early printk is working
++ */
++void __init board_setup(void)
++{
++	if (!board.name[0])
++		panic("unable to detect bcm963xx board");
++	printk(KERN_INFO PFX "board name: %s\n", board.name);
++
++	/* make sure we're running on expected cpu */
++	if (bcm63xx_get_cpu_id() != board.expected_cpu_id)
++		panic("unexpected CPU for bcm963xx board");
++}
++
++static struct gpio_led_platform_data bcm63xx_led_data;
++
++static struct platform_device bcm63xx_gpio_leds = {
++	.name			= "leds-gpio",
++	.id			= 0,
++	.dev.platform_data	= &bcm63xx_led_data,
++};
++
++/*
++ * third stage init callback, register all board devices.
++ */
++int __init board_register_devices(void)
++{
++	if (board.has_uart0)
++		bcm63xx_uart_register(0);
++
++	if (board.has_uart1)
++		bcm63xx_uart_register(1);
++
++	if (board.has_pccard)
++		bcm63xx_pcmcia_register();
++
++	if (board.has_enet0 &&
++	    !bcm63xx_nvram_get_mac_address(board.enet0.mac_addr))
++		bcm63xx_enet_register(0, &board.enet0);
++
++	if (board.has_enet1 &&
++	    !bcm63xx_nvram_get_mac_address(board.enet1.mac_addr))
++		bcm63xx_enet_register(1, &board.enet1);
++
++	if (board.has_enetsw &&
++	    !bcm63xx_nvram_get_mac_address(board.enetsw.mac_addr))
++		bcm63xx_enetsw_register(&board.enetsw);
++
++	if (board.has_usbd)
++		bcm63xx_usbd_register(&board.usbd);
++
++	if (board.has_ehci0)
++		bcm63xx_ehci_register();
++
++	if (board.has_ohci0)
++		bcm63xx_ohci_register();
++
++	if (board.has_dsp)
++		bcm63xx_dsp_register(&board.dsp);
++
++	/* Generate MAC address for WLAN and register our SPROM,
++	 * do this after registering enet devices
++	 */
++#ifdef CONFIG_SSB_PCIHOST
++	if (!bcm63xx_nvram_get_mac_address(bcm63xx_sprom.il0mac)) {
++		memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
++		memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
++		if (ssb_arch_register_fallback_sprom(
++				&bcm63xx_get_fallback_sprom) < 0)
++			pr_err(PFX "failed to register fallback SPROM\n");
++	}
++#endif
++
++	bcm63xx_spi_register();
++
++	bcm63xx_hsspi_register();
++
++	bcm63xx_flash_register();
++
++	bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds);
++	bcm63xx_led_data.leds = board.leds;
++
++	platform_device_register(&bcm63xx_gpio_leds);
++
++	if (board.ephy_reset_gpio && board.ephy_reset_gpio_flags)
++		gpio_request_one(board.ephy_reset_gpio,
++				board.ephy_reset_gpio_flags, "ephy-reset");
++
++	return 0;
++}
+--- /dev/null
++++ b/arch/mips/bcm63xx/boards/board_common.h
+@@ -0,0 +1,8 @@
++#ifndef __BOARD_COMMON_H
++#define __BOARD_COMMON_H
++
++#include <board_bcm963xx.h>
++
++void board_early_setup(const struct board_info *board);
++
++#endif /* __BOARD_COMMON_H */

target/linux/brcm63xx/patches-4.9/208-MIPS-BCM63XX-pass-a-mac-addresss-allocator-to-board-.patch

@@ -0,0 +1,100 @@
+From 4e9c34a37bd3442b286ba55441bfe22c1ac5b65f Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 9 Mar 2014 04:08:06 +0100
+Subject: [PATCH 41/44] MIPS: BCM63XX: pass a mac addresss allocator to board
+ setup
+
+Pass a mac address allocator to board setup code to allow board
+implementations to work with third party bootloaders not using nvram
+for configuration storage.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/boards/board_bcm963xx.c |  3 ++-
+ arch/mips/bcm63xx/boards/board_common.c   | 16 ++++++++++------
+ arch/mips/bcm63xx/boards/board_common.h   |  3 ++-
+ 3 files changed, 14 insertions(+), 8 deletions(-)
+
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -743,7 +743,8 @@ void __init board_prom_init(void)
+ 		if (strncmp(board_name, bcm963xx_boards[i]->name, 16))
+ 			continue;
+ 		/* copy, board desc array is marked initdata */
+-		board_early_setup(bcm963xx_boards[i]);
++		board_early_setup(bcm963xx_boards[i],
++				  bcm63xx_nvram_get_mac_address);
+ 		break;
+ 	}
+ 
+--- a/arch/mips/bcm63xx/boards/board_common.c
++++ b/arch/mips/bcm63xx/boards/board_common.c
+@@ -18,7 +18,6 @@
+ #include <bcm63xx_dev_uart.h>
+ #include <bcm63xx_regs.h>
+ #include <bcm63xx_io.h>
+-#include <bcm63xx_nvram.h>
+ #include <bcm63xx_gpio.h>
+ #include <bcm63xx_dev_pci.h>
+ #include <bcm63xx_dev_enet.h>
+@@ -82,15 +81,20 @@ const char *board_get_name(void)
+ 	return board.name;
+ }
+ 
++static int (*board_get_mac_address)(u8 mac[ETH_ALEN]);
++
+ /*
+  * setup board for device registration
+  */
+-void __init board_early_setup(const struct board_info *target)
++void __init board_early_setup(const struct board_info *target,
++			      int (*get_mac_address)(u8 mac[ETH_ALEN]))
+ {
+ 	u32 val;
+ 
+ 	memcpy(&board, target, sizeof(board));
+ 
++	board_get_mac_address = get_mac_address;
++
+ 	/* setup pin multiplexing depending on board enabled device,
+ 	 * this has to be done this early since PCI init is done
+ 	 * inside arch_initcall */
+@@ -163,15 +167,15 @@ int __init board_register_devices(void)
+ 		bcm63xx_pcmcia_register();
+ 
+ 	if (board.has_enet0 &&
+-	    !bcm63xx_nvram_get_mac_address(board.enet0.mac_addr))
++	    !board_get_mac_address(board.enet0.mac_addr))
+ 		bcm63xx_enet_register(0, &board.enet0);
+ 
+ 	if (board.has_enet1 &&
+-	    !bcm63xx_nvram_get_mac_address(board.enet1.mac_addr))
++	    !board_get_mac_address(board.enet1.mac_addr))
+ 		bcm63xx_enet_register(1, &board.enet1);
+ 
+ 	if (board.has_enetsw &&
+-	    !bcm63xx_nvram_get_mac_address(board.enetsw.mac_addr))
++	    !board_get_mac_address(board.enetsw.mac_addr))
+ 		bcm63xx_enetsw_register(&board.enetsw);
+ 
+ 	if (board.has_usbd)
+@@ -190,7 +194,7 @@ int __init board_register_devices(void)
+ 	 * do this after registering enet devices
+ 	 */
+ #ifdef CONFIG_SSB_PCIHOST
+-	if (!bcm63xx_nvram_get_mac_address(bcm63xx_sprom.il0mac)) {
++	if (!board_get_mac_address(bcm63xx_sprom.il0mac)) {
+ 		memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
+ 		memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
+ 		if (ssb_arch_register_fallback_sprom(
+--- a/arch/mips/bcm63xx/boards/board_common.h
++++ b/arch/mips/bcm63xx/boards/board_common.h
+@@ -3,6 +3,7 @@
+ 
+ #include <board_bcm963xx.h>
+ 
+-void board_early_setup(const struct board_info *board);
++void board_early_setup(const struct board_info *board,
++		       int (*get_mac_address)(u8 mac[ETH_ALEN]));
+ 
+ #endif /* __BOARD_COMMON_H */

target/linux/brcm63xx/patches-4.9/309-cfe_version_mod.patch

@@ -0,0 +1,27 @@
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -723,10 +723,20 @@ void __init board_prom_init(void)
+ 
+ 	/* dump cfe version */
+ 	cfe = boot_addr + BCM963XX_CFE_VERSION_OFFSET;
+-	if (!memcmp(cfe, "cfe-v", 5))
+-		snprintf(cfe_version, sizeof(cfe_version), "%u.%u.%u-%u.%u",
+-			 cfe[5], cfe[6], cfe[7], cfe[8], cfe[9]);
+-	else
++	if (strstarts(cfe, "cfe-")) {
++		if(cfe[4] == 'v') {
++			if(cfe[5] == 'd')
++				snprintf(cfe_version, 11, "%s", (char *) &cfe[5]);
++			else if (cfe[10] > 0)
++				snprintf(cfe_version, sizeof(cfe_version), "%u.%u.%u-%u.%u-%u",
++					 cfe[5], cfe[6], cfe[7], cfe[8], cfe[9], cfe[10]);
++			else
++				snprintf(cfe_version, sizeof(cfe_version), "%u.%u.%u-%u.%u",
++					 cfe[5], cfe[6], cfe[7], cfe[8], cfe[9]);
++		} else {
++			snprintf(cfe_version, 12, "%s", (char *) &cfe[4]);
++		}
++	} else
+ 		strcpy(cfe_version, "unknown");
+ 	pr_info("CFE version: %s\n", cfe_version);
+ 

target/linux/brcm63xx/patches-4.9/310-cfe_simplify_detection.patch

@@ -0,0 +1,20 @@
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h
+@@ -1,6 +1,8 @@
+ #ifndef BCM63XX_BOARD_H_
+ #define BCM63XX_BOARD_H_
+ 
++#include <asm/bootinfo.h>
++
+ const char *board_get_name(void);
+ 
+ void board_prom_init(void);
+@@ -9,4 +11,8 @@ void board_setup(void);
+ 
+ int board_register_devices(void);
+ 
++static inline bool bcm63xx_is_cfe_present(void) {
++	return fw_arg3 == 0x43464531;
++}
++
+ #endif /* ! BCM63XX_BOARD_H_ */

target/linux/brcm63xx/patches-4.9/311-bcm63xxpart_use_cfedetection.patch

@@ -0,0 +1,51 @@
+--- a/drivers/mtd/bcm63xxpart.c
++++ b/drivers/mtd/bcm63xxpart.c
+@@ -35,6 +35,8 @@
+ #include <linux/mtd/mtd.h>
+ #include <linux/mtd/partitions.h>
+ #include <linux/of.h>
++ 
++#include <asm/mach-bcm63xx/bcm63xx_board.h>
+ 
+ #define BCM963XX_CFE_BLOCK_SIZE		SZ_64K	/* always at least 64KiB */
+ 
+@@ -46,30 +48,6 @@
+ #define STR_NULL_TERMINATE(x) \
+ 	do { char *_str = (x); _str[sizeof(x) - 1] = 0; } while (0)
+ 
+-static int bcm63xx_detect_cfe(struct mtd_info *master)
+-{
+-	char buf[9];
+-	int ret;
+-	size_t retlen;
+-
+-	ret = mtd_read(master, BCM963XX_CFE_VERSION_OFFSET, 5, &retlen,
+-		       (void *)buf);
+-	buf[retlen] = 0;
+-
+-	if (ret)
+-		return ret;
+-
+-	if (strncmp("cfe-v", buf, 5) == 0)
+-		return 0;
+-
+-	/* very old CFE's do not have the cfe-v string, so check for magic */
+-	ret = mtd_read(master, BCM963XX_CFE_MAGIC_OFFSET, 8, &retlen,
+-		       (void *)buf);
+-	buf[retlen] = 0;
+-
+-	return strncmp("CFE1CFE1", buf, 8);
+-}
+-
+ static int bcm63xx_read_nvram(struct mtd_info *master,
+ 	struct bcm963xx_nvram *nvram)
+ {
+@@ -152,7 +130,7 @@ static int bcm63xx_parse_cfe_partitions(
+ 	struct bcm963xx_nvram *nvram = NULL;
+ 	int ret;
+ 
+-	if (bcm63xx_detect_cfe(master))
++	if (!bcm63xx_is_cfe_present())
+ 		return -EINVAL;
+ 
+ 	nvram = vzalloc(sizeof(*nvram));

target/linux/brcm63xx/patches-4.9/320-irqchip-add-support-for-bcm6345-style-periphery-irq-.patch

@@ -0,0 +1,455 @@
+From 301744ecbeece89ab3a9d6beef7802fa22598f00 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 30 Nov 2014 14:53:12 +0100
+Subject: [PATCH 1/5] irqchip: add support for bcm6345-style periphery irq
+ controller
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ .../brcm,bcm6345-periph-intc.txt                   |   50 +++
+ drivers/irqchip/Kconfig                            |    4 +
+ drivers/irqchip/Makefile                           |    1 +
+ drivers/irqchip/irq-bcm6345-periph.c               |  339 ++++++++++++++++++++
+ include/linux/irqchip/irq-bcm6345-periph.h         |   16 +
+ 5 files changed, 410 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-periph-intc.txt
+ create mode 100644 drivers/irqchip/irq-bcm6345-periph.c
+ create mode 100644 include/linux/irqchip/irq-bcm6345-periph.h
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-periph-intc.txt
+@@ -0,0 +1,50 @@
++Broadcom BCM6345 Level 1 periphery interrupt controller
++
++This block is a  interrupt controller that is typically connected directly
++to one of the HW INT lines on each CPU.  Every BCM63XX xDSL chip since
++BCM6345 has contained this hardware.
++
++Key elements of the hardware design include:
++
++- 32, 64, or 128 incoming level IRQ lines
++
++- All onchip peripherals are wired directly to an L2 input
++
++- A separate instance of the register set for each CPU, allowing individual
++  peripheral IRQs to be routed to any CPU
++
++- No atomic mask/unmask operations
++
++- No polarity/level/edge settings
++
++- No FIFO or priority encoder logic; software is expected to read all
++  1-4 status words to determine which IRQs are pending
++
++Required properties:
++
++- compatible: Should be "brcm,bcm6345-periph-intc".
++- reg: Specifies the base physical address and size of the registers.
++  Multiple register addresses may be specified, and must match the amount of
++  parent interrupts.
++- interrupt-controller: Identifies the node as an interrupt controller.
++- #interrupt-cells: Specifies the number of cells needed to encode an interrupt
++  source, should be 1.
++- interrupt-parent: Specifies the phandle to the parent interrupt controller
++  this one is cascaded from.
++- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller
++  node, valid values depend on the type of parent interrupt controller.
++  Multiple lines are used to route interrupts to different cpus, with the first
++  assumed to be for the boot CPU.
++
++Example:
++
++periph_intc: interrupt-controller@f0406800 {
++	compatible = "brcm,bcm6345-periph-intc";
++	reg = <0x10000020 0x10>, <0x10000030 0x10>;
++
++	interrupt-controller;
++	#interrupt-cells = <1>;
++
++	interrupt-parent = <&cpu_intc>;
++	interrupts = <2>, <3>;
++};
+--- a/drivers/irqchip/Kconfig
++++ b/drivers/irqchip/Kconfig
+@@ -110,6 +110,10 @@ config BRCMSTB_L2_IRQ
+ 	select GENERIC_IRQ_CHIP
+ 	select IRQ_DOMAIN
+ 
++config BCM6345_PERIPH_IRQ
++	bool
++	select IRQ_DOMAIN
++
+ config DW_APB_ICTL
+ 	bool
+ 	select GENERIC_IRQ_CHIP
+--- a/drivers/irqchip/Makefile
++++ b/drivers/irqchip/Makefile
+@@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_MMP)			+= irq-mmp.o
+ obj-$(CONFIG_IRQ_MXS)			+= irq-mxs.o
+ obj-$(CONFIG_ARCH_TEGRA)		+= irq-tegra.o
+ obj-$(CONFIG_ARCH_S3C24XX)		+= irq-s3c24xx.o
++obj-$(CONFIG_BCM6345_PERIPH_IRQ)	+= irq-bcm6345-periph.o
+ obj-$(CONFIG_DW_APB_ICTL)		+= irq-dw-apb-ictl.o
+ obj-$(CONFIG_METAG)			+= irq-metag-ext.o
+ obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)	+= irq-metag.o
+--- /dev/null
++++ b/drivers/irqchip/irq-bcm6345-periph.c
+@@ -0,0 +1,339 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2014 Jonas Gorski <[email protected]>
++ */
++
++#include <linux/ioport.h>
++#include <linux/irq.h>
++#include <linux/irqchip.h>
++#include <linux/irqchip/chained_irq.h>
++#include <linux/irqchip/irq-bcm6345-periph.h>
++#include <linux/kernel.h>
++#include <linux/of.h>
++#include <linux/of_irq.h>
++#include <linux/of_address.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++
++#ifdef CONFIG_BCM63XX
++#include <asm/mach-bcm63xx/bcm63xx_irq.h>
++
++#define VIRQ_BASE	IRQ_INTERNAL_BASE
++#else
++#define VIRQ_BASE	0
++#endif
++
++#define MAX_WORDS	4
++#define MAX_PARENT_IRQS	2
++#define IRQS_PER_WORD	32
++
++struct intc_block {
++	int parent_irq;
++	void __iomem *base;
++	void __iomem *en_reg[MAX_WORDS];
++	void __iomem *status_reg[MAX_WORDS];
++	u32 mask_cache[MAX_WORDS];
++};
++
++struct intc_data {
++	struct irq_chip chip;
++	struct intc_block block[MAX_PARENT_IRQS];
++
++	int num_words;
++
++	struct irq_domain *domain;
++	raw_spinlock_t lock;
++};
++
++static void bcm6345_periph_irq_handle(struct irq_desc *desc)
++{
++	struct intc_data *data = irq_desc_get_handler_data(desc);
++	struct irq_chip *chip = irq_desc_get_chip(desc);
++	struct intc_block *block;
++	unsigned int irq = irq_desc_get_irq(desc);
++	unsigned int idx;
++
++	chained_irq_enter(chip, desc);
++
++	for (idx = 0; idx < MAX_PARENT_IRQS; idx++)
++		if (irq == data->block[idx].parent_irq)
++			block = &data->block[idx];
++
++	for (idx = 0; idx < data->num_words; idx++) {
++		int base = idx * IRQS_PER_WORD;
++		unsigned long pending;
++		int hw_irq;
++
++		raw_spin_lock(&data->lock);
++		pending = __raw_readl(block->en_reg[idx]) &
++			  __raw_readl(block->status_reg[idx]);
++		raw_spin_unlock(&data->lock);
++
++		for_each_set_bit(hw_irq, &pending, IRQS_PER_WORD) {
++			int virq;
++
++			virq  = irq_find_mapping(data->domain, base + hw_irq);
++			generic_handle_irq(virq);
++		}
++	}
++
++	chained_irq_exit(chip, desc);
++}
++
++static void __bcm6345_periph_enable(struct intc_block *block, int reg, int bit,
++				    bool enable)
++{
++	u32 val;
++
++	val = __raw_readl(block->en_reg[reg]);
++	if (enable)
++		val |= BIT(bit);
++	else
++		val &= ~BIT(bit);
++	__raw_writel(val, block->en_reg[reg]);
++}
++
++static void bcm6345_periph_irq_mask(struct irq_data *data)
++{
++	unsigned int i, reg, bit;
++	struct intc_data *priv = data->domain->host_data;
++	irq_hw_number_t hwirq = irqd_to_hwirq(data);
++
++	reg = hwirq / IRQS_PER_WORD;
++	bit = hwirq % IRQS_PER_WORD;
++
++	raw_spin_lock(&priv->lock);
++	for (i = 0; i < MAX_PARENT_IRQS; i++) {
++		struct intc_block *block = &priv->block[i];
++
++		if (!block->parent_irq)
++			break;
++
++		__bcm6345_periph_enable(block, reg, bit, false);
++	}
++	raw_spin_unlock(&priv->lock);
++}
++
++static void bcm6345_periph_irq_unmask(struct irq_data *data)
++{
++	struct intc_data *priv = data->domain->host_data;
++	irq_hw_number_t hwirq = irqd_to_hwirq(data);
++	unsigned int i, reg, bit;
++
++	reg = hwirq / IRQS_PER_WORD;
++	bit = hwirq % IRQS_PER_WORD;
++
++	raw_spin_lock(&priv->lock);
++	for (i = 0; i < MAX_PARENT_IRQS; i++) {
++		struct intc_block *block = &priv->block[i];
++
++		if (!block->parent_irq)
++			break;
++
++		if (block->mask_cache[reg] & BIT(bit))
++			__bcm6345_periph_enable(block, reg, bit, true);
++		else
++			__bcm6345_periph_enable(block, reg, bit, false);
++	}
++	raw_spin_unlock(&priv->lock);
++}
++
++#ifdef CONFIG_SMP
++static int bcm6345_periph_set_affinity(struct irq_data *data,
++				       const struct cpumask *mask, bool force)
++{
++	irq_hw_number_t hwirq = irqd_to_hwirq(data);
++	struct intc_data *priv = data->domain->host_data;
++	unsigned int i, reg, bit;
++	unsigned long flags;
++	bool enabled;
++	int cpu;
++
++	reg = hwirq / IRQS_PER_WORD;
++	bit = hwirq % IRQS_PER_WORD;
++
++	/* we could route to more than one cpu, but performance
++	   suffers, so fix it to one.
++	 */
++	cpu = cpumask_any_and(mask, cpu_online_mask);
++	if (cpu >= nr_cpu_ids)
++		return -EINVAL;
++
++	if (cpu >= MAX_PARENT_IRQS)
++		return -EINVAL;
++
++	if (!priv->block[cpu].parent_irq)
++		return -EINVAL;
++
++	raw_spin_lock_irqsave(&priv->lock, flags);
++	enabled = !irqd_irq_masked(data);
++	for (i = 0; i < MAX_PARENT_IRQS; i++) {
++		struct intc_block *block = &priv->block[i];
++
++		if (!block->parent_irq)
++			break;
++
++		if (i == cpu) {
++			block->mask_cache[reg] |= BIT(bit);
++			__bcm6345_periph_enable(block, reg, bit, enabled);
++		} else {
++			block->mask_cache[reg] &= ~BIT(bit);
++			__bcm6345_periph_enable(block, reg, bit, false);
++		}
++	}
++	raw_spin_unlock_irqrestore(&priv->lock, flags);
++
++	return 0;
++}
++#endif
++
++static int bcm6345_periph_map(struct irq_domain *d, unsigned int irq,
++			      irq_hw_number_t hw)
++{
++	struct intc_data *priv = d->host_data;
++
++	irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq);
++
++	return 0;
++}
++
++static const struct irq_domain_ops bcm6345_periph_domain_ops = {
++	.xlate = irq_domain_xlate_onecell,
++	.map = bcm6345_periph_map,
++};
++
++static int __init __bcm6345_periph_intc_init(struct device_node *node,
++					     int num_blocks, int *irq,
++					     void __iomem **base, int num_words)
++{
++	struct intc_data *data;
++	unsigned int i, w, status_offset;
++
++	data = kzalloc(sizeof(*data), GFP_KERNEL);
++	if (!data)
++		return -ENOMEM;
++
++	raw_spin_lock_init(&data->lock);
++
++	status_offset = num_words * sizeof(u32);
++
++	for (i = 0; i < num_blocks; i++) {
++		struct intc_block *block = &data->block[i];
++
++		block->parent_irq = irq[i];
++		block->base = base[i];
++
++		for (w = 0; w < num_words; w++) {
++			int word_offset = sizeof(u32) * ((num_words - w) - 1);
++
++			block->en_reg[w] = base[i] + word_offset;
++			block->status_reg[w] = base[i] + status_offset;
++			block->status_reg[w] += word_offset;
++
++			/* route all interrupts to line 0 by default */
++			if (i == 0)
++				block->mask_cache[w] = 0xffffffff;
++		}
++
++		irq_set_handler_data(block->parent_irq, data);
++		irq_set_chained_handler(block->parent_irq,
++					bcm6345_periph_irq_handle);
++	}
++
++	data->num_words = num_words;
++
++	data->chip.name = "bcm6345-periph-intc";
++	data->chip.irq_mask = bcm6345_periph_irq_mask;
++	data->chip.irq_unmask = bcm6345_periph_irq_unmask;
++
++#ifdef CONFIG_SMP
++	if (num_blocks > 1)
++		data->chip.irq_set_affinity = bcm6345_periph_set_affinity;
++#endif
++
++	data->domain = irq_domain_add_simple(node, IRQS_PER_WORD * num_words,
++					     VIRQ_BASE,
++					     &bcm6345_periph_domain_ops, data);
++	if (!data->domain) {
++		kfree(data);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++void __init bcm6345_periph_intc_init(int num_blocks, int *irq,
++				     void __iomem **base, int num_words)
++{
++	__bcm6345_periph_intc_init(NULL, num_blocks, irq, base, num_words);
++}
++
++#ifdef CONFIG_OF
++static int __init bcm6345_periph_of_init(struct device_node *node,
++					 struct device_node *parent)
++{
++	struct resource res;
++	int num_irqs, ret = -EINVAL;
++	int irqs[MAX_PARENT_IRQS] = { 0 };
++	void __iomem *bases[MAX_PARENT_IRQS] = { NULL };
++	int words = 0;
++	int i;
++
++	num_irqs = of_irq_count(node);
++
++	if (num_irqs < 1 || num_irqs > MAX_PARENT_IRQS)
++		return -EINVAL;
++
++	for (i = 0; i < num_irqs; i++) {
++		resource_size_t size;
++
++		irqs[i] = irq_of_parse_and_map(node, i);
++		if (!irqs[i])
++			goto out_unmap;
++
++		if (of_address_to_resource(node, i, &res))
++			goto out_unmap;
++
++		size = resource_size(&res);
++		switch (size) {
++		case 8:
++		case 16:
++		case 32:
++			size = size / 8;
++			break;
++		default:
++			goto out_unmap;
++		}
++
++		if (words && words != size) {
++			ret = -EINVAL;
++			goto out_unmap;
++		}
++		words = size;
++
++		bases[i] = of_iomap(node, i);
++		if (!bases[i]) {
++			ret = -ENOMEM;
++			goto out_unmap;
++		}
++	}
++
++	ret = __bcm6345_periph_intc_init(node, num_irqs, irqs, bases, words);
++	if (!ret)
++		return 0;
++
++out_unmap:
++	for (i = 0; i < num_irqs; i++) {
++		iounmap(bases[i]);
++		irq_dispose_mapping(irqs[i]);
++	}
++
++	return ret;
++}
++
++IRQCHIP_DECLARE(bcm6345_periph_intc, "brcm,bcm6345-l1-intc",
++		bcm6345_periph_of_init);
++#endif
+--- /dev/null
++++ b/include/linux/irqchip/irq-bcm6345-periph.h
+@@ -0,0 +1,16 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <[email protected]>
++ * Copyright (C) 2008 Nicolas Schichan <[email protected]>
++ */
++
++#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H
++#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H
++
++void bcm6345_periph_intc_init(int num_blocks, int *irq, void __iomem **base,
++			      int num_words);
++
++#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H */

target/linux/brcm63xx/patches-4.9/321-irqchip-add-support-for-bcm6345-style-external-inter.patch

@@ -0,0 +1,394 @@
+From cf908990d4a8ccdb73ee4484aa8cadad379ca314 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 30 Nov 2014 14:54:27 +0100
+Subject: [PATCH 2/5] irqchip: add support for bcm6345-style external
+ interrupt controller
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ .../interrupt-controller/brcm,bcm6345-ext-intc.txt |   29 ++
+ drivers/irqchip/Kconfig                            |    4 +
+ drivers/irqchip/Makefile                           |    1 +
+ drivers/irqchip/irq-bcm6345-ext.c                  |  287 ++++++++++++++++++++
+ include/linux/irqchip/irq-bcm6345-ext.h            |   14 +
+ 5 files changed, 335 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt
+ create mode 100644 drivers/irqchip/irq-bcm6345-ext.c
+ create mode 100644 include/linux/irqchip/irq-bcm6345-ext.h
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt
+@@ -0,0 +1,29 @@
++Broadcom BCM6345-style external interrupt controller
++
++Required properties:
++
++- compatible: Should be "brcm,bcm6345-ext-intc" or "brcm,bcm6318-ext-intc".
++- reg: Specifies the base physical addresses and size of the registers.
++- interrupt-controller: identifies the node as an interrupt controller.
++- #interrupt-cells: Specifies the number of cells needed to encode an interrupt
++  source, Should be 2.
++- interrupt-parent: Specifies the phandle to the parent interrupt controller
++  this one is cascaded from.
++- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller
++  node, valid values depend on the type of parent interrupt controller.
++
++Optional properties:
++
++- brcm,field-width: Size of each field (mask, clear, sense, ...) in bits in the
++  register. Defaults to 4.
++
++Example:
++
++ext_intc: interrupt-controller@10000018 {
++	compatible = "brcm,bcm6345-ext-intc";
++	interrupt-parent = <&periph_intc>;
++	#interrupt-cells = <2>;
++	reg = <0x10000018 0x4>;
++	interrupt-controller;
++	interrupts = <24>, <25>, <26>, <27>;
++};
+--- a/drivers/irqchip/Kconfig
++++ b/drivers/irqchip/Kconfig
+@@ -110,6 +110,10 @@ config BRCMSTB_L2_IRQ
+ 	select GENERIC_IRQ_CHIP
+ 	select IRQ_DOMAIN
+ 
++config BCM6345_EXT_IRQ
++	bool
++	select IRQ_DOMAIN
++
+ config BCM6345_PERIPH_IRQ
+ 	bool
+ 	select IRQ_DOMAIN
+--- a/drivers/irqchip/Makefile
++++ b/drivers/irqchip/Makefile
+@@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_MMP)			+= irq-mmp.o
+ obj-$(CONFIG_IRQ_MXS)			+= irq-mxs.o
+ obj-$(CONFIG_ARCH_TEGRA)		+= irq-tegra.o
+ obj-$(CONFIG_ARCH_S3C24XX)		+= irq-s3c24xx.o
++obj-$(CONFIG_BCM6345_EXT_IRQ)		+= irq-bcm6345-ext.o
+ obj-$(CONFIG_BCM6345_PERIPH_IRQ)	+= irq-bcm6345-periph.o
+ obj-$(CONFIG_DW_APB_ICTL)		+= irq-dw-apb-ictl.o
+ obj-$(CONFIG_METAG)			+= irq-metag-ext.o
+--- /dev/null
++++ b/drivers/irqchip/irq-bcm6345-ext.c
+@@ -0,0 +1,301 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2014 Jonas Gorski <[email protected]>
++ */
++
++#include <linux/ioport.h>
++#include <linux/irq.h>
++#include <linux/irqchip.h>
++#include <linux/irqchip/chained_irq.h>
++#include <linux/irqchip/irq-bcm6345-ext.h>
++#include <linux/kernel.h>
++#include <linux/of.h>
++#include <linux/of_irq.h>
++#include <linux/of_address.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++
++#ifdef CONFIG_BCM63XX
++#include <asm/mach-bcm63xx/bcm63xx_irq.h>
++
++#define VIRQ_BASE		IRQ_EXTERNAL_BASE
++#else
++#define VIRQ_BASE		0
++#endif
++
++#define MAX_IRQS		4
++
++#define EXTIRQ_CFG_SENSE	0
++#define EXTIRQ_CFG_STAT		1
++#define EXTIRQ_CFG_CLEAR	2
++#define EXTIRQ_CFG_MASK		3
++#define EXTIRQ_CFG_BOTHEDGE	4
++#define EXTIRQ_CFG_LEVELSENSE	5
++
++struct intc_data {
++	struct irq_chip chip;
++	struct irq_domain *domain;
++	raw_spinlock_t lock;
++
++	int parent_irq[MAX_IRQS];
++	void __iomem *reg;
++	int shift;
++	unsigned int toggle_clear_on_ack:1;
++};
++
++static void bcm6345_ext_intc_irq_handle(struct irq_desc *desc)
++{
++	struct intc_data *data = irq_desc_get_handler_data(desc);
++	struct irq_chip *chip = irq_desc_get_chip(desc);
++	unsigned int irq = irq_desc_get_irq(desc);
++	unsigned int idx;
++
++	chained_irq_enter(chip, desc);
++
++	for (idx = 0; idx < MAX_IRQS; idx++) {
++		if (data->parent_irq[idx] != irq)
++			continue;
++
++		generic_handle_irq(irq_find_mapping(data->domain, idx));
++	}
++
++	chained_irq_exit(chip, desc);
++}
++
++static void bcm6345_ext_intc_irq_ack(struct irq_data *data)
++{
++	struct intc_data *priv = data->domain->host_data;
++	irq_hw_number_t hwirq = irqd_to_hwirq(data);
++	u32 reg;
++
++	raw_spin_lock(&priv->lock);
++	reg = __raw_readl(priv->reg);
++	__raw_writel(reg | (1 << (hwirq + EXTIRQ_CFG_CLEAR * priv->shift)),
++		     priv->reg);
++	if (priv->toggle_clear_on_ack)
++		__raw_writel(reg, priv->reg);
++	raw_spin_unlock(&priv->lock);
++}
++
++static void bcm6345_ext_intc_irq_mask(struct irq_data *data)
++{
++	struct intc_data *priv = data->domain->host_data;
++	irq_hw_number_t hwirq = irqd_to_hwirq(data);
++	u32 reg;
++
++	raw_spin_lock(&priv->lock);
++	reg = __raw_readl(priv->reg);
++	reg &= ~(1 << (hwirq + EXTIRQ_CFG_MASK * priv->shift));
++	__raw_writel(reg, priv->reg);
++	raw_spin_unlock(&priv->lock);
++}
++
++static void bcm6345_ext_intc_irq_unmask(struct irq_data *data)
++{
++	struct intc_data *priv = data->domain->host_data;
++	irq_hw_number_t hwirq = irqd_to_hwirq(data);
++	u32 reg;
++
++	raw_spin_lock(&priv->lock);
++	reg = __raw_readl(priv->reg);
++	reg |= 1 << (hwirq + EXTIRQ_CFG_MASK * priv->shift);
++	__raw_writel(reg, priv->reg);
++	raw_spin_unlock(&priv->lock);
++}
++
++static int bcm6345_ext_intc_set_type(struct irq_data *data,
++				     unsigned int flow_type)
++{
++	struct intc_data *priv = data->domain->host_data;
++	irq_hw_number_t hwirq = irqd_to_hwirq(data);
++	bool levelsense = 0, sense = 0, bothedge = 0;
++	u32 reg;
++
++	flow_type &= IRQ_TYPE_SENSE_MASK;
++
++	if (flow_type == IRQ_TYPE_NONE)
++		flow_type = IRQ_TYPE_LEVEL_LOW;
++
++	switch (flow_type) {
++	case IRQ_TYPE_EDGE_BOTH:
++		bothedge = 1;
++		break;
++
++	case IRQ_TYPE_EDGE_RISING:
++		sense = 1;
++		break;
++
++	case IRQ_TYPE_EDGE_FALLING:
++		break;
++
++	case IRQ_TYPE_LEVEL_HIGH:
++		levelsense = 1;
++		sense = 1;
++		break;
++
++	case IRQ_TYPE_LEVEL_LOW:
++		levelsense = 1;
++		break;
++
++	default:
++		pr_err("bogus flow type combination given!\n");
++		return -EINVAL;
++	}
++
++	raw_spin_lock(&priv->lock);
++	reg = __raw_readl(priv->reg);
++
++	if (levelsense)
++		reg |= 1 << (hwirq + EXTIRQ_CFG_LEVELSENSE * priv->shift);
++	else
++		reg &= ~(1 << (hwirq + EXTIRQ_CFG_LEVELSENSE * priv->shift));
++	if (sense)
++		reg |= 1 << (hwirq + EXTIRQ_CFG_SENSE * priv->shift);
++	else
++		reg &= ~(1 << (hwirq + EXTIRQ_CFG_SENSE * priv->shift));
++	if (bothedge)
++		reg |= 1 << (hwirq + EXTIRQ_CFG_BOTHEDGE * priv->shift);
++	else
++		reg &= ~(1 << (hwirq + EXTIRQ_CFG_BOTHEDGE * priv->shift));
++
++	__raw_writel(reg, priv->reg);
++	raw_spin_unlock(&priv->lock);
++
++	irqd_set_trigger_type(data, flow_type);
++	if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
++		irq_set_handler_locked(data, handle_level_irq);
++	else
++		irq_set_handler_locked(data, handle_edge_irq);
++
++	return 0;
++}
++
++static int bcm6345_ext_intc_map(struct irq_domain *d, unsigned int irq,
++				irq_hw_number_t hw)
++{
++	struct intc_data *priv = d->host_data;
++
++	irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq);
++
++	return 0;
++}
++
++static const struct irq_domain_ops bcm6345_ext_domain_ops = {
++	.xlate = irq_domain_xlate_twocell,
++	.map = bcm6345_ext_intc_map,
++};
++
++static int __init __bcm6345_ext_intc_init(struct device_node *node,
++					  int num_irqs, int *irqs,
++					  void __iomem *reg, int shift,
++					  bool toggle_clear_on_ack)
++{
++	struct intc_data *data;
++	unsigned int i;
++	int start = VIRQ_BASE;
++
++	data = kzalloc(sizeof(*data), GFP_KERNEL);
++	if (!data)
++		return -ENOMEM;
++
++	raw_spin_lock_init(&data->lock);
++
++	for (i = 0; i < num_irqs; i++) {
++		data->parent_irq[i] = irqs[i];
++
++		irq_set_handler_data(irqs[i], data);
++		irq_set_chained_handler(irqs[i], bcm6345_ext_intc_irq_handle);
++	}
++
++	data->reg = reg;
++	data->shift = shift;
++	data->toggle_clear_on_ack = toggle_clear_on_ack;
++
++	data->chip.name = "bcm6345-ext-intc";
++	data->chip.irq_ack = bcm6345_ext_intc_irq_ack;
++	data->chip.irq_mask = bcm6345_ext_intc_irq_mask;
++	data->chip.irq_unmask = bcm6345_ext_intc_irq_unmask;
++	data->chip.irq_set_type = bcm6345_ext_intc_set_type;
++
++	/*
++	 * If we have less than 4 irqs, this is the second controller on
++	 * bcm63xx. So increase the VIRQ start to not overlap with the first
++	 * one, but only do so if we actually use a non-zero start.
++	 *
++	 * This can be removed when bcm63xx has no legacy users anymore.
++	 */
++	if (start && num_irqs < 4)
++		start += 4;
++
++	data->domain = irq_domain_add_simple(node, num_irqs, start,
++					     &bcm6345_ext_domain_ops, data);
++	if (!data->domain) {
++		kfree(data);
++		return -ENOMEM;
++	}
++
++	return 0;
++}
++
++void __init bcm6345_ext_intc_init(int num_irqs, int *irqs, void __iomem *reg,
++				  int shift)
++{
++	__bcm6345_ext_intc_init(NULL, num_irqs, irqs, reg, shift, false);
++}
++
++#ifdef CONFIG_OF
++static int __init bcm6345_ext_intc_of_init(struct device_node *node,
++					   struct device_node *parent)
++{
++	int num_irqs, ret = -EINVAL;
++	unsigned i;
++	void __iomem *base;
++	int irqs[MAX_IRQS] = { 0 };
++	u32 shift;
++	bool toggle_clear_on_ack = false;
++
++	num_irqs = of_irq_count(node);
++
++	if (!num_irqs || num_irqs > MAX_IRQS)
++		return -EINVAL;
++
++	if (of_property_read_u32(node, "brcm,field-width", &shift))
++		shift = 4;
++
++	/* on BCM6318 setting CLEAR seems to continuously mask interrupts */
++	if (of_device_is_compatible(node, "brcm,bcm6318-ext-intc"))
++		toggle_clear_on_ack = true;
++
++	for (i = 0; i < num_irqs; i++) {
++		irqs[i] = irq_of_parse_and_map(node, i);
++		if (!irqs[i]) {
++			ret = -ENOMEM;
++			goto out_unmap;
++		}
++	}
++
++	base = of_iomap(node, 0);
++	if (!base)
++		goto out_unmap;
++
++	ret = __bcm6345_ext_intc_init(node, num_irqs, irqs, base, shift,
++				      toggle_clear_on_ack);
++	if (!ret)
++		return 0;
++out_unmap:
++	iounmap(base);
++
++	for (i = 0; i < num_irqs; i++)
++		irq_dispose_mapping(irqs[i]);
++
++	return ret;
++}
++
++IRQCHIP_DECLARE(bcm6318_ext_intc, "brcm,bcm6318-ext-intc",
++		bcm6345_ext_intc_of_init);
++IRQCHIP_DECLARE(bcm6345_ext_intc, "brcm,bcm6345-ext-intc",
++		bcm6345_ext_intc_of_init);
++#endif
+--- /dev/null
++++ b/include/linux/irqchip/irq-bcm6345-ext.h
+@@ -0,0 +1,14 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2014 Jonas Gorski <[email protected]>
++ */
++
++#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H
++#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H
++
++void bcm6345_ext_intc_init(int n_irqs, int *irqs, void __iomem *reg, int shift);
++
++#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H */

target/linux/brcm63xx/patches-4.9/322-MIPS-BCM63XX-switch-to-IRQ_DOMAIN.patch

@@ -0,0 +1,695 @@
+From d2d2489e0a4b740abd980e9d1cad952d15bc2d9e Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 30 Nov 2014 14:55:02 +0100
+Subject: [PATCH] MIPS: BCM63XX: switch to IRQ_DOMAIN
+
+Now that we have working IRQ_DOMAIN drivers for both interrupt controllers,
+switch to using them.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/Kconfig       |   3 +
+ arch/mips/bcm63xx/irq.c | 612 +++++++++---------------------------------------
+ 2 files changed, 108 insertions(+), 507 deletions(-)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -264,6 +264,9 @@ config BCM63XX
+ 	select SYNC_R4K
+ 	select DMA_NONCOHERENT
+ 	select IRQ_MIPS_CPU
++	select BCM6345_EXT_IRQ
++	select BCM6345_PERIPH_IRQ
++	select IRQ_DOMAIN
+ 	select SYS_SUPPORTS_32BIT_KERNEL
+ 	select SYS_SUPPORTS_BIG_ENDIAN
+ 	select SYS_HAS_EARLY_PRINTK
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -12,7 +12,9 @@
+ #include <linux/interrupt.h>
+ #include <linux/module.h>
+ #include <linux/irq.h>
+-#include <linux/spinlock.h>
++#include <linux/irqchip.h>
++#include <linux/irqchip/irq-bcm6345-ext.h>
++#include <linux/irqchip/irq-bcm6345-periph.h>
+ #include <asm/irq_cpu.h>
+ #include <asm/mipsregs.h>
+ #include <bcm63xx_cpu.h>
+@@ -20,544 +22,140 @@
+ #include <bcm63xx_io.h>
+ #include <bcm63xx_irq.h>
+ 
+-
+-static DEFINE_SPINLOCK(ipic_lock);
+-static DEFINE_SPINLOCK(epic_lock);
+-
+-static u32 irq_stat_addr[2];
+-static u32 irq_mask_addr[2];
+-static void (*dispatch_internal)(int cpu);
+-static int is_ext_irq_cascaded;
+-static unsigned int ext_irq_count;
+-static unsigned int ext_irq_start, ext_irq_end;
+-static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
+-static void (*internal_irq_mask)(struct irq_data *d);
+-static void (*internal_irq_unmask)(struct irq_data *d, const struct cpumask *m);
+-
+-
+-static inline u32 get_ext_irq_perf_reg(int irq)
+-{
+-	if (irq < 4)
+-		return ext_irq_cfg_reg1;
+-	return ext_irq_cfg_reg2;
+-}
+-
+-static inline void handle_internal(int intbit)
+-{
+-	if (is_ext_irq_cascaded &&
+-	    intbit >= ext_irq_start && intbit <= ext_irq_end)
+-		do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE);
+-	else
+-		do_IRQ(intbit + IRQ_INTERNAL_BASE);
+-}
+-
+-static inline int enable_irq_for_cpu(int cpu, struct irq_data *d,
+-				     const struct cpumask *m)
+-{
+-	bool enable = cpu_online(cpu);
+-
+-#ifdef CONFIG_SMP
+-	if (m)
+-		enable &= cpumask_test_cpu(cpu, m);
+-	else if (irqd_affinity_was_set(d))
+-		enable &= cpumask_test_cpu(cpu, irq_data_get_affinity_mask(d));
+-#endif
+-	return enable;
+-}
+-
+-/*
+- * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
+- * prioritize any interrupt relatively to another. the static counter
+- * will resume the loop where it ended the last time we left this
+- * function.
+- */
+-
+-#define BUILD_IPIC_INTERNAL(width)					\
+-void __dispatch_internal_##width(int cpu)				\
+-{									\
+-	u32 pending[width / 32];					\
+-	unsigned int src, tgt;						\
+-	bool irqs_pending = false;					\
+-	static unsigned int i[2];					\
+-	unsigned int *next = &i[cpu];					\
+-	unsigned long flags;						\
+-									\
+-	/* read registers in reverse order */				\
+-	spin_lock_irqsave(&ipic_lock, flags);				\
+-	for (src = 0, tgt = (width / 32); src < (width / 32); src++) {	\
+-		u32 val;						\
+-									\
+-		val = bcm_readl(irq_stat_addr[cpu] + src * sizeof(u32)); \
+-		val &= bcm_readl(irq_mask_addr[cpu] + src * sizeof(u32)); \
+-		pending[--tgt] = val;					\
+-									\
+-		if (val)						\
+-			irqs_pending = true;				\
+-	}								\
+-	spin_unlock_irqrestore(&ipic_lock, flags);			\
+-									\
+-	if (!irqs_pending)						\
+-		return;							\
+-									\
+-	while (1) {							\
+-		unsigned int to_call = *next;				\
+-									\
+-		*next = (*next + 1) & (width - 1);			\
+-		if (pending[to_call / 32] & (1 << (to_call & 0x1f))) {	\
+-			handle_internal(to_call);			\
+-			break;						\
+-		}							\
+-	}								\
+-}									\
+-									\
+-static void __internal_irq_mask_##width(struct irq_data *d)		\
+-{									\
+-	u32 val;							\
+-	unsigned irq = d->irq - IRQ_INTERNAL_BASE;			\
+-	unsigned reg = (irq / 32) ^ (width/32 - 1);			\
+-	unsigned bit = irq & 0x1f;					\
+-	unsigned long flags;						\
+-	int cpu;							\
+-									\
+-	spin_lock_irqsave(&ipic_lock, flags);				\
+-	for_each_present_cpu(cpu) {					\
+-		if (!irq_mask_addr[cpu])				\
+-			break;						\
+-									\
+-		val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\
+-		val &= ~(1 << bit);					\
+-		bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\
+-	}								\
+-	spin_unlock_irqrestore(&ipic_lock, flags);			\
+-}									\
+-									\
+-static void __internal_irq_unmask_##width(struct irq_data *d,		\
+-					  const struct cpumask *m)	\
+-{									\
+-	u32 val;							\
+-	unsigned irq = d->irq - IRQ_INTERNAL_BASE;			\
+-	unsigned reg = (irq / 32) ^ (width/32 - 1);			\
+-	unsigned bit = irq & 0x1f;					\
+-	unsigned long flags;						\
+-	int cpu;							\
+-									\
+-	spin_lock_irqsave(&ipic_lock, flags);				\
+-	for_each_present_cpu(cpu) {					\
+-		if (!irq_mask_addr[cpu])				\
+-			break;						\
+-									\
+-		val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\
+-		if (enable_irq_for_cpu(cpu, d, m))			\
+-			val |= (1 << bit);				\
+-		else							\
+-			val &= ~(1 << bit);				\
+-		bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\
+-	}								\
+-	spin_unlock_irqrestore(&ipic_lock, flags);			\
+-}
+-
+-BUILD_IPIC_INTERNAL(32);
+-BUILD_IPIC_INTERNAL(64);
+-
+-asmlinkage void plat_irq_dispatch(void)
+-{
+-	u32 cause;
+-
+-	do {
+-		cause = read_c0_cause() & read_c0_status() & ST0_IM;
+-
+-		if (!cause)
+-			break;
+-
+-		if (cause & CAUSEF_IP7)
+-			do_IRQ(7);
+-		if (cause & CAUSEF_IP0)
+-			do_IRQ(0);
+-		if (cause & CAUSEF_IP1)
+-			do_IRQ(1);
+-		if (cause & CAUSEF_IP2)
+-			dispatch_internal(0);
+-		if (is_ext_irq_cascaded) {
+-			if (cause & CAUSEF_IP3)
+-				dispatch_internal(1);
+-		} else {
+-			if (cause & CAUSEF_IP3)
+-				do_IRQ(IRQ_EXT_0);
+-			if (cause & CAUSEF_IP4)
+-				do_IRQ(IRQ_EXT_1);
+-			if (cause & CAUSEF_IP5)
+-				do_IRQ(IRQ_EXT_2);
+-			if (cause & CAUSEF_IP6)
+-				do_IRQ(IRQ_EXT_3);
+-		}
+-	} while (1);
+-}
+-
+-/*
+- * internal IRQs operations: only mask/unmask on PERF irq mask
+- * register.
+- */
+-static void bcm63xx_internal_irq_mask(struct irq_data *d)
+-{
+-	internal_irq_mask(d);
+-}
+-
+-static void bcm63xx_internal_irq_unmask(struct irq_data *d)
+-{
+-	internal_irq_unmask(d, NULL);
+-}
+-
+-/*
+- * external IRQs operations: mask/unmask and clear on PERF external
+- * irq control register.
+- */
+-static void bcm63xx_external_irq_mask(struct irq_data *d)
+-{
+-	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+-	u32 reg, regaddr;
+-	unsigned long flags;
+-
+-	regaddr = get_ext_irq_perf_reg(irq);
+-	spin_lock_irqsave(&epic_lock, flags);
+-	reg = bcm_perf_readl(regaddr);
+-
+-	if (BCMCPU_IS_6348())
+-		reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4);
+-	else
+-		reg &= ~EXTIRQ_CFG_MASK(irq % 4);
+-
+-	bcm_perf_writel(reg, regaddr);
+-	spin_unlock_irqrestore(&epic_lock, flags);
+-
+-	if (is_ext_irq_cascaded)
+-		internal_irq_mask(irq_get_irq_data(irq + ext_irq_start));
+-}
+-
+-static void bcm63xx_external_irq_unmask(struct irq_data *d)
+-{
+-	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+-	u32 reg, regaddr;
+-	unsigned long flags;
+-
+-	regaddr = get_ext_irq_perf_reg(irq);
+-	spin_lock_irqsave(&epic_lock, flags);
+-	reg = bcm_perf_readl(regaddr);
+-
+-	if (BCMCPU_IS_6348())
+-		reg |= EXTIRQ_CFG_MASK_6348(irq % 4);
+-	else
+-		reg |= EXTIRQ_CFG_MASK(irq % 4);
+-
+-	bcm_perf_writel(reg, regaddr);
+-	spin_unlock_irqrestore(&epic_lock, flags);
+-
+-	if (is_ext_irq_cascaded)
+-		internal_irq_unmask(irq_get_irq_data(irq + ext_irq_start),
+-				    NULL);
+-}
+-
+-static void bcm63xx_external_irq_clear(struct irq_data *d)
+-{
+-	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+-	u32 reg, regaddr;
+-	unsigned long flags;
+-
+-	regaddr = get_ext_irq_perf_reg(irq);
+-	spin_lock_irqsave(&epic_lock, flags);
+-	reg = bcm_perf_readl(regaddr);
+-
+-	if (BCMCPU_IS_6348())
+-		reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4);
+-	else
+-		reg |= EXTIRQ_CFG_CLEAR(irq % 4);
+-
+-	bcm_perf_writel(reg, regaddr);
+-	spin_unlock_irqrestore(&epic_lock, flags);
+-}
+-
+-static int bcm63xx_external_irq_set_type(struct irq_data *d,
+-					 unsigned int flow_type)
+-{
+-	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+-	u32 reg, regaddr;
+-	int levelsense, sense, bothedge;
+-	unsigned long flags;
+-
+-	flow_type &= IRQ_TYPE_SENSE_MASK;
+-
+-	if (flow_type == IRQ_TYPE_NONE)
+-		flow_type = IRQ_TYPE_LEVEL_LOW;
+-
+-	levelsense = sense = bothedge = 0;
+-	switch (flow_type) {
+-	case IRQ_TYPE_EDGE_BOTH:
+-		bothedge = 1;
+-		break;
+-
+-	case IRQ_TYPE_EDGE_RISING:
+-		sense = 1;
+-		break;
+-
+-	case IRQ_TYPE_EDGE_FALLING:
+-		break;
+-
+-	case IRQ_TYPE_LEVEL_HIGH:
+-		levelsense = 1;
+-		sense = 1;
+-		break;
+-
+-	case IRQ_TYPE_LEVEL_LOW:
+-		levelsense = 1;
+-		break;
+-
+-	default:
+-		pr_err("bogus flow type combination given !\n");
+-		return -EINVAL;
+-	}
+-
+-	regaddr = get_ext_irq_perf_reg(irq);
+-	spin_lock_irqsave(&epic_lock, flags);
+-	reg = bcm_perf_readl(regaddr);
+-	irq %= 4;
+-
+-	switch (bcm63xx_get_cpu_id()) {
+-	case BCM6348_CPU_ID:
+-		if (levelsense)
+-			reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);
+-		else
+-			reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq);
+-		if (sense)
+-			reg |= EXTIRQ_CFG_SENSE_6348(irq);
+-		else
+-			reg &= ~EXTIRQ_CFG_SENSE_6348(irq);
+-		if (bothedge)
+-			reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);
+-		else
+-			reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
+-		break;
+-
+-	case BCM3368_CPU_ID:
+-	case BCM6328_CPU_ID:
+-	case BCM6338_CPU_ID:
+-	case BCM6345_CPU_ID:
+-	case BCM6358_CPU_ID:
+-	case BCM6362_CPU_ID:
+-	case BCM6368_CPU_ID:
+-		if (levelsense)
+-			reg |= EXTIRQ_CFG_LEVELSENSE(irq);
+-		else
+-			reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
+-		if (sense)
+-			reg |= EXTIRQ_CFG_SENSE(irq);
+-		else
+-			reg &= ~EXTIRQ_CFG_SENSE(irq);
+-		if (bothedge)
+-			reg |= EXTIRQ_CFG_BOTHEDGE(irq);
+-		else
+-			reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
+-		break;
+-	default:
+-		BUG();
+-	}
+-
+-	bcm_perf_writel(reg, regaddr);
+-	spin_unlock_irqrestore(&epic_lock, flags);
+-
+-	irqd_set_trigger_type(d, flow_type);
+-	if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
+-		irq_set_handler_locked(d, handle_level_irq);
+-	else
+-		irq_set_handler_locked(d, handle_edge_irq);
+-
+-	return IRQ_SET_MASK_OK_NOCOPY;
+-}
+-
+-#ifdef CONFIG_SMP
+-static int bcm63xx_internal_set_affinity(struct irq_data *data,
+-					 const struct cpumask *dest,
+-					 bool force)
+-{
+-	if (!irqd_irq_disabled(data))
+-		internal_irq_unmask(data, dest);
+-
+-	return 0;
+-}
+-#endif
+-
+-static struct irq_chip bcm63xx_internal_irq_chip = {
+-	.name		= "bcm63xx_ipic",
+-	.irq_mask	= bcm63xx_internal_irq_mask,
+-	.irq_unmask	= bcm63xx_internal_irq_unmask,
+-};
+-
+-static struct irq_chip bcm63xx_external_irq_chip = {
+-	.name		= "bcm63xx_epic",
+-	.irq_ack	= bcm63xx_external_irq_clear,
+-
+-	.irq_mask	= bcm63xx_external_irq_mask,
+-	.irq_unmask	= bcm63xx_external_irq_unmask,
+-
+-	.irq_set_type	= bcm63xx_external_irq_set_type,
+-};
+-
+-static struct irqaction cpu_ip2_cascade_action = {
+-	.handler	= no_action,
+-	.name		= "cascade_ip2",
+-	.flags		= IRQF_NO_THREAD,
+-};
+-
+-#ifdef CONFIG_SMP
+-static struct irqaction cpu_ip3_cascade_action = {
+-	.handler	= no_action,
+-	.name		= "cascade_ip3",
+-	.flags		= IRQF_NO_THREAD,
+-};
+-#endif
+-
+-static struct irqaction cpu_ext_cascade_action = {
+-	.handler	= no_action,
+-	.name		= "cascade_extirq",
+-	.flags		= IRQF_NO_THREAD,
+-};
+-
+-static void bcm63xx_init_irq(void)
++void __init arch_init_irq(void)
+ {
+-	int irq_bits;
+-
+-	irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF);
+-	irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF);
+-	irq_stat_addr[1] = bcm63xx_regset_address(RSET_PERF);
+-	irq_mask_addr[1] = bcm63xx_regset_address(RSET_PERF);
++	void __iomem *periph_bases[2];
++	void __iomem *ext_intc_bases[2];
++	int periph_irq_count, periph_width, ext_irq_count, ext_shift;
++	int periph_irqs[2] = { 2, 3 };
++	int ext_irqs[6];
++
++	periph_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
++	periph_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
++	ext_intc_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
++	ext_intc_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
+ 
+ 	switch (bcm63xx_get_cpu_id()) {
+ 	case BCM3368_CPU_ID:
+-		irq_stat_addr[0] += PERF_IRQSTAT_3368_REG;
+-		irq_mask_addr[0] += PERF_IRQMASK_3368_REG;
+-		irq_stat_addr[1] = 0;
+-		irq_mask_addr[1] = 0;
+-		irq_bits = 32;
+-		ext_irq_count = 4;
+-		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
++		periph_bases[0] += PERF_IRQMASK_3368_REG;
++		periph_irq_count = 1;
++		periph_width = 1;
++
++		ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_3368;
++		ext_irq_count = 4;
++		ext_irqs[0] = BCM_3368_EXT_IRQ0;
++		ext_irqs[1] = BCM_3368_EXT_IRQ1;
++		ext_irqs[2] = BCM_3368_EXT_IRQ2;
++		ext_irqs[3] = BCM_3368_EXT_IRQ3;
++		ext_shift = 4;
+ 		break;
+ 	case BCM6328_CPU_ID:
+-		irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0);
+-		irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0);
+-		irq_stat_addr[1] += PERF_IRQSTAT_6328_REG(1);
+-		irq_mask_addr[1] += PERF_IRQMASK_6328_REG(1);
+-		irq_bits = 64;
+-		ext_irq_count = 4;
+-		is_ext_irq_cascaded = 1;
+-		ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
+-		ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
+-		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
++		periph_bases[0] += PERF_IRQMASK_6328_REG(0);
++		periph_bases[1] += PERF_IRQMASK_6328_REG(1);
++		periph_irq_count = 2;
++		periph_width = 2;
++
++		ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6328;
++		ext_irq_count = 4;
++		ext_irqs[0] = BCM_6328_EXT_IRQ0;
++		ext_irqs[1] = BCM_6328_EXT_IRQ1;
++		ext_irqs[2] = BCM_6328_EXT_IRQ2;
++		ext_irqs[3] = BCM_6328_EXT_IRQ3;
++		ext_shift = 4;
+ 		break;
+ 	case BCM6338_CPU_ID:
+-		irq_stat_addr[0] += PERF_IRQSTAT_6338_REG;
+-		irq_mask_addr[0] += PERF_IRQMASK_6338_REG;
+-		irq_stat_addr[1] = 0;
+-		irq_mask_addr[1] = 0;
+-		irq_bits = 32;
+-		ext_irq_count = 4;
+-		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
++		periph_bases[0] += PERF_IRQMASK_6338_REG;
++		periph_irq_count = 1;
++		periph_width = 1;
++
++		ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6338;
++		ext_irq_count = 4;
++		ext_irqs[0] = 3;
++		ext_irqs[1] = 4;
++		ext_irqs[2] = 5;
++		ext_irqs[3] = 6;
++		ext_shift = 4;
+ 		break;
+ 	case BCM6345_CPU_ID:
+-		irq_stat_addr[0] += PERF_IRQSTAT_6345_REG;
+-		irq_mask_addr[0] += PERF_IRQMASK_6345_REG;
+-		irq_stat_addr[1] = 0;
+-		irq_mask_addr[1] = 0;
+-		irq_bits = 32;
+-		ext_irq_count = 4;
+-		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
++		periph_bases[0] += PERF_IRQMASK_6345_REG;
++		periph_irq_count = 1;
++		periph_width = 1;
++
++		ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6345;
++		ext_irq_count = 4;
++		ext_irqs[0] = 3;
++		ext_irqs[1] = 4;
++		ext_irqs[2] = 5;
++		ext_irqs[3] = 6;
++		ext_shift = 4;
+ 		break;
+ 	case BCM6348_CPU_ID:
+-		irq_stat_addr[0] += PERF_IRQSTAT_6348_REG;
+-		irq_mask_addr[0] += PERF_IRQMASK_6348_REG;
+-		irq_stat_addr[1] = 0;
+-		irq_mask_addr[1] = 0;
+-		irq_bits = 32;
+-		ext_irq_count = 4;
+-		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
++		periph_bases[0] += PERF_IRQMASK_6348_REG;
++		periph_irq_count = 1;
++		periph_width = 1;
++
++		ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6348;
++		ext_irq_count = 4;
++		ext_irqs[0] = 3;
++		ext_irqs[1] = 4;
++		ext_irqs[2] = 5;
++		ext_irqs[3] = 6;
++		ext_shift = 5;
+ 		break;
+ 	case BCM6358_CPU_ID:
+-		irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0);
+-		irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0);
+-		irq_stat_addr[1] += PERF_IRQSTAT_6358_REG(1);
+-		irq_mask_addr[1] += PERF_IRQMASK_6358_REG(1);
+-		irq_bits = 32;
+-		ext_irq_count = 4;
+-		is_ext_irq_cascaded = 1;
+-		ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
+-		ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
+-		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
++		periph_bases[0] += PERF_IRQMASK_6358_REG(0);
++		periph_bases[1] += PERF_IRQMASK_6358_REG(1);
++		periph_irq_count = 2;
++		periph_width = 1;
++
++		ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6358;
++		ext_irq_count = 4;
++		ext_irqs[0] = BCM_6358_EXT_IRQ0;
++		ext_irqs[1] = BCM_6358_EXT_IRQ1;
++		ext_irqs[2] = BCM_6358_EXT_IRQ2;
++		ext_irqs[3] = BCM_6358_EXT_IRQ3;
++		ext_shift = 4;
+ 		break;
+ 	case BCM6362_CPU_ID:
+-		irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0);
+-		irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0);
+-		irq_stat_addr[1] += PERF_IRQSTAT_6362_REG(1);
+-		irq_mask_addr[1] += PERF_IRQMASK_6362_REG(1);
+-		irq_bits = 64;
+-		ext_irq_count = 4;
+-		is_ext_irq_cascaded = 1;
+-		ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
+-		ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
+-		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
++		periph_bases[0] += PERF_IRQMASK_6362_REG(0);
++		periph_bases[1] += PERF_IRQMASK_6362_REG(1);
++		periph_irq_count = 2;
++		periph_width = 2;
++
++		ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6362;
++		ext_irq_count = 4;
++		ext_irqs[0] = BCM_6362_EXT_IRQ0;
++		ext_irqs[1] = BCM_6362_EXT_IRQ1;
++		ext_irqs[2] = BCM_6362_EXT_IRQ2;
++		ext_irqs[3] = BCM_6362_EXT_IRQ3;
++		ext_shift = 4;
+ 		break;
+ 	case BCM6368_CPU_ID:
+-		irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0);
+-		irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0);
+-		irq_stat_addr[1] += PERF_IRQSTAT_6368_REG(1);
+-		irq_mask_addr[1] += PERF_IRQMASK_6368_REG(1);
+-		irq_bits = 64;
++		periph_bases[0] += PERF_IRQMASK_6368_REG(0);
++		periph_bases[1] += PERF_IRQMASK_6368_REG(1);
++		periph_irq_count = 2;
++		periph_width = 2;
++
++		ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6368;
++		ext_intc_bases[1] += PERF_EXTIRQ_CFG_REG2_6368;
+ 		ext_irq_count = 6;
+-		is_ext_irq_cascaded = 1;
+-		ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
+-		ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
+-		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
+-		ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
++		ext_irqs[0] = BCM_6368_EXT_IRQ0;
++		ext_irqs[1] = BCM_6368_EXT_IRQ1;
++		ext_irqs[2] = BCM_6368_EXT_IRQ2;
++		ext_irqs[3] = BCM_6368_EXT_IRQ3;
++		ext_irqs[4] = BCM_6368_EXT_IRQ4;
++		ext_irqs[5] = BCM_6368_EXT_IRQ5;
++		ext_shift = 4;
+ 		break;
+ 	default:
+ 		BUG();
+ 	}
+ 
+-	if (irq_bits == 32) {
+-		dispatch_internal = __dispatch_internal_32;
+-		internal_irq_mask = __internal_irq_mask_32;
+-		internal_irq_unmask = __internal_irq_unmask_32;
+-	} else {
+-		dispatch_internal = __dispatch_internal_64;
+-		internal_irq_mask = __internal_irq_mask_64;
+-		internal_irq_unmask = __internal_irq_unmask_64;
+-	}
+-}
+-
+-void __init arch_init_irq(void)
+-{
+-	int i;
+-
+-	bcm63xx_init_irq();
+ 	mips_cpu_irq_init();
+-	for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
+-		irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
+-					 handle_level_irq);
+-
+-	for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i)
+-		irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
+-					 handle_edge_irq);
+-
+-	if (!is_ext_irq_cascaded) {
+-		for (i = 3; i < 3 + ext_irq_count; ++i)
+-			setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action);
+-	}
+-
+-	setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
+-#ifdef CONFIG_SMP
+-	if (is_ext_irq_cascaded) {
+-		setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action);
+-		bcm63xx_internal_irq_chip.irq_set_affinity =
+-			bcm63xx_internal_set_affinity;
+-
+-		cpumask_clear(irq_default_affinity);
+-		cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
+-	}
+-#endif
++	bcm6345_periph_intc_init(periph_irq_count, periph_irqs, periph_bases,
++				 periph_width);
++	bcm6345_ext_intc_init(4, ext_irqs, ext_intc_bases[0], ext_shift);
++	if (ext_irq_count > 4)
++		bcm6345_ext_intc_init(2, &ext_irqs[4], ext_intc_bases[1],
++				      ext_shift);
+ }

target/linux/brcm63xx/patches-4.9/323-MIPS-BCM63XX-wire-up-BCM6358-s-external-interrupts-4.patch

@@ -0,0 +1,57 @@
+From 4fd286c3e5a5bebab0391cf1937695b3ed6721a3 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 30 Nov 2014 20:20:30 +0100
+Subject: [PATCH 4/5] MIPS: BCM63XX: wire up BCM6358's external interrupts 4
+ and 5
+
+Due to the external interrupts being non consecutive, the previous
+implementation did not support them. Now that we treat both registers
+as separate irq controllers, there is no such limitation anymore and
+we can expose them for drivers to use.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/irq.c                           |    5 ++++-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |    2 ++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |    1 +
+ 3 files changed, 7 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -109,11 +109,14 @@ void __init arch_init_irq(void)
+ 		periph_width = 1;
+ 
+ 		ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6358;
+-		ext_irq_count = 4;
++		ext_intc_bases[1] += PERF_EXTIRQ_CFG_REG2_6358;
++		ext_irq_count = 6;
+ 		ext_irqs[0] = BCM_6358_EXT_IRQ0;
+ 		ext_irqs[1] = BCM_6358_EXT_IRQ1;
+ 		ext_irqs[2] = BCM_6358_EXT_IRQ2;
+ 		ext_irqs[3] = BCM_6358_EXT_IRQ3;
++		ext_irqs[4] = BCM_6358_EXT_IRQ4;
++		ext_irqs[5] = BCM_6358_EXT_IRQ5;
+ 		ext_shift = 4;
+ 		break;
+ 	case BCM6362_CPU_ID:
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -895,6 +895,8 @@ enum bcm63xx_irq {
+ #define BCM_6358_EXT_IRQ1		(IRQ_INTERNAL_BASE + 26)
+ #define BCM_6358_EXT_IRQ2		(IRQ_INTERNAL_BASE + 27)
+ #define BCM_6358_EXT_IRQ3		(IRQ_INTERNAL_BASE + 28)
++#define BCM_6358_EXT_IRQ4		(IRQ_INTERNAL_BASE + 20)
++#define BCM_6358_EXT_IRQ5		(IRQ_INTERNAL_BASE + 21)
+ 
+ /*
+  * 6362 irqs
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -243,6 +243,7 @@
+ #define PERF_EXTIRQ_CFG_REG_6362	0x18
+ #define PERF_EXTIRQ_CFG_REG_6368	0x18
+ 
++#define PERF_EXTIRQ_CFG_REG2_6358	0x1c
+ #define PERF_EXTIRQ_CFG_REG2_6368	0x1c
+ 
+ /* for 6348 only */

target/linux/brcm63xx/patches-4.9/330-MIPS-BCM63XX-add-a-new-cpu-variant-helper.patch

@@ -0,0 +1,77 @@
+From c50acd37b425a8a907a6f7f93aa2e658256e79ce Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sat, 7 Dec 2013 14:08:36 +0100
+Subject: [PATCH 40/53] MIPS: BCM63XX: add a new cpu variant helper
+
+---
+ arch/mips/bcm63xx/cpu.c                          | 10 ++++++++++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 18 ++++++++++++++++++
+ 2 files changed, 28 insertions(+)
+
+--- a/arch/mips/bcm63xx/cpu.c
++++ b/arch/mips/bcm63xx/cpu.c
+@@ -27,6 +27,8 @@ EXPORT_SYMBOL(bcm63xx_irqs);
+ u16 bcm63xx_cpu_id __read_mostly;
+ EXPORT_SYMBOL(bcm63xx_cpu_id);
+ 
++static u32 bcm63xx_cpu_variant __read_mostly;
++
+ static u8 bcm63xx_cpu_rev;
+ static unsigned int bcm63xx_cpu_freq;
+ static unsigned int bcm63xx_memory_size;
+@@ -99,6 +101,13 @@ static const int bcm6368_irqs[] = {
+ 
+ };
+ 
++u32 bcm63xx_get_cpu_variant(void)
++{
++	return bcm63xx_cpu_variant;
++}
++
++EXPORT_SYMBOL(bcm63xx_get_cpu_variant);
++
+ u8 bcm63xx_get_cpu_rev(void)
+ {
+ 	return bcm63xx_cpu_rev;
+@@ -333,6 +342,7 @@ void __init bcm63xx_cpu_init(void)
+ 	/* read out CPU type */
+ 	tmp = bcm_readl(chipid_reg);
+ 	bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
++	bcm63xx_cpu_variant = bcm63xx_cpu_id;
+ 	bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
+ 
+ 	switch (bcm63xx_cpu_id) {
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -19,6 +19,7 @@
+ #define BCM6368_CPU_ID		0x6368
+ 
+ void __init bcm63xx_cpu_init(void);
++u32 bcm63xx_get_cpu_variant(void);
+ u8 bcm63xx_get_cpu_rev(void);
+ unsigned int bcm63xx_get_cpu_freq(void);
+ 
+@@ -82,6 +83,23 @@ static inline u16 __pure bcm63xx_get_cpu
+ #define BCMCPU_IS_6362()	(bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
+ #define BCMCPU_IS_6368()	(bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
+ 
++#define BCMCPU_VARIANT_IS_3368() \
++	(bcm63xx_get_cpu_variant() == BCM3368_CPU_ID)
++#define BCMCPU_VARIANT_IS_6328() \
++	(bcm63xx_get_cpu_variant() == BCM6328_CPU_ID)
++#define BCMCPU_VARIANT_IS_6338() \
++	(bcm63xx_get_cpu_variant() == BCM6338_CPU_ID)
++#define BCMCPU_VARIANT_IS_6345() \
++	(bcm63xx_get_cpu_variant() == BCM6345_CPU_ID)
++#define BCMCPU_VARIANT_IS_6348() \
++	(bcm63xx_get_cpu_variant() == BCM6348_CPU_ID)
++#define BCMCPU_VARIANT_IS_6358() \
++	(bcm63xx_get_cpu_cariant() == BCM6358_CPU_ID)
++#define BCMCPU_VARIANT_IS_6362() \
++	(bcm63xx_get_cpu_variant() == BCM6362_CPU_ID)
++#define BCMCPU_VARIANT_IS_6368() \
++	(bcm63xx_get_cpu_variant() == BCM6368_CPU_ID)
++
+ /*
+  * While registers sets are (mostly) the same across 63xx CPU, base
+  * address of these sets do change.

target/linux/brcm63xx/patches-4.9/331-MIPS-BCM63XX-define-variant-id-field.patch

@@ -0,0 +1,23 @@
+From 3bd8e2535265f06f79ed9c0ad788405441e091dc Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sat, 7 Dec 2013 14:22:41 +0100
+Subject: [PATCH 21/45] MIPS: BCM63XX: define variant id field
+
+Some SoC have a variant id field in the chip id register.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -9,6 +9,8 @@
+ #define PERF_REV_REG			0x0
+ #define REV_CHIPID_SHIFT		16
+ #define REV_CHIPID_MASK			(0xffff << REV_CHIPID_SHIFT)
++#define REV_VARID_SHIFT			12
++#define REV_VARID_MASK			(0xf << REV_VARID_SHIFT)
+ #define REV_REVID_SHIFT			0
+ #define REV_REVID_MASK			(0xff << REV_REVID_SHIFT)
+ 

target/linux/brcm63xx/patches-4.9/332-MIPS-BCM63XX-detect-BCM6328-variants.patch

@@ -0,0 +1,68 @@
+From d59120f23279ef62a48d9f94847254b061d0a8b6 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sat, 7 Dec 2013 14:30:59 +0100
+Subject: [PATCH 22/45] MIPS: BCM63XX: detect BCM6328 variants
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/cpu.c                          | 10 ++++++++++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h |  8 ++++++--
+ 2 files changed, 16 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/bcm63xx/cpu.c
++++ b/arch/mips/bcm63xx/cpu.c
+@@ -305,6 +305,7 @@ void __init bcm63xx_cpu_init(void)
+ 	unsigned int tmp;
+ 	unsigned int cpu = smp_processor_id();
+ 	u32 chipid_reg;
++	u8 __maybe_unused varid = 0;
+ 
+ 	/* soc registers location depends on cpu type */
+ 	chipid_reg = 0;
+@@ -344,6 +345,7 @@ void __init bcm63xx_cpu_init(void)
+ 	bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
+ 	bcm63xx_cpu_variant = bcm63xx_cpu_id;
+ 	bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
++	varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT;
+ 
+ 	switch (bcm63xx_cpu_id) {
+ 	case BCM3368_CPU_ID:
+@@ -353,6 +355,14 @@ void __init bcm63xx_cpu_init(void)
+ 	case BCM6328_CPU_ID:
+ 		bcm63xx_regs_base = bcm6328_regs_base;
+ 		bcm63xx_irqs = bcm6328_irqs;
++
++		if (varid == 1)
++			bcm63xx_cpu_variant = BCM63281_CPU_ID;
++		else if (varid == 3)
++			bcm63xx_cpu_variant = BCM63283_CPU_ID;
++		else
++			pr_warn("unknown BCM6328 variant: %x\n", varid);
++
+ 		break;
+ 	case BCM6338_CPU_ID:
+ 		bcm63xx_regs_base = bcm6338_regs_base;
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -11,6 +11,8 @@
+  */
+ #define BCM3368_CPU_ID		0x3368
+ #define BCM6328_CPU_ID		0x6328
++#define BCM63281_CPU_ID		0x63281
++#define BCM63283_CPU_ID		0x63283
+ #define BCM6338_CPU_ID		0x6338
+ #define BCM6345_CPU_ID		0x6345
+ #define BCM6348_CPU_ID		0x6348
+@@ -85,8 +87,10 @@ static inline u16 __pure bcm63xx_get_cpu
+ 
+ #define BCMCPU_VARIANT_IS_3368() \
+ 	(bcm63xx_get_cpu_variant() == BCM3368_CPU_ID)
+-#define BCMCPU_VARIANT_IS_6328() \
+-	(bcm63xx_get_cpu_variant() == BCM6328_CPU_ID)
++#define BCMCPU_VARIANT_IS_63281() \
++	(bcm63xx_get_cpu_variant() == BCM63281_CPU_ID)
++#define BCMCPU_VARIANT_IS_63283() \
++	(bcm63xx_get_cpu_variant() == BCM63283_CPU_ID)
+ #define BCMCPU_VARIANT_IS_6338() \
+ 	(bcm63xx_get_cpu_variant() == BCM6338_CPU_ID)
+ #define BCMCPU_VARIANT_IS_6345() \

target/linux/brcm63xx/patches-4.9/333-MIPS-BCM63XX-detect-BCM6362-variants.patch

@@ -0,0 +1,46 @@
+From 04458c3db8eb79da21ecde40ab36a1dde52bef06 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sat, 7 Dec 2013 14:33:28 +0100
+Subject: [PATCH 23/45] MIPS: BCM63XX: detect BCM6362 variants
+
+---
+ arch/mips/bcm63xx/cpu.c                          | 8 ++++++++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 3 +++
+ 2 files changed, 11 insertions(+)
+
+--- a/arch/mips/bcm63xx/cpu.c
++++ b/arch/mips/bcm63xx/cpu.c
+@@ -383,6 +383,14 @@ void __init bcm63xx_cpu_init(void)
+ 	case BCM6362_CPU_ID:
+ 		bcm63xx_regs_base = bcm6362_regs_base;
+ 		bcm63xx_irqs = bcm6362_irqs;
++
++		if (varid == 1)
++			bcm63xx_cpu_variant = BCM6362_CPU_ID;
++		else if (varid == 2)
++			bcm63xx_cpu_variant = BCM6361_CPU_ID;
++		else
++			pr_warn("unknown BCM6362 variant: %x\n", varid);
++
+ 		break;
+ 	case BCM6368_CPU_ID:
+ 		bcm63xx_regs_base = bcm6368_regs_base;
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -17,6 +17,7 @@
+ #define BCM6345_CPU_ID		0x6345
+ #define BCM6348_CPU_ID		0x6348
+ #define BCM6358_CPU_ID		0x6358
++#define BCM6361_CPU_ID		0x6361
+ #define BCM6362_CPU_ID		0x6362
+ #define BCM6368_CPU_ID		0x6368
+ 
+@@ -99,6 +100,8 @@ static inline u16 __pure bcm63xx_get_cpu
+ 	(bcm63xx_get_cpu_variant() == BCM6348_CPU_ID)
+ #define BCMCPU_VARIANT_IS_6358() \
+ 	(bcm63xx_get_cpu_cariant() == BCM6358_CPU_ID)
++#define BCMCPU_VARIANT_IS_6361() \
++	(bcm63xx_get_cpu_variant() == BCM6361_CPU_ID)
+ #define BCMCPU_VARIANT_IS_6362() \
+ 	(bcm63xx_get_cpu_variant() == BCM6362_CPU_ID)
+ #define BCMCPU_VARIANT_IS_6368() \

target/linux/brcm63xx/patches-4.9/334-MIPS-BCM63XX-detect-BCM6368-variants.patch

@@ -0,0 +1,48 @@
+From 825cc67e56b5e624a05f6850a86d91508b786848 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sat, 7 Dec 2013 14:36:56 +0100
+Subject: [PATCH 24/44] MIPS: BCM63XX: detect BCM6368 variants
+
+The DSL-less BCM6368 variant BCM6367 uses a different chip id. Apart
+from missing DSL, there is no difference to BCM6368, so treat it such.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/cpu.c                          | 4 ++++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 3 +++
+ 2 files changed, 7 insertions(+)
+
+--- a/arch/mips/bcm63xx/cpu.c
++++ b/arch/mips/bcm63xx/cpu.c
+@@ -393,8 +393,12 @@ void __init bcm63xx_cpu_init(void)
+ 
+ 		break;
+ 	case BCM6368_CPU_ID:
++	case BCM6369_CPU_ID:
+ 		bcm63xx_regs_base = bcm6368_regs_base;
+ 		bcm63xx_irqs = bcm6368_irqs;
++
++		/* BCM6369 is a BCM6368 without xDSL, so treat it the same */
++		bcm63xx_cpu_id = BCM6368_CPU_ID;
+ 		break;
+ 	default:
+ 		panic("unsupported broadcom CPU %x", bcm63xx_cpu_id);
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -20,6 +20,7 @@
+ #define BCM6361_CPU_ID		0x6361
+ #define BCM6362_CPU_ID		0x6362
+ #define BCM6368_CPU_ID		0x6368
++#define BCM6369_CPU_ID		0x6369
+ 
+ void __init bcm63xx_cpu_init(void);
+ u32 bcm63xx_get_cpu_variant(void);
+@@ -106,6 +107,8 @@ static inline u16 __pure bcm63xx_get_cpu
+ 	(bcm63xx_get_cpu_variant() == BCM6362_CPU_ID)
+ #define BCMCPU_VARIANT_IS_6368() \
+ 	(bcm63xx_get_cpu_variant() == BCM6368_CPU_ID)
++#define BCMCPU_VARIANT_IS_6369() \
++	(bcm63xx_get_cpu_variant() == BCM6369_CPU_ID)
+ 
+ /*
+  * While registers sets are (mostly) the same across 63xx CPU, base

target/linux/brcm63xx/patches-4.9/335-MIPS-BCM63XX-fix-PCIe-memory-window-size.patch

@@ -0,0 +1,20 @@
+From f67f8134b4537c8bbafe7e1975edfe808b813997 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 8 Dec 2013 03:05:54 +0100
+Subject: [PATCH 45/53] MIPS: BCM63XX: fix PCIe memory window size
+
+---
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+@@ -41,7 +41,7 @@
+ 					BCM_CB_MEM_SIZE - 1)
+ 
+ #define BCM_PCIE_MEM_BASE_PA		0x10f00000
+-#define BCM_PCIE_MEM_SIZE		(16 * 1024 * 1024)
++#define BCM_PCIE_MEM_SIZE		(1 * 1024 * 1024)
+ #define BCM_PCIE_MEM_END_PA		(BCM_PCIE_MEM_BASE_PA +		\
+ 					BCM_PCIE_MEM_SIZE - 1)
+ 

target/linux/brcm63xx/patches-4.9/336-MIPS-BCM63XX-dynamically-set-the-pcie-memory-windows.patch

@@ -0,0 +1,70 @@
+From aa05464973bc176478af462ca7c53a9239c651d4 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 8 Dec 2013 03:13:06 +0100
+Subject: [PATCH 46/53] MIPS: BCM63XX: dynamically set the pcie memory windows
+
+Different SoCs use different memory windows (and sizes), so don't
+hardcode it.
+---
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h |  8 ++++----
+ arch/mips/pci/pci-bcm63xx.c                     | 15 ++++++++++-----
+ 2 files changed, 14 insertions(+), 9 deletions(-)
+
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+@@ -40,10 +40,10 @@
+ #define BCM_CB_MEM_END_PA		(BCM_CB_MEM_BASE_PA +		\
+ 					BCM_CB_MEM_SIZE - 1)
+ 
+-#define BCM_PCIE_MEM_BASE_PA		0x10f00000
+-#define BCM_PCIE_MEM_SIZE		(1 * 1024 * 1024)
+-#define BCM_PCIE_MEM_END_PA		(BCM_PCIE_MEM_BASE_PA +		\
+-					BCM_PCIE_MEM_SIZE - 1)
++#define BCM_PCIE_MEM_BASE_PA_6328	0x10f00000
++#define BCM_PCIE_MEM_SIZE_6328		(1 * 1024 * 1024)
++#define BCM_PCIE_MEM_END_PA_6328	(BCM_PCIE_MEM_BASE_PA_6328 +	\
++					BCM_PCIE_MEM_SIZE_6328 - 1)
+ 
+ /*
+  * Internal registers are accessed through KSEG3
+--- a/arch/mips/pci/pci-bcm63xx.c
++++ b/arch/mips/pci/pci-bcm63xx.c
+@@ -77,8 +77,8 @@ struct pci_controller bcm63xx_cb_control
+ 
+ static struct resource bcm_pcie_mem_resource = {
+ 	.name	= "bcm63xx PCIe memory space",
+-	.start	= BCM_PCIE_MEM_BASE_PA,
+-	.end	= BCM_PCIE_MEM_END_PA,
++	.start	= 0,
++	.end	= 0,
+ 	.flags	= IORESOURCE_MEM,
+ };
+ 
+@@ -195,12 +195,12 @@ static int __init bcm63xx_register_pcie(
+ 	bcm_pcie_writel(val, PCIE_CONFIG2_REG);
+ 
+ 	/* set bar0 to little endian */
+-	val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT;
+-	val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT;
++	val = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT;
++	val |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT;
+ 	val |= BASEMASK_REMAP_EN;
+ 	bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
+ 
+-	val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT;
++	val = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT;
+ 	bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
+ 
+ 	register_pci_controller(&bcm63xx_pcie_controller);
+@@ -334,6 +334,11 @@ static int __init bcm63xx_pci_init(void)
+ 	if (!bcm63xx_pci_enabled)
+ 		return -ENODEV;
+ 
++	if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
++		bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328;
++		bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328;
++	}
++
+ 	switch (bcm63xx_get_cpu_id()) {
+ 	case BCM6328_CPU_ID:
+ 	case BCM6362_CPU_ID:

target/linux/brcm63xx/patches-4.9/337-MIPS-BCM63XX-widen-cpuid-field.patch

@@ -0,0 +1,56 @@
+From f1477f6e3551fd6beecfee5368fed1325dcd421f Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sat, 7 Dec 2013 14:54:51 +0100
+Subject: [PATCH 47/53] MIPS: BCM63XX: widen cpuid field
+
+---
+ arch/mips/bcm63xx/cpu.c                          | 2 +-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 8 ++++----
+ 2 files changed, 5 insertions(+), 5 deletions(-)
+
+--- a/arch/mips/bcm63xx/cpu.c
++++ b/arch/mips/bcm63xx/cpu.c
+@@ -24,7 +24,7 @@ EXPORT_SYMBOL(bcm63xx_regs_base);
+ const int *bcm63xx_irqs;
+ EXPORT_SYMBOL(bcm63xx_irqs);
+ 
+-u16 bcm63xx_cpu_id __read_mostly;
++u32 bcm63xx_cpu_id __read_mostly;
+ EXPORT_SYMBOL(bcm63xx_cpu_id);
+ 
+ static u32 bcm63xx_cpu_variant __read_mostly;
+@@ -127,7 +127,7 @@ unsigned int bcm63xx_get_memory_size(voi
+ 
+ static unsigned int detect_cpu_clock(void)
+ {
+-	u16 cpu_id = bcm63xx_get_cpu_id();
++	u32 cpu_id = bcm63xx_get_cpu_id();
+ 
+ 	switch (cpu_id) {
+ 	case BCM3368_CPU_ID:
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -27,7 +27,7 @@ u32 bcm63xx_get_cpu_variant(void);
+ u8 bcm63xx_get_cpu_rev(void);
+ unsigned int bcm63xx_get_cpu_freq(void);
+ 
+-static inline u16 __pure __bcm63xx_get_cpu_id(const u16 cpu_id)
++static inline u32 __pure __bcm63xx_get_cpu_id(const u32 cpu_id)
+ {
+ 	switch (cpu_id) {
+ #ifdef CONFIG_BCM63XX_CPU_3368
+@@ -69,11 +69,11 @@ static inline u16 __pure __bcm63xx_get_c
+ 	return cpu_id;
+ }
+ 
+-extern u16 bcm63xx_cpu_id;
++extern u32 bcm63xx_cpu_id;
+ 
+-static inline u16 __pure bcm63xx_get_cpu_id(void)
++static inline u32 __pure bcm63xx_get_cpu_id(void)
+ {
+-	const u16 cpu_id = bcm63xx_cpu_id;
++	const u32 cpu_id = bcm63xx_cpu_id;
+ 
+ 	return __bcm63xx_get_cpu_id(cpu_id);
+ }

target/linux/brcm63xx/patches-4.9/338-MIPS-BCM63XX-increase-number-of-IRQs.patch

@@ -0,0 +1,39 @@
+From 6f5658c845cf1f79213b1d20423a04967259fdaa Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 15 Dec 2013 20:46:26 +0100
+Subject: [PATCH 48/53] MIPS: BCM63XX: increase number of IRQs
+
+Newer SoCs have 128 bit wide irq registers, thus 128 available internal
+interupts.
+---
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h | 4 +++-
+ arch/mips/include/asm/mach-bcm63xx/irq.h         | 2 +-
+ 2 files changed, 4 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
+@@ -1,10 +1,12 @@
+ #ifndef BCM63XX_IRQ_H_
+ #define BCM63XX_IRQ_H_
+ 
++#include <irq.h>
+ #include <bcm63xx_cpu.h>
+ 
+ #define IRQ_INTERNAL_BASE		8
+-#define IRQ_EXTERNAL_BASE		100
++#define NR_INTERNAL_IRQS		128
++#define IRQ_EXTERNAL_BASE		(IRQ_INTERNAL_BASE + NR_INTERNAL_IRQS)
+ #define IRQ_EXT_0			(IRQ_EXTERNAL_BASE + 0)
+ #define IRQ_EXT_1			(IRQ_EXTERNAL_BASE + 1)
+ #define IRQ_EXT_2			(IRQ_EXTERNAL_BASE + 2)
+--- a/arch/mips/include/asm/mach-bcm63xx/irq.h
++++ b/arch/mips/include/asm/mach-bcm63xx/irq.h
+@@ -1,7 +1,7 @@
+ #ifndef __ASM_MACH_BCM63XX_IRQ_H
+ #define __ASM_MACH_BCM63XX_IRQ_H
+ 
+-#define NR_IRQS 128
++#define NR_IRQS 256
+ #define MIPS_CPU_IRQ_BASE 0
+ 
+ #endif

target/linux/brcm63xx/patches-4.9/339-MIPS-BCM63XX-add-support-for-BCM63268.patch

@@ -0,0 +1,737 @@
+From 98f63141190ac02c58b78d58f771bd263c61d756 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sat, 7 Dec 2013 17:14:17 +0100
+Subject: [PATCH 48/56] MIPS: BCM63XX: add support for BCM63268
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/Kconfig                         |   5 +
+ arch/mips/bcm63xx/boards/board_bcm963xx.c         |   2 +-
+ arch/mips/bcm63xx/clk.c                           |  25 ++++-
+ arch/mips/bcm63xx/cpu.c                           |  59 +++++++++-
+ arch/mips/bcm63xx/dev-flash.c                     |   6 +
+ arch/mips/bcm63xx/dev-spi.c                       |   4 +-
+ arch/mips/bcm63xx/irq.c                           |  20 +++-
+ arch/mips/bcm63xx/reset.c                         |  21 ++++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  | 130 ++++++++++++++++++++++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h |   2 +
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |  79 +++++++++++++
+ arch/mips/include/asm/mach-bcm63xx/ioremap.h      |   1 +
+ 12 files changed, 342 insertions(+), 12 deletions(-)
+
+--- a/arch/mips/bcm63xx/Kconfig
++++ b/arch/mips/bcm63xx/Kconfig
+@@ -60,6 +60,11 @@ config BCM63XX_CPU_6368
+ 	select HW_HAS_PCI
+ 	select BCM63XX_OHCI
+ 	select BCM63XX_EHCI
++
++config BCM63XX_CPU_63268
++	bool "support 63268 CPU"
++	select SYS_HAS_CPU_BMIPS4350
++	select HW_HAS_PCI
+ endmenu
+ 
+ source "arch/mips/bcm63xx/boards/Kconfig"
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -713,7 +713,7 @@ void __init board_prom_init(void)
+ 	/* read base address of boot chip select (0)
+ 	 * 6328/6362 do not have MPI but boot from a fixed address
+ 	 */
+-	if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
++	if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) {
+ 		val = 0x18000000;
+ 	} else {
+ 		val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -168,6 +168,8 @@ static void enetsw_set(struct clk *clk,
+ 			clk_disable_unlocked(&clk_swpkt_sar);
+ 		}
+ 		bcm_hwclock_set(CKCTL_6368_ROBOSW_EN, enable);
++	} else if (BCMCPU_IS_63268()) {
++		bcm_hwclock_set(CKCTL_63268_ROBOSW_EN, enable);
+ 	} else {
+ 		return;
+ 	}
+@@ -213,6 +215,8 @@ static void usbh_set(struct clk *clk, in
+ 		bcm_hwclock_set(CKCTL_6362_USBH_EN, enable);
+ 	else if (BCMCPU_IS_6368())
+ 		bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
++	else if (BCMCPU_IS_63268())
++		bcm_hwclock_set(CKCTL_63268_USBH_EN, enable);
+ 	else
+ 		return;
+ 
+@@ -235,6 +239,8 @@ static void usbd_set(struct clk *clk, in
+ 		bcm_hwclock_set(CKCTL_6362_USBD_EN, enable);
+ 	else if (BCMCPU_IS_6368())
+ 		bcm_hwclock_set(CKCTL_6368_USBD_EN, enable);
++	else if (BCMCPU_IS_63268())
++		bcm_hwclock_set(CKCTL_63268_USBD_EN, enable);
+ 	else
+ 		return;
+ 
+@@ -261,9 +267,13 @@ static void spi_set(struct clk *clk, int
+ 		mask = CKCTL_6358_SPI_EN;
+ 	else if (BCMCPU_IS_6362())
+ 		mask = CKCTL_6362_SPI_EN;
+-	else
+-		/* BCMCPU_IS_6368 */
++	else if (BCMCPU_IS_6368())
+ 		mask = CKCTL_6368_SPI_EN;
++	else if (BCMCPU_IS_63268())
++		mask = CKCTL_63268_SPI_EN;
++	else
++		return;
++
+ 	bcm_hwclock_set(mask, enable);
+ }
+ 
+@@ -282,6 +292,8 @@ static void hsspi_set(struct clk *clk, i
+ 		mask = CKCTL_6328_HSSPI_EN;
+ 	else if (BCMCPU_IS_6362())
+ 		mask = CKCTL_6362_HSSPI_EN;
++	else if (BCMCPU_IS_63268())
++		mask = CKCTL_63268_HSSPI_EN;
+ 	else
+ 		return;
+ 
+@@ -351,6 +363,8 @@ static void pcie_set(struct clk *clk, in
+ 		bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable);
+ 	else if (BCMCPU_IS_6362())
+ 		bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable);
++	else if (BCMCPU_IS_63268())
++		bcm_hwclock_set(CKCTL_63268_PCIE_EN, enable);
+ }
+ 
+ static struct clk clk_pcie = {
+@@ -535,6 +549,21 @@ static struct clk_lookup bcm6368_clks[]
+ 	CLKDEV_INIT(NULL, "ipsec", &clk_ipsec),
+ };
+ 
++static struct clk_lookup bcm63268_clks[] = {
++	/* fixed rate clocks */
++	CLKDEV_INIT(NULL, "periph", &clk_periph),
++	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
++	CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
++	CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
++	/* gated clocks */
++	CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
++	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
++	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
++	CLKDEV_INIT(NULL, "spi", &clk_spi),
++	CLKDEV_INIT(NULL, "hsspi", &clk_hsspi),
++	CLKDEV_INIT(NULL, "pcie", &clk_pcie),
++};
++
+ #define HSSPI_PLL_HZ_6328	133333333
+ #define HSSPI_PLL_HZ_6362	400000000
+ 
+@@ -567,6 +596,10 @@ static int __init bcm63xx_clk_init(void)
+ 	case BCM6368_CPU_ID:
+ 		clkdev_add_table(bcm6368_clks, ARRAY_SIZE(bcm6368_clks));
+ 		break;
++	case BCM63268_CPU_ID:
++		clk_hsspi_pll.rate = HSSPI_PLL_HZ_6362;
++		clkdev_add_table(bcm63268_clks, ARRAY_SIZE(bcm63268_clks));
++		break;
+ 	}
+ 
+ 	return 0;
+--- a/arch/mips/bcm63xx/cpu.c
++++ b/arch/mips/bcm63xx/cpu.c
+@@ -101,6 +101,15 @@ static const int bcm6368_irqs[] = {
+ 
+ };
+ 
++static const unsigned long bcm63268_regs_base[] = {
++	__GEN_CPU_REGS_TABLE(63268)
++};
++
++static const int bcm63268_irqs[] = {
++	__GEN_CPU_IRQ_TABLE(63268)
++
++};
++
+ u32 bcm63xx_get_cpu_variant(void)
+ {
+ 	return bcm63xx_cpu_variant;
+@@ -253,6 +262,27 @@ static unsigned int detect_cpu_clock(voi
+ 
+ 		return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
+ 	}
++	case BCM63268_CPU_ID:
++	{
++		unsigned int tmp, mips_pll_fcvo;
++
++		tmp = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
++		mips_pll_fcvo = (tmp & STRAPBUS_63268_FCVO_MASK) >>
++				STRAPBUS_63268_FCVO_SHIFT;
++		switch (mips_pll_fcvo) {
++		case 0x3:
++		case 0xe:
++			return 320000000;
++		case 0xa:
++			return 333000000;
++		case 0x2:
++		case 0xb:
++		case 0xf:
++			return 400000000;
++		default:
++			return 0;
++		}
++	}
+ 
+ 	default:
+ 		panic("Failed to detect clock for CPU with id=%04X\n", cpu_id);
+@@ -267,7 +297,7 @@ static unsigned int detect_memory_size(v
+ 	unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
+ 	u32 val;
+ 
+-	if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
++	if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268())
+ 		return bcm_ddr_readl(DDR_CSEND_REG) << 24;
+ 
+ 	if (BCMCPU_IS_6345()) {
+@@ -305,6 +335,7 @@ void __init bcm63xx_cpu_init(void)
+ 	unsigned int tmp;
+ 	unsigned int cpu = smp_processor_id();
+ 	u32 chipid_reg;
++	bool long_chipid = false;
+ 	u8 __maybe_unused varid = 0;
+ 
+ 	/* soc registers location depends on cpu type */
+@@ -326,6 +357,9 @@ void __init bcm63xx_cpu_init(void)
+ 		case 0x10:
+ 			chipid_reg = BCM_6345_PERF_BASE;
+ 			break;
++		case 0x80:
++			long_chipid = true;
++			/* fall-through */
+ 		default:
+ 			chipid_reg = BCM_6368_PERF_BASE;
+ 			break;
+@@ -333,6 +367,7 @@ void __init bcm63xx_cpu_init(void)
+ 		break;
+ 	}
+ 
++
+ 	/*
+ 	 * really early to panic, but delaying panic would not help since we
+ 	 * will never get any working console
+@@ -342,10 +377,17 @@ void __init bcm63xx_cpu_init(void)
+ 
+ 	/* read out CPU type */
+ 	tmp = bcm_readl(chipid_reg);
+-	bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
+-	bcm63xx_cpu_variant = bcm63xx_cpu_id;
++
++	if (long_chipid) {
++		bcm63xx_cpu_id = tmp & REV_LONG_CHIPID_MASK;
++		bcm63xx_cpu_id >>= REV_LONG_CHIPID_SHIFT;
++	} else {
++		bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
++		varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT;
++	}
++
+ 	bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
+-	varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT;
++	bcm63xx_cpu_variant = bcm63xx_cpu_id;
+ 
+ 	switch (bcm63xx_cpu_id) {
+ 	case BCM3368_CPU_ID:
+@@ -400,6 +442,15 @@ void __init bcm63xx_cpu_init(void)
+ 		/* BCM6369 is a BCM6368 without xDSL, so treat it the same */
+ 		bcm63xx_cpu_id = BCM6368_CPU_ID;
+ 		break;
++	case BCM63168_CPU_ID:
++	case BCM63169_CPU_ID:
++	case BCM63268_CPU_ID:
++	case BCM63269_CPU_ID:
++		bcm63xx_regs_base = bcm63268_regs_base;
++		bcm63xx_irqs = bcm63268_irqs;
++
++		bcm63xx_cpu_id = BCM63268_CPU_ID;
++		break;
+ 	default:
+ 		panic("unsupported broadcom CPU %x", bcm63xx_cpu_id);
+ 		break;
+--- a/arch/mips/bcm63xx/dev-flash.c
++++ b/arch/mips/bcm63xx/dev-flash.c
+@@ -94,6 +94,12 @@ static int __init bcm63xx_detect_flash_t
+ 		case STRAPBUS_6368_BOOT_SEL_PARALLEL:
+ 			return BCM63XX_FLASH_TYPE_PARALLEL;
+ 		}
++	case BCM63268_CPU_ID:
++		val = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
++		if (val & STRAPBUS_63268_BOOT_SEL_SERIAL)
++			return BCM63XX_FLASH_TYPE_SERIAL;
++		else
++			return BCM63XX_FLASH_TYPE_NAND;
+ 	default:
+ 		return -EINVAL;
+ 	}
+--- a/arch/mips/bcm63xx/dev-spi.c
++++ b/arch/mips/bcm63xx/dev-spi.c
+@@ -51,7 +51,7 @@ int __init bcm63xx_spi_register(void)
+ 	}
+ 
+ 	if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() ||
+-		BCMCPU_IS_6368()) {
++		BCMCPU_IS_6368() || BCMCPU_IS_63268()) {
+ 		bcm63xx_spi_device.name = "bcm6358-spi",
+ 		spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
+ 	}
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -150,6 +150,20 @@ void __init arch_init_irq(void)
+ 		ext_irqs[5] = BCM_6368_EXT_IRQ5;
+ 		ext_shift = 4;
+ 		break;
++	case BCM63268_CPU_ID:
++		periph_bases[0] += PERF_IRQMASK_63268_REG(0);
++		periph_bases[1] += PERF_IRQMASK_63268_REG(1);
++		periph_irq_count = 2;
++		periph_width = 4;
++
++		ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_63268;
++		ext_irq_count = 4;
++		ext_irqs[0] = BCM_63268_EXT_IRQ0;
++		ext_irqs[1] = BCM_63268_EXT_IRQ1;
++		ext_irqs[2] = BCM_63268_EXT_IRQ2;
++		ext_irqs[3] = BCM_63268_EXT_IRQ3;
++		ext_shift = 4;
++		break;
+ 	default:
+ 		BUG();
+ 	}
+--- a/arch/mips/bcm63xx/reset.c
++++ b/arch/mips/bcm63xx/reset.c
+@@ -125,6 +125,20 @@
+ #define BCM6368_RESET_PCIE	0
+ #define BCM6368_RESET_PCIE_EXT	0
+ 
++#define BCM63268_RESET_SPI	SOFTRESET_63268_SPI_MASK
++#define BCM63268_RESET_ENET	0
++#define BCM63268_RESET_USBH	SOFTRESET_63268_USBH_MASK
++#define BCM63268_RESET_USBD	SOFTRESET_63268_USBS_MASK
++#define BCM63268_RESET_DSL	0
++#define BCM63268_RESET_SAR	SOFTRESET_63268_SAR_MASK
++#define BCM63268_RESET_EPHY	0
++#define BCM63268_RESET_ENETSW	SOFTRESET_63268_ENETSW_MASK
++#define BCM63268_RESET_PCM	SOFTRESET_63268_PCM_MASK
++#define BCM63268_RESET_MPI	0
++#define BCM63268_RESET_PCIE	(SOFTRESET_63268_PCIE_MASK | \
++				 SOFTRESET_63268_PCIE_CORE_MASK)
++#define BCM63268_RESET_PCIE_EXT	SOFTRESET_63268_PCIE_EXT_MASK
++
+ /*
+  * core reset bits
+  */
+@@ -156,6 +170,10 @@ static const u32 bcm6368_reset_bits[] =
+ 	__GEN_RESET_BITS_TABLE(6368)
+ };
+ 
++static const u32 bcm63268_reset_bits[] = {
++	__GEN_RESET_BITS_TABLE(63268)
++};
++
+ const u32 *bcm63xx_reset_bits;
+ static int reset_reg;
+ 
+@@ -182,6 +200,9 @@ static int __init bcm63xx_reset_bits_ini
+ 	} else if (BCMCPU_IS_6368()) {
+ 		reset_reg = PERF_SOFTRESET_6368_REG;
+ 		bcm63xx_reset_bits = bcm6368_reset_bits;
++	} else if (BCMCPU_IS_63268()) {
++		reset_reg = PERF_SOFTRESET_63268_REG;
++		bcm63xx_reset_bits = bcm63268_reset_bits;
+ 	}
+ 
+ 	return 0;
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -21,6 +21,10 @@
+ #define BCM6362_CPU_ID		0x6362
+ #define BCM6368_CPU_ID		0x6368
+ #define BCM6369_CPU_ID		0x6369
++#define BCM63168_CPU_ID		0x63168
++#define BCM63169_CPU_ID		0x63169
++#define BCM63268_CPU_ID		0x63268
++#define BCM63269_CPU_ID		0x63269
+ 
+ void __init bcm63xx_cpu_init(void);
+ u32 bcm63xx_get_cpu_variant(void);
+@@ -61,6 +65,10 @@ static inline u32 __pure __bcm63xx_get_c
+ #ifdef CONFIG_BCM63XX_CPU_6368
+ 		case BCM6368_CPU_ID:
+ #endif
++
++#ifdef CONFIG_BCM63XX_CPU_63268
++		case BCM63268_CPU_ID:
++#endif
+ 		break;
+ 	default:
+ 		unreachable();
+@@ -86,6 +94,7 @@ static inline u32 __pure bcm63xx_get_cpu
+ #define BCMCPU_IS_6358()	(bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
+ #define BCMCPU_IS_6362()	(bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
+ #define BCMCPU_IS_6368()	(bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
++#define BCMCPU_IS_63268()	(bcm63xx_get_cpu_id() == BCM63268_CPU_ID)
+ 
+ #define BCMCPU_VARIANT_IS_3368() \
+ 	(bcm63xx_get_cpu_variant() == BCM3368_CPU_ID)
+@@ -109,6 +118,14 @@ static inline u32 __pure bcm63xx_get_cpu
+ 	(bcm63xx_get_cpu_variant() == BCM6368_CPU_ID)
+ #define BCMCPU_VARIANT_IS_6369() \
+ 	(bcm63xx_get_cpu_variant() == BCM6369_CPU_ID)
++#define BCMCPU_VARIANT_IS_63168() \
++	(bcm63xx_get_cpu_variant() == BCM63168_CPU_ID)
++#define BCMCPU_VARIANT_IS_63169() \
++	(bcm63xx_get_cpu_variant() == BCM63169_CPU_ID)
++#define BCMCPU_VARIANT_IS_63268() \
++	(bcm63xx_get_cpu_variant() == BCM63268_CPU_ID)
++#define BCMCPU_VARIANT_IS_63269() \
++	(bcm63xx_get_cpu_variant() == BCM63269_CPU_ID)
+ 
+ /*
+  * While registers sets are (mostly) the same across 63xx CPU, base
+@@ -573,6 +590,52 @@ enum bcm63xx_regs_set {
+ #define BCM_6368_RNG_BASE		(0xb0004180)
+ #define BCM_6368_MISC_BASE		(0xdeadbeef)
+ 
++/*
++ * 63268 register sets base address
++ */
++#define BCM_63268_DSL_LMEM_BASE		(0xdeadbeef)
++#define BCM_63268_PERF_BASE		(0xb0000000)
++#define BCM_63268_TIMER_BASE		(0xb0000080)
++#define BCM_63268_WDT_BASE		(0xb000009c)
++#define BCM_63268_UART0_BASE		(0xb0000180)
++#define BCM_63268_UART1_BASE		(0xb00001a0)
++#define BCM_63268_GPIO_BASE		(0xb00000c0)
++#define BCM_63268_SPI_BASE		(0xb0000800)
++#define BCM_63268_HSSPI_BASE		(0xb0001000)
++#define BCM_63268_UDC0_BASE		(0xdeadbeef)
++#define BCM_63268_USBDMA_BASE		(0xb000c800)
++#define BCM_63268_OHCI0_BASE		(0xb0002600)
++#define BCM_63268_OHCI_PRIV_BASE	(0xdeadbeef)
++#define BCM_63268_USBH_PRIV_BASE	(0xb0002700)
++#define BCM_63268_USBD_BASE		(0xb0002400)
++#define BCM_63268_MPI_BASE		(0xdeadbeef)
++#define BCM_63268_PCMCIA_BASE		(0xdeadbeef)
++#define BCM_63268_PCIE_BASE		(0xb06e0000)
++#define BCM_63268_SDRAM_REGS_BASE	(0xdeadbeef)
++#define BCM_63268_DSL_BASE		(0xdeadbeef)
++#define BCM_63268_UBUS_BASE		(0xdeadbeef)
++#define BCM_63268_ENET0_BASE		(0xdeadbeef)
++#define BCM_63268_ENET1_BASE		(0xdeadbeef)
++#define BCM_63268_ENETDMA_BASE		(0xb000d800)
++#define BCM_63268_ENETDMAC_BASE		(0xb000da00)
++#define BCM_63268_ENETDMAS_BASE		(0xb000dc00)
++#define BCM_63268_ENETSW_BASE		(0xb0700000)
++#define BCM_63268_EHCI0_BASE		(0xb0002500)
++#define BCM_63268_SDRAM_BASE		(0xdeadbeef)
++#define BCM_63268_MEMC_BASE		(0xdeadbeef)
++#define BCM_63268_DDR_BASE		(0xb0003000)
++#define BCM_63268_M2M_BASE		(0xdeadbeef)
++#define BCM_63268_ATM_BASE		(0xdeadbeef)
++#define BCM_63268_XTM_BASE		(0xb0007000)
++#define BCM_63268_XTMDMA_BASE		(0xb000b800)
++#define BCM_63268_XTMDMAC_BASE		(0xdeadbeef)
++#define BCM_63268_XTMDMAS_BASE		(0xdeadbeef)
++#define BCM_63268_PCM_BASE		(0xb000b000)
++#define BCM_63268_PCMDMA_BASE		(0xb000b800)
++#define BCM_63268_PCMDMAC_BASE		(0xdeadbeef)
++#define BCM_63268_PCMDMAS_BASE		(0xdeadbeef)
++#define BCM_63268_RNG_BASE		(0xdeadbeef)
++#define BCM_63268_MISC_BASE		(0xb0001800)
+ 
+ extern const unsigned long *bcm63xx_regs_base;
+ 
+@@ -1041,6 +1104,73 @@ enum bcm63xx_irq {
+ #define BCM_6368_EXT_IRQ4		(IRQ_INTERNAL_BASE + 24)
+ #define BCM_6368_EXT_IRQ5		(IRQ_INTERNAL_BASE + 25)
+ 
++/*
++ * 63268 irqs
++ */
++#define BCM_63268_HIGH_IRQ_BASE		(IRQ_INTERNAL_BASE + 32)
++#define BCM_63268_VERY_HIGH_IRQ_BASE	(BCM_63268_HIGH_IRQ_BASE + 32)
++
++#define BCM_63268_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
++#define BCM_63268_SPI_IRQ		(BCM_63268_VERY_HIGH_IRQ_BASE + 16)
++#define BCM_63268_UART0_IRQ		(IRQ_INTERNAL_BASE + 5)
++#define BCM_63268_UART1_IRQ		(BCM_63268_HIGH_IRQ_BASE + 2)
++#define BCM_63268_DSL_IRQ		(IRQ_INTERNAL_BASE + 23)
++#define BCM_63268_UDC0_IRQ		0
++#define BCM_63268_ENET0_IRQ		0
++#define BCM_63268_ENET1_IRQ		0
++#define BCM_63268_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 13)
++#define BCM_63268_HSSPI_IRQ		(IRQ_INTERNAL_BASE + 6)
++#define BCM_63268_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 9)
++#define BCM_63268_EHCI0_IRQ		(IRQ_INTERNAL_BASE + 10)
++#define BCM_63268_USBD_IRQ		(IRQ_INTERNAL_BASE + 11)
++#define BCM_63268_USBD_RXDMA0_IRQ	(IRQ_INTERNAL_BASE + 19)
++#define BCM_63268_USBD_TXDMA0_IRQ	(BCM_63268_HIGH_IRQ_BASE + 4)
++#define BCM_63268_USBD_RXDMA1_IRQ	(IRQ_INTERNAL_BASE + 20)
++#define BCM_63268_USBD_TXDMA1_IRQ	(BCM_63268_HIGH_IRQ_BASE + 5)
++#define BCM_63268_USBD_RXDMA2_IRQ	(IRQ_INTERNAL_BASE + 21)
++#define BCM_63268_USBD_TXDMA2_IRQ	(BCM_63268_HIGH_IRQ_BASE + 6)
++#define BCM_63268_PCMCIA_IRQ		0
++#define BCM_63268_ENET0_RXDMA_IRQ	0
++#define BCM_63268_ENET0_TXDMA_IRQ	0
++#define BCM_63268_ENET1_RXDMA_IRQ	0
++#define BCM_63268_ENET1_TXDMA_IRQ	0
++#define BCM_63268_PCI_IRQ		(BCM_63268_HIGH_IRQ_BASE + 8)
++#define BCM_63268_ATM_IRQ		0
++#define BCM_63268_ENETSW_RXDMA0_IRQ	(IRQ_INTERNAL_BASE + 1)
++#define BCM_63268_ENETSW_RXDMA1_IRQ	(IRQ_INTERNAL_BASE + 2)
++#define BCM_63268_ENETSW_RXDMA2_IRQ	(IRQ_INTERNAL_BASE + 3)
++#define BCM_63268_ENETSW_RXDMA3_IRQ	(IRQ_INTERNAL_BASE + 4)
++#define BCM_63268_ENETSW_TXDMA0_IRQ	(BCM_63268_VERY_HIGH_IRQ_BASE + 0)
++#define BCM_63268_ENETSW_TXDMA1_IRQ	(BCM_63268_VERY_HIGH_IRQ_BASE + 1)
++#define BCM_63268_ENETSW_TXDMA2_IRQ	(BCM_63268_VERY_HIGH_IRQ_BASE + 2)
++#define BCM_63268_ENETSW_TXDMA3_IRQ	(BCM_63268_VERY_HIGH_IRQ_BASE + 3)
++#define BCM_63268_XTM_IRQ		(BCM_63268_HIGH_IRQ_BASE + 17)
++#define BCM_63268_XTM_DMA0_IRQ		(IRQ_INTERNAL_BASE + 26)
++
++#define BCM_63268_RING_OSC_IRQ		(BCM_63268_HIGH_IRQ_BASE + 20)
++#define BCM_63268_WLAN_GPIO_IRQ		(BCM_63268_HIGH_IRQ_BASE + 3)
++#define BCM_63268_WLAN_IRQ		(IRQ_INTERNAL_BASE + 7)
++#define BCM_63268_IPSEC_IRQ		(IRQ_INTERNAL_BASE + 8)
++#define BCM_63268_NAND_IRQ		(BCM_63268_HIGH_IRQ_BASE + 18)
++#define BCM_63268_PCM_IRQ		(IRQ_INTERNAL_BASE + 13)
++#define BCM_63268_DG_IRQ		(IRQ_INTERNAL_BASE + 15)
++#define BCM_63268_EPHY_ENERGY0_IRQ	(IRQ_INTERNAL_BASE + 16)
++#define BCM_63268_EPHY_ENERGY1_IRQ	(IRQ_INTERNAL_BASE + 17)
++#define BCM_63268_EPHY_ENERGY2_IRQ	(IRQ_INTERNAL_BASE + 18)
++#define BCM_63268_EPHY_ENERGY3_IRQ	(IRQ_INTERNAL_BASE + 19)
++#define BCM_63268_IPSEC_DMA0_IRQ	(IRQ_INTERNAL_BASE + 22)
++#define BCM_63268_IPSEC_DMA1_IRQ	(BCM_63268_HIGH_IRQ_BASE + 7)
++#define BCM_63268_FAP0_IRQ		(IRQ_INTERNAL_BASE + 24)
++#define BCM_63268_FAP1_IRQ		(IRQ_INTERNAL_BASE + 25)
++#define BCM_63268_PCM_DMA0_IRQ		(BCM_63268_HIGH_IRQ_BASE + 10)
++#define BCM_63268_PCM_DMA1_IRQ		(BCM_63268_HIGH_IRQ_BASE + 11)
++#define BCM_63268_DECT0_IRQ		(BCM_63268_HIGH_IRQ_BASE + 0)
++#define BCM_63268_DECT1_IRQ		(BCM_63268_HIGH_IRQ_BASE + 1)
++#define BCM_63268_EXT_IRQ0		(BCM_63268_HIGH_IRQ_BASE + 12)
++#define BCM_63268_EXT_IRQ1		(BCM_63268_HIGH_IRQ_BASE + 13)
++#define BCM_63268_EXT_IRQ2		(BCM_63268_HIGH_IRQ_BASE + 14)
++#define BCM_63268_EXT_IRQ3		(BCM_63268_HIGH_IRQ_BASE + 15)
++
+ extern const int *bcm63xx_irqs;
+ 
+ #define __GEN_CPU_IRQ_TABLE(__cpu)					\
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+@@ -22,6 +22,8 @@ static inline unsigned long bcm63xx_gpio
+ 		return 48;
+ 	case BCM6368_CPU_ID:
+ 		return 38;
++	case BCM63268_CPU_ID:
++		return 52;
+ 	case BCM6348_CPU_ID:
+ 	default:
+ 		return 37;
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -9,6 +9,8 @@
+ #define PERF_REV_REG			0x0
+ #define REV_CHIPID_SHIFT		16
+ #define REV_CHIPID_MASK			(0xffff << REV_CHIPID_SHIFT)
++#define REV_LONG_CHIPID_SHIFT		12
++#define REV_LONG_CHIPID_MASK		(0xfffff << REV_LONG_CHIPID_SHIFT)
+ #define REV_VARID_SHIFT			12
+ #define REV_VARID_MASK			(0xf << REV_VARID_SHIFT)
+ #define REV_REVID_SHIFT			0
+@@ -211,6 +213,52 @@
+ 					CKCTL_6368_NAND_EN |		\
+ 					CKCTL_6368_IPSEC_EN)
+ 
++#define CKCTL_63268_DISABLE_GLESS	(1 << 0)
++#define CKCTL_63268_VDSL_QPROC_EN	(1 << 1)
++#define CKCTL_63268_VDSL_AFE_EN		(1 << 2)
++#define CKCTL_63268_VDSL_EN		(1 << 3)
++#define CKCTL_63268_MIPS_EN		(1 << 4)
++#define CKCTL_63268_WLAN_OCP_EN		(1 << 5)
++#define CKCTL_63268_DECT_EN		(1 << 6)
++#define CKCTL_63268_FAP0_EN		(1 << 7)
++#define CKCTL_63268_FAP1_EN		(1 << 8)
++#define CKCTL_63268_SAR_EN		(1 << 9)
++#define CKCTL_63268_ROBOSW_EN		(1 << 10)
++#define CKCTL_63268_PCM_EN		(1 << 11)
++#define CKCTL_63268_USBD_EN		(1 << 12)
++#define CKCTL_63268_USBH_EN		(1 << 13)
++#define CKCTL_63268_IPSEC_EN		(1 << 14)
++#define CKCTL_63268_SPI_EN		(1 << 15)
++#define CKCTL_63268_HSSPI_EN		(1 << 16)
++#define CKCTL_63268_PCIE_EN		(1 << 17)
++#define CKCTL_63268_PHYMIPS_EN		(1 << 18)
++#define CKCTL_63268_GMAC_EN		(1 << 19)
++#define CKCTL_63268_NAND_EN		(1 << 20)
++#define CKCTL_63268_TBUS_EN		(1 << 27)
++#define CKCTL_63268_ROBOSW250_EN	(1 << 31)
++
++#define CKCTL_63268_ALL_SAFE_EN		(CKCTL_63268_VDSL_QPROC_EN |	\
++					CKCTL_63268_VDSL_AFE_EN |	\
++					CKCTL_63268_VDSL_EN |		\
++					CKCTL_63268_WLAN_OCP_EN |	\
++					CKCTL_63268_DECT_EN |		\
++					CKCTL_63268_FAP0_EN |		\
++					CKCTL_63268_FAP1_EN |		\
++					CKCTL_63268_SAR_EN |		\
++					CKCTL_63268_ROBOSW_EN |		\
++					CKCTL_63268_PCM_EN |		\
++					CKCTL_63268_USBD_EN |		\
++					CKCTL_63268_USBH_EN |		\
++					CKCTL_63268_IPSEC_EN |		\
++					CKCTL_63268_SPI_EN |		\
++					CKCTL_63268_HSSPI_EN |		\
++					CKCTL_63268_PCIE_EN |		\
++					CKCTL_63268_PHYMIPS_EN |	\
++					CKCTL_63268_GMAC_EN |		\
++					CKCTL_63268_NAND_EN |		\
++					CKCTL_63268_TBUS_EN |		\
++					CKCTL_63268_ROBOSW250_EN)
++
+ /* System PLL Control register	*/
+ #define PERF_SYS_PLL_CTL_REG		0x8
+ #define SYS_PLL_SOFT_RESET		0x1
+@@ -224,6 +272,7 @@
+ #define PERF_IRQMASK_6358_REG(x)	(0xc + (x) * 0x2c)
+ #define PERF_IRQMASK_6362_REG(x)	(0x20 + (x) * 0x10)
+ #define PERF_IRQMASK_6368_REG(x)	(0x20 + (x) * 0x10)
++#define PERF_IRQMASK_63268_REG(x)	(0x20 + (x) * 0x20)
+ 
+ /* Interrupt Status register */
+ #define PERF_IRQSTAT_3368_REG		0x10
+@@ -234,6 +283,7 @@
+ #define PERF_IRQSTAT_6358_REG(x)	(0x10 + (x) * 0x2c)
+ #define PERF_IRQSTAT_6362_REG(x)	(0x28 + (x) * 0x10)
+ #define PERF_IRQSTAT_6368_REG(x)	(0x28 + (x) * 0x10)
++#define PERF_IRQSTAT_63268_REG(x)	(0x30 + (x) * 0x20)
+ 
+ /* External Interrupt Configuration register */
+ #define PERF_EXTIRQ_CFG_REG_3368	0x14
+@@ -244,6 +294,7 @@
+ #define PERF_EXTIRQ_CFG_REG_6358	0x14
+ #define PERF_EXTIRQ_CFG_REG_6362	0x18
+ #define PERF_EXTIRQ_CFG_REG_6368	0x18
++#define PERF_EXTIRQ_CFG_REG_63268	0x18
+ 
+ #define PERF_EXTIRQ_CFG_REG2_6358	0x1c
+ #define PERF_EXTIRQ_CFG_REG2_6368	0x1c
+@@ -274,6 +325,7 @@
+ #define PERF_SOFTRESET_6358_REG		0x34
+ #define PERF_SOFTRESET_6362_REG		0x10
+ #define PERF_SOFTRESET_6368_REG		0x10
++#define PERF_SOFTRESET_63268_REG	0x10
+ 
+ #define SOFTRESET_3368_SPI_MASK		(1 << 0)
+ #define SOFTRESET_3368_ENET_MASK	(1 << 2)
+@@ -367,6 +419,26 @@
+ #define SOFTRESET_6368_USBH_MASK	(1 << 12)
+ #define SOFTRESET_6368_PCM_MASK		(1 << 13)
+ 
++#define SOFTRESET_63268_SPI_MASK	(1 << 0)
++#define SOFTRESET_63268_IPSEC_MASK	(1 << 1)
++#define SOFTRESET_63268_EPHY_MASK	(1 << 2)
++#define SOFTRESET_63268_SAR_MASK	(1 << 3)
++#define SOFTRESET_63268_ENETSW_MASK	(1 << 4)
++#define SOFTRESET_63268_USBS_MASK	(1 << 5)
++#define SOFTRESET_63268_USBH_MASK	(1 << 6)
++#define SOFTRESET_63268_PCM_MASK	(1 << 7)
++#define SOFTRESET_63268_PCIE_CORE_MASK	(1 << 8)
++#define SOFTRESET_63268_PCIE_MASK	(1 << 9)
++#define SOFTRESET_63268_PCIE_EXT_MASK	(1 << 10)
++#define SOFTRESET_63268_WLAN_SHIM_MASK	(1 << 11)
++#define SOFTRESET_63268_DDR_PHY_MASK	(1 << 12)
++#define SOFTRESET_63268_FAP0_MASK	(1 << 13)
++#define SOFTRESET_63268_WLAN_UBUS_MASK	(1 << 14)
++#define SOFTRESET_63268_DECT_MASK	(1 << 15)
++#define SOFTRESET_63268_FAP1_MASK	(1 << 16)
++#define SOFTRESET_63268_PCIE_HARD_MASK	(1 << 17)
++#define SOFTRESET_63268_GPHY_MASK	(1 << 18)
++
+ /* MIPS PLL control register */
+ #define PERF_MIPSPLLCTL_REG		0x34
+ #define MIPSPLLCTL_N1_SHIFT		20
+@@ -1366,6 +1438,13 @@
+ #define STRAPBUS_6362_BOOT_SEL_SERIAL	(1 << 15)
+ #define STRAPBUS_6362_BOOT_SEL_NAND	(0 << 15)
+ 
++#define MISC_STRAPBUS_63268_REG		0x14
++#define STRAPBUS_63268_HSSPI_CLK_FAST	(1 << 9)
++#define STRAPBUS_63268_BOOT_SEL_SERIAL	(1 << 11)
++#define STRAPBUS_63268_BOOT_SEL_NAND	(0 << 11)
++#define STRAPBUS_63268_FCVO_SHIFT	21
++#define STRAPBUS_63268_FCVO_MASK	(0xf << STRAPBUS_63268_FCVO_SHIFT)
++
+ #define MISC_STRAPBUS_6328_REG		0x240
+ #define STRAPBUS_6328_FCVO_SHIFT	7
+ #define STRAPBUS_6328_FCVO_MASK		(0x1f << STRAPBUS_6328_FCVO_SHIFT)
+--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
++++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+@@ -25,6 +25,7 @@ static inline int is_bcm63xx_internal_re
+ 	case BCM6328_CPU_ID:
+ 	case BCM6362_CPU_ID:
+ 	case BCM6368_CPU_ID:
++	case BCM63268_CPU_ID:
+ 		if (offset >= 0xb0000000 && offset < 0xb1000000)
+ 			return 1;
+ 		break;
+--- a/arch/mips/bcm63xx/dev-hsspi.c
++++ b/arch/mips/bcm63xx/dev-hsspi.c
+@@ -35,7 +35,7 @@ static struct platform_device bcm63xx_hs
+ 
+ int __init bcm63xx_hsspi_register(void)
+ {
+-	if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362())
++	if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_63268())
+ 		return -ENODEV;
+ 
+ 	spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI);
+--- a/arch/mips/bcm63xx/dev-enet.c
++++ b/arch/mips/bcm63xx/dev-enet.c
+@@ -176,7 +176,8 @@ static int __init register_shared(void)
+ 	else
+ 		shared_res[0].end += (RSET_ENETDMA_SIZE)  - 1;
+ 
+-	if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
++	if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() ||
++		BCMCPU_IS_63268())
+ 		chan_count = 32;
+ 	else if (BCMCPU_IS_6345())
+ 		chan_count = 8;
+@@ -284,7 +285,8 @@ bcm63xx_enetsw_register(const struct bcm
+ {
+ 	int ret;
+ 
+-	if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
++	if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368() &&
++		!BCMCPU_IS_63268())
+ 		return -ENODEV;
+ 
+ 	ret = register_shared();
+@@ -305,6 +307,8 @@ bcm63xx_enetsw_register(const struct bcm
+ 		enetsw_pd.num_ports = ENETSW_PORTS_6328;
+ 	else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
+ 		enetsw_pd.num_ports = ENETSW_PORTS_6368;
++	else if (BCMCPU_IS_63268())
++		enetsw_pd.num_ports = ENETSW_PORTS_63268;
+ 
+ 	enetsw_pd.dma_has_sram = true;
+ 	enetsw_pd.dma_chan_width = ENETDMA_CHAN_WIDTH;
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
+@@ -66,6 +66,7 @@ struct bcm63xx_enet_platform_data {
+ #define ENETSW_MAX_PORT	8
+ #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
+ #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
++#define ENETSW_PORTS_63268 8 /* 3 FE PHY + 1 GE PHY + 4 RGMII */
+ 
+ #define ENETSW_RGMII_PORT0	4
+ 

target/linux/brcm63xx/patches-4.9/340-MIPS-BCM63XX-add-pcie-support-for-BCM63268.patch

@@ -0,0 +1,55 @@
+From 5c290c81dbdb4433600593fe80c88eb4af86e791 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 8 Dec 2013 03:22:40 +0100
+Subject: [PATCH 50/53] MIPS: BCM63XX: add pcie support for BCM63268
+
+---
+ arch/mips/bcm63xx/reset.c                       | 3 ++-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 5 +++++
+ arch/mips/pci/pci-bcm63xx.c                     | 4 ++++
+ 3 files changed, 11 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/bcm63xx/reset.c
++++ b/arch/mips/bcm63xx/reset.c
+@@ -136,7 +136,8 @@
+ #define BCM63268_RESET_PCM	SOFTRESET_63268_PCM_MASK
+ #define BCM63268_RESET_MPI	0
+ #define BCM63268_RESET_PCIE	(SOFTRESET_63268_PCIE_MASK | \
+-				 SOFTRESET_63268_PCIE_CORE_MASK)
++				 SOFTRESET_63268_PCIE_CORE_MASK | \
++				 SOFTRESET_63268_PCIE_HARD_MASK)
+ #define BCM63268_RESET_PCIE_EXT	SOFTRESET_63268_PCIE_EXT_MASK
+ 
+ /*
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+@@ -45,6 +45,11 @@
+ #define BCM_PCIE_MEM_END_PA_6328	(BCM_PCIE_MEM_BASE_PA_6328 +	\
+ 					BCM_PCIE_MEM_SIZE_6328 - 1)
+ 
++#define BCM_PCIE_MEM_BASE_PA_63268	0x11000000
++#define BCM_PCIE_MEM_SIZE_63268		(15 * 1024 * 1024)
++#define BCM_PCIE_MEM_END_PA_63268	(BCM_PCIE_MEM_BASE_PA_63268 +	\
++					BCM_PCIE_MEM_SIZE_63268 - 1)
++
+ /*
+  * Internal registers are accessed through KSEG3
+  */
+--- a/arch/mips/pci/pci-bcm63xx.c
++++ b/arch/mips/pci/pci-bcm63xx.c
+@@ -337,11 +337,15 @@ static int __init bcm63xx_pci_init(void)
+ 	if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
+ 		bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328;
+ 		bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328;
++	} else if (BCMCPU_IS_63268()) {
++		bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_63268;
++		bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_63268;
+ 	}
+ 
+ 	switch (bcm63xx_get_cpu_id()) {
+ 	case BCM6328_CPU_ID:
+ 	case BCM6362_CPU_ID:
++	case BCM63268_CPU_ID:
+ 		return bcm63xx_register_pcie();
+ 	case BCM3368_CPU_ID:
+ 	case BCM6348_CPU_ID:

target/linux/brcm63xx/patches-4.9/341-MIPS-BCM63XX-add-support-for-BCM6318.patch

@@ -0,0 +1,697 @@
+From 60c29522a8c77d96145d965589c56befda7d4c3d Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 8 Dec 2013 01:24:09 +0100
+Subject: [PATCH 51/53] MIPS: BCM63XX: add support for BCM6318
+
+---
+ arch/mips/bcm63xx/Kconfig                         |   5 +
+ arch/mips/bcm63xx/boards/board_bcm963xx.c         |   2 +-
+ arch/mips/bcm63xx/clk.c                           |   8 +-
+ arch/mips/bcm63xx/cpu.c                           |  53 +++++++++++
+ arch/mips/bcm63xx/dev-flash.c                     |   3 +
+ arch/mips/bcm63xx/dev-spi.c                       |   2 +-
+ arch/mips/bcm63xx/irq.c                           |  10 ++
+ arch/mips/bcm63xx/prom.c                          |   2 +-
+ arch/mips/bcm63xx/reset.c                         |  24 +++++
+ arch/mips/bcm63xx/setup.c                         |   5 +-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  | 107 ++++++++++++++++++++++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |  75 ++++++++++++++-
+ arch/mips/include/asm/mach-bcm63xx/ioremap.h      |   1 +
+ 13 files changed, 291 insertions(+), 6 deletions(-)
+
+--- a/arch/mips/bcm63xx/Kconfig
++++ b/arch/mips/bcm63xx/Kconfig
+@@ -18,6 +18,11 @@ config BCM63XX_EHCI
+ 	select USB_EHCI_BIG_ENDIAN_DESC if USB_EHCI_HCD
+ 	select USB_EHCI_BIG_ENDIAN_MMIO if USB_EHCI_HCD
+ 
++config BCM63XX_CPU_6318
++	bool "support 6318 CPU"
++	select SYS_HAS_CPU_BMIPS32_3300
++	select HW_HAS_PCI
++
+ config BCM63XX_CPU_6328
+ 	bool "support 6328 CPU"
+ 	select SYS_HAS_CPU_BMIPS4350
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -713,7 +713,7 @@ void __init board_prom_init(void)
+ 	/* read base address of boot chip select (0)
+ 	 * 6328/6362 do not have MPI but boot from a fixed address
+ 	 */
+-	if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) {
++	if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) {
+ 		val = 0x18000000;
+ 	} else {
+ 		val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -288,7 +288,9 @@ static void hsspi_set(struct clk *clk, i
+ {
+ 	u32 mask;
+ 
+-	if (BCMCPU_IS_6328())
++	if (BCMCPU_IS_6318())
++		mask = CKCTL_6318_HSSPI_EN;
++	else if (BCMCPU_IS_6328())
+ 		mask = CKCTL_6328_HSSPI_EN;
+ 	else if (BCMCPU_IS_6362())
+ 		mask = CKCTL_6362_HSSPI_EN;
+@@ -443,6 +445,19 @@ static struct clk_lookup bcm3368_clks[]
+ 	CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1),
+ };
+ 
++static struct clk_lookup bcm6318_clks[] = {
++	/* fixed rate clocks */
++	CLKDEV_INIT(NULL, "periph", &clk_periph),
++	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
++	CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
++	/* gated clocks */
++	CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
++	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
++	CLKDEV_INIT(NULL, "usbd", &clk_usbh),
++	CLKDEV_INIT(NULL, "hsspi", &clk_hsspi),
++	CLKDEV_INIT(NULL, "pcie", &clk_pcie),
++};
++
+ static struct clk_lookup bcm6328_clks[] = {
+ 	/* fixed rate clocks */
+ 	CLKDEV_INIT(NULL, "periph", &clk_periph),
+@@ -564,6 +579,7 @@ static struct clk_lookup bcm63268_clks[]
+ 	CLKDEV_INIT(NULL, "pcie", &clk_pcie),
+ };
+ 
++#define HSSPI_PLL_HZ_6318	250000000
+ #define HSSPI_PLL_HZ_6328	133333333
+ #define HSSPI_PLL_HZ_6362	400000000
+ 
+@@ -573,6 +589,10 @@ static int __init bcm63xx_clk_init(void)
+ 	case BCM3368_CPU_ID:
+ 		clkdev_add_table(bcm3368_clks, ARRAY_SIZE(bcm3368_clks));
+ 		break;
++	case BCM6318_CPU_ID:
++		clk_hsspi_pll.rate = HSSPI_PLL_HZ_6318;
++		clkdev_add_table(bcm6318_clks, ARRAY_SIZE(bcm6318_clks));
++		break;
+ 	case BCM6328_CPU_ID:
+ 		clk_hsspi_pll.rate = HSSPI_PLL_HZ_6328;
+ 		clkdev_add_table(bcm6328_clks, ARRAY_SIZE(bcm6328_clks));
+--- a/arch/mips/bcm63xx/cpu.c
++++ b/arch/mips/bcm63xx/cpu.c
+@@ -41,6 +41,14 @@ static const int bcm3368_irqs[] = {
+ 	__GEN_CPU_IRQ_TABLE(3368)
+ };
+ 
++static const unsigned long bcm6318_regs_base[] = {
++	__GEN_CPU_REGS_TABLE(6318)
++};
++
++static const int bcm6318_irqs[] = {
++	__GEN_CPU_IRQ_TABLE(6318)
++};
++
+ static const unsigned long bcm6328_regs_base[] = {
+ 	__GEN_CPU_REGS_TABLE(6328)
+ };
+@@ -134,6 +142,10 @@ unsigned int bcm63xx_get_memory_size(voi
+ 	return bcm63xx_memory_size;
+ }
+ 
++#define STRAP_OVERRIDE_BUS_REG		0x0
++#define OVERRIDE_BUS_MIPS_FREQ_SHIFT	23
++#define OVERRIDE_BUS_MIPS_FREQ_MASK	(0x3 << OVERRIDE_BUS_MIPS_FREQ_SHIFT)
++
+ static unsigned int detect_cpu_clock(void)
+ {
+ 	u32 cpu_id = bcm63xx_get_cpu_id();
+@@ -142,6 +154,28 @@ static unsigned int detect_cpu_clock(voi
+ 	case BCM3368_CPU_ID:
+ 		return 300000000;
+ 
++	case BCM6318_CPU_ID:
++	{
++		unsigned int tmp, mips_pll_fcvo;
++
++		tmp = bcm_readl(BCM_6318_STRAP_BASE + STRAP_OVERRIDE_BUS_REG);
++
++		pr_info("strap_override_bus = %08x\n", tmp);
++
++		mips_pll_fcvo = (tmp & OVERRIDE_BUS_MIPS_FREQ_MASK)
++				>> OVERRIDE_BUS_MIPS_FREQ_SHIFT;
++
++		switch (mips_pll_fcvo) {
++		case 0:
++			return 166000000;
++		case 1:
++			return 400000000;
++		case 2:
++			return 250000000;
++		case 3:
++			return 333000000;
++		};
++	}
+ 	case BCM6328_CPU_ID:
+ 	{
+ 		unsigned int tmp, mips_pll_fcvo;
+@@ -297,6 +331,13 @@ static unsigned int detect_memory_size(v
+ 	unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
+ 	u32 val;
+ 
++	if (BCMCPU_IS_6318()) {
++		val = bcm_sdram_readl(SDRAM_CFG_REG);
++		val = val & SDRAM_CFG_6318_SPACE_MASK;
++		val >>= SDRAM_CFG_6318_SPACE_SHIFT;
++		return 1 << (val + 20);
++	}
++
+ 	if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268())
+ 		return bcm_ddr_readl(DDR_CSEND_REG) << 24;
+ 
+@@ -343,6 +384,12 @@ void __init bcm63xx_cpu_init(void)
+ 
+ 	switch (current_cpu_type()) {
+ 	case CPU_BMIPS3300:
++		if ((read_c0_prid() & 0xff) >= 0x33) {
++			/* BCM6318 */
++			chipid_reg = BCM_6368_PERF_BASE;
++			break;
++		}
++
+ 		if ((read_c0_prid() & PRID_IMP_MASK) != PRID_IMP_BMIPS3300_ALT)
+ 			__cpu_name[cpu] = "Broadcom BCM6338";
+ 		/* fall-through */
+@@ -390,6 +437,10 @@ void __init bcm63xx_cpu_init(void)
+ 	bcm63xx_cpu_variant = bcm63xx_cpu_id;
+ 
+ 	switch (bcm63xx_cpu_id) {
++	case BCM6318_CPU_ID:
++		bcm63xx_regs_base = bcm6318_regs_base;
++		bcm63xx_irqs = bcm6318_irqs;
++		break;
+ 	case BCM3368_CPU_ID:
+ 		bcm63xx_regs_base = bcm3368_regs_base;
+ 		bcm63xx_irqs = bcm3368_irqs;
+--- a/arch/mips/bcm63xx/dev-flash.c
++++ b/arch/mips/bcm63xx/dev-flash.c
+@@ -60,6 +60,9 @@ static int __init bcm63xx_detect_flash_t
+ 	u32 val;
+ 
+ 	switch (bcm63xx_get_cpu_id()) {
++	case BCM6318_CPU_ID:
++		/* only support serial flash */
++		return BCM63XX_FLASH_TYPE_SERIAL;
+ 	case BCM6328_CPU_ID:
+ 		val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
+ 		if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
+--- a/arch/mips/bcm63xx/dev-spi.c
++++ b/arch/mips/bcm63xx/dev-spi.c
+@@ -38,7 +38,7 @@ static struct platform_device bcm63xx_sp
+ 
+ int __init bcm63xx_spi_register(void)
+ {
+-	if (BCMCPU_IS_6328() || BCMCPU_IS_6345())
++	if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6345())
+ 		return -ENODEV;
+ 
+ 	spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -49,6 +49,19 @@ void __init arch_init_irq(void)
+ 		ext_irqs[3] = BCM_3368_EXT_IRQ3;
+ 		ext_shift = 4;
+ 		break;
++	case BCM6318_CPU_ID:
++		periph_bases[0] += PERF_IRQMASK_6318_REG;
++		periph_irq_count = 1;
++		periph_width = 4;
++
++		ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6318;
++		ext_irq_count = 4;
++		ext_irqs[0] = BCM_6318_EXT_IRQ0;
++		ext_irqs[1] = BCM_6318_EXT_IRQ0;
++		ext_irqs[2] = BCM_6318_EXT_IRQ0;
++		ext_irqs[3] = BCM_6318_EXT_IRQ0;
++		ext_shift = 4;
++		break;
+ 	case BCM6328_CPU_ID:
+ 		periph_bases[0] += PERF_IRQMASK_6328_REG(0);
+ 		periph_bases[1] += PERF_IRQMASK_6328_REG(1);
+--- a/arch/mips/bcm63xx/prom.c
++++ b/arch/mips/bcm63xx/prom.c
+@@ -68,7 +68,7 @@ void __init prom_init(void)
+ 
+ 			if (reg & OTP_6328_REG3_TP1_DISABLED)
+ 				bmips_smp_enabled = 0;
+-		} else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
++		} else if (BCMCPU_IS_6318() || BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
+ 			bmips_smp_enabled = 0;
+ 		}
+ 
+--- a/arch/mips/bcm63xx/reset.c
++++ b/arch/mips/bcm63xx/reset.c
+@@ -43,6 +43,23 @@
+ #define BCM3368_RESET_PCIE	0
+ #define BCM3368_RESET_PCIE_EXT	0
+ 
++
++#define BCM6318_RESET_SPI	SOFTRESET_6318_SPI_MASK
++#define BCM6318_RESET_ENET	0
++#define BCM6318_RESET_USBH	SOFTRESET_6318_USBH_MASK
++#define BCM6318_RESET_USBD	SOFTRESET_6318_USBS_MASK
++#define BCM6318_RESET_DSL	0
++#define BCM6318_RESET_SAR	SOFTRESET_6318_SAR_MASK
++#define BCM6318_RESET_EPHY	SOFTRESET_6318_EPHY_MASK
++#define BCM6318_RESET_ENETSW	SOFTRESET_6318_ENETSW_MASK
++#define BCM6318_RESET_PCM	0
++#define BCM6318_RESET_MPI	0
++#define BCM6318_RESET_PCIE	\
++				(SOFTRESET_6318_PCIE_MASK |		\
++				 SOFTRESET_6318_PCIE_CORE_MASK |	\
++				 SOFTRESET_6318_PCIE_HARD_MASK)
++#define BCM6318_RESET_PCIE_EXT	SOFTRESET_6318_PCIE_EXT_MASK
++
+ #define BCM6328_RESET_SPI	SOFTRESET_6328_SPI_MASK
+ #define BCM6328_RESET_ENET	0
+ #define BCM6328_RESET_USBH	SOFTRESET_6328_USBH_MASK
+@@ -147,6 +164,10 @@ static const u32 bcm3368_reset_bits[] =
+ 	__GEN_RESET_BITS_TABLE(3368)
+ };
+ 
++static const u32 bcm6318_reset_bits[] = {
++	__GEN_RESET_BITS_TABLE(6318)
++};
++
+ static const u32 bcm6328_reset_bits[] = {
+ 	__GEN_RESET_BITS_TABLE(6328)
+ };
+@@ -183,6 +204,9 @@ static int __init bcm63xx_reset_bits_ini
+ 	if (BCMCPU_IS_3368()) {
+ 		reset_reg = PERF_SOFTRESET_6358_REG;
+ 		bcm63xx_reset_bits = bcm3368_reset_bits;
++	} else if (BCMCPU_IS_6318()) {
++		reset_reg = PERF_SOFTRESET_6318_REG;
++		bcm63xx_reset_bits = bcm6318_reset_bits;
+ 	} else if (BCMCPU_IS_6328()) {
+ 		reset_reg = PERF_SOFTRESET_6328_REG;
+ 		bcm63xx_reset_bits = bcm6328_reset_bits;
+--- a/arch/mips/bcm63xx/setup.c
++++ b/arch/mips/bcm63xx/setup.c
+@@ -72,6 +72,9 @@ void bcm63xx_machine_reboot(void)
+ 	case BCM3368_CPU_ID:
+ 		perf_regs[0] = PERF_EXTIRQ_CFG_REG_3368;
+ 		break;
++	case BCM6318_CPU_ID:
++		perf_regs[0] = PERF_EXTIRQ_CFG_REG_6318;
++		break;
+ 	case BCM6328_CPU_ID:
+ 		perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
+ 		break;
+@@ -111,7 +114,7 @@ void bcm63xx_machine_reboot(void)
+ 		bcm6348_a1_reboot();
+ 
+ 	pr_info("triggering watchdog soft-reset...\n");
+-	if (BCMCPU_IS_6328()) {
++	if (BCMCPU_IS_6318() || BCMCPU_IS_6328()) {
+ 		bcm_wdt_writel(1, WDT_SOFTRESET_REG);
+ 	} else {
+ 		reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -10,6 +10,7 @@
+  * arm mach-types)
+  */
+ #define BCM3368_CPU_ID		0x3368
++#define BCM6318_CPU_ID		0x6318
+ #define BCM6328_CPU_ID		0x6328
+ #define BCM63281_CPU_ID		0x63281
+ #define BCM63283_CPU_ID		0x63283
+@@ -38,6 +39,10 @@ static inline u32 __pure __bcm63xx_get_c
+ 		case BCM3368_CPU_ID:
+ #endif
+ 
++#ifdef CONFIG_BCM63XX_CPU_6318
++		case BCM6318_CPU_ID:
++#endif
++
+ #ifdef CONFIG_BCM63XX_CPU_6328
+ 		case BCM6328_CPU_ID:
+ #endif
+@@ -87,6 +92,7 @@ static inline u32 __pure bcm63xx_get_cpu
+ }
+ 
+ #define BCMCPU_IS_3368()	(bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
++#define BCMCPU_IS_6318()	(bcm63xx_get_cpu_id() == BCM6318_CPU_ID)
+ #define BCMCPU_IS_6328()	(bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
+ #define BCMCPU_IS_6338()	(bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
+ #define BCMCPU_IS_6345()	(bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
+@@ -98,6 +104,8 @@ static inline u32 __pure bcm63xx_get_cpu
+ 
+ #define BCMCPU_VARIANT_IS_3368() \
+ 	(bcm63xx_get_cpu_variant() == BCM3368_CPU_ID)
++#define BCMCPU_VARIANT_IS_6318() \
++	(bcm63xx_get_cpu_variant() == BCM6318_CPU_ID)
+ #define BCMCPU_VARIANT_IS_63281() \
+ 	(bcm63xx_get_cpu_variant() == BCM63281_CPU_ID)
+ #define BCMCPU_VARIANT_IS_63283() \
+@@ -252,6 +260,56 @@ enum bcm63xx_regs_set {
+ #define BCM_3368_MISC_BASE		(0xdeadbeef)
+ 
+ /*
++ * 6318 register sets base address
++ */
++#define BCM_6318_DSL_LMEM_BASE		(0xdeadbeef)
++#define BCM_6318_PERF_BASE		(0xb0000000)
++#define BCM_6318_TIMER_BASE		(0xb0000040)
++#define BCM_6318_WDT_BASE		(0xb0000068)
++#define BCM_6318_UART0_BASE		(0xb0000100)
++#define BCM_6318_UART1_BASE		(0xdeadbeef)
++#define BCM_6318_GPIO_BASE		(0xb0000080)
++#define BCM_6318_SPI_BASE		(0xdeadbeef)
++#define BCM_6318_HSSPI_BASE		(0xb0003000)
++#define BCM_6318_UDC0_BASE		(0xdeadbeef)
++#define BCM_6318_USBDMA_BASE		(0xb0006800)
++#define BCM_6318_OHCI0_BASE		(0xb0005100)
++#define BCM_6318_OHCI_PRIV_BASE		(0xdeadbeef)
++#define BCM_6318_USBH_PRIV_BASE		(0xb0005200)
++#define BCM_6318_USBD_BASE		(0xb0006000)
++#define BCM_6318_MPI_BASE		(0xdeadbeef)
++#define BCM_6318_PCMCIA_BASE		(0xdeadbeef)
++#define BCM_6318_PCIE_BASE		(0xb0010000)
++#define BCM_6318_SDRAM_REGS_BASE	(0xdeadbeef)
++#define BCM_6318_DSL_BASE		(0xdeadbeef)
++#define BCM_6318_UBUS_BASE		(0xdeadbeef)
++#define BCM_6318_ENET0_BASE		(0xdeadbeef)
++#define BCM_6318_ENET1_BASE		(0xdeadbeef)
++#define BCM_6318_ENETDMA_BASE		(0xb0088000)
++#define BCM_6318_ENETDMAC_BASE		(0xb0088200)
++#define BCM_6318_ENETDMAS_BASE		(0xb0088400)
++#define BCM_6318_ENETSW_BASE		(0xb0080000)
++#define BCM_6318_EHCI0_BASE		(0xb0005000)
++#define BCM_6318_SDRAM_BASE		(0xb0004000)
++#define BCM_6318_MEMC_BASE		(0xdeadbeef)
++#define BCM_6318_DDR_BASE		(0xdeadbeef)
++#define BCM_6318_M2M_BASE		(0xdeadbeef)
++#define BCM_6318_ATM_BASE		(0xdeadbeef)
++#define BCM_6318_XTM_BASE		(0xdeadbeef)
++#define BCM_6318_XTMDMA_BASE		(0xb000c000)
++#define BCM_6318_XTMDMAC_BASE		(0xdeadbeef)
++#define BCM_6318_XTMDMAS_BASE		(0xdeadbeef)
++#define BCM_6318_PCM_BASE		(0xdeadbeef)
++#define BCM_6318_PCMDMA_BASE		(0xdeadbeef)
++#define BCM_6318_PCMDMAC_BASE		(0xdeadbeef)
++#define BCM_6318_PCMDMAS_BASE		(0xdeadbeef)
++#define BCM_6318_RNG_BASE		(0xdeadbeef)
++#define BCM_6318_MISC_BASE		(0xb0000280)
++#define BCM_6318_OTP_BASE		(0xdeadbeef)
++
++#define BCM_6318_STRAP_BASE		(0xb0000900)
++
++/*
+  * 6328 register sets base address
+  */
+ #define BCM_6328_DSL_LMEM_BASE		(0xdeadbeef)
+@@ -774,6 +832,55 @@ enum bcm63xx_irq {
+ #define BCM_3368_EXT_IRQ2		(IRQ_INTERNAL_BASE + 27)
+ #define BCM_3368_EXT_IRQ3		(IRQ_INTERNAL_BASE + 28)
+ 
++/*
++ * 6318 irqs
++ */
++#define BCM_6318_HIGH_IRQ_BASE		(IRQ_INTERNAL_BASE + 32)
++#define BCM_6318_VERY_HIGH_IRQ_BASE	(BCM_6318_HIGH_IRQ_BASE + 32)
++
++#define BCM_6318_TIMER_IRQ		(IRQ_INTERNAL_BASE + 31)
++#define BCM_6318_SPI_IRQ		0
++#define BCM_6318_UART0_IRQ		(IRQ_INTERNAL_BASE + 28)
++#define BCM_6318_UART1_IRQ		0
++#define BCM_6318_DSL_IRQ		(IRQ_INTERNAL_BASE + 21)
++#define BCM_6318_UDC0_IRQ		0
++#define BCM_6318_ENET0_IRQ		0
++#define BCM_6318_ENET1_IRQ		0
++#define BCM_6318_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 12)
++#define BCM_6318_HSSPI_IRQ		(IRQ_INTERNAL_BASE + 29)
++#define BCM_6318_OHCI0_IRQ		(BCM_6318_HIGH_IRQ_BASE + 9)
++#define BCM_6318_EHCI0_IRQ		(BCM_6318_HIGH_IRQ_BASE + 10)
++#define BCM_6318_USBD_IRQ		(IRQ_INTERNAL_BASE + 4)
++#define BCM_6318_USBD_RXDMA0_IRQ	(IRQ_INTERNAL_BASE + 5)
++#define BCM_6318_USBD_TXDMA0_IRQ	(IRQ_INTERNAL_BASE + 6)
++#define BCM_6318_USBD_RXDMA1_IRQ	(IRQ_INTERNAL_BASE + 7)
++#define BCM_6318_USBD_TXDMA1_IRQ	(IRQ_INTERNAL_BASE + 8)
++#define BCM_6318_USBD_RXDMA2_IRQ	(IRQ_INTERNAL_BASE + 9)
++#define BCM_6318_USBD_TXDMA2_IRQ	(IRQ_INTERNAL_BASE + 10)
++#define BCM_6318_PCMCIA_IRQ		0
++#define BCM_6318_ENET0_RXDMA_IRQ	0
++#define BCM_6318_ENET0_TXDMA_IRQ	0
++#define BCM_6318_ENET1_RXDMA_IRQ	0
++#define BCM_6318_ENET1_TXDMA_IRQ	0
++#define BCM_6318_PCI_IRQ		(IRQ_INTERNAL_BASE + 23)
++#define BCM_6318_ATM_IRQ		0
++#define BCM_6318_ENETSW_RXDMA0_IRQ	(BCM_6318_HIGH_IRQ_BASE + 0)
++#define BCM_6318_ENETSW_RXDMA1_IRQ	(BCM_6318_HIGH_IRQ_BASE + 1)
++#define BCM_6318_ENETSW_RXDMA2_IRQ	(BCM_6318_HIGH_IRQ_BASE + 2)
++#define BCM_6318_ENETSW_RXDMA3_IRQ	(BCM_6318_HIGH_IRQ_BASE + 3)
++#define BCM_6318_ENETSW_TXDMA0_IRQ	(BCM_6318_VERY_HIGH_IRQ_BASE + 10)
++#define BCM_6318_ENETSW_TXDMA1_IRQ	(BCM_6318_VERY_HIGH_IRQ_BASE + 11)
++#define BCM_6318_ENETSW_TXDMA2_IRQ	(BCM_6318_VERY_HIGH_IRQ_BASE + 12)
++#define BCM_6318_ENETSW_TXDMA3_IRQ	(BCM_6318_VERY_HIGH_IRQ_BASE + 13)
++#define BCM_6318_XTM_IRQ		(BCM_6318_HIGH_IRQ_BASE + 31)
++#define BCM_6318_XTM_DMA0_IRQ		(BCM_6318_HIGH_IRQ_BASE + 11)
++
++#define BCM_6318_PCM_DMA0_IRQ		(IRQ_INTERNAL_BASE + 2)
++#define BCM_6318_PCM_DMA1_IRQ		(IRQ_INTERNAL_BASE + 3)
++#define BCM_6318_EXT_IRQ0		(IRQ_INTERNAL_BASE + 24)
++#define BCM_6318_EXT_IRQ1		(IRQ_INTERNAL_BASE + 25)
++#define BCM_6318_EXT_IRQ2		(IRQ_INTERNAL_BASE + 26)
++#define BCM_6318_EXT_IRQ3		(IRQ_INTERNAL_BASE + 27)
+ 
+ /*
+  * 6328 irqs
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -52,6 +52,39 @@
+ 					 CKCTL_3368_EMUSB_EN | \
+ 					 CKCTL_3368_USBU_EN)
+ 
++#define CKCTL_6318_ADSL_ASB_EN		(1 << 0)
++#define CKCTL_6318_USB_ASB_EN		(1 << 1)
++#define CKCTL_6318_MIPS_ASB_EN		(1 << 2)
++#define CKCTL_6318_PCIE_ASB_EN		(1 << 3)
++#define CKCTL_6318_PHYMIPS_ASB_EN	(1 << 4)
++#define CKCTL_6318_ROBOSW_ASB_EN	(1 << 5)
++#define CKCTL_6318_SAR_ASB_EN		(1 << 6)
++#define CKCTL_6318_SDR_ASB_EN		(1 << 7)
++#define CKCTL_6318_SWREG_ASB_EN		(1 << 8)
++#define CKCTL_6318_PERIPH_ASB_EN	(1 << 9)
++#define CKCTL_6318_CPUBUS160_EN		(1 << 10)
++#define CKCTL_6318_ADSL_EN		(1 << 11)
++#define CKCTL_6318_SAR125_EN		(1 << 12)
++#define CKCTL_6318_MIPS_EN		(1 << 13)
++#define CKCTL_6318_PCIE_EN		(1 << 14)
++#define CKCTL_6318_ROBOSW250_EN		(1 << 16)
++#define CKCTL_6318_ROBOSW025_EN		(1 << 17)
++#define CKCTL_6318_SDR_EN		(1 << 19)
++#define CKCTL_6318_USB_EN		(1 << 20) /* both device and host */
++#define CKCTL_6318_HSSPI_EN		(1 << 25)
++#define CKCTL_6318_PCIE25_EN		(1 << 27)
++#define CKCTL_6318_PHYMIPS_EN		(1 << 28)
++#define CKCTL_6318_ADSL_AFE_EN		(1 << 29)
++#define CKCTL_6318_ADSL_QPROC_EN	(1 << 30)
++
++#define CKCTL_6318_ALL_SAFE_EN		(CKCTL_6318_PHYMIPS_EN |	\
++					CKCTL_6318_ADSL_QPROC_EN |	\
++					CKCTL_6318_ADSL_AFE_EN |	\
++					CKCTL_6318_ADSL_EN |		\
++					CKCTL_6318_SAR_EN  |		\
++					CKCTL_6318_USB_EN |		\
++					CKCTL_6318_PCIE_EN)
++
+ #define CKCTL_6328_PHYMIPS_EN		(1 << 0)
+ #define CKCTL_6328_ADSL_QPROC_EN	(1 << 1)
+ #define CKCTL_6328_ADSL_AFE_EN		(1 << 2)
+@@ -259,12 +292,27 @@
+ 					CKCTL_63268_TBUS_EN |		\
+ 					CKCTL_63268_ROBOSW250_EN)
+ 
++/* UBUS Clock Control register */
++#define PERF_UB_CKCTL_REG		0x10
++
++#define UB_CKCTL_6318_ADSL_EN		(1 << 0)
++#define UB_CKCTL_6318_ARB_EN		(1 << 1)
++#define UB_CKCTL_6318_MIPS_EN		(1 << 2)
++#define UB_CKCTL_6318_PCIE_EN		(1 << 3)
++#define UB_CKCTL_6318_PERIPH_EN		(1 << 4)
++#define UB_CKCTL_6318_PHYMIPS_EN	(1 << 5)
++#define UB_CKCTL_6318_ROBOSW_EN		(1 << 6)
++#define UB_CKCTL_6318_SAR_EN		(1 << 7)
++#define UB_CKCTL_6318_SDR_EN		(1 << 8)
++#define UB_CKCTL_6318_USB_EN		(1 << 9)
++
+ /* System PLL Control register	*/
+ #define PERF_SYS_PLL_CTL_REG		0x8
+ #define SYS_PLL_SOFT_RESET		0x1
+ 
+ /* Interrupt Mask register */
+ #define PERF_IRQMASK_3368_REG		0xc
++#define PERF_IRQMASK_6318_REG		0x20
+ #define PERF_IRQMASK_6328_REG(x)	(0x20 + (x) * 0x10)
+ #define PERF_IRQMASK_6338_REG		0xc
+ #define PERF_IRQMASK_6345_REG		0xc
+@@ -276,6 +324,7 @@
+ 
+ /* Interrupt Status register */
+ #define PERF_IRQSTAT_3368_REG		0x10
++#define PERF_IRQSTAT_6318_REG		0x30
+ #define PERF_IRQSTAT_6328_REG(x)	(0x28 + (x) * 0x10)
+ #define PERF_IRQSTAT_6338_REG		0x10
+ #define PERF_IRQSTAT_6345_REG		0x10
+@@ -287,6 +336,7 @@
+ 
+ /* External Interrupt Configuration register */
+ #define PERF_EXTIRQ_CFG_REG_3368	0x14
++#define PERF_EXTIRQ_CFG_REG_6318	0x18
+ #define PERF_EXTIRQ_CFG_REG_6328	0x18
+ #define PERF_EXTIRQ_CFG_REG_6338	0x14
+ #define PERF_EXTIRQ_CFG_REG_6345	0x14
+@@ -321,6 +371,7 @@
+ 
+ /* Soft Reset register */
+ #define PERF_SOFTRESET_REG		0x28
++#define PERF_SOFTRESET_6318_REG		0x10
+ #define PERF_SOFTRESET_6328_REG		0x10
+ #define PERF_SOFTRESET_6358_REG		0x34
+ #define PERF_SOFTRESET_6362_REG		0x10
+@@ -334,6 +385,18 @@
+ #define SOFTRESET_3368_USBS_MASK	(1 << 11)
+ #define SOFTRESET_3368_PCM_MASK		(1 << 13)
+ 
++#define SOFTRESET_6318_SPI_MASK		(1 << 0)
++#define SOFTRESET_6318_EPHY_MASK	(1 << 1)
++#define SOFTRESET_6318_SAR_MASK		(1 << 2)
++#define SOFTRESET_6318_ENETSW_MASK	(1 << 3)
++#define SOFTRESET_6318_USBS_MASK	(1 << 4)
++#define SOFTRESET_6318_USBH_MASK	(1 << 5)
++#define SOFTRESET_6318_PCIE_CORE_MASK	(1 << 6)
++#define SOFTRESET_6318_PCIE_MASK	(1 << 7)
++#define SOFTRESET_6318_PCIE_EXT_MASK	(1 << 8)
++#define SOFTRESET_6318_PCIE_HARD_MASK	(1 << 9)
++#define SOFTRESET_6318_ADSL_MASK	(1 << 10)
++
+ #define SOFTRESET_6328_SPI_MASK		(1 << 0)
+ #define SOFTRESET_6328_EPHY_MASK	(1 << 1)
+ #define SOFTRESET_6328_SAR_MASK		(1 << 2)
+@@ -505,8 +568,17 @@
+ #define TIMER_IRQSTAT_TIMER1_IR_EN	(1 << 9)
+ #define TIMER_IRQSTAT_TIMER2_IR_EN	(1 << 10)
+ 
++#define TIMER_IRQMASK_6318_REG		0x0
++#define TIMER_IRQSTAT_6318_REG		0x4
++#define IRQSTATMASK_TIMER0		(1 << 0)
++#define IRQSTATMASK_TIMER1		(1 << 1)
++#define IRQSTATMASK_TIMER2		(1 << 2)
++#define IRQSTATMASK_TIMER3		(1 << 3)
++#define IRQSTATMASK_WDT			(1 << 4)
++
+ /* Timer control register */
+ #define TIMER_CTLx_REG(x)		(0x4 + (x * 4))
++#define TIMER_CTRx_6318_REG(x)		(0x8 + (x * 4))
+ #define TIMER_CTL0_REG			0x4
+ #define TIMER_CTL1_REG			0x8
+ #define TIMER_CTL2_REG			0xC
+@@ -1253,6 +1325,8 @@
+ #define SDRAM_CFG_32B_MASK		(1 << SDRAM_CFG_32B_SHIFT)
+ #define SDRAM_CFG_BANK_SHIFT		13
+ #define SDRAM_CFG_BANK_MASK		(1 << SDRAM_CFG_BANK_SHIFT)
++#define SDRAM_CFG_6318_SPACE_SHIFT	4
++#define SDRAM_CFG_6318_SPACE_MASK	(0xf << SDRAM_CFG_6318_SPACE_SHIFT)
+ 
+ #define SDRAM_MBASE_REG			0xc
+ 
+--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
++++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+@@ -22,6 +22,7 @@ static inline int is_bcm63xx_internal_re
+ 		if (offset >= 0xfff00000)
+ 			return 1;
+ 		break;
++	case BCM6318_CPU_ID:
+ 	case BCM6328_CPU_ID:
+ 	case BCM6362_CPU_ID:
+ 	case BCM6368_CPU_ID:
+--- a/arch/mips/bcm63xx/dev-hsspi.c
++++ b/arch/mips/bcm63xx/dev-hsspi.c
+@@ -35,7 +35,8 @@ static struct platform_device bcm63xx_hs
+ 
+ int __init bcm63xx_hsspi_register(void)
+ {
+-	if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_63268())
++	if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6362() &&
++		!BCMCPU_IS_63268())
+ 		return -ENODEV;
+ 
+ 	spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI);
+--- a/arch/mips/bcm63xx/dev-usb-usbd.c
++++ b/arch/mips/bcm63xx/dev-usb-usbd.c
+@@ -41,7 +41,7 @@ int __init bcm63xx_usbd_register(const s
+ 		IRQ_USBD_RXDMA2, IRQ_USBD_TXDMA2 };
+ 	int i;
+ 
+-	if (!BCMCPU_IS_6328() && !BCMCPU_IS_6368())
++	if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6368())
+ 		return 0;
+ 
+ 	usbd_resources[0].start = bcm63xx_regset_address(RSET_USBD);
+--- a/arch/mips/bcm63xx/dev-enet.c
++++ b/arch/mips/bcm63xx/dev-enet.c
+@@ -176,8 +176,8 @@ static int __init register_shared(void)
+ 	else
+ 		shared_res[0].end += (RSET_ENETDMA_SIZE)  - 1;
+ 
+-	if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() ||
+-		BCMCPU_IS_63268())
++	if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() ||
++		BCMCPU_IS_6368() || BCMCPU_IS_63268())
+ 		chan_count = 32;
+ 	else if (BCMCPU_IS_6345())
+ 		chan_count = 8;
+@@ -285,8 +285,8 @@ bcm63xx_enetsw_register(const struct bcm
+ {
+ 	int ret;
+ 
+-	if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368() &&
+-		!BCMCPU_IS_63268())
++	if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6362() &&
++		!BCMCPU_IS_6368() && !BCMCPU_IS_63268())
+ 		return -ENODEV;
+ 
+ 	ret = register_shared();
+@@ -303,7 +303,7 @@ bcm63xx_enetsw_register(const struct bcm
+ 
+ 	memcpy(bcm63xx_enetsw_device.dev.platform_data, pd, sizeof(*pd));
+ 
+-	if (BCMCPU_IS_6328())
++	if (BCMCPU_IS_6318() || BCMCPU_IS_6328())
+ 		enetsw_pd.num_ports = ENETSW_PORTS_6328;
+ 	else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
+ 		enetsw_pd.num_ports = ENETSW_PORTS_6368;
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+@@ -9,6 +9,8 @@ int __init bcm63xx_gpio_init(void);
+ static inline unsigned long bcm63xx_gpio_count(void)
+ {
+ 	switch (bcm63xx_get_cpu_id()) {
++	case BCM6318_CPU_ID:
++		return 50;
+ 	case BCM6328_CPU_ID:
+ 		return 32;
+ 	case BCM3368_CPU_ID:
+--- a/arch/mips/bcm63xx/dev-usb-ehci.c
++++ b/arch/mips/bcm63xx/dev-usb-ehci.c
+@@ -81,7 +81,8 @@ static struct platform_device bcm63xx_eh
+ 
+ int __init bcm63xx_ehci_register(void)
+ {
+-	if (!BCMCPU_IS_6328() && !BCMCPU_IS_6358() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
++	if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() &&
++		!BCMCPU_IS_6362() && !BCMCPU_IS_6368())
+ 		return 0;
+ 
+ 	ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0);

target/linux/brcm63xx/patches-4.9/342-MIPS-BCM63XX-split-PCIe-reset-signals.patch

@@ -0,0 +1,156 @@
+From 4bdfacdeaf3c988c4f3256c88118893eac640b03 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 8 Dec 2013 14:17:50 +0100
+Subject: [PATCH 52/53] MIPS: BCM63XX: split PCIE reset signals
+
+---
+ arch/mips/bcm63xx/reset.c                          | 39 ++++++++++++++--------
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h |  2 ++
+ arch/mips/pci/pci-bcm63xx.c                        |  7 ++++
+ 3 files changed, 34 insertions(+), 14 deletions(-)
+
+--- a/arch/mips/bcm63xx/reset.c
++++ b/arch/mips/bcm63xx/reset.c
+@@ -28,7 +28,9 @@
+ 	[BCM63XX_RESET_PCM]		= BCM## __cpu ##_RESET_PCM,	\
+ 	[BCM63XX_RESET_MPI]		= BCM## __cpu ##_RESET_MPI,	\
+ 	[BCM63XX_RESET_PCIE]		= BCM## __cpu ##_RESET_PCIE,	\
+-	[BCM63XX_RESET_PCIE_EXT]	= BCM## __cpu ##_RESET_PCIE_EXT,
++	[BCM63XX_RESET_PCIE_EXT]	= BCM## __cpu ##_RESET_PCIE_EXT, \
++	[BCM63XX_RESET_PCIE_CORE]	= BCM## __cpu ##_RESET_PCIE_CORE, \
++	[BCM63XX_RESET_PCIE_HARD]	= BCM## __cpu ##_RESET_PCIE_HARD,
+ 
+ #define BCM3368_RESET_SPI	SOFTRESET_3368_SPI_MASK
+ #define BCM3368_RESET_ENET	SOFTRESET_3368_ENET_MASK
+@@ -42,6 +44,8 @@
+ #define BCM3368_RESET_MPI	SOFTRESET_3368_MPI_MASK
+ #define BCM3368_RESET_PCIE	0
+ #define BCM3368_RESET_PCIE_EXT	0
++#define BCM3368_RESET_PCIE_CORE	0
++#define BCM3368_RESET_PCIE_HARD	0
+ 
+ 
+ #define BCM6318_RESET_SPI	SOFTRESET_6318_SPI_MASK
+@@ -54,11 +58,10 @@
+ #define BCM6318_RESET_ENETSW	SOFTRESET_6318_ENETSW_MASK
+ #define BCM6318_RESET_PCM	0
+ #define BCM6318_RESET_MPI	0
+-#define BCM6318_RESET_PCIE	\
+-				(SOFTRESET_6318_PCIE_MASK |		\
+-				 SOFTRESET_6318_PCIE_CORE_MASK |	\
+-				 SOFTRESET_6318_PCIE_HARD_MASK)
++#define BCM6318_RESET_PCIE	SOFTRESET_6318_PCIE_MASK
+ #define BCM6318_RESET_PCIE_EXT	SOFTRESET_6318_PCIE_EXT_MASK
++#define BCM6318_RESET_PCIE_CORE	SOFTRESET_6318_PCIE_CORE_MASK
++#define BCM6318_RESET_PCIE_HARD	SOFTRESET_6318_PCIE_HARD_MASK
+ 
+ #define BCM6328_RESET_SPI	SOFTRESET_6328_SPI_MASK
+ #define BCM6328_RESET_ENET	0
+@@ -70,11 +73,10 @@
+ #define BCM6328_RESET_ENETSW	SOFTRESET_6328_ENETSW_MASK
+ #define BCM6328_RESET_PCM	SOFTRESET_6328_PCM_MASK
+ #define BCM6328_RESET_MPI	0
+-#define BCM6328_RESET_PCIE	\
+-				(SOFTRESET_6328_PCIE_MASK |		\
+-				 SOFTRESET_6328_PCIE_CORE_MASK |	\
+-				 SOFTRESET_6328_PCIE_HARD_MASK)
++#define BCM6328_RESET_PCIE	SOFTRESET_6328_PCIE_MASK
+ #define BCM6328_RESET_PCIE_EXT	SOFTRESET_6328_PCIE_EXT_MASK
++#define BCM6328_RESET_PCIE_CORE	SOFTRESET_6328_PCIE_CORE_MASK
++#define BCM6328_RESET_PCIE_HARD	SOFTRESET_6328_PCIE_HARD_MASK
+ 
+ #define BCM6338_RESET_SPI	SOFTRESET_6338_SPI_MASK
+ #define BCM6338_RESET_ENET	SOFTRESET_6338_ENET_MASK
+@@ -88,6 +90,8 @@
+ #define BCM6338_RESET_MPI	0
+ #define BCM6338_RESET_PCIE	0
+ #define BCM6338_RESET_PCIE_EXT	0
++#define BCM6338_RESET_PCIE_CORE	0
++#define BCM6338_RESET_PCIE_HARD	0
+ 
+ #define BCM6348_RESET_SPI	SOFTRESET_6348_SPI_MASK
+ #define BCM6348_RESET_ENET	SOFTRESET_6348_ENET_MASK
+@@ -101,6 +105,8 @@
+ #define BCM6348_RESET_MPI	0
+ #define BCM6348_RESET_PCIE	0
+ #define BCM6348_RESET_PCIE_EXT	0
++#define BCM6348_RESET_PCIE_CORE	0
++#define BCM6348_RESET_PCIE_HARD	0
+ 
+ #define BCM6358_RESET_SPI	SOFTRESET_6358_SPI_MASK
+ #define BCM6358_RESET_ENET	SOFTRESET_6358_ENET_MASK
+@@ -114,6 +120,8 @@
+ #define BCM6358_RESET_MPI	SOFTRESET_6358_MPI_MASK
+ #define BCM6358_RESET_PCIE	0
+ #define BCM6358_RESET_PCIE_EXT	0
++#define BCM6358_RESET_PCIE_CORE	0
++#define BCM6358_RESET_PCIE_HARD	0
+ 
+ #define BCM6362_RESET_SPI	SOFTRESET_6362_SPI_MASK
+ #define BCM6362_RESET_ENET	0
+@@ -125,9 +133,10 @@
+ #define BCM6362_RESET_ENETSW	SOFTRESET_6362_ENETSW_MASK
+ #define BCM6362_RESET_PCM	SOFTRESET_6362_PCM_MASK
+ #define BCM6362_RESET_MPI	0
+-#define BCM6362_RESET_PCIE      (SOFTRESET_6362_PCIE_MASK | \
+-				 SOFTRESET_6362_PCIE_CORE_MASK)
++#define BCM6362_RESET_PCIE      SOFTRESET_6362_PCIE_MASK
+ #define BCM6362_RESET_PCIE_EXT	SOFTRESET_6362_PCIE_EXT_MASK
++#define BCM6362_RESET_PCIE_CORE	SOFTRESET_6362_PCIE_CORE_MASK
++#define BCM6362_RESET_PCIE_HARD	0
+ 
+ #define BCM6368_RESET_SPI	SOFTRESET_6368_SPI_MASK
+ #define BCM6368_RESET_ENET	0
+@@ -141,6 +150,8 @@
+ #define BCM6368_RESET_MPI	SOFTRESET_6368_MPI_MASK
+ #define BCM6368_RESET_PCIE	0
+ #define BCM6368_RESET_PCIE_EXT	0
++#define BCM6368_RESET_PCIE_CORE	0
++#define BCM6368_RESET_PCIE_HARD	0
+ 
+ #define BCM63268_RESET_SPI	SOFTRESET_63268_SPI_MASK
+ #define BCM63268_RESET_ENET	0
+@@ -152,10 +163,10 @@
+ #define BCM63268_RESET_ENETSW	SOFTRESET_63268_ENETSW_MASK
+ #define BCM63268_RESET_PCM	SOFTRESET_63268_PCM_MASK
+ #define BCM63268_RESET_MPI	0
+-#define BCM63268_RESET_PCIE	(SOFTRESET_63268_PCIE_MASK | \
+-				 SOFTRESET_63268_PCIE_CORE_MASK | \
+-				 SOFTRESET_63268_PCIE_HARD_MASK)
++#define BCM63268_RESET_PCIE	SOFTRESET_63268_PCIE_MASK
+ #define BCM63268_RESET_PCIE_EXT	SOFTRESET_63268_PCIE_EXT_MASK
++#define BCM63268_RESET_PCIE_CORE	SOFTRESET_63268_PCIE_CORE_MASK
++#define BCM63268_RESET_PCIE_HARD	SOFTRESET_63268_PCIE_HARD_MASK
+ 
+ /*
+  * core reset bits
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
+@@ -14,6 +14,8 @@ enum bcm63xx_core_reset {
+ 	BCM63XX_RESET_MPI,
+ 	BCM63XX_RESET_PCIE,
+ 	BCM63XX_RESET_PCIE_EXT,
++	BCM63XX_RESET_PCIE_CORE,
++	BCM63XX_RESET_PCIE_HARD,
+ };
+ 
+ void bcm63xx_core_set_reset(enum bcm63xx_core_reset, int reset);
+--- a/arch/mips/pci/pci-bcm63xx.c
++++ b/arch/mips/pci/pci-bcm63xx.c
+@@ -135,9 +135,16 @@ static void __init bcm63xx_reset_pcie(vo
+ 
+ 	/* reset the PCIe core */
+ 	bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
++	bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 1);
+ 	bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1);
++	if (BCMCPU_IS_6328() || BCMCPU_IS_63268()) {
++		bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 1);
++		mdelay(10);
++		bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 0);
++	}
+ 	mdelay(10);
+ 
++	bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 0);
+ 	bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0);
+ 	mdelay(10);
+ 

target/linux/brcm63xx/patches-4.9/343-MIPS-BCM63XX-add-PCIe-support-for-BCM6318.patch

@@ -0,0 +1,333 @@
+From 11a8ab8dac4ef5d0d70199843043927edce1d4db Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 15 Dec 2013 20:47:34 +0100
+Subject: [PATCH 53/53] MIPS: BCM63XX: add PCIe support for BCM6318
+
+---
+ arch/mips/bcm63xx/clk.c                           |  25 ++++-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h   |   6 ++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |  60 +++++++++++-
+ arch/mips/pci/ops-bcm63xx.c                       |  16 +++-
+ arch/mips/pci/pci-bcm63xx.c                       | 106 ++++++++++++++++++----
+ 5 files changed, 184 insertions(+), 29 deletions(-)
+
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -51,6 +51,18 @@ static void bcm_hwclock_set(u32 mask, in
+ 	bcm_perf_writel(reg, PERF_CKCTL_REG);
+ }
+ 
++static void bcm_ub_hwclock_set(u32 mask, int enable)
++{
++	u32 reg;
++
++	reg = bcm_perf_readl(PERF_UB_CKCTL_REG);
++	if (enable)
++		reg |= mask;
++	else
++		reg &= ~mask;
++	bcm_perf_writel(reg, PERF_UB_CKCTL_REG);
++}
++
+ /*
+  * Ethernet MAC "misc" clock: dma clocks and main clock on 6348
+  */
+@@ -361,12 +373,17 @@ static struct clk clk_ipsec = {
+ 
+ static void pcie_set(struct clk *clk, int enable)
+ {
+-	if (BCMCPU_IS_6328())
++	if (BCMCPU_IS_6318()) {
++		bcm_hwclock_set(CKCTL_6318_PCIE_EN, enable);
++		bcm_hwclock_set(CKCTL_6318_PCIE25_EN, enable);
++		bcm_ub_hwclock_set(UB_CKCTL_6318_PCIE_EN, enable);
++	} else if (BCMCPU_IS_6328()) {
+ 		bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable);
+-	else if (BCMCPU_IS_6362())
++	} else if (BCMCPU_IS_6362()) {
+ 		bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable);
+-	else if (BCMCPU_IS_63268())
++	} else if (BCMCPU_IS_63268()) {
+ 		bcm_hwclock_set(CKCTL_63268_PCIE_EN, enable);
++	}
+ }
+ 
+ static struct clk clk_pcie = {
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+@@ -40,6 +40,12 @@
+ #define BCM_CB_MEM_END_PA		(BCM_CB_MEM_BASE_PA +		\
+ 					BCM_CB_MEM_SIZE - 1)
+ 
++#define BCM_PCIE_MEM_BASE_PA_6318	0x10200000
++#define BCM_PCIE_MEM_SIZE_6318		(1 * 1024 * 1024)
++#define BCM_PCIE_MEM_END_PA_6318	(BCM_PCIE_MEM_BASE_PA_6318 +	\
++					BCM_PCIE_MEM_SIZE_6318 - 1)
++
++
+ #define BCM_PCIE_MEM_BASE_PA_6328	0x10f00000
+ #define BCM_PCIE_MEM_SIZE_6328		(1 * 1024 * 1024)
+ #define BCM_PCIE_MEM_END_PA_6328	(BCM_PCIE_MEM_BASE_PA_6328 +	\
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -1529,6 +1529,17 @@
+  * _REG relative to RSET_PCIE
+  *************************************************************************/
+ 
++#define PCIE_SPECIFIC_REG		0x188
++#define SPECIFIC_ENDIAN_MODE_BAR1_SHIFT	0
++#define SPECIFIC_ENDIAN_MODE_BAR1_MASK	(0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)
++#define SPECIFIC_ENDIAN_MODE_BAR2_SHIFT	2
++#define SPECIFIC_ENDIAN_MODE_BAR2_MASK	(0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)
++#define SPECIFIC_ENDIAN_MODE_BAR3_SHIFT	4
++#define SPECIFIC_ENDIAN_MODE_BAR3_MASK	(0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)
++#define SPECIFIC_ENDIAN_MODE_WORD_ALIGN	0
++#define SPECIFIC_ENDIAN_MODE_HALFWORD_ALIGN 1
++#define SPECIFIC_ENDIAN_MODE_BYTE_ALIGN	2
++
+ #define PCIE_CONFIG2_REG		0x408
+ #define CONFIG2_BAR1_SIZE_EN		1
+ #define CONFIG2_BAR1_SIZE_MASK		0xf
+@@ -1574,7 +1585,54 @@
+ #define PCIE_RC_INT_C			(1 << 2)
+ #define PCIE_RC_INT_D			(1 << 3)
+ 
+-#define PCIE_DEVICE_OFFSET		0x8000
++#define PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG	0x400c
++#define C2P_MEM_WIN_ENDIAN_MODE_MASK	0x3
++#define C2P_MEM_WIN_ENDIAN_NO_SWAP	0
++#define C2P_MEM_WIN_ENDIAN_HALF_WORD_SWAP 1
++#define C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP 2
++#define C2P_MEM_WIN_BASE_ADDR_SHIFT	20
++#define C2P_MEM_WIN_BASE_ADDR_MASK	(0xfff << C2P_MEM_WIN_BASE_ADDR_SHIFT)
++
++#define PCIE_RC_BAR1_CONFIG_LO_REG	0x402c
++#define RC_BAR_CFG_LO_SIZE_256MB	0xd
++#define RC_BAR_CFG_LO_MATCH_ADDR_SHIFT	20
++#define RC_BAR_CFG_LO_MATCH_ADDR_MASK	(0xfff << RC_BAR_CFG_LO_MATCH_ADDR_SHIFT)
++
++#define PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG 0x4070
++#define C2P_BASELIMIT_LIMIT_SHIFT	20
++#define C2P_BASELIMIT_LIMIT_MASK	(0xfff << C2P_BASELIMIT_LIMIT_SHIFT)
++#define C2P_BASELIMIT_BASE_SHIFT	4
++#define C2P_BASELIMIT_BASE_MASK		(0xfff << C2P_BASELIMIT_BASE_SHIFT)
++
++#define PCIE_UBUS_BAR1_CFG_REMAP_REG	0x4088
++#define BAR1_CFG_REMAP_OFFSET_SHIFT	20
++#define BAR1_CFG_REMAP_OFFSET_MASK	(0xfff << BAR1_CFG_REMAP_OFFSET_SHIFT)
++#define BAR1_CFG_REMAP_ACCESS_EN	1
++
++#define PCIE_HARD_DEBUG_REG		0x4204
++#define HARD_DEBUG_SERDES_IDDQ		(1 << 23)
++
++#define PCIE_CPU_INT1_MASK_CLEAR_REG	0x830c
++#define CPU_INT_PCIE_ERR_ATTN_CPU	(1 << 0)
++#define CPU_INT_PCIE_INTA		(1 << 1)
++#define CPU_INT_PCIE_INTB		(1 << 2)
++#define CPU_INT_PCIE_INTC		(1 << 3)
++#define CPU_INT_PCIE_INTD		(1 << 4)
++#define CPU_INT_PCIE_INTR		(1 << 5)
++#define CPU_INT_PCIE_NMI		(1 << 6)
++#define CPU_INT_PCIE_UBUS		(1 << 7)
++#define CPU_INT_IPI			(1 << 8)
++
++#define PCIE_EXT_CFG_INDEX_REG		0x8400
++#define EXT_CFG_FUNC_NUM_SHIFT		12
++#define EXT_CFG_FUNC_NUM_MASK		(0x7 << EXT_CFG_FUNC_NUM_SHIFT)
++#define EXT_CFG_DEV_NUM_SHIFT		15
++#define EXT_CFG_DEV_NUM_MASK		(0xf << EXT_CFG_DEV_NUM_SHIFT)
++#define EXT_CFG_BUS_NUM_SHIFT		20
++#define EXT_CFG_BUS_NUM_MASK		(0xff << EXT_CFG_BUS_NUM_SHIFT)
++
++#define PCIE_DEVICE_OFFSET_6318		0x9000
++#define PCIE_DEVICE_OFFSET_6328		0x8000
+ 
+ /*************************************************************************
+  * _REG relative to RSET_OTP
+--- a/arch/mips/pci/ops-bcm63xx.c
++++ b/arch/mips/pci/ops-bcm63xx.c
+@@ -488,8 +488,12 @@ static int bcm63xx_pcie_read(struct pci_
+ 	if (!bcm63xx_pcie_can_access(bus, devfn))
+ 		return PCIBIOS_DEVICE_NOT_FOUND;
+ 
+-	if (bus->number == PCIE_BUS_DEVICE)
+-		reg += PCIE_DEVICE_OFFSET;
++	if (bus->number == PCIE_BUS_DEVICE) {
++		if (BCMCPU_IS_6318())
++			reg += PCIE_DEVICE_OFFSET_6318;
++		else
++			reg += PCIE_DEVICE_OFFSET_6328;
++	}
+ 
+ 	data = bcm_pcie_readl(reg);
+ 
+@@ -508,8 +512,12 @@ static int bcm63xx_pcie_write(struct pci
+ 	if (!bcm63xx_pcie_can_access(bus, devfn))
+ 		return PCIBIOS_DEVICE_NOT_FOUND;
+ 
+-	if (bus->number == PCIE_BUS_DEVICE)
+-		reg += PCIE_DEVICE_OFFSET;
++	if (bus->number == PCIE_BUS_DEVICE) {
++		if (BCMCPU_IS_6318())
++			reg += PCIE_DEVICE_OFFSET_6318;
++		else
++			reg += PCIE_DEVICE_OFFSET_6328;
++	}
+ 
+ 
+ 	data = bcm_pcie_readl(reg);
+--- a/arch/mips/pci/pci-bcm63xx.c
++++ b/arch/mips/pci/pci-bcm63xx.c
+@@ -118,7 +118,7 @@ static void bcm63xx_int_cfg_writel(u32 v
+ 
+ void __iomem *pci_iospace_start;
+ 
+-static void __init bcm63xx_reset_pcie(void)
++static void __init bcm63xx_reset_pcie_gen1(void)
+ {
+ 	u32 val;
+ 	u32 reg;
+@@ -152,20 +152,32 @@ static void __init bcm63xx_reset_pcie(vo
+ 	mdelay(200);
+ }
+ 
+-static struct clk *pcie_clk;
+-
+-static int __init bcm63xx_register_pcie(void)
++static void __init bcm63xx_reset_pcie_gen2(void)
+ {
+ 	u32 val;
+ 
+-	/* enable clock */
+-	pcie_clk = clk_get(NULL, "pcie");
+-	if (IS_ERR_OR_NULL(pcie_clk))
+-		return -ENODEV;
++	bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 0);
+ 
+-	clk_prepare_enable(pcie_clk);
++	/* reset the PCIe core */
++	bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
++	bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1);
++	bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 1);
++	mdelay(10);
++	bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 0);
++	mdelay(10);
++	bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0);
++	mdelay(10);
++	val = bcm_pcie_readl(PCIE_HARD_DEBUG_REG);
++	val &= ~HARD_DEBUG_SERDES_IDDQ;
++	bcm_pcie_writel(val, PCIE_HARD_DEBUG_REG);
++	mdelay(10);
++	bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 0);
++	mdelay(200);
++}
+ 
+-	bcm63xx_reset_pcie();
++static void __init bcm63xx_init_pcie_gen1(void)
++{
++	u32 val;
+ 
+ 	/* configure the PCIe bridge */
+ 	val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG);
+@@ -190,6 +202,65 @@ static int __init bcm63xx_register_pcie(
+ 	val |= OPT2_CFG_TYPE1_BD_SEL;
+ 	bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG);
+ 
++	/* set bar0 to little endian */
++	val = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT;
++	val |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT;
++	val |= BASEMASK_REMAP_EN;
++	bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
++
++	val = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT;
++	bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
++}
++
++static void __init bcm63xx_init_pcie_gen2(void)
++{
++	u32 val;
++
++	bcm_pcie_writel(CPU_INT_PCIE_INTA | CPU_INT_PCIE_INTB |
++			CPU_INT_PCIE_INTC | CPU_INT_PCIE_INTD,
++			PCIE_CPU_INT1_MASK_CLEAR_REG);
++
++	val = bcm_pcie_mem_resource.end & C2P_BASELIMIT_LIMIT_MASK;
++	val |= (bcm_pcie_mem_resource.start >> C2P_BASELIMIT_LIMIT_SHIFT) <<
++	       C2P_BASELIMIT_BASE_SHIFT;
++
++	bcm_pcie_writel(val, PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG);
++
++	/* set bar0 to little endian */
++	val = bcm_pcie_readl(PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG);
++	val |= bcm_pcie_mem_resource.start & C2P_MEM_WIN_BASE_ADDR_MASK;
++	val |= C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP;
++	bcm_pcie_writel(val, PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG);
++
++	bcm_pcie_writel(SPECIFIC_ENDIAN_MODE_BYTE_ALIGN, PCIE_SPECIFIC_REG);
++	bcm_pcie_writel(RC_BAR_CFG_LO_SIZE_256MB, PCIE_RC_BAR1_CONFIG_LO_REG);
++	bcm_pcie_writel(BAR1_CFG_REMAP_ACCESS_EN, PCIE_UBUS_BAR1_CFG_REMAP_REG);
++
++	bcm_pcie_writel(PCIE_BUS_DEVICE << EXT_CFG_BUS_NUM_SHIFT,
++			PCIE_EXT_CFG_INDEX_REG);
++}
++
++static struct clk *pcie_clk;
++
++static int __init bcm63xx_register_pcie(void)
++{
++	u32 val;
++
++	/* enable clock */
++	pcie_clk = clk_get(NULL, "pcie");
++	if (IS_ERR_OR_NULL(pcie_clk))
++		return -ENODEV;
++
++	clk_prepare_enable(pcie_clk);
++
++	if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) {
++		bcm63xx_reset_pcie_gen1();
++		bcm63xx_init_pcie_gen1();
++	} else {
++		bcm63xx_reset_pcie_gen2();
++		bcm63xx_init_pcie_gen2();
++	}
++
+ 	/* setup class code as bridge */
+ 	val = bcm_pcie_readl(PCIE_IDVAL3_REG);
+ 	val &= ~IDVAL3_CLASS_CODE_MASK;
+@@ -201,15 +272,6 @@ static int __init bcm63xx_register_pcie(
+ 	val &= ~CONFIG2_BAR1_SIZE_MASK;
+ 	bcm_pcie_writel(val, PCIE_CONFIG2_REG);
+ 
+-	/* set bar0 to little endian */
+-	val = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT;
+-	val |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT;
+-	val |= BASEMASK_REMAP_EN;
+-	bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
+-
+-	val = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT;
+-	bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
+-
+ 	register_pci_controller(&bcm63xx_pcie_controller);
+ 
+ 	return 0;
+@@ -341,7 +403,10 @@ static int __init bcm63xx_pci_init(void)
+ 	if (!bcm63xx_pci_enabled)
+ 		return -ENODEV;
+ 
+-	if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
++	if (BCMCPU_IS_6318()) {
++		bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6318;
++		bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6318;
++	} if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
+ 		bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328;
+ 		bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328;
+ 	} else if (BCMCPU_IS_63268()) {
+@@ -350,6 +415,7 @@ static int __init bcm63xx_pci_init(void)
+ 	}
+ 
+ 	switch (bcm63xx_get_cpu_id()) {
++	case BCM6318_CPU_ID:
+ 	case BCM6328_CPU_ID:
+ 	case BCM6362_CPU_ID:
+ 	case BCM63268_CPU_ID:

target/linux/brcm63xx/patches-4.9/344-MIPS-BCM63XX-detect-flash-type-early-and-store-the-r.patch

@@ -0,0 +1,74 @@
+From 9a97177b907330971aa7bf41855fafc2602e1c18 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 22 Dec 2013 12:26:57 +0100
+Subject: [PATCH 51/56] MIPS: BCM63XX: detect flash type early and store the
+ result
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/dev-flash.c                          | 10 +++++++---
+ arch/mips/bcm63xx/prom.c                               |  4 ++++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h |  2 ++
+ 3 files changed, 13 insertions(+), 3 deletions(-)
+
+--- a/arch/mips/bcm63xx/dev-flash.c
++++ b/arch/mips/bcm63xx/dev-flash.c
+@@ -22,6 +22,8 @@
+ #include <bcm63xx_regs.h>
+ #include <bcm63xx_io.h>
+ 
++static int flash_type;
++
+ static struct mtd_partition mtd_partitions[] = {
+ 	{
+ 		.name		= "cfe",
+@@ -108,13 +110,15 @@ static int __init bcm63xx_detect_flash_t
+ 	}
+ }
+ 
++void __init bcm63xx_flash_detect(void)
++{
++	flash_type = bcm63xx_detect_flash_type();
++}
++
+ int __init bcm63xx_flash_register(void)
+ {
+-	int flash_type;
+ 	u32 val;
+ 
+-	flash_type = bcm63xx_detect_flash_type();
+-
+ 	switch (flash_type) {
+ 	case BCM63XX_FLASH_TYPE_PARALLEL:
+ 		/* read base address of boot chip select (0) */
+--- a/arch/mips/bcm63xx/prom.c
++++ b/arch/mips/bcm63xx/prom.c
+@@ -17,6 +17,7 @@
+ #include <bcm63xx_cpu.h>
+ #include <bcm63xx_io.h>
+ #include <bcm63xx_regs.h>
++#include <bcm63xx_dev_flash.h>
+ 
+ void __init prom_init(void)
+ {
+@@ -52,6 +53,9 @@ void __init prom_init(void)
+ 	reg &= ~mask;
+ 	bcm_perf_writel(reg, PERF_CKCTL_REG);
+ 
++	/* detect and setup flash access */
++	bcm63xx_flash_detect();
++
+ 	/* do low level board init */
+ 	board_prom_init();
+ 
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
+@@ -7,6 +7,8 @@ enum {
+ 	BCM63XX_FLASH_TYPE_NAND,
+ };
+ 
++void bcm63xx_flash_detect(void);
++
+ int __init bcm63xx_flash_register(void);
+ 
+ #endif /* __BCM63XX_FLASH_H */

target/linux/brcm63xx/patches-4.9/345-MIPS-BCM63XX-fixup-mapped-SPI-flash-access-on-boot.patch

@@ -0,0 +1,84 @@
+From 1cacd0f7b0d35f8e3d3f8a69ecb3b5e436d6b9e8 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 22 Dec 2013 13:25:25 +0100
+Subject: [PATCH 52/56] MIPS: BCM63XX: fixup mapped SPI flash access on boot
+
+Some bootloaders leave the flash access in an invalid state with dual
+read enabled; fix it by disabling it and falling back to simple fast
+reads.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/dev-flash.c | 51 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 51 insertions(+)
+
+--- a/arch/mips/bcm63xx/dev-flash.c
++++ b/arch/mips/bcm63xx/dev-flash.c
+@@ -16,6 +16,7 @@
+ #include <linux/mtd/mtd.h>
+ #include <linux/mtd/partitions.h>
+ #include <linux/mtd/physmap.h>
++#include <linux/mtd/spi-nor.h>
+ 
+ #include <bcm63xx_cpu.h>
+ #include <bcm63xx_dev_flash.h>
+@@ -110,9 +111,59 @@ static int __init bcm63xx_detect_flash_t
+ 	}
+ }
+ 
++#define HSSPI_FLASH_CTRL_REG		0x14
++#define FLASH_CTRL_READ_OPCODE_MASK	0xff
++#define FLASH_CTRL_ADDR_BYTES_MASK	(0x3 << 8)
++#define FLASH_CTRL_ADDR_BYTES_2		(0 << 8)
++#define FLASH_CTRL_ADDR_BYTES_3		(1 << 8)
++#define FLASH_CTRL_ADDR_BYTES_4		(2 << 8)
++#define FLASH_CTRL_DUMMY_BYTES_SHIFT	10
++#define FLASH_CTRL_DUMMY_BYTES_MASK	(0x3 << FLASH_CTRL_DUMMY_BYTES_SHIFT)
++#define FLASH_CTRL_MB_EN		(1 << 23)
++
+ void __init bcm63xx_flash_detect(void)
+ {
+ 	flash_type = bcm63xx_detect_flash_type();
++
++	/* ensure flash mapping has sane values */
++	if (flash_type == BCM63XX_FLASH_TYPE_SERIAL &&
++	    (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() ||
++	     BCMCPU_IS_63268())) {
++		u32 val = bcm_rset_readl(RSET_HSSPI, HSSPI_FLASH_CTRL_REG);
++
++		if (val & FLASH_CTRL_MB_EN) {
++			/* cfe might configure non working dual-io mode */
++			val &= ~FLASH_CTRL_MB_EN;
++			val &= ~FLASH_CTRL_READ_OPCODE_MASK;
++			val &= ~FLASH_CTRL_DUMMY_BYTES_MASK;
++			val |= 1 << FLASH_CTRL_DUMMY_BYTES_SHIFT;
++
++			switch (val & FLASH_CTRL_ADDR_BYTES_MASK) {
++			case FLASH_CTRL_ADDR_BYTES_3:
++				val |= SPINOR_OP_READ_FAST;
++				break;
++			case FLASH_CTRL_ADDR_BYTES_4:
++				val |= SPINOR_OP_READ_FAST_4B;
++				break;
++			case FLASH_CTRL_ADDR_BYTES_2:
++			default:
++				pr_warn("unsupported address byte mode (%x), not fixing up\n",
++					val & FLASH_CTRL_ADDR_BYTES_MASK);
++				return;
++			}
++		} else {
++			/* ensure dummy bytes is set to 1 for _FAST reads */
++			u8 cmd = val & FLASH_CTRL_READ_OPCODE_MASK;
++
++			if (cmd != SPINOR_OP_READ_FAST && cmd != SPINOR_OP_READ_FAST_4B)
++				return;
++
++			val &= ~FLASH_CTRL_DUMMY_BYTES_MASK;
++			val |= 1 << FLASH_CTRL_DUMMY_BYTES_SHIFT;
++		}
++
++		bcm_rset_writel(RSET_HSSPI, val, HSSPI_FLASH_CTRL_REG);
++	}
+ }
+ 
+ int __init bcm63xx_flash_register(void)

target/linux/brcm63xx/patches-4.9/346-MIPS-BCM63XX-USB-ENETSW-6318-clocks.patch

@@ -0,0 +1,44 @@
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -167,7 +167,11 @@ static struct clk clk_swpkt_usb = {
+  */
+ static void enetsw_set(struct clk *clk, int enable)
+ {
+-	if (BCMCPU_IS_6328()) {
++	if (BCMCPU_IS_6318()) {
++		bcm_hwclock_set(CKCTL_6318_ROBOSW250_EN |
++				CKCTL_6318_ROBOSW025_EN, enable);
++		bcm_ub_hwclock_set(UB_CKCTL_6318_ROBOSW_EN, enable);
++	} else if (BCMCPU_IS_6328()) {
+ 		bcm_hwclock_set(CKCTL_6328_ROBOSW_EN, enable);
+ 	} else if (BCMCPU_IS_6362()) {
+ 		bcm_hwclock_set(CKCTL_6362_ROBOSW_EN, enable);
+@@ -219,18 +223,22 @@ static struct clk clk_pcm = {
+  */
+ static void usbh_set(struct clk *clk, int enable)
+ {
+-	if (BCMCPU_IS_6328())
++	if (BCMCPU_IS_6318()) {
++		bcm_hwclock_set(CKCTL_6318_USB_EN, enable);
++		bcm_ub_hwclock_set(UB_CKCTL_6318_USB_EN, enable);
++	} else if (BCMCPU_IS_6328()) {
+ 		bcm_hwclock_set(CKCTL_6328_USBH_EN, enable);
+-	else if (BCMCPU_IS_6348())
++	} else if (BCMCPU_IS_6348()) {
+ 		bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
+-	else if (BCMCPU_IS_6362())
++	} else if (BCMCPU_IS_6362()) {
+ 		bcm_hwclock_set(CKCTL_6362_USBH_EN, enable);
+-	else if (BCMCPU_IS_6368())
++	} else if (BCMCPU_IS_6368()) {
+ 		bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
+-	else if (BCMCPU_IS_63268())
++	} else if (BCMCPU_IS_63268()) {
+ 		bcm_hwclock_set(CKCTL_63268_USBH_EN, enable);
+-	else
++	} else {
+ 		return;
++	}
+ 
+ 	if (enable)
+ 		msleep(100);

target/linux/brcm63xx/patches-4.9/347-MIPS-BCM6318-USB-support.patch

@@ -0,0 +1,124 @@
+--- a/arch/mips/bcm63xx/usb-common.c
++++ b/arch/mips/bcm63xx/usb-common.c
+@@ -109,6 +109,27 @@ void bcm63xx_usb_priv_ohci_cfg_set(void)
+ 		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
+ 		reg |= USBH_PRIV_SETUP_IOC_MASK;
+ 		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
++	} else if (BCMCPU_IS_6318()) {
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
++		reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN;
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
++
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG);
++		reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK;
++		reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK;
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6318_REG);
++
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6318_REG);
++		reg |= USBH_PRIV_SETUP_IOC_MASK;
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG);
++
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
++		reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN;
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
++
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG);
++		reg |= USBH_PRIV_SIM_CTRL_LADDR_SEL;
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SIM_CTRL_6318_REG);
+ 	}
+ 
+ 	spin_unlock_irqrestore(&usb_priv_reg_lock, flags);
+@@ -144,6 +165,27 @@ void bcm63xx_usb_priv_ehci_cfg_set(void)
+ 		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
+ 		reg |= USBH_PRIV_SETUP_IOC_MASK;
+ 		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
++	} else if (BCMCPU_IS_6318()) {
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
++		reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN;
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
++
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG);
++		reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK;
++		reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK;
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6318_REG);
++
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6318_REG);
++		reg |= USBH_PRIV_SETUP_IOC_MASK;
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG);
++
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
++		reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN;
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
++
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG);
++		reg |= USBH_PRIV_SIM_CTRL_LADDR_SEL;
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SIM_CTRL_6318_REG);
+ 	}
+ 
+ 	spin_unlock_irqrestore(&usb_priv_reg_lock, flags);
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -681,6 +681,12 @@
+ #define GPIO_MODE_6368_SPI_SSN4		(1 << 30)
+ #define GPIO_MODE_6368_SPI_SSN5		(1 << 31)
+ 
++#define GPIO_PINMUX_SEL0_6318		0x1c
++#define GPIO_PINMUX_SEL0_GPIO13_SHIFT	26
++#define GPIO_PINMUX_SEL0_GPIO13_MASK	(0x3 << GPIO_PINMUX_SEL0_GPIO13_SHIFT)
++#define GPIO_PINMUX_SEL0_GPIO13_PWRON	(1 << GPIO_PINMUX_SEL0_GPIO13_SHIFT)
++#define GPIO_PINMUX_SEL0_GPIO13_LED	(2 << GPIO_PINMUX_SEL0_GPIO13_SHIFT)
++#define GPIO_PINMUX_SEL0_GPIO13_GPIO	(3 << GPIO_PINMUX_SEL0_GPIO13_SHIFT)
+ 
+ #define GPIO_PINMUX_OTHR_REG		0x24
+ #define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12
+@@ -999,6 +1005,7 @@
+ 
+ #define USBH_PRIV_SWAP_6358_REG		0x0
+ #define USBH_PRIV_SWAP_6368_REG		0x1c
++#define USBH_PRIV_SWAP_6318_REG		0x0c
+ 
+ #define USBH_PRIV_SWAP_USBD_SHIFT	6
+ #define USBH_PRIV_SWAP_USBD_MASK	(1 << USBH_PRIV_SWAP_USBD_SHIFT)
+@@ -1024,6 +1031,13 @@
+ #define USBH_PRIV_SETUP_IOC_SHIFT	4
+ #define USBH_PRIV_SETUP_IOC_MASK	(1 << USBH_PRIV_SETUP_IOC_SHIFT)
+ 
++#define USBH_PRIV_SETUP_6318_REG	0x00
++#define USBH_PRIV_PLL_CTRL1_6318_REG	0x04
++#define USBH_PRIV_PLL_CTRL1_SUSP_EN	(1 << 27)
++#define USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN	(1 << 31)
++#define USBH_PRIV_SIM_CTRL_6318_REG	0x20
++#define USBH_PRIV_SIM_CTRL_LADDR_SEL	(1 << 5)
++
+ 
+ /*************************************************************************
+  * _REG relative to RSET_USBD
+--- a/arch/mips/bcm63xx/boards/board_common.c
++++ b/arch/mips/bcm63xx/boards/board_common.c
+@@ -126,6 +126,15 @@ void __init board_early_setup(const stru
+ 	}
+ 
+ 	bcm_gpio_writel(val, GPIO_MODE_REG);
++
++#if IS_ENABLED(CONFIG_USB)
++	if (BCMCPU_IS_6318() && (board.has_ehci0 || board.has_ohci0)) {
++		val = bcm_gpio_readl(GPIO_PINMUX_SEL0_6318);
++		val &= ~GPIO_PINMUX_SEL0_GPIO13_MASK;
++		val |= GPIO_PINMUX_SEL0_GPIO13_PWRON;
++		bcm_gpio_writel(val, GPIO_PINMUX_SEL0_6318);
++	}
++#endif
+ }
+ 
+ 
+--- a/arch/mips/bcm63xx/Kconfig
++++ b/arch/mips/bcm63xx/Kconfig
+@@ -22,6 +22,8 @@ config BCM63XX_CPU_6318
+ 	bool "support 6318 CPU"
+ 	select SYS_HAS_CPU_BMIPS32_3300
+ 	select HW_HAS_PCI
++	select BCM63XX_OHCI
++	select BCM63XX_EHCI
+ 
+ config BCM63XX_CPU_6328
+ 	bool "support 6328 CPU"

target/linux/brcm63xx/patches-4.9/348-MIPS-BCM63XX-fix-BCM63268-USB-clock.patch

@@ -0,0 +1,71 @@
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -586,6 +586,9 @@
+ #define TIMER_CTL_MONOTONIC_MASK	(1 << 30)
+ #define TIMER_CTL_ENABLE_MASK		(1 << 31)
+ 
++/* Clock reset control (63268 only) */
++#define TIMER_CLK_RST_CTL_REG		0x2c
++#define CLK_RST_CTL_USB_REF_CLK_EN	(1 << 18)
+ 
+ /*************************************************************************
+  * _REG relative to RSET_WDT
+@@ -1533,6 +1536,11 @@
+ #define STRAPBUS_63268_FCVO_SHIFT	21
+ #define STRAPBUS_63268_FCVO_MASK	(0xf << STRAPBUS_63268_FCVO_SHIFT)
+ 
++#define MISC_IDDQ_CTRL_6328_REG		0x48
++#define MISC_IDDQ_CTRL_63268_REG	0x4c
++
++#define IDDQ_CTRL_63268_USBH		(1 << 4)
++
+ #define MISC_STRAPBUS_6328_REG		0x240
+ #define STRAPBUS_6328_FCVO_SHIFT	7
+ #define STRAPBUS_6328_FCVO_MASK		(0x1f << STRAPBUS_6328_FCVO_SHIFT)
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -63,6 +63,26 @@ static void bcm_ub_hwclock_set(u32 mask,
+ 	bcm_perf_writel(reg, PERF_UB_CKCTL_REG);
+ }
+ 
++static void bcm_misc_iddq_set(u32 mask, int enable)
++{
++	u32 offset;
++	u32 reg;
++
++	if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
++		offset = MISC_IDDQ_CTRL_6328_REG;
++	else if (BCMCPU_IS_63268())
++		offset = MISC_IDDQ_CTRL_63268_REG;
++	else
++		return;
++
++	reg = bcm_misc_readl(offset);
++	if (enable)
++		reg &= ~mask;
++	else
++		reg |= mask;
++	bcm_misc_writel(reg, offset);
++}
++
+ /*
+  * Ethernet MAC "misc" clock: dma clocks and main clock on 6348
+  */
+@@ -235,7 +255,17 @@ static void usbh_set(struct clk *clk, in
+ 	} else if (BCMCPU_IS_6368()) {
+ 		bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
+ 	} else if (BCMCPU_IS_63268()) {
++		u32 reg;
++
+ 		bcm_hwclock_set(CKCTL_63268_USBH_EN, enable);
++		bcm_misc_iddq_set(IDDQ_CTRL_63268_USBH, enable);
++		bcm63xx_core_set_reset(BCM63XX_RESET_USBH, !enable);
++		reg = bcm_timer_readl(TIMER_CLK_RST_CTL_REG);
++		if (enable)
++			reg |= CLK_RST_CTL_USB_REF_CLK_EN;
++		else
++			reg &= ~CLK_RST_CTL_USB_REF_CLK_EN;
++		bcm_timer_writel(reg, TIMER_CLK_RST_CTL_REG);
+ 	} else {
+ 		return;
+ 	}

target/linux/brcm63xx/patches-4.9/349-MIPS-BCM63XX-add-BCM63268-USB-support.patch

@@ -0,0 +1,117 @@
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -1033,11 +1033,18 @@
+ #define USBH_PRIV_SETUP_6368_REG	0x28
+ #define USBH_PRIV_SETUP_IOC_SHIFT	4
+ #define USBH_PRIV_SETUP_IOC_MASK	(1 << USBH_PRIV_SETUP_IOC_SHIFT)
++#define USBH_PRIV_SETUP_IPP_SHIFT	5
++#define USBH_PRIV_SETUP_IPP_MASK	(1 << USBH_PRIV_SETUP_IPP_SHIFT)
+ 
+ #define USBH_PRIV_SETUP_6318_REG	0x00
++#define USBH_PRIV_PLL_CTRL1_6368_REG	0x18
+ #define USBH_PRIV_PLL_CTRL1_6318_REG	0x04
+-#define USBH_PRIV_PLL_CTRL1_SUSP_EN	(1 << 27)
+-#define USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN	(1 << 31)
++
++#define USBH_PRIV_PLL_CTRL1_6318_SUSP_EN	(1 << 27)
++#define USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN	(1 << 31)
++#define USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN	(1 << 9)
++#define USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY	(1 << 10)
++
+ #define USBH_PRIV_SIM_CTRL_6318_REG	0x20
+ #define USBH_PRIV_SIM_CTRL_LADDR_SEL	(1 << 5)
+ 
+--- a/arch/mips/bcm63xx/Kconfig
++++ b/arch/mips/bcm63xx/Kconfig
+@@ -72,6 +72,8 @@ config BCM63XX_CPU_63268
+ 	bool "support 63268 CPU"
+ 	select SYS_HAS_CPU_BMIPS4350
+ 	select HW_HAS_PCI
++	select BCM63XX_OHCI
++	select BCM63XX_EHCI
+ endmenu
+ 
+ source "arch/mips/bcm63xx/boards/Kconfig"
+--- a/arch/mips/bcm63xx/dev-usb-ehci.c
++++ b/arch/mips/bcm63xx/dev-usb-ehci.c
+@@ -82,7 +82,7 @@ static struct platform_device bcm63xx_eh
+ int __init bcm63xx_ehci_register(void)
+ {
+ 	if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() &&
+-		!BCMCPU_IS_6362() && !BCMCPU_IS_6368())
++		!BCMCPU_IS_6362() && !BCMCPU_IS_6368() && !BCMCPU_IS_63268())
+ 		return 0;
+ 
+ 	ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0);
+--- a/arch/mips/bcm63xx/usb-common.c
++++ b/arch/mips/bcm63xx/usb-common.c
+@@ -109,9 +109,24 @@ void bcm63xx_usb_priv_ohci_cfg_set(void)
+ 		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
+ 		reg |= USBH_PRIV_SETUP_IOC_MASK;
+ 		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
++	} else if (BCMCPU_IS_63268()) {
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);
++		reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK;
++		reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK;
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG);
++
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
++		reg |= USBH_PRIV_SETUP_IOC_MASK;
++		reg &= ~USBH_PRIV_SETUP_IPP_MASK;
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
++
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6368_REG);
++		reg &= ~(USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN |
++			 USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY);
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6368_REG);
+ 	} else if (BCMCPU_IS_6318()) {
+ 		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
+-		reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN;
++		reg |= USBH_PRIV_PLL_CTRL1_6318_SUSP_EN;
+ 		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
+ 
+ 		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG);
+@@ -124,7 +139,7 @@ void bcm63xx_usb_priv_ohci_cfg_set(void)
+ 		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG);
+ 
+ 		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
+-		reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN;
++		reg &= ~USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN;
+ 		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
+ 
+ 		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG);
+@@ -165,9 +180,24 @@ void bcm63xx_usb_priv_ehci_cfg_set(void)
+ 		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
+ 		reg |= USBH_PRIV_SETUP_IOC_MASK;
+ 		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
++	} else if (BCMCPU_IS_63268()) {
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);
++		reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK;
++		reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK;
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG);
++
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
++		reg |= USBH_PRIV_SETUP_IOC_MASK;
++		reg &= ~USBH_PRIV_SETUP_IPP_MASK;
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
++
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6368_REG);
++		reg &= ~(USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN |
++			 USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY);
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6368_REG);
+ 	} else if (BCMCPU_IS_6318()) {
+ 		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
+-		reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN;
++		reg |= USBH_PRIV_PLL_CTRL1_6318_SUSP_EN;
+ 		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
+ 
+ 		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG);
+@@ -180,7 +210,7 @@ void bcm63xx_usb_priv_ehci_cfg_set(void)
+ 		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG);
+ 
+ 		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
+-		reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN;
++		reg &= ~USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN;
+ 		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
+ 
+ 		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG);

target/linux/brcm63xx/patches-4.9/350-MIPS-BCM63XX-support-settings-num-usbh-ports.patch

@@ -0,0 +1,108 @@
+--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+@@ -41,6 +41,7 @@ struct board_info {
+ 
+ 	/* USB config */
+ 	struct bcm63xx_usbd_platform_data usbd;
++	unsigned int num_usbh_ports:2;
+ 
+ 	/* DSP config */
+ 	struct bcm63xx_dsp_platform_data dsp;
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h
+@@ -1,6 +1,6 @@
+ #ifndef BCM63XX_DEV_USB_EHCI_H_
+ #define BCM63XX_DEV_USB_EHCI_H_
+ 
+-int bcm63xx_ehci_register(void);
++int bcm63xx_ehci_register(unsigned int num_ports);
+ 
+ #endif /* BCM63XX_DEV_USB_EHCI_H_ */
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h
+@@ -1,6 +1,6 @@
+ #ifndef BCM63XX_DEV_USB_OHCI_H_
+ #define BCM63XX_DEV_USB_OHCI_H_
+ 
+-int bcm63xx_ohci_register(void);
++int bcm63xx_ohci_register(unsigned int num_ports);
+ 
+ #endif /* BCM63XX_DEV_USB_OHCI_H_ */
+--- a/arch/mips/bcm63xx/boards/board_common.c
++++ b/arch/mips/bcm63xx/boards/board_common.c
+@@ -166,6 +166,8 @@ static struct platform_device bcm63xx_gp
+  */
+ int __init board_register_devices(void)
+ {
++	int usbh_ports = 0;
++
+ 	if (board.has_uart0)
+ 		bcm63xx_uart_register(0);
+ 
+@@ -187,14 +189,21 @@ int __init board_register_devices(void)
+ 	    !board_get_mac_address(board.enetsw.mac_addr))
+ 		bcm63xx_enetsw_register(&board.enetsw);
+ 
++	if ((board.has_ohci0 || board.has_ehci0)) {
++		usbh_ports = board.num_usbh_ports;
++
++		if (!usbh_ports || WARN_ON(usbh_ports > 1 && board.has_usbd))
++			usbh_ports = 1;
++	}
++
+ 	if (board.has_usbd)
+ 		bcm63xx_usbd_register(&board.usbd);
+ 
+ 	if (board.has_ehci0)
+-		bcm63xx_ehci_register();
++		bcm63xx_ehci_register(usbh_ports);
+ 
+ 	if (board.has_ohci0)
+-		bcm63xx_ohci_register();
++		bcm63xx_ohci_register(usbh_ports);
+ 
+ 	if (board.has_dsp)
+ 		bcm63xx_dsp_register(&board.dsp);
+--- a/arch/mips/bcm63xx/dev-usb-ehci.c
++++ b/arch/mips/bcm63xx/dev-usb-ehci.c
+@@ -79,12 +79,14 @@ static struct platform_device bcm63xx_eh
+ 	},
+ };
+ 
+-int __init bcm63xx_ehci_register(void)
++int __init bcm63xx_ehci_register(unsigned int num_ports)
+ {
+ 	if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() &&
+ 		!BCMCPU_IS_6362() && !BCMCPU_IS_6368() && !BCMCPU_IS_63268())
+ 		return 0;
+ 
++	bcm63xx_ehci_pdata.num_ports = num_ports;	
++
+ 	ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0);
+ 	ehci_resources[0].end = ehci_resources[0].start;
+ 	ehci_resources[0].end += RSET_EHCI_SIZE - 1;
+--- a/arch/mips/bcm63xx/dev-usb-ohci.c
++++ b/arch/mips/bcm63xx/dev-usb-ohci.c
+@@ -62,7 +62,6 @@ static struct usb_ohci_pdata bcm63xx_ohc
+ 	.big_endian_desc	= 1,
+ 	.big_endian_mmio	= 1,
+ 	.no_big_frame_no	= 1,
+-	.num_ports		= 1,
+ 	.power_on		= bcm63xx_ohci_power_on,
+ 	.power_off		= bcm63xx_ohci_power_off,
+ 	.power_suspend		= bcm63xx_ohci_power_off,
+@@ -80,11 +79,13 @@ static struct platform_device bcm63xx_oh
+ 	},
+ };
+ 
+-int __init bcm63xx_ohci_register(void)
++int __init bcm63xx_ohci_register(unsigned int num_ports)
+ {
+ 	if (BCMCPU_IS_6345() || BCMCPU_IS_6338())
+ 		return -ENODEV;
+ 
++	bcm63xx_ohci_pdata.num_ports = num_ports;
++
+ 	ohci_resources[0].start = bcm63xx_regset_address(RSET_OHCI0);
+ 	ohci_resources[0].end = ohci_resources[0].start;
+ 	ohci_resources[0].end += RSET_OHCI_SIZE - 1;

target/linux/brcm63xx/patches-4.9/351-set-board-usbh-ports.patch

@@ -0,0 +1,10 @@
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -592,6 +592,7 @@ static struct board_info __initdata boar
+ 	.has_ohci0 = 1,
+ 	.has_pccard = 1,
+ 	.has_ehci0 = 1,
++	.num_usbh_ports			= 2,
+ 
+ 	.leds = {
+ 		{

target/linux/brcm63xx/patches-4.9/354-MIPS-BCM63XX-allow-building-support-for-more-than-on.patch

@@ -0,0 +1,95 @@
+From 0daf361ea799fba0af5a232036d0f06cea85ad24 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sat, 21 Jun 2014 12:47:49 +0200
+Subject: [PATCH 42/44] MIPS: BCM63XX: allow building support for more than one
+ board type
+
+Use the arguments passed to the kernel to detect being booted with
+CFE as the indicator for bcm963xx board support, allowing the
+non presence of CFE_EPTSEAL to assume a different board type.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/boards/Kconfig          |  7 +++----
+ arch/mips/bcm63xx/boards/board_bcm963xx.c |  2 +-
+ arch/mips/bcm63xx/boards/board_common.c   | 13 +++++++++++++
+ arch/mips/bcm63xx/boards/board_common.h   |  6 ++++++
+ 4 files changed, 23 insertions(+), 5 deletions(-)
+
+--- a/arch/mips/bcm63xx/boards/Kconfig
++++ b/arch/mips/bcm63xx/boards/Kconfig
+@@ -1,11 +1,10 @@
+-choice
+-	prompt "Board support"
++menu "Board support"
+ 	depends on BCM63XX
+-	default BOARD_BCM963XX
+ 
+ config BOARD_BCM963XX
+        bool "Generic Broadcom 963xx boards"
+ 	select SSB
++	default y
+        help
+ 
+-endchoice
++endmenu
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -702,7 +702,7 @@ static const struct board_info __initcon
+ /*
+  * early init callback, read nvram data from flash and checksum it
+  */
+-void __init board_prom_init(void)
++void __init board_bcm963xx_init(void)
+ {
+ 	unsigned int i;
+ 	u8 *boot_addr, *cfe;
+--- a/arch/mips/bcm63xx/boards/board_common.c
++++ b/arch/mips/bcm63xx/boards/board_common.c
+@@ -13,6 +13,8 @@
+ #include <linux/platform_device.h>
+ #include <linux/ssb/ssb.h>
+ #include <asm/addrspace.h>
++#include <asm/bootinfo.h>
++#include <asm/fw/cfe/cfe_api.h>
+ #include <bcm63xx_board.h>
+ #include <bcm63xx_cpu.h>
+ #include <bcm63xx_dev_uart.h>
+@@ -31,6 +33,8 @@
+ #include <bcm63xx_dev_usb_usbd.h>
+ #include <board_bcm963xx.h>
+ 
++#include "board_common.h"
++
+ #define PFX	"board: "
+ 
+ static struct board_info board;
+@@ -81,6 +85,15 @@ const char *board_get_name(void)
+ 	return board.name;
+ }
+ 
++void __init board_prom_init(void)
++{
++	/* detect bootloader */
++	if (fw_arg3 == CFE_EPTSEAL)
++		board_bcm963xx_init();
++	else
++		panic("unsupported bootloader detected");
++}
++
+ static int (*board_get_mac_address)(u8 mac[ETH_ALEN]);
+ 
+ /*
+--- a/arch/mips/bcm63xx/boards/board_common.h
++++ b/arch/mips/bcm63xx/boards/board_common.h
+@@ -6,4 +6,10 @@
+ void board_early_setup(const struct board_info *board,
+ 		       int (*get_mac_address)(u8 mac[ETH_ALEN]));
+ 
++#if defined(CONFIG_BOARD_BCM963XX)
++void board_bcm963xx_init(void);
++#else
++static inline void board_bcm963xx_init(void) { }
++#endif
++
+ #endif /* __BOARD_COMMON_H */

target/linux/brcm63xx/patches-4.9/355-MIPS-BCM63XX-allow-board-implementations-to-force-fl.patch

@@ -0,0 +1,61 @@
+From 8a30097a899b975709f728666d5ad20c8b832d21 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Sun, 9 Mar 2014 04:28:14 +0100
+Subject: [PATCH 43/44] MIPS: BCM63XX: allow board implementations to force
+ flash address
+
+Allow board implementations to force the physmap address.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/dev-flash.c                         | 19 ++++++++++++++-----
+ .../mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h |  2 ++
+ 2 files changed, 16 insertions(+), 5 deletions(-)
+
+--- a/arch/mips/bcm63xx/dev-flash.c
++++ b/arch/mips/bcm63xx/dev-flash.c
+@@ -58,6 +58,12 @@ static struct platform_device mtd_dev =
+ 	},
+ };
+ 
++void __init bcm63xx_flash_force_phys_base_address(u32 start, u32 end)
++{
++	mtd_resources[0].start = start;
++	mtd_resources[0].end = end;
++}
++
+ static int __init bcm63xx_detect_flash_type(void)
+ {
+ 	u32 val;
+@@ -172,12 +178,15 @@ int __init bcm63xx_flash_register(void)
+ 
+ 	switch (flash_type) {
+ 	case BCM63XX_FLASH_TYPE_PARALLEL:
+-		/* read base address of boot chip select (0) */
+-		val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+-		val &= MPI_CSBASE_BASE_MASK;
+ 
+-		mtd_resources[0].start = val;
+-		mtd_resources[0].end = 0x1FFFFFFF;
++		if (!mtd_resources[0].start) {
++			/* read base address of boot chip select (0) */
++			val = bcm_mpi_readl(MPI_CSBASE_REG(0));
++			val &= MPI_CSBASE_BASE_MASK;
++
++			mtd_resources[0].start = val;
++			mtd_resources[0].end = 0x1FFFFFFF;
++		}
+ 
+ 		return platform_device_register(&mtd_dev);
+ 	case BCM63XX_FLASH_TYPE_SERIAL:
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
+@@ -9,6 +9,8 @@ enum {
+ 
+ void bcm63xx_flash_detect(void);
+ 
++void bcm63xx_flash_force_phys_base_address(u32 start, u32 end);
++
+ int __init bcm63xx_flash_register(void);
+ 
+ #endif /* __BCM63XX_FLASH_H */

target/linux/brcm63xx/patches-4.9/356-MIPS-BCM63XX-move-fallback-sprom-support-into-its-ow.patch

@@ -0,0 +1,188 @@
+From cc025e749a1fece61a6cc0d64bbe7b12472259cc Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Tue, 29 Jul 2014 21:31:12 +0200
+Subject: [PATCH 01/10] MIPS: BCM63XX: move fallback sprom support into its own
+ unit
+
+In preparation for enhancing it, move it into its own file. Require a
+mac address to be passed as the argument to always "reserve" the mac
+regardless of the inclusion state of SSB.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/Makefile                         |  2 +-
+ arch/mips/bcm63xx/boards/board_common.c            | 53 ++--------------
+ arch/mips/bcm63xx/sprom.c                          | 70 ++++++++++++++++++++++
+ .../asm/mach-bcm63xx/bcm63xx_fallback_sprom.h      |  6 ++
+ 4 files changed, 83 insertions(+), 48 deletions(-)
+ create mode 100644 arch/mips/bcm63xx/sprom.c
+ create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h
+
+--- a/arch/mips/bcm63xx/Makefile
++++ b/arch/mips/bcm63xx/Makefile
+@@ -2,7 +2,7 @@ obj-y		+= clk.o cpu.o cs.o gpio.o irq.o
+ 		   setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \
+ 		   dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \
+ 		   dev-wdt.o dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o \
+-		   usb-common.o
++		   usb-common.o sprom.o
+ obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
+ 
+ obj-y		+= boards/
+--- a/arch/mips/bcm63xx/boards/board_common.c
++++ b/arch/mips/bcm63xx/boards/board_common.c
+@@ -40,44 +40,6 @@
+ static struct board_info board;
+ 
+ /*
+- * Register a sane SPROMv2 to make the on-board
+- * bcm4318 WLAN work
+- */
+-#ifdef CONFIG_SSB_PCIHOST
+-static struct ssb_sprom bcm63xx_sprom = {
+-	.revision		= 0x02,
+-	.board_rev		= 0x17,
+-	.country_code		= 0x0,
+-	.ant_available_bg	= 0x3,
+-	.pa0b0			= 0x15ae,
+-	.pa0b1			= 0xfa85,
+-	.pa0b2			= 0xfe8d,
+-	.pa1b0			= 0xffff,
+-	.pa1b1			= 0xffff,
+-	.pa1b2			= 0xffff,
+-	.gpio0			= 0xff,
+-	.gpio1			= 0xff,
+-	.gpio2			= 0xff,
+-	.gpio3			= 0xff,
+-	.maxpwr_bg		= 0x004c,
+-	.itssi_bg		= 0x00,
+-	.boardflags_lo		= 0x2848,
+-	.boardflags_hi		= 0x0000,
+-};
+-
+-int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)
+-{
+-	if (bus->bustype == SSB_BUSTYPE_PCI) {
+-		memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom));
+-		return 0;
+-	} else {
+-		printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n");
+-		return -EINVAL;
+-	}
+-}
+-#endif
+-
+-/*
+  * return board name for /proc/cpuinfo
+  */
+ const char *board_get_name(void)
+@@ -180,6 +142,7 @@ static struct platform_device bcm63xx_gp
+ int __init board_register_devices(void)
+ {
+ 	int usbh_ports = 0;
++	u8 mac[ETH_ALEN];
+ 
+ 	if (board.has_uart0)
+ 		bcm63xx_uart_register(0);
+@@ -224,15 +187,10 @@ int __init board_register_devices(void)
+ 	/* Generate MAC address for WLAN and register our SPROM,
+ 	 * do this after registering enet devices
+ 	 */
+-#ifdef CONFIG_SSB_PCIHOST
+-	if (!board_get_mac_address(bcm63xx_sprom.il0mac)) {
+-		memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
+-		memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
+-		if (ssb_arch_register_fallback_sprom(
+-				&bcm63xx_get_fallback_sprom) < 0)
+-			pr_err(PFX "failed to register fallback SPROM\n");
+-	}
+-#endif
++
++	if (board_get_mac_address(mac) ||
++	    bcm63xx_register_fallback_sprom(mac))
++		pr_err(PFX "failed to register fallback SPROM\n");
+ 
+ 	bcm63xx_spi_register();
+ 
+--- /dev/null
++++ b/arch/mips/bcm63xx/sprom.c
+@@ -0,0 +1,70 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <[email protected]>
++ * Copyright (C) 2008 Florian Fainelli <[email protected]>
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/string.h>
++#include <linux/platform_device.h>
++#include <linux/ssb/ssb.h>
++#include <bcm63xx_fallback_sprom.h>
++#include <board_bcm963xx.h>
++
++#define PFX	"sprom: "
++
++/*
++ * Register a sane SPROMv2 to make the on-board
++ * bcm4318 WLAN work
++ */
++#ifdef CONFIG_SSB_PCIHOST
++static struct ssb_sprom bcm63xx_sprom = {
++	.revision		= 0x02,
++	.board_rev		= 0x17,
++	.country_code		= 0x0,
++	.ant_available_bg	= 0x3,
++	.pa0b0			= 0x15ae,
++	.pa0b1			= 0xfa85,
++	.pa0b2			= 0xfe8d,
++	.pa1b0			= 0xffff,
++	.pa1b1			= 0xffff,
++	.pa1b2			= 0xffff,
++	.gpio0			= 0xff,
++	.gpio1			= 0xff,
++	.gpio2			= 0xff,
++	.gpio3			= 0xff,
++	.maxpwr_bg		= 0x004c,
++	.itssi_bg		= 0x00,
++	.boardflags_lo		= 0x2848,
++	.boardflags_hi		= 0x0000,
++};
++
++int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)
++{
++	if (bus->bustype == SSB_BUSTYPE_PCI) {
++		memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom));
++		return 0;
++	} else {
++		printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n");
++		return -EINVAL;
++	}
++}
++#endif
++
++int __init bcm63xx_register_fallback_sprom(u8 *mac)
++{
++	int ret = 0;
++
++#ifdef CONFIG_SSB_PCIHOST
++	memcpy(bcm63xx_sprom.il0mac, mac, ETH_ALEN);
++	memcpy(bcm63xx_sprom.et0mac, mac, ETH_ALEN);
++	memcpy(bcm63xx_sprom.et1mac, mac, ETH_ALEN);
++
++	ret = ssb_arch_register_fallback_sprom(&bcm63xx_get_fallback_sprom);
++#endif
++	return ret;
++}
+--- /dev/null
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h
+@@ -0,0 +1,6 @@
++#ifndef __BCM63XX_FALLBACK_SPROM
++#define __BCM63XX_FALLBACK_SPROM
++
++int bcm63xx_register_fallback_sprom(u8 *mac);
++
++#endif

target/linux/brcm63xx/patches-4.9/357-MIPS-BCM63XX-use-platform-data-for-the-sprom.patch

@@ -0,0 +1,95 @@
+From 9912a8b3c240a9b0af01ff496b7e8ed9e4cc5b82 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Tue, 29 Jul 2014 21:43:49 +0200
+Subject: [PATCH 02/10] MIPS: BCM63XX: use platform data for the sprom
+
+Similar to ethernet setup, use a platform data struct for passing
+the mac. This eliminates the requirement to allocate an array on
+stack for the mac passed.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/boards/board_common.c                     | 6 ++----
+ arch/mips/bcm63xx/sprom.c                                   | 8 ++++----
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h | 8 +++++++-
+ arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h         | 4 ++++
+ 4 files changed, 17 insertions(+), 9 deletions(-)
+
+--- a/arch/mips/bcm63xx/boards/board_common.c
++++ b/arch/mips/bcm63xx/boards/board_common.c
+@@ -142,7 +142,6 @@ static struct platform_device bcm63xx_gp
+ int __init board_register_devices(void)
+ {
+ 	int usbh_ports = 0;
+-	u8 mac[ETH_ALEN];
+ 
+ 	if (board.has_uart0)
+ 		bcm63xx_uart_register(0);
+@@ -188,8 +187,8 @@ int __init board_register_devices(void)
+ 	 * do this after registering enet devices
+ 	 */
+ 
+-	if (board_get_mac_address(mac) ||
+-	    bcm63xx_register_fallback_sprom(mac))
++	if (board_get_mac_address(board.fallback_sprom.mac_addr) ||
++	    bcm63xx_register_fallback_sprom(&board.fallback_sprom))
+ 		pr_err(PFX "failed to register fallback SPROM\n");
+ 
+ 	bcm63xx_spi_register();
+--- a/arch/mips/bcm63xx/sprom.c
++++ b/arch/mips/bcm63xx/sprom.c
+@@ -55,14 +55,14 @@ int bcm63xx_get_fallback_sprom(struct ss
+ }
+ #endif
+ 
+-int __init bcm63xx_register_fallback_sprom(u8 *mac)
++int __init bcm63xx_register_fallback_sprom(struct fallback_sprom_data *data)
+ {
+ 	int ret = 0;
+ 
+ #ifdef CONFIG_SSB_PCIHOST
+-	memcpy(bcm63xx_sprom.il0mac, mac, ETH_ALEN);
+-	memcpy(bcm63xx_sprom.et0mac, mac, ETH_ALEN);
+-	memcpy(bcm63xx_sprom.et1mac, mac, ETH_ALEN);
++	memcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN);
++	memcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN);
++	memcpy(bcm63xx_sprom.et1mac, data->mac_addr, ETH_ALEN);
+ 
+ 	ret = ssb_arch_register_fallback_sprom(&bcm63xx_get_fallback_sprom);
+ #endif
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h
+@@ -1,6 +1,12 @@
+ #ifndef __BCM63XX_FALLBACK_SPROM
+ #define __BCM63XX_FALLBACK_SPROM
+ 
+-int bcm63xx_register_fallback_sprom(u8 *mac);
++#include <linux/if_ether.h>
++
++struct fallback_sprom_data {
++	u8 mac_addr[ETH_ALEN];
++};
++
++int bcm63xx_register_fallback_sprom(struct fallback_sprom_data *data);
+ 
+ #endif
+--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+@@ -7,6 +7,7 @@
+ #include <bcm63xx_dev_enet.h>
+ #include <bcm63xx_dev_usb_usbd.h>
+ #include <bcm63xx_dev_dsp.h>
++#include <bcm63xx_fallback_sprom.h>
+ 
+ /*
+  * flash mapping
+@@ -54,6 +55,9 @@ struct board_info {
+ 
+ 	/* External PHY reset GPIO flags from gpio.h */
+ 	unsigned long ephy_reset_gpio_flags;
++
++	/* fallback sprom config */
++	struct fallback_sprom_data fallback_sprom;
+ };
+ 
+ #endif /* ! BOARD_BCM963XX_H_ */

target/linux/brcm63xx/patches-4.9/358-MIPS-BCM63XX-make-fallback-sprom-optional.patch

@@ -0,0 +1,140 @@
+From 83131acbfb59760a19f3711c09526e191c8aad54 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Tue, 29 Jul 2014 21:52:56 +0200
+Subject: [PATCH 03/10] MIPS: BCM63XX: make fallback sprom optional
+
+Some devices do not provide enough mac addresses to populate wifi in
+addition to ethernet.
+
+Use having pci enabled as a rough heuristic which boards should have it
+enabled.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/boards/board_bcm963xx.c           | 12 ++++++++++++
+ arch/mips/bcm63xx/boards/board_common.c             |  5 +++--
+ arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h |  1 +
+ 3 files changed, 16 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -70,6 +70,7 @@ static struct board_info __initdata boar
+ 	.has_uart0			= 1,
+ 	.has_pci			= 1,
+ 	.has_usbd			= 0,
++	.use_fallback_sprom		= 1,
+ 
+ 	.usbd = {
+ 		.use_fullspeed		= 0,
+@@ -219,6 +220,7 @@ static struct board_info __initdata boar
+ 	.has_uart0			= 1,
+ 	.has_enet0			= 1,
+ 	.has_pci			= 1,
++	.use_fallback_sprom		= 1,
+ 
+ 	.enet0 = {
+ 		.has_phy		= 1,
+@@ -264,6 +266,7 @@ static struct board_info __initdata boar
+ 	.has_enet0			= 1,
+ 	.has_enet1			= 1,
+ 	.has_pci			= 1,
++	.use_fallback_sprom		= 1,
+ 
+ 	.enet0 = {
+ 		.has_phy		= 1,
+@@ -324,6 +327,7 @@ static struct board_info __initdata boar
+ 	.has_enet0			= 1,
+ 	.has_enet1			= 1,
+ 	.has_pci			= 1,
++	.use_fallback_sprom		= 1,
+ 
+ 	.enet0 = {
+ 		.has_phy		= 1,
+@@ -378,6 +382,7 @@ static struct board_info __initdata boar
+ 	.has_enet0			= 1,
+ 	.has_enet1			= 1,
+ 	.has_pci			= 1,
++	.use_fallback_sprom		= 1,
+ 
+ 	.enet0 = {
+ 		.has_phy		= 1,
+@@ -436,6 +441,7 @@ static struct board_info __initdata boar
+ 	.has_enet0			= 1,
+ 	.has_enet1			= 1,
+ 	.has_pci			= 1,
++	.use_fallback_sprom		= 1,
+ 
+ 	.enet0 = {
+ 		.has_phy		= 1,
+@@ -459,6 +465,7 @@ static struct board_info __initdata boar
+ 	.has_enet0			= 1,
+ 	.has_enet1			= 1,
+ 	.has_pci			= 1,
++	.use_fallback_sprom		= 1,
+ 
+ 	.enet0 = {
+ 		.has_phy		= 1,
+@@ -477,6 +484,7 @@ static struct board_info __initdata boar
+ 
+ 	.has_uart0			= 1,
+ 	.has_pci			= 1,
++	.use_fallback_sprom		= 1,
+ 	.has_ohci0			= 1,
+ 
+ 	.has_enet0			= 1,
+@@ -499,6 +507,7 @@ static struct board_info __initdata boar
+ 	.has_enet0			= 1,
+ 	.has_enet1			= 1,
+ 	.has_pci			= 1,
++	.use_fallback_sprom		= 1,
+ 
+ 	.enet0 = {
+ 		.has_phy		= 1,
+@@ -525,6 +534,7 @@ static struct board_info __initdata boar
+ 	.has_enet0			= 1,
+ 	.has_enet1			= 1,
+ 	.has_pci			= 1,
++	.use_fallback_sprom		= 1,
+ 
+ 	.enet0 = {
+ 		.has_phy		= 1,
+@@ -577,6 +587,7 @@ static struct board_info __initdata boar
+ 	.has_enet0			= 1,
+ 	.has_enet1			= 1,
+ 	.has_pci			= 1,
++	.use_fallback_sprom		= 1,
+ 
+ 	.enet0 = {
+ 		.has_phy		= 1,
+@@ -648,6 +659,7 @@ static struct board_info __initdata boar
+ 	.has_enet0			= 1,
+ 	.has_enet1			= 1,
+ 	.has_pci			= 1,
++	.use_fallback_sprom		= 1,
+ 
+ 	.enet0 = {
+ 		.has_phy		= 1,
+--- a/arch/mips/bcm63xx/boards/board_common.c
++++ b/arch/mips/bcm63xx/boards/board_common.c
+@@ -187,8 +187,9 @@ int __init board_register_devices(void)
+ 	 * do this after registering enet devices
+ 	 */
+ 
+-	if (board_get_mac_address(board.fallback_sprom.mac_addr) ||
+-	    bcm63xx_register_fallback_sprom(&board.fallback_sprom))
++	if (board.use_fallback_sprom &&
++	    (board_get_mac_address(board.fallback_sprom.mac_addr) ||
++	     bcm63xx_register_fallback_sprom(&board.fallback_sprom)))
+ 		pr_err(PFX "failed to register fallback SPROM\n");
+ 
+ 	bcm63xx_spi_register();
+--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+@@ -34,6 +34,7 @@ struct board_info {
+ 	unsigned int	has_dsp:1;
+ 	unsigned int	has_uart0:1;
+ 	unsigned int	has_uart1:1;
++	unsigned int	use_fallback_sprom:1;
+ 
+ 	/* ethernet config */
+ 	struct bcm63xx_enet_platform_data enet0;

target/linux/brcm63xx/patches-4.9/359-MIPS-BCM63XX-allow-different-types-of-sprom.patch

@@ -0,0 +1,66 @@
+From 1cece9f7aca1f0c193edce201f77a87008c5a405 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Tue, 29 Jul 2014 21:58:38 +0200
+Subject: [PATCH 04/10] MIPS: BCM63XX: allow different types of sprom
+
+Different chips require different sprom contents, so prepare for
+supplying the appropriate sprom type.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/sprom.c                                   | 13 ++++++++++++-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h |  5 +++++
+ 2 files changed, 17 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/bcm63xx/sprom.c
++++ b/arch/mips/bcm63xx/sprom.c
+@@ -22,7 +22,7 @@
+  * bcm4318 WLAN work
+  */
+ #ifdef CONFIG_SSB_PCIHOST
+-static struct ssb_sprom bcm63xx_sprom = {
++static __initconst struct ssb_sprom bcm63xx_default_sprom = {
+ 	.revision		= 0x02,
+ 	.board_rev		= 0x17,
+ 	.country_code		= 0x0,
+@@ -43,6 +43,8 @@ static struct ssb_sprom bcm63xx_sprom =
+ 	.boardflags_hi		= 0x0000,
+ };
+ 
++static struct ssb_sprom bcm63xx_sprom;
++
+ int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)
+ {
+ 	if (bus->bustype == SSB_BUSTYPE_PCI) {
+@@ -60,6 +62,15 @@ int __init bcm63xx_register_fallback_spr
+ 	int ret = 0;
+ 
+ #ifdef CONFIG_SSB_PCIHOST
++	switch (data->type) {
++	case SPROM_DEFAULT:
++		memcpy(&bcm63xx_sprom, &bcm63xx_default_sprom,
++		       sizeof(bcm63xx_sprom));
++		break;
++	default:
++		return -EINVAL;
++	}
++
+ 	memcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN);
+ 	memcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN);
+ 	memcpy(bcm63xx_sprom.et1mac, data->mac_addr, ETH_ALEN);
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h
+@@ -3,8 +3,13 @@
+ 
+ #include <linux/if_ether.h>
+ 
++enum sprom_type {
++	SPROM_DEFAULT, /* default fallback sprom */
++};
++
+ struct fallback_sprom_data {
+ 	u8 mac_addr[ETH_ALEN];
++	enum sprom_type type;
+ };
+ 
+ int bcm63xx_register_fallback_sprom(struct fallback_sprom_data *data);

target/linux/brcm63xx/patches-4.9/360-MIPS-BCM63XX-add-support-for-raw-sproms.patch

@@ -0,0 +1,517 @@
+From cedee63bc73f8b7d45b8c0cba1236986812c1f83 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Tue, 29 Jul 2014 22:16:36 +0200
+Subject: [PATCH 05/10] MIPS: BCM63XX: add support for "raw" sproms
+
+Allow using raw sprom content as templates.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/sprom.c | 482 ++++++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 482 insertions(+)
+
+--- a/arch/mips/bcm63xx/sprom.c
++++ b/arch/mips/bcm63xx/sprom.c
+@@ -55,13 +55,492 @@ int bcm63xx_get_fallback_sprom(struct ss
+ 		return -EINVAL;
+ 	}
+ }
++
++/* FIXME: use lib_sprom after submission upstream */
++
++/* Get the word-offset for a SSB_SPROM_XXX define. */
++#define SPOFF(offset)	((offset) / sizeof(u16))
++/* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
++#define SPEX16(_outvar, _offset, _mask, _shift)	\
++	out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
++#define SPEX32(_outvar, _offset, _mask, _shift)	\
++	out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
++			   in[SPOFF(_offset)]) & (_mask)) >> (_shift))
++#define SPEX(_outvar, _offset, _mask, _shift) \
++	SPEX16(_outvar, _offset, _mask, _shift)
++
++#define SPEX_ARRAY8(_field, _offset, _mask, _shift)	\
++	do {	\
++		SPEX(_field[0], _offset +  0, _mask, _shift);	\
++		SPEX(_field[1], _offset +  2, _mask, _shift);	\
++		SPEX(_field[2], _offset +  4, _mask, _shift);	\
++		SPEX(_field[3], _offset +  6, _mask, _shift);	\
++		SPEX(_field[4], _offset +  8, _mask, _shift);	\
++		SPEX(_field[5], _offset + 10, _mask, _shift);	\
++		SPEX(_field[6], _offset + 12, _mask, _shift);	\
++		SPEX(_field[7], _offset + 14, _mask, _shift);	\
++	} while (0)
++
++
++static s8 r123_extract_antgain(u8 sprom_revision, const u16 *in,
++			       u16 mask, u16 shift)
++{
++	u16 v;
++	u8 gain;
++
++	v = in[SPOFF(SSB_SPROM1_AGAIN)];
++	gain = (v & mask) >> shift;
++	if (gain == 0xFF)
++		gain = 2; /* If unset use 2dBm */
++	if (sprom_revision == 1) {
++		/* Convert to Q5.2 */
++		gain <<= 2;
++	} else {
++		/* Q5.2 Fractional part is stored in 0xC0 */
++		gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
++	}
++
++	return (s8)gain;
++}
++
++static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
++{
++	SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
++	SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
++	SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
++	SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
++	SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
++	SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
++	SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
++	SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
++	SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
++	SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
++	     SSB_SPROM2_MAXP_A_LO_SHIFT);
++}
++
++static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
++{
++	u16 loc[3];
++
++	if (out->revision == 3)			/* rev 3 moved MAC */
++		loc[0] = SSB_SPROM3_IL0MAC;
++	else {
++		loc[0] = SSB_SPROM1_IL0MAC;
++		loc[1] = SSB_SPROM1_ET0MAC;
++		loc[2] = SSB_SPROM1_ET1MAC;
++	}
++
++	SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
++	SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
++	     SSB_SPROM1_ETHPHY_ET1A_SHIFT);
++	SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
++	SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
++	SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
++	SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
++	if (out->revision == 1)
++		SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
++		     SSB_SPROM1_BINF_CCODE_SHIFT);
++	SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
++	     SSB_SPROM1_BINF_ANTA_SHIFT);
++	SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
++	     SSB_SPROM1_BINF_ANTBG_SHIFT);
++	SPEX(pa0b0, SSB_SPROM1_PA0B0, 0xFFFF, 0);
++	SPEX(pa0b1, SSB_SPROM1_PA0B1, 0xFFFF, 0);
++	SPEX(pa0b2, SSB_SPROM1_PA0B2, 0xFFFF, 0);
++	SPEX(pa1b0, SSB_SPROM1_PA1B0, 0xFFFF, 0);
++	SPEX(pa1b1, SSB_SPROM1_PA1B1, 0xFFFF, 0);
++	SPEX(pa1b2, SSB_SPROM1_PA1B2, 0xFFFF, 0);
++	SPEX(gpio0, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P0, 0);
++	SPEX(gpio1, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P1,
++	     SSB_SPROM1_GPIOA_P1_SHIFT);
++	SPEX(gpio2, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P2, 0);
++	SPEX(gpio3, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P3,
++	     SSB_SPROM1_GPIOB_P3_SHIFT);
++	SPEX(maxpwr_a, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_A,
++	     SSB_SPROM1_MAXPWR_A_SHIFT);
++	SPEX(maxpwr_bg, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_BG, 0);
++	SPEX(itssi_a, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_A,
++	     SSB_SPROM1_ITSSI_A_SHIFT);
++	SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
++	SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
++
++	SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
++	SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
++
++	/* Extract the antenna gain values. */
++	out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
++						    SSB_SPROM1_AGAIN_BG,
++						    SSB_SPROM1_AGAIN_BG_SHIFT);
++	out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
++						    SSB_SPROM1_AGAIN_A,
++						    SSB_SPROM1_AGAIN_A_SHIFT);
++	if (out->revision >= 2)
++		sprom_extract_r23(out, in);
++}
++
++/* Revs 4 5 and 8 have partially shared layout */
++static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
++{
++	SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
++	     SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
++	SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
++	     SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
++	SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
++	     SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
++	SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
++	     SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
++
++	SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
++	     SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
++	SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
++	     SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
++	SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
++	     SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
++	SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
++	     SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
++
++	SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
++	     SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
++	SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
++	     SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
++	SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
++	     SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
++	SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
++	     SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
++
++	SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
++	     SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
++	SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
++	     SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
++	SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
++	     SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
++	SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
++	     SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
++}
++
++static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
++{
++	u16 il0mac_offset;
++
++	if (out->revision == 4)
++		il0mac_offset = SSB_SPROM4_IL0MAC;
++	else
++		il0mac_offset = SSB_SPROM5_IL0MAC;
++
++	SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
++	SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
++	     SSB_SPROM4_ETHPHY_ET1A_SHIFT);
++	SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
++	SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
++	if (out->revision == 4) {
++		SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
++		SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
++		SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
++		SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
++		SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
++		SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
++	} else {
++		SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);
++		SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);
++		SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
++		SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
++		SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
++		SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
++	}
++	SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
++	     SSB_SPROM4_ANTAVAIL_A_SHIFT);
++	SPEX(ant_available_bg, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_BG,
++	     SSB_SPROM4_ANTAVAIL_BG_SHIFT);
++	SPEX(maxpwr_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_MAXP_BG_MASK, 0);
++	SPEX(itssi_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_ITSSI_BG,
++	     SSB_SPROM4_ITSSI_BG_SHIFT);
++	SPEX(maxpwr_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_MAXP_A_MASK, 0);
++	SPEX(itssi_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_ITSSI_A,
++	     SSB_SPROM4_ITSSI_A_SHIFT);
++	if (out->revision == 4) {
++		SPEX(gpio0, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P0, 0);
++		SPEX(gpio1, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P1,
++		     SSB_SPROM4_GPIOA_P1_SHIFT);
++		SPEX(gpio2, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P2, 0);
++		SPEX(gpio3, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P3,
++		     SSB_SPROM4_GPIOB_P3_SHIFT);
++	} else {
++		SPEX(gpio0, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P0, 0);
++		SPEX(gpio1, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P1,
++		     SSB_SPROM5_GPIOA_P1_SHIFT);
++		SPEX(gpio2, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P2, 0);
++		SPEX(gpio3, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P3,
++		     SSB_SPROM5_GPIOB_P3_SHIFT);
++	}
++
++	/* Extract the antenna gain values. */
++	SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
++	     SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
++	SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
++	     SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
++	SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
++	     SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
++	SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
++	     SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
++
++	sprom_extract_r458(out, in);
++
++	/* TODO - get remaining rev 4 stuff needed */
++}
++
++static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
++{
++	int i;
++	u16 o;
++	u16 pwr_info_offset[] = {
++		SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
++		SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
++	};
++	BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
++			ARRAY_SIZE(out->core_pwr_info));
++
++	SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
++	SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
++	SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
++	SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
++	SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
++	SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
++	SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
++	SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0);
++	SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
++	     SSB_SPROM8_ANTAVAIL_A_SHIFT);
++	SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
++	     SSB_SPROM8_ANTAVAIL_BG_SHIFT);
++	SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);
++	SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,
++	     SSB_SPROM8_ITSSI_BG_SHIFT);
++	SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
++	SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
++	     SSB_SPROM8_ITSSI_A_SHIFT);
++	SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
++	SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
++	     SSB_SPROM8_MAXP_AL_SHIFT);
++	SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
++	SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
++	     SSB_SPROM8_GPIOA_P1_SHIFT);
++	SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
++	SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
++	     SSB_SPROM8_GPIOB_P3_SHIFT);
++	SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
++	SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
++	     SSB_SPROM8_TRI5G_SHIFT);
++	SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
++	SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
++	     SSB_SPROM8_TRI5GH_SHIFT);
++	SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0);
++	SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
++	     SSB_SPROM8_RXPO5G_SHIFT);
++	SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
++	SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
++	     SSB_SPROM8_RSSISMC2G_SHIFT);
++	SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
++	     SSB_SPROM8_RSSISAV2G_SHIFT);
++	SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
++	     SSB_SPROM8_BXA2G_SHIFT);
++	SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
++	SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
++	     SSB_SPROM8_RSSISMC5G_SHIFT);
++	SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
++	     SSB_SPROM8_RSSISAV5G_SHIFT);
++	SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
++	     SSB_SPROM8_BXA5G_SHIFT);
++	SPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0);
++	SPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0);
++	SPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0);
++	SPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0);
++	SPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0);
++	SPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0);
++	SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0);
++	SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0);
++	SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0);
++	SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0);
++	SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0);
++	SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0);
++	SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0);
++	SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0);
++	SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0);
++	SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0);
++	SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
++
++	/* Extract the antenna gain values. */
++	SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
++	     SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
++	SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
++	     SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
++	SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
++	     SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
++	SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
++	     SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
++
++	/* Extract cores power info info */
++	for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
++		o = pwr_info_offset[i];
++		SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
++			SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
++		SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
++			SSB_SPROM8_2G_MAXP, 0);
++
++		SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
++		SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
++		SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
++
++		SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
++			SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
++		SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
++			SSB_SPROM8_5G_MAXP, 0);
++		SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
++			SSB_SPROM8_5GH_MAXP, 0);
++		SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
++			SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
++
++		SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
++		SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
++		SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
++		SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
++		SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
++		SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
++		SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
++		SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
++		SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
++	}
++
++	/* Extract FEM info */
++	SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
++		SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
++	SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
++		SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
++	SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
++		SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
++	SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
++		SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
++	SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
++		SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
++
++	SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
++		SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
++	SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
++		SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
++	SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
++		SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
++	SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
++		SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
++	SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
++		SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
++
++	SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
++	     SSB_SPROM8_LEDDC_ON_SHIFT);
++	SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
++	     SSB_SPROM8_LEDDC_OFF_SHIFT);
++
++	SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
++	     SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
++	SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
++	     SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
++	SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
++	     SSB_SPROM8_TXRXC_SWITCH_SHIFT);
++
++	SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
++
++	SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
++	SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
++	SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
++	SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
++
++	SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
++	     SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
++	SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
++	     SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
++	SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
++	     SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
++	     SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
++	SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
++	     SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
++	SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
++	     SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
++	     SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
++	SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
++	     SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
++	     SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
++	SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
++	     SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
++	     SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
++	SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
++	     SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
++
++	SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
++	SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
++	SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
++	SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
++
++	SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
++	     SSB_SPROM8_THERMAL_TRESH_SHIFT);
++	SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
++	     SSB_SPROM8_THERMAL_OFFSET_SHIFT);
++	SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
++	     SSB_SPROM8_TEMPDELTA_PHYCAL,
++	     SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
++	SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
++	     SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
++	SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
++	     SSB_SPROM8_TEMPDELTA_HYSTERESIS,
++	     SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
++	sprom_extract_r458(out, in);
++
++	/* TODO - get remaining rev 8 stuff needed */
++}
++
++static int sprom_extract(struct ssb_sprom *out, const u16 *in, u16 size)
++{
++	memset(out, 0, sizeof(*out));
++
++	out->revision = in[size - 1] & 0x00FF;
++	memset(out->et0mac, 0xFF, 6);		/* preset et0 and et1 mac */
++	memset(out->et1mac, 0xFF, 6);
++
++	switch (out->revision) {
++	case 1:
++	case 2:
++	case 3:
++		sprom_extract_r123(out, in);
++		break;
++	case 4:
++	case 5:
++		sprom_extract_r45(out, in);
++		break;
++	case 8:
++		sprom_extract_r8(out, in);
++		break;
++	default:
++		pr_warn("Unsupported SPROM revision %d detected. Will extract v1\n",
++			 out->revision);
++		out->revision = 1;
++		sprom_extract_r123(out, in);
++	}
++
++	if (out->boardflags_lo == 0xFFFF)
++		out->boardflags_lo = 0;  /* per specs */
++	if (out->boardflags_hi == 0xFFFF)
++		out->boardflags_hi = 0;  /* per specs */
++
++	return 0;
++}
++
++static __initdata u16 template_sprom[220];
+ #endif
+ 
++
+ int __init bcm63xx_register_fallback_sprom(struct fallback_sprom_data *data)
+ {
+ 	int ret = 0;
+ 
+ #ifdef CONFIG_SSB_PCIHOST
++	u16 size = 0;
++
+ 	switch (data->type) {
+ 	case SPROM_DEFAULT:
+ 		memcpy(&bcm63xx_sprom, &bcm63xx_default_sprom,
+@@ -71,6 +550,9 @@ int __init bcm63xx_register_fallback_spr
+ 		return -EINVAL;
+ 	}
+ 
++	if (size > 0)
++		sprom_extract(&bcm63xx_sprom, template_sprom, size);
++
+ 	memcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN);
+ 	memcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN);
+ 	memcpy(bcm63xx_sprom.et1mac, data->mac_addr, ETH_ALEN);

target/linux/brcm63xx/patches-4.9/361-MIPS-BCM63XX-add-raw-fallback-sproms-for-most-common.patch

@@ -0,0 +1,181 @@
+From 7be5bb46003295c9e04fd4e795593b2deaacd783 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Tue, 29 Jul 2014 22:33:38 +0200
+Subject: [PATCH 06/10] MIPS: BCM63XX: add raw fallback sproms for most common
+ ssb cards
+
+Add template sproms for BCM4306, BCM4318, BCM4321, BCM4322, and BCM43222.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/sprom.c                          | 136 +++++++++++++++++++++
+ .../asm/mach-bcm63xx/bcm63xx_fallback_sprom.h      |   6 +
+ 2 files changed, 142 insertions(+)
+
+--- a/arch/mips/bcm63xx/sprom.c
++++ b/arch/mips/bcm63xx/sprom.c
+@@ -43,6 +43,122 @@ static __initconst struct ssb_sprom bcm6
+ 	.boardflags_hi		= 0x0000,
+ };
+ 
++
++static __initconst u16 bcm4306_sprom[] = {
++	0x4001, 0x0000, 0x0453, 0x14e4, 0x4320, 0x8000, 0x0002, 0x0002,
++	0x1000, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x3034, 0x14d4,
++	0xfa91, 0xfe60, 0xffff, 0xffff, 0x004c, 0xffff, 0xffff, 0xffff,
++	0x003e, 0x0a49, 0xff02, 0x0000, 0xff10, 0xffff, 0xffff, 0x0002,
++};
++
++static __initconst u16 bcm4318_sprom[] = {
++	0x2001, 0x0000, 0x0449, 0x14e4, 0x4318, 0x8000, 0x0002, 0x0000,
++	0x1000, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x3046, 0x15a7,
++	0xfab0, 0xfe97, 0xffff, 0xffff, 0x0048, 0xffff, 0xffff, 0xffff,
++	0x003e, 0xea49, 0xff02, 0x0000, 0xff08, 0xffff, 0xffff, 0x0002,
++};
++
++static __initconst u16 bcm4321_sprom[] = {
++	0x3001, 0x0000, 0x046c, 0x14e4, 0x4328, 0x8000, 0x0002, 0x0000,
++	0x1000, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x5372, 0x0032, 0x4a01, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0x0303, 0x0202,
++	0xffff, 0x2728, 0x5b5b, 0x222b, 0x5b5b, 0x1927, 0x5b5b, 0x1e36,
++	0x5b5b, 0x303c, 0x3030, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x3e4c, 0x0000, 0x0000, 0x0000, 0x0000, 0x7838, 0x3a34, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0x3e4c,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x7838, 0x3a34, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0x0008, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0x0004,
++};
++
++static __initconst u16 bcm4322_sprom[] = {
++	0x3001, 0x0000, 0x04bc, 0x14e4, 0x432c, 0x8000, 0x0002, 0x0000,
++	0x1730, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x5372, 0x1209, 0x0200, 0x0000, 0x0400, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0x0303, 0x0202,
++	0xffff, 0x0033, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0301,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x2048, 0xfe9a, 0x1571, 0xfabd, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x2048, 0xfeb9, 0x159f, 0xfadd, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x3333, 0x5555, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0x0008,
++};
++
++static __initconst u16 bcm43222_sprom[] = {
++	0x2001, 0x0000, 0x04d4, 0x14e4, 0x4351, 0x8000, 0x0002, 0x0000,
++	0x1730, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x5372, 0x2305, 0x0200, 0x0000, 0x2400, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0x0303, 0x0202,
++	0xffff, 0x0033, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0325,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x204c, 0xfea6, 0x1717, 0xfa6d, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x204c, 0xfeb8, 0x167c, 0xfa9e, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x0000, 0x3333, 0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x3333, 0x3333, 0x3333, 0x3333, 0x3333, 0x3333, 0x3333,
++	0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0004, 0x0000, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0x0008,
++};
++
+ static struct ssb_sprom bcm63xx_sprom;
+ 
+ int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)
+@@ -542,6 +658,26 @@ int __init bcm63xx_register_fallback_spr
+ 	u16 size = 0;
+ 
+ 	switch (data->type) {
++	case SPROM_BCM4306:
++		memcpy(&template_sprom, &bcm4306_sprom, sizeof(bcm4306_sprom));
++		size = ARRAY_SIZE(bcm4306_sprom);
++		break;
++	case SPROM_BCM4318:
++		memcpy(&template_sprom, &bcm4318_sprom, sizeof(bcm4318_sprom));
++		size = ARRAY_SIZE(bcm4318_sprom);
++		break;
++	case SPROM_BCM4321:
++		memcpy(&template_sprom, &bcm4321_sprom, sizeof(bcm4321_sprom));
++		size = ARRAY_SIZE(bcm4321_sprom);
++		break;
++	case SPROM_BCM4322:
++		memcpy(&template_sprom, &bcm4322_sprom, sizeof(bcm4322_sprom));
++		size = ARRAY_SIZE(bcm4322_sprom);
++		break;
++	case SPROM_BCM43222:
++		memcpy(&template_sprom, &bcm43222_sprom, sizeof(bcm43222_sprom));
++		size = ARRAY_SIZE(bcm43222_sprom);
++		break;
+ 	case SPROM_DEFAULT:
+ 		memcpy(&bcm63xx_sprom, &bcm63xx_default_sprom,
+ 		       sizeof(bcm63xx_sprom));
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h
+@@ -5,6 +5,12 @@
+ 
+ enum sprom_type {
+ 	SPROM_DEFAULT, /* default fallback sprom */
++	/* SSB based */
++	SPROM_BCM4306,
++	SPROM_BCM4318,
++	SPROM_BCM4321,
++	SPROM_BCM4322,
++	SPROM_BCM43222,
+ };
+ 
+ struct fallback_sprom_data {

target/linux/brcm63xx/patches-4.9/362-MIPS-BCM63XX-also-register-a-fallback-sprom-for-bcma.patch

@@ -0,0 +1,128 @@
+From 03feb9db77fba3eef3d83e17a87a56979659b248 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Tue, 29 Jul 2014 22:48:26 +0200
+Subject: [PATCH 07/10] MIPS: BCM63XX: also register a fallback sprom for bcma
+
+Similar to SSB, register a fallback sprom handler for BCMA.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/boards/Kconfig |  1 +
+ arch/mips/bcm63xx/sprom.c        | 40 +++++++++++++++++++++++++++++++++++-----
+ 2 files changed, 36 insertions(+), 5 deletions(-)
+
+--- a/arch/mips/bcm63xx/boards/Kconfig
++++ b/arch/mips/bcm63xx/boards/Kconfig
+@@ -4,6 +4,7 @@ menu "Board support"
+ config BOARD_BCM963XX
+        bool "Generic Broadcom 963xx boards"
+ 	select SSB
++	select BCMA
+ 	default y
+        help
+ 
+--- a/arch/mips/bcm63xx/sprom.c
++++ b/arch/mips/bcm63xx/sprom.c
+@@ -12,6 +12,7 @@
+ #include <linux/string.h>
+ #include <linux/platform_device.h>
+ #include <linux/ssb/ssb.h>
++#include <linux/bcma/bcma.h>
+ #include <bcm63xx_fallback_sprom.h>
+ #include <board_bcm963xx.h>
+ 
+@@ -21,7 +22,7 @@
+  * Register a sane SPROMv2 to make the on-board
+  * bcm4318 WLAN work
+  */
+-#ifdef CONFIG_SSB_PCIHOST
++#if defined(CONFIG_SSB_PCIHOST) || defined(CONFIG_BCMA_HOST_PCI)
+ static __initconst struct ssb_sprom bcm63xx_default_sprom = {
+ 	.revision		= 0x02,
+ 	.board_rev		= 0x17,
+@@ -43,7 +44,7 @@ static __initconst struct ssb_sprom bcm6
+ 	.boardflags_hi		= 0x0000,
+ };
+ 
+-
++#if defined (CONFIG_SSB_PCIHOST)
+ static __initconst u16 bcm4306_sprom[] = {
+ 	0x4001, 0x0000, 0x0453, 0x14e4, 0x4320, 0x8000, 0x0002, 0x0002,
+ 	0x1000, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff,
+@@ -158,10 +159,12 @@ static __initconst u16 bcm43222_sprom[]
+ 	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+ 	0xffff, 0xffff, 0xffff, 0x0008,
+ };
++#endif /* CONFIG_SSB_PCIHOST */
+ 
+ static struct ssb_sprom bcm63xx_sprom;
+ 
+-int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)
++#if defined(CONFIG_SSB_PCIHOST)
++int bcm63xx_get_fallback_ssb_sprom(struct ssb_bus *bus, struct ssb_sprom *out)
+ {
+ 	if (bus->bustype == SSB_BUSTYPE_PCI) {
+ 		memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom));
+@@ -171,6 +174,20 @@ int bcm63xx_get_fallback_sprom(struct ss
+ 		return -EINVAL;
+ 	}
+ }
++#endif
++
++#if defined(CONFIG_BCMA_HOST_PCI)
++int bcm63xx_get_fallback_bcma_sprom(struct bcma_bus *bus, struct ssb_sprom *out)
++{
++	if (bus->hosttype == BCMA_HOSTTYPE_PCI) {
++		memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom));
++		return 0;
++	} else {
++		printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n");
++		return -EINVAL;
++	}
++}
++#endif
+ 
+ /* FIXME: use lib_sprom after submission upstream */
+ 
+@@ -654,10 +671,11 @@ int __init bcm63xx_register_fallback_spr
+ {
+ 	int ret = 0;
+ 
+-#ifdef CONFIG_SSB_PCIHOST
++#if defined(CONFIG_SSB_PCIHOST) || defined(CONFIG_BCMA_HOST_PCI)
+ 	u16 size = 0;
+ 
+ 	switch (data->type) {
++#if defined(CONFIG_SSB_PCIHOST)
+ 	case SPROM_BCM4306:
+ 		memcpy(&template_sprom, &bcm4306_sprom, sizeof(bcm4306_sprom));
+ 		size = ARRAY_SIZE(bcm4306_sprom);
+@@ -678,6 +696,7 @@ int __init bcm63xx_register_fallback_spr
+ 		memcpy(&template_sprom, &bcm43222_sprom, sizeof(bcm43222_sprom));
+ 		size = ARRAY_SIZE(bcm43222_sprom);
+ 		break;
++#endif
+ 	case SPROM_DEFAULT:
+ 		memcpy(&bcm63xx_sprom, &bcm63xx_default_sprom,
+ 		       sizeof(bcm63xx_sprom));
+@@ -692,8 +711,19 @@ int __init bcm63xx_register_fallback_spr
+ 	memcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN);
+ 	memcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN);
+ 	memcpy(bcm63xx_sprom.et1mac, data->mac_addr, ETH_ALEN);
++#endif /* defined(CONFIG_SSB_PCIHOST) || defined(CONFIG_BCMA_HOST_PCI) */
++
++#if defined(CONFIG_SSB_PCIHOST)
++	ret = ssb_arch_register_fallback_sprom(&bcm63xx_get_fallback_ssb_sprom);
++	if (ret)
++		return ret;
++
++#endif
+ 
+-	ret = ssb_arch_register_fallback_sprom(&bcm63xx_get_fallback_sprom);
++#if defined(CONFIG_BCMA_HOST_PCI)
++	ret = bcma_arch_register_fallback_sprom(bcm63xx_get_fallback_bcma_sprom);
++	if (ret)
++		return ret;
+ #endif
+ 	return ret;
+ }

target/linux/brcm63xx/patches-4.9/363-MIPS-BCM63XX-add-BCMA-based-sprom-templates.patch

@@ -0,0 +1,303 @@
+From 27bf70e3fe797691b17df07ecbfaf9f5a4419f49 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Wed, 30 Jul 2014 23:14:27 +0200
+Subject: [PATCH 08/10] MIPS: BCM63XX: add BCMA based sprom templates
+
+Add fallback sproms for BCM4313, BCM43131, BCM43217, BCM43225, BCM43227,
+BCM43228, and BCM4331.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/sprom.c                          | 256 +++++++++++++++++++++
+ .../asm/mach-bcm63xx/bcm63xx_fallback_sprom.h      |   8 +
+ 2 files changed, 264 insertions(+)
+
+--- a/arch/mips/bcm63xx/sprom.c
++++ b/arch/mips/bcm63xx/sprom.c
+@@ -161,6 +161,226 @@ static __initconst u16 bcm43222_sprom[]
+ };
+ #endif /* CONFIG_SSB_PCIHOST */
+ 
++#if defined(CONFIG_BCMA_HOST_PCI)
++static __initconst u16 bcm4313_sprom[] = {
++	0x2801, 0x0000, 0x0510, 0x14e4, 0x0078, 0xedbe, 0x0000, 0x2bc4,
++	0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820,
++	0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100,
++	0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x4727, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x5372, 0x1215, 0x2a00, 0x0800, 0x0800, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0003, 0x0202,
++	0xffff, 0x0011, 0x007a, 0x0000, 0x0000, 0x0000, 0x0000, 0x0201,
++	0x0000, 0x7800, 0x7c0a, 0x0398, 0x0008, 0x0000, 0x0000, 0x0000,
++	0x0044, 0x1684, 0xfd0d, 0xff35, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0048, 0xfed2, 0x15d9, 0xfac6, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0008,
++};
++
++static __initconst u16 bcm43131_sprom[] = {
++	0x2801, 0x0000, 0x05f7, 0x14e4, 0x0070, 0xedbe, 0x1c00, 0x2bc4,
++	0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820,
++	0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100,
++	0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x43aa, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x5372, 0x1280, 0x0200, 0x0000, 0x8800, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0002, 0x0202,
++	0xffff, 0x0022, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0415,
++	0x0000, 0x7800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x204c, 0xfe96, 0x192c, 0xfa15, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x204c, 0xfe91, 0x1950, 0xfa0a, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x0000, 0x4444, 0x4444, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x4444, 0x4444, 0x4444, 0x4444, 0x6666, 0x6666, 0x6666,
++	0x6666, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0x0008,
++};
++
++static __initconst u16 bcm43217_sprom[] = {
++	0x2801, 0x0000, 0x05e9, 0x14e4, 0x0070, 0xedbe, 0x0000, 0x2bc4,
++	0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820,
++	0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100,
++	0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x43a9, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x5372, 0x1252, 0x0200, 0x0000, 0x9800, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0003, 0x0202,
++	0xffff, 0x0033, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0415,
++	0x0000, 0x7800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x204c, 0xfe96, 0x192c, 0xfa15, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x204c, 0xfe91, 0x1950, 0xfa0a, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x0000, 0x4444, 0x4444, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x4444, 0x4444, 0x4444, 0x4444, 0x6666, 0x6666, 0x6666,
++	0x6666, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0x7a08,
++};
++
++static __initconst u16 bcm43225_sprom[] = {
++	0x2801, 0x0000, 0x04da, 0x14e4, 0x0078, 0xedbe, 0x0000, 0x2bc4,
++	0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820,
++	0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100,
++	0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0x1008, 0x0005, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x4357, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x5372, 0x1200, 0x0200, 0x0000, 0x1000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x88ff, 0xffff, 0xffff, 0x0303, 0x0202,
++	0xffff, 0x0033, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0325,
++	0xffff, 0x7800, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x204e, 0xfead, 0x1611, 0xfa9a, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x204e, 0xfec1, 0x1674, 0xfab2, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x0000, 0x5555, 0x5555, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x5555, 0x7555, 0x5555, 0x7555, 0x5555, 0x7555, 0x5555,
++	0x7555, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0002, 0x0000, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0x0008,
++};
++
++static __initconst u16 bcm43227_sprom[] = {
++	0x2801, 0x0000, 0x0543, 0x14e4, 0x0070, 0xedbe, 0x0000, 0x2bc4,
++	0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820,
++	0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100,
++	0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x4358, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x5372, 0x1402, 0x0200, 0x0000, 0x0800, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0003, 0x0202,
++	0xffff, 0x0033, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0415,
++	0x0000, 0x7800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x204c, 0xff36, 0x16d2, 0xfaae, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x204c, 0xfeca, 0x159b, 0xfa80, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x0000, 0x4444, 0x4444, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x4444, 0x4444, 0x4444, 0x4444, 0x6666, 0x6666, 0x6666,
++	0x6666, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0x0008,
++};
++
++static __initconst u16 bcm43228_sprom[] = {
++	0x2801, 0x0000, 0x0011, 0x1028, 0x0070, 0xedbe, 0x0000, 0x2bc4,
++	0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820,
++	0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100,
++	0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x4359, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x5372, 0x1203, 0x0200, 0x0000, 0x0800, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0303, 0x0202,
++	0xffff, 0x0033, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0215,
++	0x0215, 0x7800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x204c, 0xff73, 0x1762, 0xfaa4, 0x3e34, 0x3434, 0xfea1, 0x154c,
++	0xfad0, 0xfea1, 0x144c, 0xfafb, 0xfe7b, 0x13fe, 0xfafc, 0x0000,
++	0x204c, 0xff41, 0x16a3, 0xfa8f, 0x3e34, 0x3434, 0xfe97, 0x1446,
++	0xfb05, 0xfe97, 0x1346, 0xfb32, 0xfeb9, 0x1516, 0xfaee, 0x0000,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x0000, 0x4444, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x4444, 0x4444, 0x4444, 0x4444, 0x8888, 0x8888, 0x8888,
++	0x8888, 0x0000, 0x0000, 0x0000, 0x0000, 0x3333, 0x3333, 0x3333,
++	0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0x3333, 0x3333, 0x3333,
++	0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0x3333, 0x3333, 0x3333,
++	0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xf008,
++};
++
++static __initconst u16 bcm4331_sprom[] = {
++	0x2801, 0x0000, 0x0525, 0x14e4, 0x0078, 0xedbe, 0x0000, 0x2bc4,
++	0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820,
++	0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100,
++	0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0x1010, 0x0005, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x4331, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x5372, 0x1104, 0x0200, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0xffff, 0x88ff, 0xffff, 0x0707, 0x0202,
++	0xff02, 0x0077, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0325,
++	0x0325, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x2048, 0xfe56, 0x16f2, 0xfa44, 0x3e3c, 0x3c3c, 0xfe77, 0x1657,
++	0xfa75, 0xffff, 0xffff, 0xffff, 0xfe76, 0x15da, 0xfa85, 0x0000,
++	0x2048, 0xfe5c, 0x16b5, 0xfa56, 0x3e3c, 0x3c3c, 0xfe7c, 0x169d,
++	0xfa6b, 0xffff, 0xffff, 0xffff, 0xfe7a, 0x1597, 0xfa97, 0x0000,
++	0x2048, 0xfe68, 0x1734, 0xfa46, 0x3e3c, 0x3c3c, 0xfe7f, 0x15e4,
++	0xfa94, 0xffff, 0xffff, 0xffff, 0xfe7d, 0x1582, 0xfa9f, 0x0000,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++	0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
++	0xffff, 0xffff, 0xffff, 0x0009,
++};
++
++#endif  /* CONFIG_BCMA_HOST_PCI */
++
+ static struct ssb_sprom bcm63xx_sprom;
+ 
+ #if defined(CONFIG_SSB_PCIHOST)
+@@ -697,6 +917,42 @@ int __init bcm63xx_register_fallback_spr
+ 		size = ARRAY_SIZE(bcm43222_sprom);
+ 		break;
+ #endif
++#if defined(CONFIG_BCMA_HOST_PCI)
++	case SPROM_BCM4313:
++		memcpy(&template_sprom, &bcm4313_sprom,
++                       sizeof(bcm4313_sprom));
++		size = ARRAY_SIZE(bcm4313_sprom);
++		break;
++	case SPROM_BCM43131:
++		memcpy(&template_sprom, &bcm43131_sprom,
++		       sizeof(bcm43131_sprom));
++		size = ARRAY_SIZE(bcm43131_sprom);
++		break;
++	case SPROM_BCM43217:
++		memcpy(&template_sprom, &bcm43217_sprom,
++		       sizeof(bcm43217_sprom));
++		size = ARRAY_SIZE(bcm43217_sprom);
++		break;
++	case SPROM_BCM43225:
++		memcpy(&template_sprom, &bcm43225_sprom,
++		       sizeof(bcm43225_sprom));
++		size = ARRAY_SIZE(bcm43225_sprom);
++		break;
++	case SPROM_BCM43227:
++		memcpy(&template_sprom, &bcm43227_sprom,
++		       sizeof(bcm43227_sprom));
++		size = ARRAY_SIZE(bcm43227_sprom);
++		break;
++	case SPROM_BCM43228:
++		memcpy(&template_sprom, &bcm43228_sprom,
++		       sizeof(bcm43228_sprom));
++		size = ARRAY_SIZE(bcm43228_sprom);
++		break;
++	case SPROM_BCM4331:
++		memcpy(&template_sprom, &bcm4331_sprom, sizeof(&bcm4331_sprom));
++		size = ARRAY_SIZE(bcm4331_sprom);
++		break;
++#endif
+ 	case SPROM_DEFAULT:
+ 		memcpy(&bcm63xx_sprom, &bcm63xx_default_sprom,
+ 		       sizeof(bcm63xx_sprom));
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h
+@@ -11,6 +11,14 @@ enum sprom_type {
+ 	SPROM_BCM4321,
+ 	SPROM_BCM4322,
+ 	SPROM_BCM43222,
++	/* BCMA based */
++	SPROM_BCM4313,
++	SPROM_BCM43131,
++	SPROM_BCM43217,
++	SPROM_BCM43225,
++	SPROM_BCM43227,
++	SPROM_BCM43228,
++	SPROM_BCM4331,
+ };
+ 
+ struct fallback_sprom_data {

target/linux/brcm63xx/patches-4.9/364-MIPS-BCM63XX-allow-board-files-to-provide-sprom-fixu.patch

@@ -0,0 +1,67 @@
+From 8575548b08e33c9ff4fd540abec09dd177e33682 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <[email protected]>
+Date: Thu, 31 Jul 2014 19:12:33 +0200
+Subject: [PATCH 09/10] MIPS: BCM63XX: allow board files to provide sprom
+ fixups
+
+Allow board_info files to supply fixups for the base sproms to adapt
+them to the actual used sprom contents in case they do not use the
+default ones.
+
+Signed-off-by: Jonas Gorski <[email protected]>
+---
+ arch/mips/bcm63xx/sprom.c                                  | 14 +++++++++++++-
+ .../mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h |  8 ++++++++
+ 2 files changed, 21 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/bcm63xx/sprom.c
++++ b/arch/mips/bcm63xx/sprom.c
+@@ -883,6 +883,14 @@ static int sprom_extract(struct ssb_spro
+ 	return 0;
+ }
+ 
++void sprom_apply_fixups(u16 *sprom, struct sprom_fixup *fixups, int n)
++{
++	unsigned int i;
++
++	for (i = 0; i < n; i++)
++		sprom[fixups[i].offset] = fixups[i].value;
++}
++
+ static __initdata u16 template_sprom[220];
+ #endif
+ 
+@@ -961,8 +969,12 @@ int __init bcm63xx_register_fallback_spr
+ 		return -EINVAL;
+ 	}
+ 
+-	if (size > 0)
++	if (size > 0) {
++		sprom_apply_fixups(template_sprom, data->board_fixups,
++				   data->num_board_fixups);
++
+ 		sprom_extract(&bcm63xx_sprom, template_sprom, size);
++	}
+ 
+ 	memcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN);
+ 	memcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN);
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h
+@@ -21,9 +21,17 @@ enum sprom_type {
+ 	SPROM_BCM4331,
+ };
+ 
++struct sprom_fixup {
++	u16 offset;
++	u16 value;
++};
++
+ struct fallback_sprom_data {
+ 	u8 mac_addr[ETH_ALEN];
+ 	enum sprom_type type;
++
++	struct sprom_fixup *board_fixups;
++	unsigned int num_board_fixups;
+ };
+ 
+ int bcm63xx_register_fallback_sprom(struct fallback_sprom_data *data);