at91: add kernel support for sama7g5 soc

Add kernel support for SAMA7G5 by back-porting mainline kernel patches.
Among SAMA7G5 features could be remembered:
- ARM Cortex-A7
- double data rate multi-port dynamic RAM controller supporting DDR2,
  DDR3, DDR3L, LPDDR2, LPDDR3 up to 533MHz
- peripherals for audio, video processing
- 1 gigabit + 1 megabit Ethernet controllers
- 6 CAN controllers
- trust zone support
- DVFS for CPU
- criptography IPs

Signed-off-by: Claudiu Beznea <[email protected]>

target/linux/at91/Makefile

@@ -8,7 +8,7 @@ ARCH:=arm
 BOARD:=at91
 BOARDNAME:=Microchip (Atmel AT91)
 FEATURES:=ext4 squashfs targz usb usbgadget ubifs
-SUBTARGETS:=sama5 sam9x
+SUBTARGETS:=sama7 sama5 sam9x
 
 KERNEL_PATCHVER:=5.10
 

target/linux/at91/patches-5.10/102-dt-bindings-clock-at91-add-sama7g5-pll-defines.patch

@@ -0,0 +1,72 @@
+From 44bb7c72cdd830f54fe18e730205f892d9cbfe39 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Thu, 19 Nov 2020 17:43:08 +0200
+Subject: [PATCH 102/247] dt-bindings: clock: at91: add sama7g5 pll defines
+
+Add SAMA7G5 specific PLL defines to be referenced in a phandle as a
+PMC_TYPE_CORE clock.
+
+Suggested-by: Claudiu Beznea <[email protected]>
+Signed-off-by: Eugen Hristev <[email protected]>
+[[email protected]: adapt comit message, adapt sama7g5.c]
+Signed-off-by: Claudiu Beznea <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/at91/sama7g5.c       |  6 +++---
+ include/dt-bindings/clock/at91.h | 10 ++++++++++
+ 2 files changed, 13 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
+index a092a940baa4..7ef7963126b6 100644
+--- a/drivers/clk/at91/sama7g5.c
++++ b/drivers/clk/at91/sama7g5.c
+@@ -182,13 +182,13 @@ static const struct {
+ 		  .p = "audiopll_fracck",
+ 		  .l = &pll_layout_divpmc,
+ 		  .t = PLL_TYPE_DIV,
+-		  .eid = PMC_I2S0_MUX, },
++		  .eid = PMC_AUDIOPMCPLL, },
+ 
+ 		{ .n = "audiopll_diviock",
+ 		  .p = "audiopll_fracck",
+ 		  .l = &pll_layout_divio,
+ 		  .t = PLL_TYPE_DIV,
+-		  .eid = PMC_I2S1_MUX, },
++		  .eid = PMC_AUDIOIOPLL, },
+ 	},
+ 
+ 	[PLL_ID_ETH] = {
+@@ -835,7 +835,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
+ 	if (IS_ERR(regmap))
+ 		return;
+ 
+-	sama7g5_pmc = pmc_data_allocate(PMC_I2S1_MUX + 1,
++	sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1,
+ 					nck(sama7g5_systemck),
+ 					nck(sama7g5_periphck),
+ 					nck(sama7g5_gck), 8);
+diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h
+index eba17106608b..fab313f62e8f 100644
+--- a/include/dt-bindings/clock/at91.h
++++ b/include/dt-bindings/clock/at91.h
+@@ -25,6 +25,16 @@
+ #define PMC_PLLBCK		8
+ #define PMC_AUDIOPLLCK		9
+ 
++/* SAMA7G5 */
++#define PMC_CPUPLL		(PMC_MAIN + 1)
++#define PMC_SYSPLL		(PMC_MAIN + 2)
++#define PMC_DDRPLL		(PMC_MAIN + 3)
++#define PMC_IMGPLL		(PMC_MAIN + 4)
++#define PMC_BAUDPLL		(PMC_MAIN + 5)
++#define PMC_AUDIOPMCPLL		(PMC_MAIN + 6)
++#define PMC_AUDIOIOPLL		(PMC_MAIN + 7)
++#define PMC_ETHPLL		(PMC_MAIN + 8)
++
+ #ifndef AT91_PMC_MOSCS
+ #define AT91_PMC_MOSCS		0		/* MOSCS Flag */
+ #define AT91_PMC_LOCKA		1		/* PLLA Lock */
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/103-clk-at91-sama7g5-allow-SYS-and-CPU-PLLs-to-be-export.patch

@@ -0,0 +1,46 @@
+From 55c14526f970805a6bf2ed4b820f062334375abe Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Thu, 19 Nov 2020 17:43:09 +0200
+Subject: [PATCH 103/247] clk: at91: sama7g5: allow SYS and CPU PLLs to be
+ exported and referenced in DT
+
+Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock
+from phandle in DT.
+
+Suggested-by: Claudiu Beznea <[email protected]>
+Signed-off-by: Eugen Hristev <[email protected]>
+[[email protected]: adapt commit message, add CPU PLL]
+Signed-off-by: Claudiu Beznea <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/at91/sama7g5.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
+index 7ef7963126b6..d3c3469d47d9 100644
+--- a/drivers/clk/at91/sama7g5.c
++++ b/drivers/clk/at91/sama7g5.c
+@@ -117,7 +117,8 @@ static const struct {
+ 		  .p = "cpupll_fracck",
+ 		  .l = &pll_layout_divpmc,
+ 		  .t = PLL_TYPE_DIV,
+-		  .c = 1, },
++		  .c = 1,
++		  .eid = PMC_CPUPLL, },
+ 	},
+ 
+ 	[PLL_ID_SYS] = {
+@@ -131,7 +132,8 @@ static const struct {
+ 		  .p = "syspll_fracck",
+ 		  .l = &pll_layout_divpmc,
+ 		  .t = PLL_TYPE_DIV,
+-		  .c = 1, },
++		  .c = 1,
++		  .eid = PMC_SYSPLL, },
+ 	},
+ 
+ 	[PLL_ID_DDR] = {
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/104-clk-at91-clk-master-add-5th-divisor-for-mck-master.patch

@@ -0,0 +1,49 @@
+From b2349278894bb381fa26a8717d3093d53f08fd36 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Thu, 19 Nov 2020 17:43:10 +0200
+Subject: [PATCH 104/247] clk: at91: clk-master: add 5th divisor for mck master
+
+clk-master can have 5 divisors with a field width of 3 bits
+on some products.
+
+Change the mask and number of divisors accordingly.
+
+Reported-by: Mihai Sain <[email protected]>
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Claudiu Beznea <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/at91/clk-master.c | 2 +-
+ drivers/clk/at91/pmc.h        | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
+index bd0d8a69a2cf..aafd003b30cf 100644
+--- a/drivers/clk/at91/clk-master.c
++++ b/drivers/clk/at91/clk-master.c
+@@ -15,7 +15,7 @@
+ #define MASTER_PRES_MASK	0x7
+ #define MASTER_PRES_MAX		MASTER_PRES_MASK
+ #define MASTER_DIV_SHIFT	8
+-#define MASTER_DIV_MASK		0x3
++#define MASTER_DIV_MASK		0x7
+ 
+ #define PMC_MCR			0x30
+ #define PMC_MCR_ID_MSK		GENMASK(3, 0)
+diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
+index 7b86affc6d7c..0a9364bde339 100644
+--- a/drivers/clk/at91/pmc.h
++++ b/drivers/clk/at91/pmc.h
+@@ -48,7 +48,7 @@ extern const struct clk_master_layout at91sam9x5_master_layout;
+ 
+ struct clk_master_characteristics {
+ 	struct clk_range output;
+-	u32 divisors[4];
++	u32 divisors[5];
+ 	u8 have_div3_pres;
+ };
+ 
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/105-clk-at91-sama7g5-add-5th-divisor-for-mck0-layout-and.patch

@@ -0,0 +1,41 @@
+From c41f013e13962dcc78239d5e4834214d44556cfb Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Thu, 19 Nov 2020 17:43:11 +0200
+Subject: [PATCH 105/247] clk: at91: sama7g5: add 5th divisor for mck0 layout
+ and characteristics
+
+This SoC has the 5th divisor for the mck0 master clock.
+Adapt the characteristics accordingly.
+
+Reported-by: Mihai Sain <[email protected]>
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Claudiu Beznea <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/at91/sama7g5.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
+index d3c3469d47d9..d685e22b2014 100644
+--- a/drivers/clk/at91/sama7g5.c
++++ b/drivers/clk/at91/sama7g5.c
+@@ -775,13 +775,13 @@ static const struct clk_pll_characteristics pll_characteristics = {
+ /* MCK0 characteristics. */
+ static const struct clk_master_characteristics mck0_characteristics = {
+ 	.output = { .min = 140000000, .max = 200000000 },
+-	.divisors = { 1, 2, 4, 3 },
++	.divisors = { 1, 2, 4, 3, 5 },
+ 	.have_div3_pres = 1,
+ };
+ 
+ /* MCK0 layout. */
+ static const struct clk_master_layout mck0_layout = {
+-	.mask = 0x373,
++	.mask = 0x773,
+ 	.pres_shift = 4,
+ 	.offset = 0x28,
+ };
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/106-clk-at91-clk-sam9x60-pll-allow-runtime-changes-for-p.patch

@@ -0,0 +1,521 @@
+From 6fe2927863de96edf35d8357712dbf83a489f556 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Thu, 19 Nov 2020 17:43:12 +0200
+Subject: [PATCH 106/247] clk: at91: clk-sam9x60-pll: allow runtime changes for
+ pll
+
+Allow runtime frequency changes for PLLs registered with proper flags.
+This is necessary for CPU PLL on SAMA7G5 which is used by DVFS.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/at91/clk-sam9x60-pll.c | 145 +++++++++++++++++++++++++----
+ drivers/clk/at91/pmc.h             |   4 +-
+ drivers/clk/at91/sam9x60.c         |  22 ++++-
+ drivers/clk/at91/sama7g5.c         |  67 +++++++++----
+ 4 files changed, 197 insertions(+), 41 deletions(-)
+
+diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
+index 5a9daa3643a7..1f52409475e9 100644
+--- a/drivers/clk/at91/clk-sam9x60-pll.c
++++ b/drivers/clk/at91/clk-sam9x60-pll.c
+@@ -229,6 +229,57 @@ static int sam9x60_frac_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ 	return sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true);
+ }
+ 
++static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate,
++					 unsigned long parent_rate)
++{
++	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
++	struct sam9x60_frac *frac = to_sam9x60_frac(core);
++	struct regmap *regmap = core->regmap;
++	unsigned long irqflags;
++	unsigned int val, cfrac, cmul;
++	long ret;
++
++	ret = sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true);
++	if (ret <= 0)
++		return ret;
++
++	spin_lock_irqsave(core->lock, irqflags);
++
++	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
++			   core->id);
++	regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
++	cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
++	cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;
++
++	if (cmul == frac->mul && cfrac == frac->frac)
++		goto unlock;
++
++	regmap_write(regmap, AT91_PMC_PLL_CTRL1,
++		     (frac->mul << core->layout->mul_shift) |
++		     (frac->frac << core->layout->frac_shift));
++
++	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
++			   AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
++			   AT91_PMC_PLL_UPDT_UPDATE | core->id);
++
++	regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
++			   AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL,
++			   AT91_PMC_PLL_CTRL0_ENLOCK |
++			   AT91_PMC_PLL_CTRL0_ENPLL);
++
++	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
++			   AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
++			   AT91_PMC_PLL_UPDT_UPDATE | core->id);
++
++	while (!sam9x60_pll_ready(regmap, core->id))
++		cpu_relax();
++
++unlock:
++	spin_unlock_irqrestore(core->lock, irqflags);
++
++	return ret;
++}
++
+ static const struct clk_ops sam9x60_frac_pll_ops = {
+ 	.prepare = sam9x60_frac_pll_prepare,
+ 	.unprepare = sam9x60_frac_pll_unprepare,
+@@ -238,6 +289,15 @@ static const struct clk_ops sam9x60_frac_pll_ops = {
+ 	.set_rate = sam9x60_frac_pll_set_rate,
+ };
+ 
++static const struct clk_ops sam9x60_frac_pll_ops_chg = {
++	.prepare = sam9x60_frac_pll_prepare,
++	.unprepare = sam9x60_frac_pll_unprepare,
++	.is_prepared = sam9x60_frac_pll_is_prepared,
++	.recalc_rate = sam9x60_frac_pll_recalc_rate,
++	.round_rate = sam9x60_frac_pll_round_rate,
++	.set_rate = sam9x60_frac_pll_set_rate_chg,
++};
++
+ static int sam9x60_div_pll_prepare(struct clk_hw *hw)
+ {
+ 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
+@@ -384,6 +444,44 @@ static int sam9x60_div_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ 	return 0;
+ }
+ 
++static int sam9x60_div_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate,
++					unsigned long parent_rate)
++{
++	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
++	struct sam9x60_div *div = to_sam9x60_div(core);
++	struct regmap *regmap = core->regmap;
++	unsigned long irqflags;
++	unsigned int val, cdiv;
++
++	div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;
++
++	spin_lock_irqsave(core->lock, irqflags);
++	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
++			   core->id);
++	regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
++	cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
++
++	/* Stop if nothing changed. */
++	if (cdiv == div->div)
++		goto unlock;
++
++	regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
++			   core->layout->div_mask,
++			   (div->div << core->layout->div_shift));
++
++	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
++			   AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
++			   AT91_PMC_PLL_UPDT_UPDATE | core->id);
++
++	while (!sam9x60_pll_ready(regmap, core->id))
++		cpu_relax();
++
++unlock:
++	spin_unlock_irqrestore(core->lock, irqflags);
++
++	return 0;
++}
++
+ static const struct clk_ops sam9x60_div_pll_ops = {
+ 	.prepare = sam9x60_div_pll_prepare,
+ 	.unprepare = sam9x60_div_pll_unprepare,
+@@ -393,17 +491,26 @@ static const struct clk_ops sam9x60_div_pll_ops = {
+ 	.set_rate = sam9x60_div_pll_set_rate,
+ };
+ 
++static const struct clk_ops sam9x60_div_pll_ops_chg = {
++	.prepare = sam9x60_div_pll_prepare,
++	.unprepare = sam9x60_div_pll_unprepare,
++	.is_prepared = sam9x60_div_pll_is_prepared,
++	.recalc_rate = sam9x60_div_pll_recalc_rate,
++	.round_rate = sam9x60_div_pll_round_rate,
++	.set_rate = sam9x60_div_pll_set_rate_chg,
++};
++
+ struct clk_hw * __init
+ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
+ 			      const char *name, const char *parent_name,
+ 			      struct clk_hw *parent_hw, u8 id,
+ 			      const struct clk_pll_characteristics *characteristics,
+-			      const struct clk_pll_layout *layout, bool critical)
++			      const struct clk_pll_layout *layout, u32 flags)
+ {
+ 	struct sam9x60_frac *frac;
+ 	struct clk_hw *hw;
+ 	struct clk_init_data init;
+-	unsigned long parent_rate, flags;
++	unsigned long parent_rate, irqflags;
+ 	unsigned int val;
+ 	int ret;
+ 
+@@ -417,10 +524,12 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
+ 	init.name = name;
+ 	init.parent_names = &parent_name;
+ 	init.num_parents = 1;
+-	init.ops = &sam9x60_frac_pll_ops;
+-	init.flags = CLK_SET_RATE_GATE;
+-	if (critical)
+-		init.flags |= CLK_IS_CRITICAL;
++	if (flags & CLK_SET_RATE_GATE)
++		init.ops = &sam9x60_frac_pll_ops;
++	else
++		init.ops = &sam9x60_frac_pll_ops_chg;
++
++	init.flags = flags;
+ 
+ 	frac->core.id = id;
+ 	frac->core.hw.init = &init;
+@@ -429,7 +538,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
+ 	frac->core.regmap = regmap;
+ 	frac->core.lock = lock;
+ 
+-	spin_lock_irqsave(frac->core.lock, flags);
++	spin_lock_irqsave(frac->core.lock, irqflags);
+ 	if (sam9x60_pll_ready(regmap, id)) {
+ 		regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
+ 				   AT91_PMC_PLL_UPDT_ID_MSK, id);
+@@ -457,7 +566,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
+ 			goto free;
+ 		}
+ 	}
+-	spin_unlock_irqrestore(frac->core.lock, flags);
++	spin_unlock_irqrestore(frac->core.lock, irqflags);
+ 
+ 	hw = &frac->core.hw;
+ 	ret = clk_hw_register(NULL, hw);
+@@ -469,7 +578,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
+ 	return hw;
+ 
+ free:
+-	spin_unlock_irqrestore(frac->core.lock, flags);
++	spin_unlock_irqrestore(frac->core.lock, irqflags);
+ 	kfree(frac);
+ 	return hw;
+ }
+@@ -478,12 +587,12 @@ struct clk_hw * __init
+ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
+ 			     const char *name, const char *parent_name, u8 id,
+ 			     const struct clk_pll_characteristics *characteristics,
+-			     const struct clk_pll_layout *layout, bool critical)
++			     const struct clk_pll_layout *layout, u32 flags)
+ {
+ 	struct sam9x60_div *div;
+ 	struct clk_hw *hw;
+ 	struct clk_init_data init;
+-	unsigned long flags;
++	unsigned long irqflags;
+ 	unsigned int val;
+ 	int ret;
+ 
+@@ -497,11 +606,11 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
+ 	init.name = name;
+ 	init.parent_names = &parent_name;
+ 	init.num_parents = 1;
+-	init.ops = &sam9x60_div_pll_ops;
+-	init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+-		     CLK_SET_RATE_PARENT;
+-	if (critical)
+-		init.flags |= CLK_IS_CRITICAL;
++	if (flags & CLK_SET_RATE_GATE)
++		init.ops = &sam9x60_div_pll_ops;
++	else
++		init.ops = &sam9x60_div_pll_ops_chg;
++	init.flags = flags;
+ 
+ 	div->core.id = id;
+ 	div->core.hw.init = &init;
+@@ -510,14 +619,14 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
+ 	div->core.regmap = regmap;
+ 	div->core.lock = lock;
+ 
+-	spin_lock_irqsave(div->core.lock, flags);
++	spin_lock_irqsave(div->core.lock, irqflags);
+ 
+ 	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
+ 			   AT91_PMC_PLL_UPDT_ID_MSK, id);
+ 	regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
+ 	div->div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, val);
+ 
+-	spin_unlock_irqrestore(div->core.lock, flags);
++	spin_unlock_irqrestore(div->core.lock, irqflags);
+ 
+ 	hw = &div->core.hw;
+ 	ret = clk_hw_register(NULL, hw);
+diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
+index 0a9364bde339..bedcd85ad750 100644
+--- a/drivers/clk/at91/pmc.h
++++ b/drivers/clk/at91/pmc.h
+@@ -190,14 +190,14 @@ struct clk_hw * __init
+ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
+ 			     const char *name, const char *parent_name, u8 id,
+ 			     const struct clk_pll_characteristics *characteristics,
+-			     const struct clk_pll_layout *layout, bool critical);
++			     const struct clk_pll_layout *layout, u32 flags);
+ 
+ struct clk_hw * __init
+ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
+ 			      const char *name, const char *parent_name,
+ 			      struct clk_hw *parent_hw, u8 id,
+ 			      const struct clk_pll_characteristics *characteristics,
+-			      const struct clk_pll_layout *layout, bool critical);
++			      const struct clk_pll_layout *layout, u32 flags);
+ 
+ struct clk_hw * __init
+ at91_clk_register_programmable(struct regmap *regmap, const char *name,
+diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
+index c8cbec5308f0..4cb0d31babf7 100644
+--- a/drivers/clk/at91/sam9x60.c
++++ b/drivers/clk/at91/sam9x60.c
+@@ -224,13 +224,24 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
+ 	hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracck",
+ 					   "mainck", sam9x60_pmc->chws[PMC_MAIN],
+ 					   0, &plla_characteristics,
+-					   &pll_frac_layout, true);
++					   &pll_frac_layout,
++					   /*
++					    * This feeds pllack_divck which
++					    * feeds CPU. It should not be
++					    * disabled.
++					    */
++					   CLK_IS_CRITICAL | CLK_SET_RATE_GATE);
+ 	if (IS_ERR(hw))
+ 		goto err_free;
+ 
+ 	hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "pllack_divck",
+ 					  "pllack_fracck", 0, &plla_characteristics,
+-					  &pll_div_layout, true);
++					  &pll_div_layout,
++					   /*
++					    * This feeds CPU. It should not
++					    * be disabled.
++					    */
++					  CLK_IS_CRITICAL | CLK_SET_RATE_GATE);
+ 	if (IS_ERR(hw))
+ 		goto err_free;
+ 
+@@ -239,13 +250,16 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
+ 	hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracck",
+ 					   "main_osc", main_osc_hw, 1,
+ 					   &upll_characteristics,
+-					   &pll_frac_layout, false);
++					   &pll_frac_layout, CLK_SET_RATE_GATE);
+ 	if (IS_ERR(hw))
+ 		goto err_free;
+ 
+ 	hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "upllck_divck",
+ 					  "upllck_fracck", 1, &upll_characteristics,
+-					  &pll_div_layout, false);
++					  &pll_div_layout,
++					  CLK_SET_RATE_GATE |
++					  CLK_SET_PARENT_GATE |
++					  CLK_SET_RATE_PARENT);
+ 	if (IS_ERR(hw))
+ 		goto err_free;
+ 
+diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
+index d685e22b2014..d7c2b731ad20 100644
+--- a/drivers/clk/at91/sama7g5.c
++++ b/drivers/clk/at91/sama7g5.c
+@@ -95,15 +95,15 @@ static const struct clk_pll_layout pll_layout_divio = {
+  * @p:		clock parent
+  * @l:		clock layout
+  * @t:		clock type
+- * @f:		true if clock is critical and cannot be disabled
++ * @f:		clock flags
+  * @eid:	export index in sama7g5->chws[] array
+  */
+ static const struct {
+ 	const char *n;
+ 	const char *p;
+ 	const struct clk_pll_layout *l;
++	unsigned long f;
+ 	u8 t;
+-	u8 c;
+ 	u8 eid;
+ } sama7g5_plls[][PLL_ID_MAX] = {
+ 	[PLL_ID_CPU] = {
+@@ -111,13 +111,18 @@ static const struct {
+ 		  .p = "mainck",
+ 		  .l = &pll_layout_frac,
+ 		  .t = PLL_TYPE_FRAC,
+-		  .c = 1, },
++		   /*
++		    * This feeds cpupll_divpmcck which feeds CPU. It should
++		    * not be disabled.
++		    */
++		  .f = CLK_IS_CRITICAL, },
+ 
+ 		{ .n = "cpupll_divpmcck",
+ 		  .p = "cpupll_fracck",
+ 		  .l = &pll_layout_divpmc,
+ 		  .t = PLL_TYPE_DIV,
+-		  .c = 1,
++		   /* This feeds CPU. It should not be disabled. */
++		  .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
+ 		  .eid = PMC_CPUPLL, },
+ 	},
+ 
+@@ -126,13 +131,22 @@ static const struct {
+ 		  .p = "mainck",
+ 		  .l = &pll_layout_frac,
+ 		  .t = PLL_TYPE_FRAC,
+-		  .c = 1, },
++		   /*
++		    * This feeds syspll_divpmcck which may feed critial parts
++		    * of the systems like timers. Therefore it should not be
++		    * disabled.
++		    */
++		  .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
+ 
+ 		{ .n = "syspll_divpmcck",
+ 		  .p = "syspll_fracck",
+ 		  .l = &pll_layout_divpmc,
+ 		  .t = PLL_TYPE_DIV,
+-		  .c = 1,
++		   /*
++		    * This may feed critial parts of the systems like timers.
++		    * Therefore it should not be disabled.
++		    */
++		  .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
+ 		  .eid = PMC_SYSPLL, },
+ 	},
+ 
+@@ -141,55 +155,71 @@ static const struct {
+ 		  .p = "mainck",
+ 		  .l = &pll_layout_frac,
+ 		  .t = PLL_TYPE_FRAC,
+-		  .c = 1, },
++		   /*
++		    * This feeds ddrpll_divpmcck which feeds DDR. It should not
++		    * be disabled.
++		    */
++		  .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
+ 
+ 		{ .n = "ddrpll_divpmcck",
+ 		  .p = "ddrpll_fracck",
+ 		  .l = &pll_layout_divpmc,
+ 		  .t = PLL_TYPE_DIV,
+-		  .c = 1, },
++		   /* This feeds DDR. It should not be disabled. */
++		  .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
+ 	},
+ 
+ 	[PLL_ID_IMG] = {
+ 		{ .n = "imgpll_fracck",
+ 		  .p = "mainck",
+ 		  .l = &pll_layout_frac,
+-		  .t = PLL_TYPE_FRAC, },
++		  .t = PLL_TYPE_FRAC,
++		  .f = CLK_SET_RATE_GATE, },
+ 
+ 		{ .n = "imgpll_divpmcck",
+ 		  .p = "imgpll_fracck",
+ 		  .l = &pll_layout_divpmc,
+-		  .t = PLL_TYPE_DIV, },
++		  .t = PLL_TYPE_DIV,
++		  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
++		       CLK_SET_RATE_PARENT, },
+ 	},
+ 
+ 	[PLL_ID_BAUD] = {
+ 		{ .n = "baudpll_fracck",
+ 		  .p = "mainck",
+ 		  .l = &pll_layout_frac,
+-		  .t = PLL_TYPE_FRAC, },
++		  .t = PLL_TYPE_FRAC,
++		  .f = CLK_SET_RATE_GATE, },
+ 
+ 		{ .n = "baudpll_divpmcck",
+ 		  .p = "baudpll_fracck",
+ 		  .l = &pll_layout_divpmc,
+-		  .t = PLL_TYPE_DIV, },
++		  .t = PLL_TYPE_DIV,
++		  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
++		       CLK_SET_RATE_PARENT, },
+ 	},
+ 
+ 	[PLL_ID_AUDIO] = {
+ 		{ .n = "audiopll_fracck",
+ 		  .p = "main_xtal",
+ 		  .l = &pll_layout_frac,
+-		  .t = PLL_TYPE_FRAC, },
++		  .t = PLL_TYPE_FRAC,
++		  .f = CLK_SET_RATE_GATE, },
+ 
+ 		{ .n = "audiopll_divpmcck",
+ 		  .p = "audiopll_fracck",
+ 		  .l = &pll_layout_divpmc,
+ 		  .t = PLL_TYPE_DIV,
++		  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
++		       CLK_SET_RATE_PARENT,
+ 		  .eid = PMC_AUDIOPMCPLL, },
+ 
+ 		{ .n = "audiopll_diviock",
+ 		  .p = "audiopll_fracck",
+ 		  .l = &pll_layout_divio,
+ 		  .t = PLL_TYPE_DIV,
++		  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
++		       CLK_SET_RATE_PARENT,
+ 		  .eid = PMC_AUDIOIOPLL, },
+ 	},
+ 
+@@ -197,12 +227,15 @@ static const struct {
+ 		{ .n = "ethpll_fracck",
+ 		  .p = "main_xtal",
+ 		  .l = &pll_layout_frac,
+-		  .t = PLL_TYPE_FRAC, },
++		  .t = PLL_TYPE_FRAC,
++		  .f = CLK_SET_RATE_GATE, },
+ 
+ 		{ .n = "ethpll_divpmcck",
+ 		  .p = "ethpll_fracck",
+ 		  .l = &pll_layout_divpmc,
+-		  .t = PLL_TYPE_DIV, },
++		  .t = PLL_TYPE_DIV,
++		  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
++		       CLK_SET_RATE_PARENT, },
+ 	},
+ };
+ 
+@@ -890,7 +923,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
+ 					sama7g5_plls[i][j].p, parent_hw, i,
+ 					&pll_characteristics,
+ 					sama7g5_plls[i][j].l,
+-					sama7g5_plls[i][j].c);
++					sama7g5_plls[i][j].f);
+ 				break;
+ 
+ 			case PLL_TYPE_DIV:
+@@ -899,7 +932,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
+ 					sama7g5_plls[i][j].p, i,
+ 					&pll_characteristics,
+ 					sama7g5_plls[i][j].l,
+-					sama7g5_plls[i][j].c);
++					sama7g5_plls[i][j].f);
+ 				break;
+ 
+ 			default:
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/107-clk-at91-sama7g5-remove-mck0-from-parent-list-of-oth.patch

@@ -0,0 +1,201 @@
+From 7cfe2dfe5ac7c72b904e4b59b240caa42721ee07 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Thu, 19 Nov 2020 17:43:13 +0200
+Subject: [PATCH 107/247] clk: at91: sama7g5: remove mck0 from parent list of
+ other clocks
+
+MCK0 is changed at runtime by DVFS. Due to this, since not all IPs
+are glitch free aware at MCK0 changes, remove MCK0 from parent list
+of other clocks (e.g. generic clock, programmable/system clock, MCKX).
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/at91/sama7g5.c | 55 ++++++++++++++++++--------------------
+ 1 file changed, 26 insertions(+), 29 deletions(-)
+
+diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
+index d7c2b731ad20..335e9c943c65 100644
+--- a/drivers/clk/at91/sama7g5.c
++++ b/drivers/clk/at91/sama7g5.c
+@@ -280,7 +280,7 @@ static const struct {
+ 	  .ep = { "syspll_divpmcck", "ddrpll_divpmcck", "imgpll_divpmcck", },
+ 	  .ep_mux_table = { 5, 6, 7, },
+ 	  .ep_count = 3,
+-	  .ep_chg_id = 6, },
++	  .ep_chg_id = 5, },
+ 
+ 	{ .n = "mck4",
+ 	  .id = 4,
+@@ -313,7 +313,7 @@ static const struct {
+ };
+ 
+ /* Mux table for programmable clocks. */
+-static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, };
++static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 5, 6, 7, 8, 9, 10, };
+ 
+ /**
+  * Peripheral clock description
+@@ -436,7 +436,7 @@ static const struct {
+ 	  .pp = { "audiopll_divpmcck", },
+ 	  .pp_mux_table = { 9, },
+ 	  .pp_count = 1,
+-	  .pp_chg_id = 4, },
++	  .pp_chg_id = 3, },
+ 
+ 	{ .n  = "csi_gclk",
+ 	  .id = 33,
+@@ -548,7 +548,7 @@ static const struct {
+ 	  .pp = { "ethpll_divpmcck", },
+ 	  .pp_mux_table = { 10, },
+ 	  .pp_count = 1,
+-	  .pp_chg_id = 4, },
++	  .pp_chg_id = 3, },
+ 
+ 	{ .n  = "gmac1_gclk",
+ 	  .id = 52,
+@@ -580,7 +580,7 @@ static const struct {
+ 	  .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
+ 	  .pp_mux_table = { 5, 9, },
+ 	  .pp_count = 2,
+-	  .pp_chg_id = 5, },
++	  .pp_chg_id = 4, },
+ 
+ 	{ .n  = "i2smcc1_gclk",
+ 	  .id = 58,
+@@ -588,7 +588,7 @@ static const struct {
+ 	  .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
+ 	  .pp_mux_table = { 5, 9, },
+ 	  .pp_count = 2,
+-	  .pp_chg_id = 5, },
++	  .pp_chg_id = 4, },
+ 
+ 	{ .n  = "mcan0_gclk",
+ 	  .id = 61,
+@@ -730,7 +730,7 @@ static const struct {
+ 	  .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
+ 	  .pp_mux_table = { 5, 8, },
+ 	  .pp_count = 2,
+-	  .pp_chg_id = 5, },
++	  .pp_chg_id = 4, },
+ 
+ 	{ .n  = "sdmmc1_gclk",
+ 	  .id = 81,
+@@ -738,7 +738,7 @@ static const struct {
+ 	  .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
+ 	  .pp_mux_table = { 5, 8, },
+ 	  .pp_count = 2,
+-	  .pp_chg_id = 5, },
++	  .pp_chg_id = 4, },
+ 
+ 	{ .n  = "sdmmc2_gclk",
+ 	  .id = 82,
+@@ -746,7 +746,7 @@ static const struct {
+ 	  .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
+ 	  .pp_mux_table = { 5, 8, },
+ 	  .pp_count = 2,
+-	  .pp_chg_id = 5, },
++	  .pp_chg_id = 4, },
+ 
+ 	{ .n  = "spdifrx_gclk",
+ 	  .id = 84,
+@@ -754,7 +754,7 @@ static const struct {
+ 	  .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
+ 	  .pp_mux_table = { 5, 9, },
+ 	  .pp_count = 2,
+-	  .pp_chg_id = 5, },
++	  .pp_chg_id = 4, },
+ 
+ 	{ .n = "spdiftx_gclk",
+ 	  .id = 85,
+@@ -762,7 +762,7 @@ static const struct {
+ 	  .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
+ 	  .pp_mux_table = { 5, 9, },
+ 	  .pp_count = 2,
+-	  .pp_chg_id = 5, },
++	  .pp_chg_id = 4, },
+ 
+ 	{ .n  = "tcb0_ch0_gclk",
+ 	  .id = 88,
+@@ -961,9 +961,8 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
+ 	parent_names[0] = md_slck_name;
+ 	parent_names[1] = td_slck_name;
+ 	parent_names[2] = "mainck";
+-	parent_names[3] = "mck0";
+ 	for (i = 0; i < ARRAY_SIZE(sama7g5_mckx); i++) {
+-		u8 num_parents = 4 + sama7g5_mckx[i].ep_count;
++		u8 num_parents = 3 + sama7g5_mckx[i].ep_count;
+ 		u32 *mux_table;
+ 
+ 		mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
+@@ -971,10 +970,10 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
+ 		if (!mux_table)
+ 			goto err_free;
+ 
+-		SAMA7G5_INIT_TABLE(mux_table, 4);
+-		SAMA7G5_FILL_TABLE(&mux_table[4], sama7g5_mckx[i].ep_mux_table,
++		SAMA7G5_INIT_TABLE(mux_table, 3);
++		SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table,
+ 				   sama7g5_mckx[i].ep_count);
+-		SAMA7G5_FILL_TABLE(&parent_names[4], sama7g5_mckx[i].ep,
++		SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_mckx[i].ep,
+ 				   sama7g5_mckx[i].ep_count);
+ 
+ 		hw = at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n,
+@@ -997,20 +996,19 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
+ 	parent_names[0] = md_slck_name;
+ 	parent_names[1] = td_slck_name;
+ 	parent_names[2] = "mainck";
+-	parent_names[3] = "mck0";
+-	parent_names[4] = "syspll_divpmcck";
+-	parent_names[5] = "ddrpll_divpmcck";
+-	parent_names[6] = "imgpll_divpmcck";
+-	parent_names[7] = "baudpll_divpmcck";
+-	parent_names[8] = "audiopll_divpmcck";
+-	parent_names[9] = "ethpll_divpmcck";
++	parent_names[3] = "syspll_divpmcck";
++	parent_names[4] = "ddrpll_divpmcck";
++	parent_names[5] = "imgpll_divpmcck";
++	parent_names[6] = "baudpll_divpmcck";
++	parent_names[7] = "audiopll_divpmcck";
++	parent_names[8] = "ethpll_divpmcck";
+ 	for (i = 0; i < 8; i++) {
+ 		char name[6];
+ 
+ 		snprintf(name, sizeof(name), "prog%d", i);
+ 
+ 		hw = at91_clk_register_programmable(regmap, name, parent_names,
+-						    10, i,
++						    9, i,
+ 						    &programmable_layout,
+ 						    sama7g5_prog_mux_table);
+ 		if (IS_ERR(hw))
+@@ -1047,9 +1045,8 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
+ 	parent_names[0] = md_slck_name;
+ 	parent_names[1] = td_slck_name;
+ 	parent_names[2] = "mainck";
+-	parent_names[3] = "mck0";
+ 	for (i = 0; i < ARRAY_SIZE(sama7g5_gck); i++) {
+-		u8 num_parents = 4 + sama7g5_gck[i].pp_count;
++		u8 num_parents = 3 + sama7g5_gck[i].pp_count;
+ 		u32 *mux_table;
+ 
+ 		mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
+@@ -1057,10 +1054,10 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
+ 		if (!mux_table)
+ 			goto err_free;
+ 
+-		SAMA7G5_INIT_TABLE(mux_table, 4);
+-		SAMA7G5_FILL_TABLE(&mux_table[4], sama7g5_gck[i].pp_mux_table,
++		SAMA7G5_INIT_TABLE(mux_table, 3);
++		SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table,
+ 				   sama7g5_gck[i].pp_count);
+-		SAMA7G5_FILL_TABLE(&parent_names[4], sama7g5_gck[i].pp,
++		SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_gck[i].pp,
+ 				   sama7g5_gck[i].pp_count);
+ 
+ 		hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/108-clk-at91-sama7g5-decrease-lower-limit-for-MCK0-rate.patch

@@ -0,0 +1,35 @@
+From 8b88f1e9918c173b24b43015cdb713cdde9e4d17 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Thu, 19 Nov 2020 17:43:14 +0200
+Subject: [PATCH 108/247] clk: at91: sama7g5: decrease lower limit for MCK0
+ rate
+
+On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and
+CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is
+also changed by DVFS to avoid over/under clocking of MCK0 consumers.
+The lower limit is changed to be able to set MCK0 accordingly by
+DVFS.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/at91/sama7g5.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
+index 335e9c943c65..29d9781e6712 100644
+--- a/drivers/clk/at91/sama7g5.c
++++ b/drivers/clk/at91/sama7g5.c
+@@ -807,7 +807,7 @@ static const struct clk_pll_characteristics pll_characteristics = {
+ 
+ /* MCK0 characteristics. */
+ static const struct clk_master_characteristics mck0_characteristics = {
+-	.output = { .min = 140000000, .max = 200000000 },
++	.output = { .min = 50000000, .max = 200000000 },
+ 	.divisors = { 1, 2, 4, 3, 5 },
+ 	.have_div3_pres = 1,
+ };
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/109-clk-at91-sama7g5-do-not-allow-cpu-pll-to-go-higher-t.patch

@@ -0,0 +1,226 @@
+From 943ed75a2a5ab08582d3bc8025e8111903698763 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Thu, 19 Nov 2020 17:43:15 +0200
+Subject: [PATCH 109/247] clk: at91: sama7g5: do not allow cpu pll to go higher
+ than 1GHz
+
+Since CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher
+than 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at
+1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/at91/sama7g5.c | 61 +++++++++++++++++++++++++++++---------
+ 1 file changed, 47 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
+index 29d9781e6712..e0c4d2eb9f59 100644
+--- a/drivers/clk/at91/sama7g5.c
++++ b/drivers/clk/at91/sama7g5.c
+@@ -89,11 +89,40 @@ static const struct clk_pll_layout pll_layout_divio = {
+ 	.endiv_shift	= 30,
+ };
+ 
++/*
++ * CPU PLL output range.
++ * Notice: The upper limit has been setup to 1000000002 due to hardware
++ * block which cannot output exactly 1GHz.
++ */
++static const struct clk_range cpu_pll_outputs[] = {
++	{ .min = 2343750, .max = 1000000002 },
++};
++
++/* PLL output range. */
++static const struct clk_range pll_outputs[] = {
++	{ .min = 2343750, .max = 1200000000 },
++};
++
++/* CPU PLL characteristics. */
++static const struct clk_pll_characteristics cpu_pll_characteristics = {
++	.input = { .min = 12000000, .max = 50000000 },
++	.num_output = ARRAY_SIZE(cpu_pll_outputs),
++	.output = cpu_pll_outputs,
++};
++
++/* PLL characteristics. */
++static const struct clk_pll_characteristics pll_characteristics = {
++	.input = { .min = 12000000, .max = 50000000 },
++	.num_output = ARRAY_SIZE(pll_outputs),
++	.output = pll_outputs,
++};
++
+ /**
+  * PLL clocks description
+  * @n:		clock name
+  * @p:		clock parent
+  * @l:		clock layout
++ * @c:		clock characteristics
+  * @t:		clock type
+  * @f:		clock flags
+  * @eid:	export index in sama7g5->chws[] array
+@@ -102,6 +131,7 @@ static const struct {
+ 	const char *n;
+ 	const char *p;
+ 	const struct clk_pll_layout *l;
++	const struct clk_pll_characteristics *c;
+ 	unsigned long f;
+ 	u8 t;
+ 	u8 eid;
+@@ -110,6 +140,7 @@ static const struct {
+ 		{ .n = "cpupll_fracck",
+ 		  .p = "mainck",
+ 		  .l = &pll_layout_frac,
++		  .c = &cpu_pll_characteristics,
+ 		  .t = PLL_TYPE_FRAC,
+ 		   /*
+ 		    * This feeds cpupll_divpmcck which feeds CPU. It should
+@@ -120,6 +151,7 @@ static const struct {
+ 		{ .n = "cpupll_divpmcck",
+ 		  .p = "cpupll_fracck",
+ 		  .l = &pll_layout_divpmc,
++		  .c = &cpu_pll_characteristics,
+ 		  .t = PLL_TYPE_DIV,
+ 		   /* This feeds CPU. It should not be disabled. */
+ 		  .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
+@@ -130,6 +162,7 @@ static const struct {
+ 		{ .n = "syspll_fracck",
+ 		  .p = "mainck",
+ 		  .l = &pll_layout_frac,
++		  .c = &pll_characteristics,
+ 		  .t = PLL_TYPE_FRAC,
+ 		   /*
+ 		    * This feeds syspll_divpmcck which may feed critial parts
+@@ -141,6 +174,7 @@ static const struct {
+ 		{ .n = "syspll_divpmcck",
+ 		  .p = "syspll_fracck",
+ 		  .l = &pll_layout_divpmc,
++		  .c = &pll_characteristics,
+ 		  .t = PLL_TYPE_DIV,
+ 		   /*
+ 		    * This may feed critial parts of the systems like timers.
+@@ -154,6 +188,7 @@ static const struct {
+ 		{ .n = "ddrpll_fracck",
+ 		  .p = "mainck",
+ 		  .l = &pll_layout_frac,
++		  .c = &pll_characteristics,
+ 		  .t = PLL_TYPE_FRAC,
+ 		   /*
+ 		    * This feeds ddrpll_divpmcck which feeds DDR. It should not
+@@ -164,6 +199,7 @@ static const struct {
+ 		{ .n = "ddrpll_divpmcck",
+ 		  .p = "ddrpll_fracck",
+ 		  .l = &pll_layout_divpmc,
++		  .c = &pll_characteristics,
+ 		  .t = PLL_TYPE_DIV,
+ 		   /* This feeds DDR. It should not be disabled. */
+ 		  .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
+@@ -173,12 +209,14 @@ static const struct {
+ 		{ .n = "imgpll_fracck",
+ 		  .p = "mainck",
+ 		  .l = &pll_layout_frac,
++		  .c = &pll_characteristics,
+ 		  .t = PLL_TYPE_FRAC,
+ 		  .f = CLK_SET_RATE_GATE, },
+ 
+ 		{ .n = "imgpll_divpmcck",
+ 		  .p = "imgpll_fracck",
+ 		  .l = &pll_layout_divpmc,
++		  .c = &pll_characteristics,
+ 		  .t = PLL_TYPE_DIV,
+ 		  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+ 		       CLK_SET_RATE_PARENT, },
+@@ -188,12 +226,14 @@ static const struct {
+ 		{ .n = "baudpll_fracck",
+ 		  .p = "mainck",
+ 		  .l = &pll_layout_frac,
++		  .c = &pll_characteristics,
+ 		  .t = PLL_TYPE_FRAC,
+ 		  .f = CLK_SET_RATE_GATE, },
+ 
+ 		{ .n = "baudpll_divpmcck",
+ 		  .p = "baudpll_fracck",
+ 		  .l = &pll_layout_divpmc,
++		  .c = &pll_characteristics,
+ 		  .t = PLL_TYPE_DIV,
+ 		  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+ 		       CLK_SET_RATE_PARENT, },
+@@ -203,12 +243,14 @@ static const struct {
+ 		{ .n = "audiopll_fracck",
+ 		  .p = "main_xtal",
+ 		  .l = &pll_layout_frac,
++		  .c = &pll_characteristics,
+ 		  .t = PLL_TYPE_FRAC,
+ 		  .f = CLK_SET_RATE_GATE, },
+ 
+ 		{ .n = "audiopll_divpmcck",
+ 		  .p = "audiopll_fracck",
+ 		  .l = &pll_layout_divpmc,
++		  .c = &pll_characteristics,
+ 		  .t = PLL_TYPE_DIV,
+ 		  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+ 		       CLK_SET_RATE_PARENT,
+@@ -217,6 +259,7 @@ static const struct {
+ 		{ .n = "audiopll_diviock",
+ 		  .p = "audiopll_fracck",
+ 		  .l = &pll_layout_divio,
++		  .c = &pll_characteristics,
+ 		  .t = PLL_TYPE_DIV,
+ 		  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+ 		       CLK_SET_RATE_PARENT,
+@@ -227,12 +270,14 @@ static const struct {
+ 		{ .n = "ethpll_fracck",
+ 		  .p = "main_xtal",
+ 		  .l = &pll_layout_frac,
++		  .c = &pll_characteristics,
+ 		  .t = PLL_TYPE_FRAC,
+ 		  .f = CLK_SET_RATE_GATE, },
+ 
+ 		{ .n = "ethpll_divpmcck",
+ 		  .p = "ethpll_fracck",
+ 		  .l = &pll_layout_divpmc,
++		  .c = &pll_characteristics,
+ 		  .t = PLL_TYPE_DIV,
+ 		  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+ 		       CLK_SET_RATE_PARENT, },
+@@ -793,18 +838,6 @@ static const struct {
+ 	  .pp_chg_id = INT_MIN, },
+ };
+ 
+-/* PLL output range. */
+-static const struct clk_range pll_outputs[] = {
+-	{ .min = 2343750, .max = 1200000000 },
+-};
+-
+-/* PLL characteristics. */
+-static const struct clk_pll_characteristics pll_characteristics = {
+-	.input = { .min = 12000000, .max = 50000000 },
+-	.num_output = ARRAY_SIZE(pll_outputs),
+-	.output = pll_outputs,
+-};
+-
+ /* MCK0 characteristics. */
+ static const struct clk_master_characteristics mck0_characteristics = {
+ 	.output = { .min = 50000000, .max = 200000000 },
+@@ -921,7 +954,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
+ 				hw = sam9x60_clk_register_frac_pll(regmap,
+ 					&pmc_pll_lock, sama7g5_plls[i][j].n,
+ 					sama7g5_plls[i][j].p, parent_hw, i,
+-					&pll_characteristics,
++					sama7g5_plls[i][j].c,
+ 					sama7g5_plls[i][j].l,
+ 					sama7g5_plls[i][j].f);
+ 				break;
+@@ -930,7 +963,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
+ 				hw = sam9x60_clk_register_div_pll(regmap,
+ 					&pmc_pll_lock, sama7g5_plls[i][j].n,
+ 					sama7g5_plls[i][j].p, i,
+-					&pll_characteristics,
++					sama7g5_plls[i][j].c,
+ 					sama7g5_plls[i][j].l,
+ 					sama7g5_plls[i][j].f);
+ 				break;
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/110-clk-at91-clk-master-re-factor-master-clock.patch

@@ -0,0 +1,1261 @@
+From 9109b768fe65994547ef464b13e508b22de3e89b Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Thu, 19 Nov 2020 17:43:16 +0200
+Subject: [PATCH 110/247] clk: at91: clk-master: re-factor master clock
+
+Re-factor master clock driver by splitting it into 2 clocks: prescaller
+and divider clocks. Based on registered clock flags the prescaler's rate
+could be changed at runtime. This is necessary for platforms supporting
+DVFS (e.g. SAMA7G5) where master clock could be changed at run-time.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/at91/at91rm9200.c  |  21 ++-
+ drivers/clk/at91/at91sam9260.c |  26 ++-
+ drivers/clk/at91/at91sam9g45.c |  32 +++-
+ drivers/clk/at91/at91sam9n12.c |  36 ++--
+ drivers/clk/at91/at91sam9rl.c  |  23 ++-
+ drivers/clk/at91/at91sam9x5.c  |  28 ++-
+ drivers/clk/at91/clk-master.c  | 335 ++++++++++++++++++++++++++++-----
+ drivers/clk/at91/dt-compat.c   |  15 +-
+ drivers/clk/at91/pmc.h         |  16 +-
+ drivers/clk/at91/sam9x60.c     |  23 ++-
+ drivers/clk/at91/sama5d2.c     |  42 +++--
+ drivers/clk/at91/sama5d3.c     |  38 ++--
+ drivers/clk/at91/sama5d4.c     |  40 ++--
+ drivers/clk/at91/sama7g5.c     |  13 +-
+ 14 files changed, 542 insertions(+), 146 deletions(-)
+
+diff --git a/drivers/clk/at91/at91rm9200.c b/drivers/clk/at91/at91rm9200.c
+index 2c3d8e6ca63c..0fad1009f315 100644
+--- a/drivers/clk/at91/at91rm9200.c
++++ b/drivers/clk/at91/at91rm9200.c
+@@ -7,6 +7,8 @@
+ 
+ #include "pmc.h"
+ 
++static DEFINE_SPINLOCK(rm9200_mck_lock);
++
+ struct sck {
+ 	char *n;
+ 	char *p;
+@@ -137,9 +139,20 @@ static void __init at91rm9200_pmc_setup(struct device_node *np)
+ 	parent_names[1] = "mainck";
+ 	parent_names[2] = "pllack";
+ 	parent_names[3] = "pllbck";
+-	hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
+-				      &at91rm9200_master_layout,
+-				      &rm9200_mck_characteristics);
++	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
++					   parent_names,
++					   &at91rm9200_master_layout,
++					   &rm9200_mck_characteristics,
++					   &rm9200_mck_lock, CLK_SET_RATE_GATE,
++					   INT_MIN);
++	if (IS_ERR(hw))
++		goto err_free;
++
++	hw = at91_clk_register_master_div(regmap, "masterck_div",
++					  "masterck_pres",
++					  &at91rm9200_master_layout,
++					  &rm9200_mck_characteristics,
++					  &rm9200_mck_lock, CLK_SET_RATE_GATE);
+ 	if (IS_ERR(hw))
+ 		goto err_free;
+ 
+@@ -181,7 +194,7 @@ static void __init at91rm9200_pmc_setup(struct device_node *np)
+ 	for (i = 0; i < ARRAY_SIZE(at91rm9200_periphck); i++) {
+ 		hw = at91_clk_register_peripheral(regmap,
+ 						  at91rm9200_periphck[i].n,
+-						  "masterck",
++						  "masterck_div",
+ 						  at91rm9200_periphck[i].id);
+ 		if (IS_ERR(hw))
+ 			goto err_free;
+diff --git a/drivers/clk/at91/at91sam9260.c b/drivers/clk/at91/at91sam9260.c
+index bb81ff731ad8..ceb5495f723a 100644
+--- a/drivers/clk/at91/at91sam9260.c
++++ b/drivers/clk/at91/at91sam9260.c
+@@ -32,6 +32,8 @@ struct at91sam926x_data {
+ 	bool has_slck;
+ };
+ 
++static DEFINE_SPINLOCK(at91sam9260_mck_lock);
++
+ static const struct clk_master_characteristics sam9260_mck_characteristics = {
+ 	.output = { .min = 0, .max = 105000000 },
+ 	.divisors = { 1, 2, 4, 0 },
+@@ -218,8 +220,8 @@ static const struct sck at91sam9261_systemck[] = {
+ 	{ .n = "pck1",  .p = "prog1",    .id = 9 },
+ 	{ .n = "pck2",  .p = "prog2",    .id = 10 },
+ 	{ .n = "pck3",  .p = "prog3",    .id = 11 },
+-	{ .n = "hclk0", .p = "masterck", .id = 16 },
+-	{ .n = "hclk1", .p = "masterck", .id = 17 },
++	{ .n = "hclk0", .p = "masterck_div", .id = 16 },
++	{ .n = "hclk1", .p = "masterck_div", .id = 17 },
+ };
+ 
+ static const struct pck at91sam9261_periphck[] = {
+@@ -413,9 +415,21 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
+ 	parent_names[1] = "mainck";
+ 	parent_names[2] = "pllack";
+ 	parent_names[3] = "pllbck";
+-	hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
+-				      &at91rm9200_master_layout,
+-				      data->mck_characteristics);
++	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
++					   parent_names,
++					   &at91rm9200_master_layout,
++					   data->mck_characteristics,
++					   &at91sam9260_mck_lock,
++					   CLK_SET_RATE_GATE, INT_MIN);
++	if (IS_ERR(hw))
++		goto err_free;
++
++	hw = at91_clk_register_master_div(regmap, "masterck_div",
++					  "masterck_pres",
++					  &at91rm9200_master_layout,
++					  data->mck_characteristics,
++					  &at91sam9260_mck_lock,
++					  CLK_SET_RATE_GATE);
+ 	if (IS_ERR(hw))
+ 		goto err_free;
+ 
+@@ -457,7 +471,7 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
+ 	for (i = 0; i < data->num_pck; i++) {
+ 		hw = at91_clk_register_peripheral(regmap,
+ 						  data->pck[i].n,
+-						  "masterck",
++						  "masterck_div",
+ 						  data->pck[i].id);
+ 		if (IS_ERR(hw))
+ 			goto err_free;
+diff --git a/drivers/clk/at91/at91sam9g45.c b/drivers/clk/at91/at91sam9g45.c
+index cb4a406ed15d..0214333dedd3 100644
+--- a/drivers/clk/at91/at91sam9g45.c
++++ b/drivers/clk/at91/at91sam9g45.c
+@@ -7,6 +7,8 @@
+ 
+ #include "pmc.h"
+ 
++static DEFINE_SPINLOCK(at91sam9g45_mck_lock);
++
+ static const struct clk_master_characteristics mck_characteristics = {
+ 	.output = { .min = 0, .max = 133333333 },
+ 	.divisors = { 1, 2, 4, 3 },
+@@ -40,10 +42,10 @@ static const struct {
+ 	char *p;
+ 	u8 id;
+ } at91sam9g45_systemck[] = {
+-	{ .n = "ddrck", .p = "masterck", .id = 2 },
+-	{ .n = "uhpck", .p = "usbck",    .id = 6 },
+-	{ .n = "pck0",  .p = "prog0",    .id = 8 },
+-	{ .n = "pck1",  .p = "prog1",    .id = 9 },
++	{ .n = "ddrck", .p = "masterck_div", .id = 2 },
++	{ .n = "uhpck", .p = "usbck",        .id = 6 },
++	{ .n = "pck0",  .p = "prog0",        .id = 8 },
++	{ .n = "pck1",  .p = "prog1",        .id = 9 },
+ };
+ 
+ struct pck {
+@@ -148,9 +150,21 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np)
+ 	parent_names[1] = "mainck";
+ 	parent_names[2] = "plladivck";
+ 	parent_names[3] = "utmick";
+-	hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
+-				      &at91rm9200_master_layout,
+-				      &mck_characteristics);
++	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
++					   parent_names,
++					   &at91rm9200_master_layout,
++					   &mck_characteristics,
++					   &at91sam9g45_mck_lock,
++					   CLK_SET_RATE_GATE, INT_MIN);
++	if (IS_ERR(hw))
++		goto err_free;
++
++	hw = at91_clk_register_master_div(regmap, "masterck_div",
++					  "masterck_pres",
++					  &at91rm9200_master_layout,
++					  &mck_characteristics,
++					  &at91sam9g45_mck_lock,
++					  CLK_SET_RATE_GATE);
+ 	if (IS_ERR(hw))
+ 		goto err_free;
+ 
+@@ -166,7 +180,7 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np)
+ 	parent_names[1] = "mainck";
+ 	parent_names[2] = "plladivck";
+ 	parent_names[3] = "utmick";
+-	parent_names[4] = "masterck";
++	parent_names[4] = "masterck_div";
+ 	for (i = 0; i < 2; i++) {
+ 		char name[6];
+ 
+@@ -195,7 +209,7 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np)
+ 	for (i = 0; i < ARRAY_SIZE(at91sam9g45_periphck); i++) {
+ 		hw = at91_clk_register_peripheral(regmap,
+ 						  at91sam9g45_periphck[i].n,
+-						  "masterck",
++						  "masterck_div",
+ 						  at91sam9g45_periphck[i].id);
+ 		if (IS_ERR(hw))
+ 			goto err_free;
+diff --git a/drivers/clk/at91/at91sam9n12.c b/drivers/clk/at91/at91sam9n12.c
+index 93f7eb216122..f9db5316a7f1 100644
+--- a/drivers/clk/at91/at91sam9n12.c
++++ b/drivers/clk/at91/at91sam9n12.c
+@@ -7,6 +7,8 @@
+ 
+ #include "pmc.h"
+ 
++static DEFINE_SPINLOCK(at91sam9n12_mck_lock);
++
+ static const struct clk_master_characteristics mck_characteristics = {
+ 	.output = { .min = 0, .max = 133333333 },
+ 	.divisors = { 1, 2, 4, 3 },
+@@ -54,12 +56,12 @@ static const struct {
+ 	char *p;
+ 	u8 id;
+ } at91sam9n12_systemck[] = {
+-	{ .n = "ddrck", .p = "masterck", .id = 2 },
+-	{ .n = "lcdck", .p = "masterck", .id = 3 },
+-	{ .n = "uhpck", .p = "usbck",    .id = 6 },
+-	{ .n = "udpck", .p = "usbck",    .id = 7 },
+-	{ .n = "pck0",  .p = "prog0",    .id = 8 },
+-	{ .n = "pck1",  .p = "prog1",    .id = 9 },
++	{ .n = "ddrck", .p = "masterck_div", .id = 2 },
++	{ .n = "lcdck", .p = "masterck_div", .id = 3 },
++	{ .n = "uhpck", .p = "usbck",        .id = 6 },
++	{ .n = "udpck", .p = "usbck",        .id = 7 },
++	{ .n = "pck0",  .p = "prog0",        .id = 8 },
++	{ .n = "pck1",  .p = "prog1",        .id = 9 },
+ };
+ 
+ static const struct clk_pcr_layout at91sam9n12_pcr_layout = {
+@@ -175,9 +177,21 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np)
+ 	parent_names[1] = "mainck";
+ 	parent_names[2] = "plladivck";
+ 	parent_names[3] = "pllbck";
+-	hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
+-				      &at91sam9x5_master_layout,
+-				      &mck_characteristics);
++	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
++					   parent_names,
++					   &at91sam9x5_master_layout,
++					   &mck_characteristics,
++					   &at91sam9n12_mck_lock,
++					   CLK_SET_RATE_GATE, INT_MIN);
++	if (IS_ERR(hw))
++		goto err_free;
++
++	hw = at91_clk_register_master_div(regmap, "masterck_div",
++					  "masterck_pres",
++					  &at91sam9x5_master_layout,
++					  &mck_characteristics,
++					  &at91sam9n12_mck_lock,
++					  CLK_SET_RATE_GATE);
+ 	if (IS_ERR(hw))
+ 		goto err_free;
+ 
+@@ -191,7 +205,7 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np)
+ 	parent_names[1] = "mainck";
+ 	parent_names[2] = "plladivck";
+ 	parent_names[3] = "pllbck";
+-	parent_names[4] = "masterck";
++	parent_names[4] = "masterck_div";
+ 	for (i = 0; i < 2; i++) {
+ 		char name[6];
+ 
+@@ -221,7 +235,7 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np)
+ 		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
+ 							 &at91sam9n12_pcr_layout,
+ 							 at91sam9n12_periphck[i].n,
+-							 "masterck",
++							 "masterck_div",
+ 							 at91sam9n12_periphck[i].id,
+ 							 &range, INT_MIN);
+ 		if (IS_ERR(hw))
+diff --git a/drivers/clk/at91/at91sam9rl.c b/drivers/clk/at91/at91sam9rl.c
+index a343eb69bb35..66736e03cfef 100644
+--- a/drivers/clk/at91/at91sam9rl.c
++++ b/drivers/clk/at91/at91sam9rl.c
+@@ -7,6 +7,8 @@
+ 
+ #include "pmc.h"
+ 
++static DEFINE_SPINLOCK(sam9rl_mck_lock);
++
+ static const struct clk_master_characteristics sam9rl_mck_characteristics = {
+ 	.output = { .min = 0, .max = 94000000 },
+ 	.divisors = { 1, 2, 4, 0 },
+@@ -117,9 +119,20 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np)
+ 	parent_names[1] = "mainck";
+ 	parent_names[2] = "pllack";
+ 	parent_names[3] = "utmick";
+-	hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
+-				      &at91rm9200_master_layout,
+-				      &sam9rl_mck_characteristics);
++	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
++					   parent_names,
++					   &at91rm9200_master_layout,
++					   &sam9rl_mck_characteristics,
++					   &sam9rl_mck_lock, CLK_SET_RATE_GATE,
++					   INT_MIN);
++	if (IS_ERR(hw))
++		goto err_free;
++
++	hw = at91_clk_register_master_div(regmap, "masterck_div",
++					  "masterck_pres",
++					  &at91rm9200_master_layout,
++					  &sam9rl_mck_characteristics,
++					  &sam9rl_mck_lock, CLK_SET_RATE_GATE);
+ 	if (IS_ERR(hw))
+ 		goto err_free;
+ 
+@@ -129,7 +142,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np)
+ 	parent_names[1] = "mainck";
+ 	parent_names[2] = "pllack";
+ 	parent_names[3] = "utmick";
+-	parent_names[4] = "masterck";
++	parent_names[4] = "masterck_div";
+ 	for (i = 0; i < 2; i++) {
+ 		char name[6];
+ 
+@@ -158,7 +171,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np)
+ 	for (i = 0; i < ARRAY_SIZE(at91sam9rl_periphck); i++) {
+ 		hw = at91_clk_register_peripheral(regmap,
+ 						  at91sam9rl_periphck[i].n,
+-						  "masterck",
++						  "masterck_div",
+ 						  at91sam9rl_periphck[i].id);
+ 		if (IS_ERR(hw))
+ 			goto err_free;
+diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c
+index 22b9aad9efb8..79b9d3667228 100644
+--- a/drivers/clk/at91/at91sam9x5.c
++++ b/drivers/clk/at91/at91sam9x5.c
+@@ -7,6 +7,8 @@
+ 
+ #include "pmc.h"
+ 
++static DEFINE_SPINLOCK(mck_lock);
++
+ static const struct clk_master_characteristics mck_characteristics = {
+ 	.output = { .min = 0, .max = 133333333 },
+ 	.divisors = { 1, 2, 4, 3 },
+@@ -41,7 +43,7 @@ static const struct {
+ 	char *p;
+ 	u8 id;
+ } at91sam9x5_systemck[] = {
+-	{ .n = "ddrck", .p = "masterck", .id = 2 },
++	{ .n = "ddrck", .p = "masterck_div", .id = 2 },
+ 	{ .n = "smdck", .p = "smdclk",   .id = 4 },
+ 	{ .n = "uhpck", .p = "usbck",    .id = 6 },
+ 	{ .n = "udpck", .p = "usbck",    .id = 7 },
+@@ -196,9 +198,19 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
+ 	parent_names[1] = "mainck";
+ 	parent_names[2] = "plladivck";
+ 	parent_names[3] = "utmick";
+-	hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
+-				      &at91sam9x5_master_layout,
+-				      &mck_characteristics);
++	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
++					   parent_names,
++					   &at91sam9x5_master_layout,
++					   &mck_characteristics, &mck_lock,
++					   CLK_SET_RATE_GATE, INT_MIN);
++	if (IS_ERR(hw))
++		goto err_free;
++
++	hw = at91_clk_register_master_div(regmap, "masterck_div",
++					  "masterck_pres",
++					  &at91sam9x5_master_layout,
++					  &mck_characteristics, &mck_lock,
++					  CLK_SET_RATE_GATE);
+ 	if (IS_ERR(hw))
+ 		goto err_free;
+ 
+@@ -218,7 +230,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
+ 	parent_names[1] = "mainck";
+ 	parent_names[2] = "plladivck";
+ 	parent_names[3] = "utmick";
+-	parent_names[4] = "masterck";
++	parent_names[4] = "masterck_div";
+ 	for (i = 0; i < 2; i++) {
+ 		char name[6];
+ 
+@@ -245,7 +257,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
+ 	}
+ 
+ 	if (has_lcdck) {
+-		hw = at91_clk_register_system(regmap, "lcdck", "masterck", 3);
++		hw = at91_clk_register_system(regmap, "lcdck", "masterck_div", 3);
+ 		if (IS_ERR(hw))
+ 			goto err_free;
+ 
+@@ -256,7 +268,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
+ 		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
+ 							 &at91sam9x5_pcr_layout,
+ 							 at91sam9x5_periphck[i].n,
+-							 "masterck",
++							 "masterck_div",
+ 							 at91sam9x5_periphck[i].id,
+ 							 &range, INT_MIN);
+ 		if (IS_ERR(hw))
+@@ -269,7 +281,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
+ 		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
+ 							 &at91sam9x5_pcr_layout,
+ 							 extra_pcks[i].n,
+-							 "masterck",
++							 "masterck_div",
+ 							 extra_pcks[i].id,
+ 							 &range, INT_MIN);
+ 		if (IS_ERR(hw))
+diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
+index aafd003b30cf..a80427980bf7 100644
+--- a/drivers/clk/at91/clk-master.c
++++ b/drivers/clk/at91/clk-master.c
+@@ -58,83 +58,309 @@ static inline bool clk_master_ready(struct clk_master *master)
+ static int clk_master_prepare(struct clk_hw *hw)
+ {
+ 	struct clk_master *master = to_clk_master(hw);
++	unsigned long flags;
++
++	spin_lock_irqsave(master->lock, flags);
+ 
+ 	while (!clk_master_ready(master))
+ 		cpu_relax();
+ 
++	spin_unlock_irqrestore(master->lock, flags);
++
+ 	return 0;
+ }
+ 
+ static int clk_master_is_prepared(struct clk_hw *hw)
+ {
+ 	struct clk_master *master = to_clk_master(hw);
++	unsigned long flags;
++	bool status;
+ 
+-	return clk_master_ready(master);
++	spin_lock_irqsave(master->lock, flags);
++	status = clk_master_ready(master);
++	spin_unlock_irqrestore(master->lock, flags);
++
++	return status;
+ }
+ 
+-static unsigned long clk_master_recalc_rate(struct clk_hw *hw,
+-					    unsigned long parent_rate)
++static unsigned long clk_master_div_recalc_rate(struct clk_hw *hw,
++						unsigned long parent_rate)
+ {
+-	u8 pres;
+ 	u8 div;
+-	unsigned long rate = parent_rate;
++	unsigned long flags, rate = parent_rate;
+ 	struct clk_master *master = to_clk_master(hw);
+ 	const struct clk_master_layout *layout = master->layout;
+ 	const struct clk_master_characteristics *characteristics =
+ 						master->characteristics;
+ 	unsigned int mckr;
+ 
++	spin_lock_irqsave(master->lock, flags);
+ 	regmap_read(master->regmap, master->layout->offset, &mckr);
++	spin_unlock_irqrestore(master->lock, flags);
++
+ 	mckr &= layout->mask;
+ 
+-	pres = (mckr >> layout->pres_shift) & MASTER_PRES_MASK;
+ 	div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
+ 
+-	if (characteristics->have_div3_pres && pres == MASTER_PRES_MAX)
+-		rate /= 3;
+-	else
+-		rate >>= pres;
+-
+ 	rate /= characteristics->divisors[div];
+ 
+ 	if (rate < characteristics->output.min)
+-		pr_warn("master clk is underclocked");
++		pr_warn("master clk div is underclocked");
+ 	else if (rate > characteristics->output.max)
+-		pr_warn("master clk is overclocked");
++		pr_warn("master clk div is overclocked");
+ 
+ 	return rate;
+ }
+ 
+-static u8 clk_master_get_parent(struct clk_hw *hw)
++static const struct clk_ops master_div_ops = {
++	.prepare = clk_master_prepare,
++	.is_prepared = clk_master_is_prepared,
++	.recalc_rate = clk_master_div_recalc_rate,
++};
++
++static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate,
++				   unsigned long parent_rate)
++{
++	struct clk_master *master = to_clk_master(hw);
++	const struct clk_master_characteristics *characteristics =
++						master->characteristics;
++	unsigned long flags;
++	int div, i;
++
++	div = DIV_ROUND_CLOSEST(parent_rate, rate);
++	if (div > ARRAY_SIZE(characteristics->divisors))
++		return -EINVAL;
++
++	for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {
++		if (!characteristics->divisors[i])
++			break;
++
++		if (div == characteristics->divisors[i]) {
++			div = i;
++			break;
++		}
++	}
++
++	if (i == ARRAY_SIZE(characteristics->divisors))
++		return -EINVAL;
++
++	spin_lock_irqsave(master->lock, flags);
++	regmap_update_bits(master->regmap, master->layout->offset,
++			   (MASTER_DIV_MASK << MASTER_DIV_SHIFT),
++			   (div << MASTER_DIV_SHIFT));
++	while (!clk_master_ready(master))
++		cpu_relax();
++	spin_unlock_irqrestore(master->lock, flags);
++
++	return 0;
++}
++
++static int clk_master_div_determine_rate(struct clk_hw *hw,
++					 struct clk_rate_request *req)
++{
++	struct clk_master *master = to_clk_master(hw);
++	const struct clk_master_characteristics *characteristics =
++						master->characteristics;
++	struct clk_hw *parent;
++	unsigned long parent_rate, tmp_rate, best_rate = 0;
++	int i, best_diff = INT_MIN, tmp_diff;
++
++	parent = clk_hw_get_parent(hw);
++	if (!parent)
++		return -EINVAL;
++
++	parent_rate = clk_hw_get_rate(parent);
++	if (!parent_rate)
++		return -EINVAL;
++
++	for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {
++		if (!characteristics->divisors[i])
++			break;
++
++		tmp_rate = DIV_ROUND_CLOSEST_ULL(parent_rate,
++						 characteristics->divisors[i]);
++		tmp_diff = abs(tmp_rate - req->rate);
++
++		if (!best_rate || best_diff > tmp_diff) {
++			best_diff = tmp_diff;
++			best_rate = tmp_rate;
++		}
++
++		if (!best_diff)
++			break;
++	}
++
++	req->best_parent_rate = best_rate;
++	req->best_parent_hw = parent;
++	req->rate = best_rate;
++
++	return 0;
++}
++
++static const struct clk_ops master_div_ops_chg = {
++	.prepare = clk_master_prepare,
++	.is_prepared = clk_master_is_prepared,
++	.recalc_rate = clk_master_div_recalc_rate,
++	.determine_rate = clk_master_div_determine_rate,
++	.set_rate = clk_master_div_set_rate,
++};
++
++static void clk_sama7g5_master_best_diff(struct clk_rate_request *req,
++					 struct clk_hw *parent,
++					 unsigned long parent_rate,
++					 long *best_rate,
++					 long *best_diff,
++					 u32 div)
++{
++	unsigned long tmp_rate, tmp_diff;
++
++	if (div == MASTER_PRES_MAX)
++		tmp_rate = parent_rate / 3;
++	else
++		tmp_rate = parent_rate >> div;
++
++	tmp_diff = abs(req->rate - tmp_rate);
++
++	if (*best_diff < 0 || *best_diff >= tmp_diff) {
++		*best_rate = tmp_rate;
++		*best_diff = tmp_diff;
++		req->best_parent_rate = parent_rate;
++		req->best_parent_hw = parent;
++	}
++}
++
++static int clk_master_pres_determine_rate(struct clk_hw *hw,
++					  struct clk_rate_request *req)
+ {
+ 	struct clk_master *master = to_clk_master(hw);
++	struct clk_rate_request req_parent = *req;
++	const struct clk_master_characteristics *characteristics =
++							master->characteristics;
++	struct clk_hw *parent;
++	long best_rate = LONG_MIN, best_diff = LONG_MIN;
++	u32 pres;
++	int i;
++
++	if (master->chg_pid < 0)
++		return -EOPNOTSUPP;
++
++	parent = clk_hw_get_parent_by_index(hw, master->chg_pid);
++	if (!parent)
++		return -EOPNOTSUPP;
++
++	for (i = 0; i <= MASTER_PRES_MAX; i++) {
++		if (characteristics->have_div3_pres && i == MASTER_PRES_MAX)
++			pres = 3;
++		else
++			pres = 1 << i;
++
++		req_parent.rate = req->rate * pres;
++		if (__clk_determine_rate(parent, &req_parent))
++			continue;
++
++		clk_sama7g5_master_best_diff(req, parent, req_parent.rate,
++					     &best_diff, &best_rate, pres);
++		if (!best_diff)
++			break;
++	}
++
++	return 0;
++}
++
++static int clk_master_pres_set_rate(struct clk_hw *hw, unsigned long rate,
++				    unsigned long parent_rate)
++{
++	struct clk_master *master = to_clk_master(hw);
++	unsigned long flags;
++	unsigned int pres;
++
++	pres = DIV_ROUND_CLOSEST(parent_rate, rate);
++	if (pres > MASTER_PRES_MAX)
++		return -EINVAL;
++
++	else if (pres == 3)
++		pres = MASTER_PRES_MAX;
++	else
++		pres = ffs(pres) - 1;
++
++	spin_lock_irqsave(master->lock, flags);
++	regmap_update_bits(master->regmap, master->layout->offset,
++			   (MASTER_PRES_MASK << master->layout->pres_shift),
++			   (pres << master->layout->pres_shift));
++
++	while (!clk_master_ready(master))
++		cpu_relax();
++	spin_unlock_irqrestore(master->lock, flags);
++
++	return 0;
++}
++
++static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw,
++						 unsigned long parent_rate)
++{
++	struct clk_master *master = to_clk_master(hw);
++	const struct clk_master_characteristics *characteristics =
++						master->characteristics;
++	unsigned long flags;
++	unsigned int val, pres;
++
++	spin_lock_irqsave(master->lock, flags);
++	regmap_read(master->regmap, master->layout->offset, &val);
++	spin_unlock_irqrestore(master->lock, flags);
++
++	pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;
++	if (pres == 3 && characteristics->have_div3_pres)
++		pres = 3;
++	else
++		pres = (1 << pres);
++
++	return DIV_ROUND_CLOSEST_ULL(parent_rate, pres);
++}
++
++static u8 clk_master_pres_get_parent(struct clk_hw *hw)
++{
++	struct clk_master *master = to_clk_master(hw);
++	unsigned long flags;
+ 	unsigned int mckr;
+ 
++	spin_lock_irqsave(master->lock, flags);
+ 	regmap_read(master->regmap, master->layout->offset, &mckr);
++	spin_unlock_irqrestore(master->lock, flags);
+ 
+ 	return mckr & AT91_PMC_CSS;
+ }
+ 
+-static const struct clk_ops master_ops = {
++static const struct clk_ops master_pres_ops = {
+ 	.prepare = clk_master_prepare,
+ 	.is_prepared = clk_master_is_prepared,
+-	.recalc_rate = clk_master_recalc_rate,
+-	.get_parent = clk_master_get_parent,
++	.recalc_rate = clk_master_pres_recalc_rate,
++	.get_parent = clk_master_pres_get_parent,
+ };
+ 
+-struct clk_hw * __init
+-at91_clk_register_master(struct regmap *regmap,
++static const struct clk_ops master_pres_ops_chg = {
++	.prepare = clk_master_prepare,
++	.is_prepared = clk_master_is_prepared,
++	.determine_rate = clk_master_pres_determine_rate,
++	.recalc_rate = clk_master_pres_recalc_rate,
++	.get_parent = clk_master_pres_get_parent,
++	.set_rate = clk_master_pres_set_rate,
++};
++
++static struct clk_hw * __init
++at91_clk_register_master_internal(struct regmap *regmap,
+ 		const char *name, int num_parents,
+ 		const char **parent_names,
+ 		const struct clk_master_layout *layout,
+-		const struct clk_master_characteristics *characteristics)
++		const struct clk_master_characteristics *characteristics,
++		const struct clk_ops *ops, spinlock_t *lock, u32 flags,
++		int chg_pid)
+ {
+ 	struct clk_master *master;
+ 	struct clk_init_data init;
+ 	struct clk_hw *hw;
+ 	int ret;
+ 
+-	if (!name || !num_parents || !parent_names)
++	if (!name || !num_parents || !parent_names || !lock)
+ 		return ERR_PTR(-EINVAL);
+ 
+ 	master = kzalloc(sizeof(*master), GFP_KERNEL);
+@@ -142,15 +368,17 @@ at91_clk_register_master(struct regmap *regmap,
+ 		return ERR_PTR(-ENOMEM);
+ 
+ 	init.name = name;
+-	init.ops = &master_ops;
++	init.ops = ops;
+ 	init.parent_names = parent_names;
+ 	init.num_parents = num_parents;
+-	init.flags = 0;
++	init.flags = flags;
+ 
+ 	master->hw.init = &init;
+ 	master->layout = layout;
+ 	master->characteristics = characteristics;
+ 	master->regmap = regmap;
++	master->chg_pid = chg_pid;
++	master->lock = lock;
+ 
+ 	hw = &master->hw;
+ 	ret = clk_hw_register(NULL, &master->hw);
+@@ -162,37 +390,54 @@ at91_clk_register_master(struct regmap *regmap,
+ 	return hw;
+ }
+ 
+-static unsigned long
+-clk_sama7g5_master_recalc_rate(struct clk_hw *hw,
+-			       unsigned long parent_rate)
++struct clk_hw * __init
++at91_clk_register_master_pres(struct regmap *regmap,
++		const char *name, int num_parents,
++		const char **parent_names,
++		const struct clk_master_layout *layout,
++		const struct clk_master_characteristics *characteristics,
++		spinlock_t *lock, u32 flags, int chg_pid)
+ {
+-	struct clk_master *master = to_clk_master(hw);
++	const struct clk_ops *ops;
+ 
+-	return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div));
++	if (flags & CLK_SET_RATE_GATE)
++		ops = &master_pres_ops;
++	else
++		ops = &master_pres_ops_chg;
++
++	return at91_clk_register_master_internal(regmap, name, num_parents,
++						 parent_names, layout,
++						 characteristics, ops,
++						 lock, flags, chg_pid);
+ }
+ 
+-static void clk_sama7g5_master_best_diff(struct clk_rate_request *req,
+-					 struct clk_hw *parent,
+-					 unsigned long parent_rate,
+-					 long *best_rate,
+-					 long *best_diff,
+-					 u32 div)
++struct clk_hw * __init
++at91_clk_register_master_div(struct regmap *regmap,
++		const char *name, const char *parent_name,
++		const struct clk_master_layout *layout,
++		const struct clk_master_characteristics *characteristics,
++		spinlock_t *lock, u32 flags)
+ {
+-	unsigned long tmp_rate, tmp_diff;
++	const struct clk_ops *ops;
+ 
+-	if (div == MASTER_PRES_MAX)
+-		tmp_rate = parent_rate / 3;
++	if (flags & CLK_SET_RATE_GATE)
++		ops = &master_div_ops;
+ 	else
+-		tmp_rate = parent_rate >> div;
++		ops = &master_div_ops_chg;
+ 
+-	tmp_diff = abs(req->rate - tmp_rate);
++	return at91_clk_register_master_internal(regmap, name, 1,
++						 &parent_name, layout,
++						 characteristics, ops,
++						 lock, flags, -EINVAL);
++}
+ 
+-	if (*best_diff < 0 || *best_diff >= tmp_diff) {
+-		*best_rate = tmp_rate;
+-		*best_diff = tmp_diff;
+-		req->best_parent_rate = parent_rate;
+-		req->best_parent_hw = parent;
+-	}
++static unsigned long
++clk_sama7g5_master_recalc_rate(struct clk_hw *hw,
++			       unsigned long parent_rate)
++{
++	struct clk_master *master = to_clk_master(hw);
++
++	return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div));
+ }
+ 
+ static int clk_sama7g5_master_determine_rate(struct clk_hw *hw,
+diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c
+index a50084de97d4..a97b99c2dc12 100644
+--- a/drivers/clk/at91/dt-compat.c
++++ b/drivers/clk/at91/dt-compat.c
+@@ -24,6 +24,8 @@
+ 
+ #define GCK_INDEX_DT_AUDIO_PLL	5
+ 
++static DEFINE_SPINLOCK(mck_lock);
++
+ #ifdef CONFIG_HAVE_AT91_AUDIO_PLL
+ static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np)
+ {
+@@ -388,9 +390,16 @@ of_at91_clk_master_setup(struct device_node *np,
+ 	if (IS_ERR(regmap))
+ 		return;
+ 
+-	hw = at91_clk_register_master(regmap, name, num_parents,
+-				      parent_names, layout,
+-				      characteristics);
++	hw = at91_clk_register_master_pres(regmap, "masterck_pres", num_parents,
++					   parent_names, layout,
++					   characteristics, &mck_lock,
++					   CLK_SET_RATE_GATE, INT_MIN);
++	if (IS_ERR(hw))
++		goto out_free_characteristics;
++
++	hw = at91_clk_register_master_div(regmap, name, "masterck_pres",
++					  layout, characteristics,
++					  &mck_lock, CLK_SET_RATE_GATE);
+ 	if (IS_ERR(hw))
+ 		goto out_free_characteristics;
+ 
+diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
+index bedcd85ad750..a49076c804a9 100644
+--- a/drivers/clk/at91/pmc.h
++++ b/drivers/clk/at91/pmc.h
+@@ -155,10 +155,18 @@ at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name,
+ 			      const char **parent_names, int num_parents);
+ 
+ struct clk_hw * __init
+-at91_clk_register_master(struct regmap *regmap, const char *name,
+-			 int num_parents, const char **parent_names,
+-			 const struct clk_master_layout *layout,
+-			 const struct clk_master_characteristics *characteristics);
++at91_clk_register_master_pres(struct regmap *regmap, const char *name,
++			      int num_parents, const char **parent_names,
++			      const struct clk_master_layout *layout,
++			      const struct clk_master_characteristics *characteristics,
++			      spinlock_t *lock, u32 flags, int chg_pid);
++
++struct clk_hw * __init
++at91_clk_register_master_div(struct regmap *regmap, const char *name,
++			     const char *parent_names,
++			     const struct clk_master_layout *layout,
++			     const struct clk_master_characteristics *characteristics,
++			     spinlock_t *lock, u32 flags);
+ 
+ struct clk_hw * __init
+ at91_clk_sama7g5_register_master(struct regmap *regmap,
+diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
+index 4cb0d31babf7..5f6fa89571b7 100644
+--- a/drivers/clk/at91/sam9x60.c
++++ b/drivers/clk/at91/sam9x60.c
+@@ -8,6 +8,7 @@
+ #include "pmc.h"
+ 
+ static DEFINE_SPINLOCK(pmc_pll_lock);
++static DEFINE_SPINLOCK(mck_lock);
+ 
+ static const struct clk_master_characteristics mck_characteristics = {
+ 	.output = { .min = 140000000, .max = 200000000 },
+@@ -76,11 +77,11 @@ static const struct {
+ 	char *p;
+ 	u8 id;
+ } sam9x60_systemck[] = {
+-	{ .n = "ddrck",  .p = "masterck", .id = 2 },
++	{ .n = "ddrck",  .p = "masterck_div", .id = 2 },
+ 	{ .n = "uhpck",  .p = "usbck",    .id = 6 },
+ 	{ .n = "pck0",   .p = "prog0",    .id = 8 },
+ 	{ .n = "pck1",   .p = "prog1",    .id = 9 },
+-	{ .n = "qspick", .p = "masterck", .id = 19 },
++	{ .n = "qspick", .p = "masterck_div", .id = 19 },
+ };
+ 
+ static const struct {
+@@ -268,9 +269,17 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
+ 	parent_names[0] = md_slck_name;
+ 	parent_names[1] = "mainck";
+ 	parent_names[2] = "pllack_divck";
+-	hw = at91_clk_register_master(regmap, "masterck", 3, parent_names,
+-				      &sam9x60_master_layout,
+-				      &mck_characteristics);
++	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 3,
++					   parent_names, &sam9x60_master_layout,
++					   &mck_characteristics, &mck_lock,
++					   CLK_SET_RATE_GATE, INT_MIN);
++	if (IS_ERR(hw))
++		goto err_free;
++
++	hw = at91_clk_register_master_div(regmap, "masterck_div",
++					  "masterck_pres", &sam9x60_master_layout,
++					  &mck_characteristics, &mck_lock,
++					  CLK_SET_RATE_GATE);
+ 	if (IS_ERR(hw))
+ 		goto err_free;
+ 
+@@ -286,7 +295,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
+ 	parent_names[0] = md_slck_name;
+ 	parent_names[1] = td_slck_name;
+ 	parent_names[2] = "mainck";
+-	parent_names[3] = "masterck";
++	parent_names[3] = "masterck_div";
+ 	parent_names[4] = "pllack_divck";
+ 	parent_names[5] = "upllck_divck";
+ 	for (i = 0; i < 2; i++) {
+@@ -318,7 +327,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
+ 		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
+ 							 &sam9x60_pcr_layout,
+ 							 sam9x60_periphck[i].n,
+-							 "masterck",
++							 "masterck_div",
+ 							 sam9x60_periphck[i].id,
+ 							 &range, INT_MIN);
+ 		if (IS_ERR(hw))
+diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
+index 8b220762941a..9a5cbc7cd55a 100644
+--- a/drivers/clk/at91/sama5d2.c
++++ b/drivers/clk/at91/sama5d2.c
+@@ -7,6 +7,8 @@
+ 
+ #include "pmc.h"
+ 
++static DEFINE_SPINLOCK(mck_lock);
++
+ static const struct clk_master_characteristics mck_characteristics = {
+ 	.output = { .min = 124000000, .max = 166000000 },
+ 	.divisors = { 1, 2, 4, 3 },
+@@ -40,14 +42,14 @@ static const struct {
+ 	char *p;
+ 	u8 id;
+ } sama5d2_systemck[] = {
+-	{ .n = "ddrck", .p = "masterck", .id = 2 },
+-	{ .n = "lcdck", .p = "masterck", .id = 3 },
+-	{ .n = "uhpck", .p = "usbck",    .id = 6 },
+-	{ .n = "udpck", .p = "usbck",    .id = 7 },
+-	{ .n = "pck0",  .p = "prog0",    .id = 8 },
+-	{ .n = "pck1",  .p = "prog1",    .id = 9 },
+-	{ .n = "pck2",  .p = "prog2",    .id = 10 },
+-	{ .n = "iscck", .p = "masterck", .id = 18 },
++	{ .n = "ddrck", .p = "masterck_div", .id = 2 },
++	{ .n = "lcdck", .p = "masterck_div", .id = 3 },
++	{ .n = "uhpck", .p = "usbck",        .id = 6 },
++	{ .n = "udpck", .p = "usbck",        .id = 7 },
++	{ .n = "pck0",  .p = "prog0",        .id = 8 },
++	{ .n = "pck1",  .p = "prog1",        .id = 9 },
++	{ .n = "pck2",  .p = "prog2",        .id = 10 },
++	{ .n = "iscck", .p = "masterck_div", .id = 18 },
+ };
+ 
+ static const struct {
+@@ -235,15 +237,25 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
+ 	parent_names[1] = "mainck";
+ 	parent_names[2] = "plladivck";
+ 	parent_names[3] = "utmick";
+-	hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
+-				      &at91sam9x5_master_layout,
+-				      &mck_characteristics);
++	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
++					   parent_names,
++					   &at91sam9x5_master_layout,
++					   &mck_characteristics, &mck_lock,
++					   CLK_SET_RATE_GATE, INT_MIN);
++	if (IS_ERR(hw))
++		goto err_free;
++
++	hw = at91_clk_register_master_div(regmap, "masterck_div",
++					  "masterck_pres",
++					  &at91sam9x5_master_layout,
++					  &mck_characteristics, &mck_lock,
++					  CLK_SET_RATE_GATE);
+ 	if (IS_ERR(hw))
+ 		goto err_free;
+ 
+ 	sama5d2_pmc->chws[PMC_MCK] = hw;
+ 
+-	hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck");
++	hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div");
+ 	if (IS_ERR(hw))
+ 		goto err_free;
+ 
+@@ -259,7 +271,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
+ 	parent_names[1] = "mainck";
+ 	parent_names[2] = "plladivck";
+ 	parent_names[3] = "utmick";
+-	parent_names[4] = "masterck";
++	parent_names[4] = "masterck_div";
+ 	parent_names[5] = "audiopll_pmcck";
+ 	for (i = 0; i < 3; i++) {
+ 		char name[6];
+@@ -290,7 +302,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
+ 		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
+ 							 &sama5d2_pcr_layout,
+ 							 sama5d2_periphck[i].n,
+-							 "masterck",
++							 "masterck_div",
+ 							 sama5d2_periphck[i].id,
+ 							 &range, INT_MIN);
+ 		if (IS_ERR(hw))
+@@ -317,7 +329,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
+ 	parent_names[1] = "mainck";
+ 	parent_names[2] = "plladivck";
+ 	parent_names[3] = "utmick";
+-	parent_names[4] = "masterck";
++	parent_names[4] = "masterck_div";
+ 	parent_names[5] = "audiopll_pmcck";
+ 	for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) {
+ 		hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
+diff --git a/drivers/clk/at91/sama5d3.c b/drivers/clk/at91/sama5d3.c
+index 7c6e0a5b9dc8..87009ee8effc 100644
+--- a/drivers/clk/at91/sama5d3.c
++++ b/drivers/clk/at91/sama5d3.c
+@@ -7,6 +7,8 @@
+ 
+ #include "pmc.h"
+ 
++static DEFINE_SPINLOCK(mck_lock);
++
+ static const struct clk_master_characteristics mck_characteristics = {
+ 	.output = { .min = 0, .max = 166000000 },
+ 	.divisors = { 1, 2, 4, 3 },
+@@ -40,14 +42,14 @@ static const struct {
+ 	char *p;
+ 	u8 id;
+ } sama5d3_systemck[] = {
+-	{ .n = "ddrck", .p = "masterck", .id = 2 },
+-	{ .n = "lcdck", .p = "masterck", .id = 3 },
+-	{ .n = "smdck", .p = "smdclk",   .id = 4 },
+-	{ .n = "uhpck", .p = "usbck",    .id = 6 },
+-	{ .n = "udpck", .p = "usbck",    .id = 7 },
+-	{ .n = "pck0",  .p = "prog0",    .id = 8 },
+-	{ .n = "pck1",  .p = "prog1",    .id = 9 },
+-	{ .n = "pck2",  .p = "prog2",    .id = 10 },
++	{ .n = "ddrck", .p = "masterck_div", .id = 2 },
++	{ .n = "lcdck", .p = "masterck_div", .id = 3 },
++	{ .n = "smdck", .p = "smdclk",       .id = 4 },
++	{ .n = "uhpck", .p = "usbck",        .id = 6 },
++	{ .n = "udpck", .p = "usbck",        .id = 7 },
++	{ .n = "pck0",  .p = "prog0",        .id = 8 },
++	{ .n = "pck1",  .p = "prog1",        .id = 9 },
++	{ .n = "pck2",  .p = "prog2",        .id = 10 },
+ };
+ 
+ static const struct {
+@@ -170,9 +172,19 @@ static void __init sama5d3_pmc_setup(struct device_node *np)
+ 	parent_names[1] = "mainck";
+ 	parent_names[2] = "plladivck";
+ 	parent_names[3] = "utmick";
+-	hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
+-				      &at91sam9x5_master_layout,
+-				      &mck_characteristics);
++	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
++					   parent_names,
++					   &at91sam9x5_master_layout,
++					   &mck_characteristics, &mck_lock,
++					   CLK_SET_RATE_GATE, INT_MIN);
++	if (IS_ERR(hw))
++		goto err_free;
++
++	hw = at91_clk_register_master_div(regmap, "masterck_div",
++					  "masterck_pres",
++					  &at91sam9x5_master_layout,
++					  &mck_characteristics, &mck_lock,
++					  CLK_SET_RATE_GATE);
+ 	if (IS_ERR(hw))
+ 		goto err_free;
+ 
+@@ -192,7 +204,7 @@ static void __init sama5d3_pmc_setup(struct device_node *np)
+ 	parent_names[1] = "mainck";
+ 	parent_names[2] = "plladivck";
+ 	parent_names[3] = "utmick";
+-	parent_names[4] = "masterck";
++	parent_names[4] = "masterck_div";
+ 	for (i = 0; i < 3; i++) {
+ 		char name[6];
+ 
+@@ -222,7 +234,7 @@ static void __init sama5d3_pmc_setup(struct device_node *np)
+ 		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
+ 							 &sama5d3_pcr_layout,
+ 							 sama5d3_periphck[i].n,
+-							 "masterck",
++							 "masterck_div",
+ 							 sama5d3_periphck[i].id,
+ 							 &sama5d3_periphck[i].r,
+ 							 INT_MIN);
+diff --git a/drivers/clk/at91/sama5d4.c b/drivers/clk/at91/sama5d4.c
+index 92d8d4141b43..57fff790188b 100644
+--- a/drivers/clk/at91/sama5d4.c
++++ b/drivers/clk/at91/sama5d4.c
+@@ -7,6 +7,8 @@
+ 
+ #include "pmc.h"
+ 
++static DEFINE_SPINLOCK(mck_lock);
++
+ static const struct clk_master_characteristics mck_characteristics = {
+ 	.output = { .min = 125000000, .max = 200000000 },
+ 	.divisors = { 1, 2, 4, 3 },
+@@ -39,14 +41,14 @@ static const struct {
+ 	char *p;
+ 	u8 id;
+ } sama5d4_systemck[] = {
+-	{ .n = "ddrck", .p = "masterck", .id = 2 },
+-	{ .n = "lcdck", .p = "masterck", .id = 3 },
+-	{ .n = "smdck", .p = "smdclk",   .id = 4 },
+-	{ .n = "uhpck", .p = "usbck",    .id = 6 },
+-	{ .n = "udpck", .p = "usbck",    .id = 7 },
+-	{ .n = "pck0",  .p = "prog0",    .id = 8 },
+-	{ .n = "pck1",  .p = "prog1",    .id = 9 },
+-	{ .n = "pck2",  .p = "prog2",    .id = 10 },
++	{ .n = "ddrck", .p = "masterck_div", .id = 2 },
++	{ .n = "lcdck", .p = "masterck_div", .id = 3 },
++	{ .n = "smdck", .p = "smdclk",       .id = 4 },
++	{ .n = "uhpck", .p = "usbck",        .id = 6 },
++	{ .n = "udpck", .p = "usbck",        .id = 7 },
++	{ .n = "pck0",  .p = "prog0",        .id = 8 },
++	{ .n = "pck1",  .p = "prog1",        .id = 9 },
++	{ .n = "pck2",  .p = "prog2",        .id = 10 },
+ };
+ 
+ static const struct {
+@@ -185,15 +187,25 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
+ 	parent_names[1] = "mainck";
+ 	parent_names[2] = "plladivck";
+ 	parent_names[3] = "utmick";
+-	hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
+-				      &at91sam9x5_master_layout,
+-				      &mck_characteristics);
++	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
++					   parent_names,
++					   &at91sam9x5_master_layout,
++					   &mck_characteristics, &mck_lock,
++					   CLK_SET_RATE_GATE, INT_MIN);
++	if (IS_ERR(hw))
++		goto err_free;
++
++	hw = at91_clk_register_master_div(regmap, "masterck_div",
++					  "masterck_pres",
++					  &at91sam9x5_master_layout,
++					  &mck_characteristics, &mck_lock,
++					  CLK_SET_RATE_GATE);
+ 	if (IS_ERR(hw))
+ 		goto err_free;
+ 
+ 	sama5d4_pmc->chws[PMC_MCK] = hw;
+ 
+-	hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck");
++	hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div");
+ 	if (IS_ERR(hw))
+ 		goto err_free;
+ 
+@@ -215,7 +227,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
+ 	parent_names[1] = "mainck";
+ 	parent_names[2] = "plladivck";
+ 	parent_names[3] = "utmick";
+-	parent_names[4] = "masterck";
++	parent_names[4] = "masterck_div";
+ 	for (i = 0; i < 3; i++) {
+ 		char name[6];
+ 
+@@ -245,7 +257,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
+ 		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
+ 							 &sama5d4_pcr_layout,
+ 							 sama5d4_periphck[i].n,
+-							 "masterck",
++							 "masterck_div",
+ 							 sama5d4_periphck[i].id,
+ 							 &range, INT_MIN);
+ 		if (IS_ERR(hw))
+diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
+index e0c4d2eb9f59..927eb3b2b126 100644
+--- a/drivers/clk/at91/sama7g5.c
++++ b/drivers/clk/at91/sama7g5.c
+@@ -32,6 +32,7 @@
+ 	} while (0)
+ 
+ static DEFINE_SPINLOCK(pmc_pll_lock);
++static DEFINE_SPINLOCK(pmc_mck0_lock);
+ static DEFINE_SPINLOCK(pmc_mckX_lock);
+ 
+ /**
+@@ -984,8 +985,16 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
+ 	parent_names[1] = "mainck";
+ 	parent_names[2] = "cpupll_divpmcck";
+ 	parent_names[3] = "syspll_divpmcck";
+-	hw = at91_clk_register_master(regmap, "mck0", 4, parent_names,
+-				      &mck0_layout, &mck0_characteristics);
++	hw = at91_clk_register_master_pres(regmap, "mck0_pres", 4, parent_names,
++					   &mck0_layout, &mck0_characteristics,
++					   &pmc_mck0_lock,
++					   CLK_SET_RATE_PARENT, 0);
++	if (IS_ERR(hw))
++		goto err_free;
++
++	hw = at91_clk_register_master_div(regmap, "mck0_div", "mck0_pres",
++					  &mck0_layout, &mck0_characteristics,
++					  &pmc_mck0_lock, 0);
+ 	if (IS_ERR(hw))
+ 		goto err_free;
+ 
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/111-clk-at91-sama7g5-register-cpu-clock.patch

@@ -0,0 +1,72 @@
+From 36e97c421dd9f866e31fe14bcb7af01334791890 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Thu, 19 Nov 2020 17:43:17 +0200
+Subject: [PATCH 111/247] clk: at91: sama7g5: register cpu clock
+
+Register CPU clock as being the master clock prescaler. This would
+be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider
+between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the
+frequencies supported by SAMA7G5 could be directly received from
+CPUPLL + master clock prescaler and the extra divider would do no work in
+case it would be enabled.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/at91/sama7g5.c       | 13 ++++++-------
+ include/dt-bindings/clock/at91.h |  1 +
+ 2 files changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
+index 927eb3b2b126..a6e20b35960e 100644
+--- a/drivers/clk/at91/sama7g5.c
++++ b/drivers/clk/at91/sama7g5.c
+@@ -904,7 +904,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
+ 	if (IS_ERR(regmap))
+ 		return;
+ 
+-	sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1,
++	sama7g5_pmc = pmc_data_allocate(PMC_CPU + 1,
+ 					nck(sama7g5_systemck),
+ 					nck(sama7g5_periphck),
+ 					nck(sama7g5_gck), 8);
+@@ -981,18 +981,17 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
+ 		}
+ 	}
+ 
+-	parent_names[0] = md_slck_name;
+-	parent_names[1] = "mainck";
+-	parent_names[2] = "cpupll_divpmcck";
+-	parent_names[3] = "syspll_divpmcck";
+-	hw = at91_clk_register_master_pres(regmap, "mck0_pres", 4, parent_names,
++	parent_names[0] = "cpupll_divpmcck";
++	hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names,
+ 					   &mck0_layout, &mck0_characteristics,
+ 					   &pmc_mck0_lock,
+ 					   CLK_SET_RATE_PARENT, 0);
+ 	if (IS_ERR(hw))
+ 		goto err_free;
+ 
+-	hw = at91_clk_register_master_div(regmap, "mck0_div", "mck0_pres",
++	sama7g5_pmc->chws[PMC_CPU] = hw;
++
++	hw = at91_clk_register_master_div(regmap, "mck0", "cpuck",
+ 					  &mck0_layout, &mck0_characteristics,
+ 					  &pmc_mck0_lock, 0);
+ 	if (IS_ERR(hw))
+diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h
+index fab313f62e8f..98e1b2ab6403 100644
+--- a/include/dt-bindings/clock/at91.h
++++ b/include/dt-bindings/clock/at91.h
+@@ -34,6 +34,7 @@
+ #define PMC_AUDIOPMCPLL		(PMC_MAIN + 6)
+ #define PMC_AUDIOIOPLL		(PMC_MAIN + 7)
+ #define PMC_ETHPLL		(PMC_MAIN + 8)
++#define PMC_CPU			(PMC_MAIN + 9)
+ 
+ #ifndef AT91_PMC_MOSCS
+ #define AT91_PMC_MOSCS		0		/* MOSCS Flag */
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/112-clk-at91-Fix-the-declaration-of-the-clocks.patch

@@ -0,0 +1,202 @@
+From 5a25e2437af0db535b17da352fb16680a8dfdeda Mon Sep 17 00:00:00 2001
+From: Tudor Ambarus <[email protected]>
+Date: Wed, 3 Feb 2021 17:43:32 +0200
+Subject: [PATCH 112/247] clk: at91: Fix the declaration of the clocks
+
+These are all "early clocks" that require initialization just at
+of_clk_init() time. Use CLK_OF_DECLARE() to declare them.
+
+This also fixes a problem that was spotted when fw_devlink was
+set to 'on' by default: the boards failed to boot. The reason is
+that CLK_OF_DECLARE_DRIVER() clears the OF_POPULATED and causes
+the consumers of the clock to be postponed by fw_devlink until
+the second initialization routine of the clock has been completed.
+One of the consumers of the clock is the timer, which is used as a
+clocksource, and needs the clock initialized early. Postponing the
+timers caused the fail at boot.
+
+Signed-off-by: Tudor Ambarus <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Acked-by: Saravana Kannan <[email protected]>
+Tested-by: Eugen Hristev <[email protected]>
+Acked-by: Nicolas Ferre <[email protected]>
+Reviewed-by: Claudiu Beznea <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/at91/at91rm9200.c  |  3 +--
+ drivers/clk/at91/at91sam9260.c | 16 ++++++++--------
+ drivers/clk/at91/at91sam9g45.c |  3 +--
+ drivers/clk/at91/at91sam9n12.c |  3 +--
+ drivers/clk/at91/at91sam9rl.c  |  3 ++-
+ drivers/clk/at91/at91sam9x5.c  | 20 ++++++++++----------
+ drivers/clk/at91/sama5d2.c     |  3 ++-
+ drivers/clk/at91/sama5d3.c     |  2 +-
+ drivers/clk/at91/sama5d4.c     |  3 ++-
+ 9 files changed, 28 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/clk/at91/at91rm9200.c b/drivers/clk/at91/at91rm9200.c
+index 0fad1009f315..428a6f4b9ebc 100644
+--- a/drivers/clk/at91/at91rm9200.c
++++ b/drivers/clk/at91/at91rm9200.c
+@@ -215,5 +215,4 @@ static void __init at91rm9200_pmc_setup(struct device_node *np)
+  * deferring properly. Once this is fixed, this can be switched to a platform
+  * driver.
+  */
+-CLK_OF_DECLARE_DRIVER(at91rm9200_pmc, "atmel,at91rm9200-pmc",
+-		      at91rm9200_pmc_setup);
++CLK_OF_DECLARE(at91rm9200_pmc, "atmel,at91rm9200-pmc", at91rm9200_pmc_setup);
+diff --git a/drivers/clk/at91/at91sam9260.c b/drivers/clk/at91/at91sam9260.c
+index ceb5495f723a..b29843bea278 100644
+--- a/drivers/clk/at91/at91sam9260.c
++++ b/drivers/clk/at91/at91sam9260.c
+@@ -491,26 +491,26 @@ static void __init at91sam9260_pmc_setup(struct device_node *np)
+ {
+ 	at91sam926x_pmc_setup(np, &at91sam9260_data);
+ }
+-CLK_OF_DECLARE_DRIVER(at91sam9260_pmc, "atmel,at91sam9260-pmc",
+-		      at91sam9260_pmc_setup);
++
++CLK_OF_DECLARE(at91sam9260_pmc, "atmel,at91sam9260-pmc", at91sam9260_pmc_setup);
+ 
+ static void __init at91sam9261_pmc_setup(struct device_node *np)
+ {
+ 	at91sam926x_pmc_setup(np, &at91sam9261_data);
+ }
+-CLK_OF_DECLARE_DRIVER(at91sam9261_pmc, "atmel,at91sam9261-pmc",
+-		      at91sam9261_pmc_setup);
++
++CLK_OF_DECLARE(at91sam9261_pmc, "atmel,at91sam9261-pmc", at91sam9261_pmc_setup);
+ 
+ static void __init at91sam9263_pmc_setup(struct device_node *np)
+ {
+ 	at91sam926x_pmc_setup(np, &at91sam9263_data);
+ }
+-CLK_OF_DECLARE_DRIVER(at91sam9263_pmc, "atmel,at91sam9263-pmc",
+-		      at91sam9263_pmc_setup);
++
++CLK_OF_DECLARE(at91sam9263_pmc, "atmel,at91sam9263-pmc", at91sam9263_pmc_setup);
+ 
+ static void __init at91sam9g20_pmc_setup(struct device_node *np)
+ {
+ 	at91sam926x_pmc_setup(np, &at91sam9g20_data);
+ }
+-CLK_OF_DECLARE_DRIVER(at91sam9g20_pmc, "atmel,at91sam9g20-pmc",
+-		      at91sam9g20_pmc_setup);
++
++CLK_OF_DECLARE(at91sam9g20_pmc, "atmel,at91sam9g20-pmc", at91sam9g20_pmc_setup);
+diff --git a/drivers/clk/at91/at91sam9g45.c b/drivers/clk/at91/at91sam9g45.c
+index 0214333dedd3..15da0dfe3ef2 100644
+--- a/drivers/clk/at91/at91sam9g45.c
++++ b/drivers/clk/at91/at91sam9g45.c
+@@ -228,5 +228,4 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np)
+  * The TCB is used as the clocksource so its clock is needed early. This means
+  * this can't be a platform driver.
+  */
+-CLK_OF_DECLARE_DRIVER(at91sam9g45_pmc, "atmel,at91sam9g45-pmc",
+-		      at91sam9g45_pmc_setup);
++CLK_OF_DECLARE(at91sam9g45_pmc, "atmel,at91sam9g45-pmc", at91sam9g45_pmc_setup);
+diff --git a/drivers/clk/at91/at91sam9n12.c b/drivers/clk/at91/at91sam9n12.c
+index f9db5316a7f1..7fe435f4b46b 100644
+--- a/drivers/clk/at91/at91sam9n12.c
++++ b/drivers/clk/at91/at91sam9n12.c
+@@ -255,5 +255,4 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np)
+  * The TCB is used as the clocksource so its clock is needed early. This means
+  * this can't be a platform driver.
+  */
+-CLK_OF_DECLARE_DRIVER(at91sam9n12_pmc, "atmel,at91sam9n12-pmc",
+-		      at91sam9n12_pmc_setup);
++CLK_OF_DECLARE(at91sam9n12_pmc, "atmel,at91sam9n12-pmc", at91sam9n12_pmc_setup);
+diff --git a/drivers/clk/at91/at91sam9rl.c b/drivers/clk/at91/at91sam9rl.c
+index 66736e03cfef..ecbabf5162bd 100644
+--- a/drivers/clk/at91/at91sam9rl.c
++++ b/drivers/clk/at91/at91sam9rl.c
+@@ -186,4 +186,5 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np)
+ err_free:
+ 	kfree(at91sam9rl_pmc);
+ }
+-CLK_OF_DECLARE_DRIVER(at91sam9rl_pmc, "atmel,at91sam9rl-pmc", at91sam9rl_pmc_setup);
++
++CLK_OF_DECLARE(at91sam9rl_pmc, "atmel,at91sam9rl-pmc", at91sam9rl_pmc_setup);
+diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c
+index 79b9d3667228..5cce48c64ea2 100644
+--- a/drivers/clk/at91/at91sam9x5.c
++++ b/drivers/clk/at91/at91sam9x5.c
+@@ -302,33 +302,33 @@ static void __init at91sam9g15_pmc_setup(struct device_node *np)
+ {
+ 	at91sam9x5_pmc_setup(np, at91sam9g15_periphck, true);
+ }
+-CLK_OF_DECLARE_DRIVER(at91sam9g15_pmc, "atmel,at91sam9g15-pmc",
+-		      at91sam9g15_pmc_setup);
++
++CLK_OF_DECLARE(at91sam9g15_pmc, "atmel,at91sam9g15-pmc", at91sam9g15_pmc_setup);
+ 
+ static void __init at91sam9g25_pmc_setup(struct device_node *np)
+ {
+ 	at91sam9x5_pmc_setup(np, at91sam9g25_periphck, false);
+ }
+-CLK_OF_DECLARE_DRIVER(at91sam9g25_pmc, "atmel,at91sam9g25-pmc",
+-		      at91sam9g25_pmc_setup);
++
++CLK_OF_DECLARE(at91sam9g25_pmc, "atmel,at91sam9g25-pmc", at91sam9g25_pmc_setup);
+ 
+ static void __init at91sam9g35_pmc_setup(struct device_node *np)
+ {
+ 	at91sam9x5_pmc_setup(np, at91sam9g35_periphck, true);
+ }
+-CLK_OF_DECLARE_DRIVER(at91sam9g35_pmc, "atmel,at91sam9g35-pmc",
+-		      at91sam9g35_pmc_setup);
++
++CLK_OF_DECLARE(at91sam9g35_pmc, "atmel,at91sam9g35-pmc", at91sam9g35_pmc_setup);
+ 
+ static void __init at91sam9x25_pmc_setup(struct device_node *np)
+ {
+ 	at91sam9x5_pmc_setup(np, at91sam9x25_periphck, false);
+ }
+-CLK_OF_DECLARE_DRIVER(at91sam9x25_pmc, "atmel,at91sam9x25-pmc",
+-		      at91sam9x25_pmc_setup);
++
++CLK_OF_DECLARE(at91sam9x25_pmc, "atmel,at91sam9x25-pmc", at91sam9x25_pmc_setup);
+ 
+ static void __init at91sam9x35_pmc_setup(struct device_node *np)
+ {
+ 	at91sam9x5_pmc_setup(np, at91sam9x35_periphck, true);
+ }
+-CLK_OF_DECLARE_DRIVER(at91sam9x35_pmc, "atmel,at91sam9x35-pmc",
+-		      at91sam9x35_pmc_setup);
++
++CLK_OF_DECLARE(at91sam9x35_pmc, "atmel,at91sam9x35-pmc", at91sam9x35_pmc_setup);
+diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
+index 9a5cbc7cd55a..3d1f78176c3e 100644
+--- a/drivers/clk/at91/sama5d2.c
++++ b/drivers/clk/at91/sama5d2.c
+@@ -372,4 +372,5 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
+ err_free:
+ 	kfree(sama5d2_pmc);
+ }
+-CLK_OF_DECLARE_DRIVER(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup);
++
++CLK_OF_DECLARE(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup);
+diff --git a/drivers/clk/at91/sama5d3.c b/drivers/clk/at91/sama5d3.c
+index 87009ee8effc..d376257807d2 100644
+--- a/drivers/clk/at91/sama5d3.c
++++ b/drivers/clk/at91/sama5d3.c
+@@ -255,4 +255,4 @@ static void __init sama5d3_pmc_setup(struct device_node *np)
+  * The TCB is used as the clocksource so its clock is needed early. This means
+  * this can't be a platform driver.
+  */
+-CLK_OF_DECLARE_DRIVER(sama5d3_pmc, "atmel,sama5d3-pmc", sama5d3_pmc_setup);
++CLK_OF_DECLARE(sama5d3_pmc, "atmel,sama5d3-pmc", sama5d3_pmc_setup);
+diff --git a/drivers/clk/at91/sama5d4.c b/drivers/clk/at91/sama5d4.c
+index 57fff790188b..5cbaac68da44 100644
+--- a/drivers/clk/at91/sama5d4.c
++++ b/drivers/clk/at91/sama5d4.c
+@@ -286,4 +286,5 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
+ err_free:
+ 	kfree(sama5d4_pmc);
+ }
+-CLK_OF_DECLARE_DRIVER(sama5d4_pmc, "atmel,sama5d4-pmc", sama5d4_pmc_setup);
++
++CLK_OF_DECLARE(sama5d4_pmc, "atmel,sama5d4-pmc", sama5d4_pmc_setup);
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/113-clk-at91-Trivial-typo-fixes-in-the-file-sama7g5.c.patch

@@ -0,0 +1,50 @@
+From 268b36c42b7d1e480dd56ecfec626a46f4b5975e Mon Sep 17 00:00:00 2001
+From: Bhaskar Chowdhury <[email protected]>
+Date: Sat, 13 Mar 2021 11:02:22 +0530
+Subject: [PATCH 113/247] clk: at91: Trivial typo fixes in the file sama7g5.c
+
+s/critial/critical/  ......two different places
+s/parrent/parent/
+
+Signed-off-by: Bhaskar Chowdhury <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Acked-by: Randy Dunlap <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/at91/sama7g5.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
+index a6e20b35960e..9e1ec48c4474 100644
+--- a/drivers/clk/at91/sama7g5.c
++++ b/drivers/clk/at91/sama7g5.c
+@@ -166,7 +166,7 @@ static const struct {
+ 		  .c = &pll_characteristics,
+ 		  .t = PLL_TYPE_FRAC,
+ 		   /*
+-		    * This feeds syspll_divpmcck which may feed critial parts
++		    * This feeds syspll_divpmcck which may feed critical parts
+ 		    * of the systems like timers. Therefore it should not be
+ 		    * disabled.
+ 		    */
+@@ -178,7 +178,7 @@ static const struct {
+ 		  .c = &pll_characteristics,
+ 		  .t = PLL_TYPE_DIV,
+ 		   /*
+-		    * This may feed critial parts of the systems like timers.
++		    * This may feed critical parts of the systems like timers.
+ 		    * Therefore it should not be disabled.
+ 		    */
+ 		  .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
+@@ -455,7 +455,7 @@ static const struct {
+  * @pp:			PLL parents
+  * @pp_mux_table:	PLL parents mux table
+  * @r:			clock output range
+- * @pp_chg_id:		id in parrent array of changeable PLL parent
++ * @pp_chg_id:		id in parent array of changeable PLL parent
+  * @pp_count:		PLL parents count
+  * @id:			clock id
+  */
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/114-clk-at91-sama7g5-remove-all-kernel-doc-kernel-doc-wa.patch

@@ -0,0 +1,95 @@
+From 9997227090cf529675aeb775585ec9f6c2f0f131 Mon Sep 17 00:00:00 2001
+From: Randy Dunlap <[email protected]>
+Date: Thu, 19 Aug 2021 15:32:37 -0700
+Subject: [PATCH 114/247] clk: at91: sama7g5: remove all kernel-doc &
+ kernel-doc warnings
+
+Remove all "/**" kernel-doc markers from sama7g5.c since they are
+all internal to this driver source file only.
+This eliminates 14 warnings that were reported by the kernel test robot.
+
+Signed-off-by: Randy Dunlap <[email protected]>
+Reported-by: kernel test robot <[email protected]>
+Cc: Claudiu Beznea <[email protected]>
+Cc: Michael Turquette <[email protected]>
+Cc: Stephen Boyd <[email protected]>
+Cc: Eugen Hristev <[email protected]>
+Cc: [email protected]
+Cc: [email protected]
+Link: https://lore.kernel.org/r/[email protected]
+Reviewed-by: Claudiu Beznea <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/at91/sama7g5.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
+index 9e1ec48c4474..cf8c079aa086 100644
+--- a/drivers/clk/at91/sama7g5.c
++++ b/drivers/clk/at91/sama7g5.c
+@@ -35,7 +35,7 @@ static DEFINE_SPINLOCK(pmc_pll_lock);
+ static DEFINE_SPINLOCK(pmc_mck0_lock);
+ static DEFINE_SPINLOCK(pmc_mckX_lock);
+ 
+-/**
++/*
+  * PLL clocks identifiers
+  * @PLL_ID_CPU:		CPU PLL identifier
+  * @PLL_ID_SYS:		System PLL identifier
+@@ -56,7 +56,7 @@ enum pll_ids {
+ 	PLL_ID_MAX,
+ };
+ 
+-/**
++/*
+  * PLL type identifiers
+  * @PLL_TYPE_FRAC:	fractional PLL identifier
+  * @PLL_TYPE_DIV:	divider PLL identifier
+@@ -118,7 +118,7 @@ static const struct clk_pll_characteristics pll_characteristics = {
+ 	.output = pll_outputs,
+ };
+ 
+-/**
++/*
+  * PLL clocks description
+  * @n:		clock name
+  * @p:		clock parent
+@@ -285,7 +285,7 @@ static const struct {
+ 	},
+ };
+ 
+-/**
++/*
+  * Master clock (MCK[1..4]) description
+  * @n:			clock name
+  * @ep:			extra parents names array
+@@ -337,7 +337,7 @@ static const struct {
+ 	  .c = 1, },
+ };
+ 
+-/**
++/*
+  * System clock description
+  * @n:	clock name
+  * @p:	clock parent name
+@@ -361,7 +361,7 @@ static const struct {
+ /* Mux table for programmable clocks. */
+ static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 5, 6, 7, 8, 9, 10, };
+ 
+-/**
++/*
+  * Peripheral clock description
+  * @n:		clock name
+  * @p:		clock parent name
+@@ -449,7 +449,7 @@ static const struct {
+ 	{ .n = "uhphs_clk",	.p = "mck1", .id = 106, },
+ };
+ 
+-/**
++/*
+  * Generic clock description
+  * @n:			clock name
+  * @pp:			PLL parents
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/115-net-macb-add-userio-bits-as-platform-configuration.patch

@@ -0,0 +1,186 @@
+From 89f37ac2780d113d3c17d329726c0e92a1400744 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Wed, 9 Dec 2020 15:03:32 +0200
+Subject: [PATCH 115/247] net: macb: add userio bits as platform configuration
+
+This is necessary for SAMA7G5 as it uses different values for
+PHY interface and also introduces hdfctlen bit.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Reviewed-by: Andrew Lunn <[email protected]>
+Signed-off-by: David S. Miller <[email protected]>
+---
+ drivers/net/ethernet/cadence/macb.h      | 10 +++++++++
+ drivers/net/ethernet/cadence/macb_main.c | 28 ++++++++++++++++++++----
+ 2 files changed, 34 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
+index 5de47f6fde5a..e9385a1390a9 100644
+--- a/drivers/net/ethernet/cadence/macb.h
++++ b/drivers/net/ethernet/cadence/macb.h
+@@ -1104,6 +1104,14 @@ struct macb_pm_data {
+ 	u32 usrio;
+ };
+ 
++struct macb_usrio_config {
++	u32 mii;
++	u32 rmii;
++	u32 rgmii;
++	u32 refclk;
++	u32 hdfctlen;
++};
++
+ struct macb_config {
+ 	u32			caps;
+ 	unsigned int		dma_burst_length;
+@@ -1112,6 +1120,7 @@ struct macb_config {
+ 			    struct clk **rx_clk, struct clk **tsu_clk);
+ 	int	(*init)(struct platform_device *pdev);
+ 	int	jumbo_max_len;
++	const struct macb_usrio_config *usrio;
+ };
+ 
+ struct tsu_incr {
+@@ -1244,6 +1253,7 @@ struct macb {
+ 	u32	rx_intr_mask;
+ 
+ 	struct macb_pm_data pm_data;
++	const struct macb_usrio_config *usrio;
+ };
+ 
+ #ifdef CONFIG_MACB_USE_HWSTAMP
+diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
+index 1e8bf6b9834b..a8326b75eca8 100644
+--- a/drivers/net/ethernet/cadence/macb_main.c
++++ b/drivers/net/ethernet/cadence/macb_main.c
+@@ -3800,15 +3800,15 @@ static int macb_init(struct platform_device *pdev)
+ 	if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
+ 		val = 0;
+ 		if (phy_interface_mode_is_rgmii(bp->phy_interface))
+-			val = GEM_BIT(RGMII);
++			val = bp->usrio->rgmii;
+ 		else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
+ 			 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
+-			val = MACB_BIT(RMII);
++			val = bp->usrio->rmii;
+ 		else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
+-			val = MACB_BIT(MII);
++			val = bp->usrio->mii;
+ 
+ 		if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
+-			val |= MACB_BIT(CLKEN);
++			val |= bp->usrio->refclk;
+ 
+ 		macb_or_gem_writel(bp, USRIO, val);
+ 	}
+@@ -4326,6 +4326,13 @@ static int fu540_c000_init(struct platform_device *pdev)
+ 	return macb_init(pdev);
+ }
+ 
++static const struct macb_usrio_config macb_default_usrio = {
++	.mii = MACB_BIT(MII),
++	.rmii = MACB_BIT(RMII),
++	.rgmii = GEM_BIT(RGMII),
++	.refclk = MACB_BIT(CLKEN),
++};
++
+ static const struct macb_config fu540_c000_config = {
+ 	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
+ 		MACB_CAPS_GEM_HAS_PTP,
+@@ -4333,12 +4340,14 @@ static const struct macb_config fu540_c000_config = {
+ 	.clk_init = fu540_c000_clk_init,
+ 	.init = fu540_c000_init,
+ 	.jumbo_max_len = 10240,
++	.usrio = &macb_default_usrio,
+ };
+ 
+ static const struct macb_config at91sam9260_config = {
+ 	.caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
+ 	.clk_init = macb_clk_init,
+ 	.init = macb_init,
++	.usrio = &macb_default_usrio,
+ };
+ 
+ static const struct macb_config sama5d3macb_config = {
+@@ -4346,6 +4355,7 @@ static const struct macb_config sama5d3macb_config = {
+ 	      | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
+ 	.clk_init = macb_clk_init,
+ 	.init = macb_init,
++	.usrio = &macb_default_usrio,
+ };
+ 
+ static const struct macb_config pc302gem_config = {
+@@ -4353,6 +4363,7 @@ static const struct macb_config pc302gem_config = {
+ 	.dma_burst_length = 16,
+ 	.clk_init = macb_clk_init,
+ 	.init = macb_init,
++	.usrio = &macb_default_usrio,
+ };
+ 
+ static const struct macb_config sama5d2_config = {
+@@ -4360,6 +4371,7 @@ static const struct macb_config sama5d2_config = {
+ 	.dma_burst_length = 16,
+ 	.clk_init = macb_clk_init,
+ 	.init = macb_init,
++	.usrio = &macb_default_usrio,
+ };
+ 
+ static const struct macb_config sama5d3_config = {
+@@ -4369,6 +4381,7 @@ static const struct macb_config sama5d3_config = {
+ 	.clk_init = macb_clk_init,
+ 	.init = macb_init,
+ 	.jumbo_max_len = 10240,
++	.usrio = &macb_default_usrio,
+ };
+ 
+ static const struct macb_config sama5d4_config = {
+@@ -4376,18 +4389,21 @@ static const struct macb_config sama5d4_config = {
+ 	.dma_burst_length = 4,
+ 	.clk_init = macb_clk_init,
+ 	.init = macb_init,
++	.usrio = &macb_default_usrio,
+ };
+ 
+ static const struct macb_config emac_config = {
+ 	.caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC,
+ 	.clk_init = at91ether_clk_init,
+ 	.init = at91ether_init,
++	.usrio = &macb_default_usrio,
+ };
+ 
+ static const struct macb_config np4_config = {
+ 	.caps = MACB_CAPS_USRIO_DISABLED,
+ 	.clk_init = macb_clk_init,
+ 	.init = macb_init,
++	.usrio = &macb_default_usrio,
+ };
+ 
+ static const struct macb_config zynqmp_config = {
+@@ -4398,6 +4414,7 @@ static const struct macb_config zynqmp_config = {
+ 	.clk_init = macb_clk_init,
+ 	.init = macb_init,
+ 	.jumbo_max_len = 10240,
++	.usrio = &macb_default_usrio,
+ };
+ 
+ static const struct macb_config zynq_config = {
+@@ -4406,6 +4423,7 @@ static const struct macb_config zynq_config = {
+ 	.dma_burst_length = 16,
+ 	.clk_init = macb_clk_init,
+ 	.init = macb_init,
++	.usrio = &macb_default_usrio,
+ };
+ 
+ static const struct of_device_id macb_dt_ids[] = {
+@@ -4527,6 +4545,8 @@ static int macb_probe(struct platform_device *pdev)
+ 		bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
+ 	device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
+ 
++	bp->usrio = macb_config->usrio;
++
+ 	spin_lock_init(&bp->lock);
+ 
+ 	/* setup capabilities */
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/116-net-macb-add-capability-to-not-set-the-clock-rate.patch

@@ -0,0 +1,92 @@
+From 1b15259551b701f416aa024050a2e619860bd0d8 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Wed, 9 Dec 2020 15:03:33 +0200
+Subject: [PATCH 116/247] net: macb: add capability to not set the clock rate
+
+SAMA7G5's ethernet IPs TX clock could be provided by its generic clock or
+by the external clock provided by the PHY. The internal IP logic divides
+properly this clock depending on the link speed. The patch adds a new
+capability so that macb_set_tx_clock() to not be called for IPs having
+this capability (the clock rate, in case of generic clock, is set at the
+boot time via device tree and the driver only enables it).
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Reviewed-by: Andrew Lunn <[email protected]>
+Signed-off-by: David S. Miller <[email protected]>
+---
+ drivers/net/ethernet/cadence/macb.h      |  1 +
+ drivers/net/ethernet/cadence/macb_main.c | 18 +++++++++---------
+ 2 files changed, 10 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
+index e9385a1390a9..23d294748779 100644
+--- a/drivers/net/ethernet/cadence/macb.h
++++ b/drivers/net/ethernet/cadence/macb.h
+@@ -658,6 +658,7 @@
+ #define MACB_CAPS_GEM_HAS_PTP			0x00000040
+ #define MACB_CAPS_BD_RD_PREFETCH		0x00000080
+ #define MACB_CAPS_NEEDS_RSTONUBR		0x00000100
++#define MACB_CAPS_CLK_HW_CHG			0x04000000
+ #define MACB_CAPS_MACB_IS_EMAC			0x08000000
+ #define MACB_CAPS_FIFO_MODE			0x10000000
+ #define MACB_CAPS_GIGABIT_MODE_AVAILABLE	0x20000000
+diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
+index a8326b75eca8..5d0d11eb6711 100644
+--- a/drivers/net/ethernet/cadence/macb_main.c
++++ b/drivers/net/ethernet/cadence/macb_main.c
+@@ -457,15 +457,14 @@ static void macb_init_buffers(struct macb *bp)
+ 
+ /**
+  * macb_set_tx_clk() - Set a clock to a new frequency
+- * @clk:	Pointer to the clock to change
++ * @bp:		pointer to struct macb
+  * @speed:	New frequency in Hz
+- * @dev:	Pointer to the struct net_device
+  */
+-static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
++static void macb_set_tx_clk(struct macb *bp, int speed)
+ {
+ 	long ferr, rate, rate_rounded;
+ 
+-	if (!clk)
++	if (!bp->tx_clk || !(bp->caps & MACB_CAPS_CLK_HW_CHG))
+ 		return;
+ 
+ 	switch (speed) {
+@@ -482,7 +481,7 @@ static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
+ 		return;
+ 	}
+ 
+-	rate_rounded = clk_round_rate(clk, rate);
++	rate_rounded = clk_round_rate(bp->tx_clk, rate);
+ 	if (rate_rounded < 0)
+ 		return;
+ 
+@@ -492,11 +491,12 @@ static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
+ 	ferr = abs(rate_rounded - rate);
+ 	ferr = DIV_ROUND_UP(ferr, rate / 100000);
+ 	if (ferr > 5)
+-		netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
++		netdev_warn(bp->dev,
++			    "unable to generate target frequency: %ld Hz\n",
+ 			    rate);
+ 
+-	if (clk_set_rate(clk, rate_rounded))
+-		netdev_err(dev, "adjusting tx_clk failed.\n");
++	if (clk_set_rate(bp->tx_clk, rate_rounded))
++		netdev_err(bp->dev, "adjusting tx_clk failed.\n");
+ }
+ 
+ static void macb_validate(struct phylink_config *config,
+@@ -649,7 +649,7 @@ static void macb_mac_link_up(struct phylink_config *config,
+ 		if (rx_pause)
+ 			ctrl |= MACB_BIT(PAE);
+ 
+-		macb_set_tx_clk(bp->tx_clk, speed, ndev);
++		macb_set_tx_clk(bp, speed);
+ 
+ 		/* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
+ 		 * cleared the pipeline and control registers.
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/117-net-macb-add-function-to-disable-all-macb-clocks.patch

@@ -0,0 +1,87 @@
+From 935d9aae15ee245a1bc6e322cbef02566a8996cc Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Wed, 9 Dec 2020 15:03:34 +0200
+Subject: [PATCH 117/247] net: macb: add function to disable all macb clocks
+
+Add function to disable all macb clocks.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Suggested-by: Andrew Lunn <[email protected]>
+Signed-off-by: David S. Miller <[email protected]>
+---
+ drivers/net/ethernet/cadence/macb_main.c | 38 +++++++++++++-----------
+ 1 file changed, 21 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
+index 5d0d11eb6711..eacf907a365d 100644
+--- a/drivers/net/ethernet/cadence/macb_main.c
++++ b/drivers/net/ethernet/cadence/macb_main.c
+@@ -3575,6 +3575,20 @@ static void macb_probe_queues(void __iomem *mem,
+ 	*num_queues = hweight32(*queue_mask);
+ }
+ 
++static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk,
++			      struct clk *rx_clk, struct clk *tsu_clk)
++{
++	struct clk_bulk_data clks[] = {
++		{ .clk = tsu_clk, },
++		{ .clk = rx_clk, },
++		{ .clk = pclk, },
++		{ .clk = hclk, },
++		{ .clk = tx_clk },
++	};
++
++	clk_bulk_disable_unprepare(ARRAY_SIZE(clks), clks);
++}
++
+ static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
+ 			 struct clk **hclk, struct clk **tx_clk,
+ 			 struct clk **rx_clk, struct clk **tsu_clk)
+@@ -4642,11 +4656,7 @@ static int macb_probe(struct platform_device *pdev)
+ 	free_netdev(dev);
+ 
+ err_disable_clocks:
+-	clk_disable_unprepare(tx_clk);
+-	clk_disable_unprepare(hclk);
+-	clk_disable_unprepare(pclk);
+-	clk_disable_unprepare(rx_clk);
+-	clk_disable_unprepare(tsu_clk);
++	macb_clks_disable(pclk, hclk, tx_clk, rx_clk, tsu_clk);
+ 	pm_runtime_disable(&pdev->dev);
+ 	pm_runtime_set_suspended(&pdev->dev);
+ 	pm_runtime_dont_use_autosuspend(&pdev->dev);
+@@ -4671,11 +4681,8 @@ static int macb_remove(struct platform_device *pdev)
+ 		pm_runtime_disable(&pdev->dev);
+ 		pm_runtime_dont_use_autosuspend(&pdev->dev);
+ 		if (!pm_runtime_suspended(&pdev->dev)) {
+-			clk_disable_unprepare(bp->tx_clk);
+-			clk_disable_unprepare(bp->hclk);
+-			clk_disable_unprepare(bp->pclk);
+-			clk_disable_unprepare(bp->rx_clk);
+-			clk_disable_unprepare(bp->tsu_clk);
++			macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk,
++					  bp->rx_clk, bp->tsu_clk);
+ 			pm_runtime_set_suspended(&pdev->dev);
+ 		}
+ 		phylink_destroy(bp->phylink);
+@@ -4854,13 +4861,10 @@ static int __maybe_unused macb_runtime_suspend(struct device *dev)
+ 	struct net_device *netdev = dev_get_drvdata(dev);
+ 	struct macb *bp = netdev_priv(netdev);
+ 
+-	if (!(device_may_wakeup(dev))) {
+-		clk_disable_unprepare(bp->tx_clk);
+-		clk_disable_unprepare(bp->hclk);
+-		clk_disable_unprepare(bp->pclk);
+-		clk_disable_unprepare(bp->rx_clk);
+-	}
+-	clk_disable_unprepare(bp->tsu_clk);
++	if (!(device_may_wakeup(dev)))
++		macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, bp->rx_clk, bp->tsu_clk);
++	else
++		macb_clks_disable(NULL, NULL, NULL, NULL, bp->tsu_clk);
+ 
+ 	return 0;
+ }
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/118-net-macb-unprepare-clocks-in-case-of-failure.patch

@@ -0,0 +1,65 @@
+From 9692c07ee8bf8f68b74d553d861d092e33264781 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Wed, 9 Dec 2020 15:03:35 +0200
+Subject: [PATCH 118/247] net: macb: unprepare clocks in case of failure
+
+Unprepare clocks in case of any failure in fu540_c000_clk_init().
+
+Fixes: c218ad559020 ("macb: Add support for SiFive FU540-C000")
+Signed-off-by: Claudiu Beznea <[email protected]>
+Signed-off-by: David S. Miller <[email protected]>
+---
+ drivers/net/ethernet/cadence/macb_main.c | 24 ++++++++++++++++++------
+ 1 file changed, 18 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
+index eacf907a365d..c8d66f966a8b 100644
+--- a/drivers/net/ethernet/cadence/macb_main.c
++++ b/drivers/net/ethernet/cadence/macb_main.c
+@@ -4307,8 +4307,10 @@ static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
+ 		return err;
+ 
+ 	mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
+-	if (!mgmt)
+-		return -ENOMEM;
++	if (!mgmt) {
++		err = -ENOMEM;
++		goto err_disable_clks;
++	}
+ 
+ 	init.name = "sifive-gemgxl-mgmt";
+ 	init.ops = &fu540_c000_ops;
+@@ -4319,16 +4321,26 @@ static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
+ 	mgmt->hw.init = &init;
+ 
+ 	*tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw);
+-	if (IS_ERR(*tx_clk))
+-		return PTR_ERR(*tx_clk);
++	if (IS_ERR(*tx_clk)) {
++		err = PTR_ERR(*tx_clk);
++		goto err_disable_clks;
++	}
+ 
+ 	err = clk_prepare_enable(*tx_clk);
+-	if (err)
++	if (err) {
+ 		dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
+-	else
++		*tx_clk = NULL;
++		goto err_disable_clks;
++	} else {
+ 		dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
++	}
+ 
+ 	return 0;
++
++err_disable_clks:
++	macb_clks_disable(*pclk, *hclk, *tx_clk, *rx_clk, *tsu_clk);
++
++	return err;
+ }
+ 
+ static int fu540_c000_init(struct platform_device *pdev)
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/119-net-macb-add-support-for-sama7g5-gem-interface.patch

@@ -0,0 +1,59 @@
+From 0085cd8576ceeaddeedf973b939b41ba96e3f77c Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Wed, 9 Dec 2020 15:03:38 +0200
+Subject: [PATCH 119/247] net: macb: add support for sama7g5 gem interface
+
+Add support for SAMA7G5 gigabit ethernet interface.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Reviewed-by: Andrew Lunn <[email protected]>
+Signed-off-by: David S. Miller <[email protected]>
+---
+ drivers/net/ethernet/cadence/macb_main.c | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
+index c8d66f966a8b..ebcc46d8aa9d 100644
+--- a/drivers/net/ethernet/cadence/macb_main.c
++++ b/drivers/net/ethernet/cadence/macb_main.c
+@@ -4359,6 +4359,14 @@ static const struct macb_usrio_config macb_default_usrio = {
+ 	.refclk = MACB_BIT(CLKEN),
+ };
+ 
++static const struct macb_usrio_config sama7g5_usrio = {
++	.mii = 0,
++	.rmii = 1,
++	.rgmii = 2,
++	.refclk = BIT(2),
++	.hdfctlen = BIT(6),
++};
++
+ static const struct macb_config fu540_c000_config = {
+ 	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
+ 		MACB_CAPS_GEM_HAS_PTP,
+@@ -4452,6 +4460,14 @@ static const struct macb_config zynq_config = {
+ 	.usrio = &macb_default_usrio,
+ };
+ 
++static const struct macb_config sama7g5_gem_config = {
++	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG,
++	.dma_burst_length = 16,
++	.clk_init = macb_clk_init,
++	.init = macb_init,
++	.usrio = &sama7g5_usrio,
++};
++
+ static const struct of_device_id macb_dt_ids[] = {
+ 	{ .compatible = "cdns,at32ap7000-macb" },
+ 	{ .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
+@@ -4469,6 +4485,7 @@ static const struct of_device_id macb_dt_ids[] = {
+ 	{ .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
+ 	{ .compatible = "cdns,zynq-gem", .data = &zynq_config },
+ 	{ .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
++	{ .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
+ 	{ /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, macb_dt_ids);
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/120-net-macb-add-support-for-sama7g5-emac-interface.patch

@@ -0,0 +1,44 @@
+From a42f90357cfcfcf5cdade4594ad79a1eae633a9f Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Wed, 9 Dec 2020 15:03:39 +0200
+Subject: [PATCH 120/247] net: macb: add support for sama7g5 emac interface
+
+Add support for SAMA7G5 10/100Mbps interface.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Reviewed-by: Andrew Lunn <[email protected]>
+Signed-off-by: David S. Miller <[email protected]>
+---
+ drivers/net/ethernet/cadence/macb_main.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
+index ebcc46d8aa9d..4ce302e03735 100644
+--- a/drivers/net/ethernet/cadence/macb_main.c
++++ b/drivers/net/ethernet/cadence/macb_main.c
+@@ -4468,6 +4468,14 @@ static const struct macb_config sama7g5_gem_config = {
+ 	.usrio = &sama7g5_usrio,
+ };
+ 
++static const struct macb_config sama7g5_emac_config = {
++	.caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_USRIO_HAS_CLKEN,
++	.dma_burst_length = 16,
++	.clk_init = macb_clk_init,
++	.init = macb_init,
++	.usrio = &sama7g5_usrio,
++};
++
+ static const struct of_device_id macb_dt_ids[] = {
+ 	{ .compatible = "cdns,at32ap7000-macb" },
+ 	{ .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
+@@ -4486,6 +4494,7 @@ static const struct of_device_id macb_dt_ids[] = {
+ 	{ .compatible = "cdns,zynq-gem", .data = &zynq_config },
+ 	{ .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
+ 	{ .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
++	{ .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
+ 	{ /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, macb_dt_ids);
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/121-ASoC-pcm5102a-Make-codec-selectable.patch

@@ -0,0 +1,33 @@
+From 5ac0e1f5577b266543756521b1a749003b0f3686 Mon Sep 17 00:00:00 2001
+From: Codrin Ciubotariu <[email protected]>
+Date: Mon, 12 Oct 2020 17:19:11 +0300
+Subject: [PATCH 121/247] ASoC: pcm5102a: Make codec selectable
+
+The TI PCM5102A codec driver can be used with the generic sound card
+drivers, so it should be selectable. For example, with the addition
+of #sound-dai-cells = <0> property in DT, it can be used with simple/graph
+card drivers.
+
+Signed-off-by: Codrin Ciubotariu <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Mark Brown <[email protected]>
+---
+ sound/soc/codecs/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
+index 34c6dd04b85a..5791b7056af6 100644
+--- a/sound/soc/codecs/Kconfig
++++ b/sound/soc/codecs/Kconfig
+@@ -1003,7 +1003,7 @@ config SND_SOC_PCM3168A_SPI
+ 	select REGMAP_SPI
+ 
+ config SND_SOC_PCM5102A
+-	tristate
++	tristate "Texas Instruments PCM5102A CODEC"
+ 
+ config SND_SOC_PCM512x
+ 	tristate
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/122-ASoC-atmel-i2s-do-not-warn-if-muxclk-is-missing.patch

@@ -0,0 +1,35 @@
+From f4389949bf422fe04775c17b833100fa0e95ea68 Mon Sep 17 00:00:00 2001
+From: Codrin Ciubotariu <[email protected]>
+Date: Tue, 3 Nov 2020 12:05:54 +0200
+Subject: [PATCH 122/247] ASoC: atmel-i2s: do not warn if muxclk is missing
+
+Besides the fact that muxclk is optional, muxclk can be set using
+assigned-clocks, removing the need to set it in driver. The warning is
+thus unneeded, so we can transform it in a debug print, eventually to just
+reflect that muxclk was not set by the driver.
+
+Signed-off-by: Codrin Ciubotariu <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Mark Brown <[email protected]>
+---
+ sound/soc/atmel/atmel-i2s.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/sound/soc/atmel/atmel-i2s.c b/sound/soc/atmel/atmel-i2s.c
+index d870f56c44cf..7483c474ccd7 100644
+--- a/sound/soc/atmel/atmel-i2s.c
++++ b/sound/soc/atmel/atmel-i2s.c
+@@ -581,8 +581,8 @@ static int atmel_i2s_sama5d2_mck_init(struct atmel_i2s_dev *dev,
+ 		err = PTR_ERR(muxclk);
+ 		if (err == -EPROBE_DEFER)
+ 			return -EPROBE_DEFER;
+-		dev_warn(dev->dev,
+-			 "failed to get the I2S clock control: %d\n", err);
++		dev_dbg(dev->dev,
++			"failed to get the I2S clock control: %d\n", err);
+ 		return 0;
+ 	}
+ 
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/123-regulator-mcp16502-add-linear_min_sel.patch

@@ -0,0 +1,30 @@
+From f5a73f3bb600b96b6149f2115360e1d0d51fbac4 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Fri, 13 Nov 2020 17:21:07 +0200
+Subject: [PATCH 123/247] regulator: mcp16502: add linear_min_sel
+
+Selectors b/w zero and VDD_LOW_SEL are not valid. Use linear_min_sel.
+
+Fixes: 919261c03e7ca ("regulator: mcp16502: add regulator driver for MCP16502")
+Signed-off-by: Claudiu Beznea <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Mark Brown <[email protected]>
+---
+ drivers/regulator/mcp16502.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/regulator/mcp16502.c b/drivers/regulator/mcp16502.c
+index 6d0ad74935b3..ab78f831f5bf 100644
+--- a/drivers/regulator/mcp16502.c
++++ b/drivers/regulator/mcp16502.c
+@@ -93,6 +93,7 @@ static unsigned int mcp16502_of_map_mode(unsigned int mode)
+ 		.owner			= THIS_MODULE,			\
+ 		.n_voltages		= MCP16502_VSEL + 1,		\
+ 		.linear_ranges		= _ranges,			\
++		.linear_min_sel		= VDD_LOW_SEL,			\
+ 		.n_linear_ranges	= ARRAY_SIZE(_ranges),		\
+ 		.of_match		= of_match_ptr(_name),		\
+ 		.of_map_mode		= mcp16502_of_map_mode,		\
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/124-regulator-mcp16502-adapt-for-get-set-on-other-regist.patch

@@ -0,0 +1,122 @@
+From 5295f4c122258a11fb6012b7e043248e681db5a2 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Fri, 13 Nov 2020 17:21:08 +0200
+Subject: [PATCH 124/247] regulator: mcp16502: adapt for get/set on other
+ registers
+
+MCP16502 have multiple registers for each regulator (as described
+in enum mcp16502_reg). Adapt the code to be able to get/set all these
+registers. This is necessary for the following commits.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Mark Brown <[email protected]>
+---
+ drivers/regulator/mcp16502.c | 43 ++++++++++++++++++++++--------------
+ 1 file changed, 27 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/regulator/mcp16502.c b/drivers/regulator/mcp16502.c
+index ab78f831f5bf..48eb64bc4018 100644
+--- a/drivers/regulator/mcp16502.c
++++ b/drivers/regulator/mcp16502.c
+@@ -54,13 +54,9 @@
+  * This function is useful for iterating over all regulators and accessing their
+  * registers in a generic way or accessing a regulator device by its id.
+  */
+-#define MCP16502_BASE(i) (((i) + 1) << 4)
++#define MCP16502_REG_BASE(i, r) ((((i) + 1) << 4) + MCP16502_REG_##r)
+ #define MCP16502_STAT_BASE(i) ((i) + 5)
+ 
+-#define MCP16502_OFFSET_MODE_A 0
+-#define MCP16502_OFFSET_MODE_LPM 1
+-#define MCP16502_OFFSET_MODE_HIB 2
+-
+ #define MCP16502_OPMODE_ACTIVE REGULATOR_MODE_NORMAL
+ #define MCP16502_OPMODE_LPM REGULATOR_MODE_IDLE
+ #define MCP16502_OPMODE_HIB REGULATOR_MODE_STANDBY
+@@ -75,6 +71,23 @@
+ #define MCP16502_MIN_REG 0x0
+ #define MCP16502_MAX_REG 0x65
+ 
++/**
++ * enum mcp16502_reg - MCP16502 regulators's registers
++ * @MCP16502_REG_A: active state register
++ * @MCP16502_REG_LPM: low power mode state register
++ * @MCP16502_REG_HIB: hibernate state register
++ * @MCP16502_REG_SEQ: startup sequence register
++ * @MCP16502_REG_CFG: configuration register
++ */
++enum mcp16502_reg {
++	MCP16502_REG_A,
++	MCP16502_REG_LPM,
++	MCP16502_REG_HIB,
++	MCP16502_REG_HPM,
++	MCP16502_REG_SEQ,
++	MCP16502_REG_CFG,
++};
++
+ static unsigned int mcp16502_of_map_mode(unsigned int mode)
+ {
+ 	if (mode == REGULATOR_MODE_NORMAL || mode == REGULATOR_MODE_IDLE)
+@@ -144,22 +157,20 @@ static void mcp16502_gpio_set_mode(struct mcp16502 *mcp, int mode)
+ }
+ 
+ /*
+- * mcp16502_get_reg() - get the PMIC's configuration register for opmode
++ * mcp16502_get_reg() - get the PMIC's state configuration register for opmode
+  *
+  * @rdev: the regulator whose register we are searching
+  * @opmode: the PMIC's operating mode ACTIVE, Low-power, Hibernate
+  */
+-static int mcp16502_get_reg(struct regulator_dev *rdev, int opmode)
++static int mcp16502_get_state_reg(struct regulator_dev *rdev, int opmode)
+ {
+-	int reg = MCP16502_BASE(rdev_get_id(rdev));
+-
+ 	switch (opmode) {
+ 	case MCP16502_OPMODE_ACTIVE:
+-		return reg + MCP16502_OFFSET_MODE_A;
++		return MCP16502_REG_BASE(rdev_get_id(rdev), A);
+ 	case MCP16502_OPMODE_LPM:
+-		return reg + MCP16502_OFFSET_MODE_LPM;
++		return MCP16502_REG_BASE(rdev_get_id(rdev), LPM);
+ 	case MCP16502_OPMODE_HIB:
+-		return reg + MCP16502_OFFSET_MODE_HIB;
++		return MCP16502_REG_BASE(rdev_get_id(rdev), HIB);
+ 	default:
+ 		return -EINVAL;
+ 	}
+@@ -179,7 +190,7 @@ static unsigned int mcp16502_get_mode(struct regulator_dev *rdev)
+ 	unsigned int val;
+ 	int ret, reg;
+ 
+-	reg = mcp16502_get_reg(rdev, MCP16502_OPMODE_ACTIVE);
++	reg = mcp16502_get_state_reg(rdev, MCP16502_OPMODE_ACTIVE);
+ 	if (reg < 0)
+ 		return reg;
+ 
+@@ -210,7 +221,7 @@ static int _mcp16502_set_mode(struct regulator_dev *rdev, unsigned int mode,
+ 	int val;
+ 	int reg;
+ 
+-	reg = mcp16502_get_reg(rdev, op_mode);
++	reg = mcp16502_get_state_reg(rdev, op_mode);
+ 	if (reg < 0)
+ 		return reg;
+ 
+@@ -269,10 +280,10 @@ static int mcp16502_suspend_get_target_reg(struct regulator_dev *rdev)
+ {
+ 	switch (pm_suspend_target_state) {
+ 	case PM_SUSPEND_STANDBY:
+-		return mcp16502_get_reg(rdev, MCP16502_OPMODE_LPM);
++		return mcp16502_get_state_reg(rdev, MCP16502_OPMODE_LPM);
+ 	case PM_SUSPEND_ON:
+ 	case PM_SUSPEND_MEM:
+-		return mcp16502_get_reg(rdev, MCP16502_OPMODE_HIB);
++		return mcp16502_get_state_reg(rdev, MCP16502_OPMODE_HIB);
+ 	default:
+ 		dev_err(&rdev->dev, "invalid suspend target: %d\n",
+ 			pm_suspend_target_state);
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/125-regulator-mcp16502-add-support-for-ramp-delay.patch

@@ -0,0 +1,146 @@
+From 7f13433e11a3c88f1fd6417c4c5e5a6c98370b9a Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Fri, 13 Nov 2020 17:21:09 +0200
+Subject: [PATCH 125/247] regulator: mcp16502: add support for ramp delay
+
+MCP16502 have configurable ramp delay support (via DVSR bits in
+regulators' CFG register).
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Mark Brown <[email protected]>
+---
+ drivers/regulator/mcp16502.c | 89 +++++++++++++++++++++++++++++++++++-
+ 1 file changed, 87 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/regulator/mcp16502.c b/drivers/regulator/mcp16502.c
+index 48eb64bc4018..f81afeeddb19 100644
+--- a/drivers/regulator/mcp16502.c
++++ b/drivers/regulator/mcp16502.c
+@@ -22,8 +22,9 @@
+ #define VDD_LOW_SEL 0x0D
+ #define VDD_HIGH_SEL 0x3F
+ 
+-#define MCP16502_FLT BIT(7)
+-#define MCP16502_ENS BIT(0)
++#define MCP16502_FLT		BIT(7)
++#define MCP16502_DVSR		GENMASK(3, 2)
++#define MCP16502_ENS		BIT(0)
+ 
+ /*
+  * The PMIC has four sets of registers corresponding to four power modes:
+@@ -88,6 +89,12 @@ enum mcp16502_reg {
+ 	MCP16502_REG_CFG,
+ };
+ 
++/* Ramp delay (uV/us) for buck1, ldo1, ldo2. */
++static const int mcp16502_ramp_b1l12[] = { 6250, 3125, 2083, 1563 };
++
++/* Ramp delay (uV/us) for buck2, buck3, buck4. */
++static const int mcp16502_ramp_b234[] = { 3125, 1563, 1042, 781 };
++
+ static unsigned int mcp16502_of_map_mode(unsigned int mode)
+ {
+ 	if (mode == REGULATOR_MODE_NORMAL || mode == REGULATOR_MODE_IDLE)
+@@ -271,6 +278,80 @@ static int mcp16502_get_status(struct regulator_dev *rdev)
+ 	return REGULATOR_STATUS_UNDEFINED;
+ }
+ 
++static int mcp16502_set_voltage_time_sel(struct regulator_dev *rdev,
++					 unsigned int old_sel,
++					 unsigned int new_sel)
++{
++	static const u8 us_ramp[] = { 8, 16, 24, 32 };
++	int id = rdev_get_id(rdev);
++	unsigned int uV_delta, val;
++	int ret;
++
++	ret = regmap_read(rdev->regmap, MCP16502_REG_BASE(id, CFG), &val);
++	if (ret)
++		return ret;
++
++	val = (val & MCP16502_DVSR) >> 2;
++	uV_delta = abs(new_sel * rdev->desc->linear_ranges->step -
++		       old_sel * rdev->desc->linear_ranges->step);
++	switch (id) {
++	case BUCK1:
++	case LDO1:
++	case LDO2:
++		ret = DIV_ROUND_CLOSEST(uV_delta * us_ramp[val],
++					mcp16502_ramp_b1l12[val]);
++		break;
++
++	case BUCK2:
++	case BUCK3:
++	case BUCK4:
++		ret = DIV_ROUND_CLOSEST(uV_delta * us_ramp[val],
++					mcp16502_ramp_b234[val]);
++		break;
++
++	default:
++		return -EINVAL;
++	}
++
++	return ret;
++}
++
++static int mcp16502_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
++{
++	const int *ramp;
++	int id = rdev_get_id(rdev);
++	unsigned int i, size;
++
++	switch (id) {
++	case BUCK1:
++	case LDO1:
++	case LDO2:
++		ramp = mcp16502_ramp_b1l12;
++		size = ARRAY_SIZE(mcp16502_ramp_b1l12);
++		break;
++
++	case BUCK2:
++	case BUCK3:
++	case BUCK4:
++		ramp = mcp16502_ramp_b234;
++		size = ARRAY_SIZE(mcp16502_ramp_b234);
++		break;
++
++	default:
++		return -EINVAL;
++	}
++
++	for (i = 0; i < size; i++) {
++		if (ramp[i] == ramp_delay)
++			break;
++	}
++	if (i == size)
++		return -EINVAL;
++
++	return regmap_update_bits(rdev->regmap, MCP16502_REG_BASE(id, CFG),
++				  MCP16502_DVSR, (i << 2));
++}
++
+ #ifdef CONFIG_SUSPEND
+ /*
+  * mcp16502_suspend_get_target_reg() - get the reg of the target suspend PMIC
+@@ -365,6 +446,8 @@ static const struct regulator_ops mcp16502_buck_ops = {
+ 	.disable			= regulator_disable_regmap,
+ 	.is_enabled			= regulator_is_enabled_regmap,
+ 	.get_status			= mcp16502_get_status,
++	.set_voltage_time_sel		= mcp16502_set_voltage_time_sel,
++	.set_ramp_delay			= mcp16502_set_ramp_delay,
+ 
+ 	.set_mode			= mcp16502_set_mode,
+ 	.get_mode			= mcp16502_get_mode,
+@@ -389,6 +472,8 @@ static const struct regulator_ops mcp16502_ldo_ops = {
+ 	.disable			= regulator_disable_regmap,
+ 	.is_enabled			= regulator_is_enabled_regmap,
+ 	.get_status			= mcp16502_get_status,
++	.set_voltage_time_sel		= mcp16502_set_voltage_time_sel,
++	.set_ramp_delay			= mcp16502_set_ramp_delay,
+ 
+ #ifdef CONFIG_SUSPEND
+ 	.set_suspend_voltage		= mcp16502_set_suspend_voltage,
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/126-regulator-mcp16502-remove-void-documentation-of-stru.patch

@@ -0,0 +1,32 @@
+From 8dcbcb052f682478dcbfa7fc9abdd909e1deab87 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Fri, 13 Nov 2020 17:21:10 +0200
+Subject: [PATCH 126/247] regulator: mcp16502: remove void documentation of
+ struct mcp16502
+
+struct mcp16502 has no members called rdev or rmap. Remove the
+documentation.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Mark Brown <[email protected]>
+---
+ drivers/regulator/mcp16502.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/regulator/mcp16502.c b/drivers/regulator/mcp16502.c
+index f81afeeddb19..74ad92dc664a 100644
+--- a/drivers/regulator/mcp16502.c
++++ b/drivers/regulator/mcp16502.c
+@@ -135,8 +135,6 @@ enum {
+ 
+ /*
+  * struct mcp16502 - PMIC representation
+- * @rdev: the regulators belonging to this chip
+- * @rmap: regmap to be used for I2C communication
+  * @lpm: LPM GPIO descriptor
+  */
+ struct mcp16502 {
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/127-regulator-core-validate-selector-against-linear_min_.patch

@@ -0,0 +1,71 @@
+From 3aee4f22ed0a22d3d6d22fc49812c03d876c7637 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Fri, 13 Nov 2020 17:21:05 +0200
+Subject: [PATCH 127/247] regulator: core: validate selector against
+ linear_min_sel
+
+There are regulators who's min selector is not zero. Selectors loops
+(looping b/w zero and regulator::desc::n_voltages) might throw errors
+because invalid selectors are used (lower than
+regulator::desc::linear_min_sel). For this situations validate selectors
+against regulator::desc::linear_min_sel.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Mark Brown <[email protected]>
+---
+ drivers/regulator/core.c    | 9 +++++++--
+ drivers/regulator/helpers.c | 3 ++-
+ 2 files changed, 9 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
+index 043b5f63b94a..dfdd42b9d773 100644
+--- a/drivers/regulator/core.c
++++ b/drivers/regulator/core.c
+@@ -2984,7 +2984,8 @@ static int _regulator_list_voltage(struct regulator_dev *rdev,
+ 		return rdev->desc->fixed_uV;
+ 
+ 	if (ops->list_voltage) {
+-		if (selector >= rdev->desc->n_voltages)
++		if (selector >= rdev->desc->n_voltages ||
++		    selector < rdev->desc->linear_min_sel)
+ 			return -EINVAL;
+ 		if (lock)
+ 			regulator_lock(rdev);
+@@ -3135,7 +3136,8 @@ int regulator_list_hardware_vsel(struct regulator *regulator,
+ 	struct regulator_dev *rdev = regulator->rdev;
+ 	const struct regulator_ops *ops = rdev->desc->ops;
+ 
+-	if (selector >= rdev->desc->n_voltages)
++	if (selector >= rdev->desc->n_voltages ||
++	    selector < rdev->desc->linear_min_sel)
+ 		return -EINVAL;
+ 	if (ops->set_voltage_sel != regulator_set_voltage_sel_regmap)
+ 		return -EOPNOTSUPP;
+@@ -4058,6 +4060,9 @@ int regulator_set_voltage_time(struct regulator *regulator,
+ 
+ 	for (i = 0; i < rdev->desc->n_voltages; i++) {
+ 		/* We only look for exact voltage matches here */
++		if (i < rdev->desc->linear_min_sel)
++			continue;
++
+ 		voltage = regulator_list_voltage(regulator, i);
+ 		if (voltage < 0)
+ 			return -EINVAL;
+diff --git a/drivers/regulator/helpers.c b/drivers/regulator/helpers.c
+index e4bb09bbd3fa..974f1a63993d 100644
+--- a/drivers/regulator/helpers.c
++++ b/drivers/regulator/helpers.c
+@@ -647,7 +647,8 @@ int regulator_list_voltage_table(struct regulator_dev *rdev,
+ 		return -EINVAL;
+ 	}
+ 
+-	if (selector >= rdev->desc->n_voltages)
++	if (selector >= rdev->desc->n_voltages ||
++	    selector < rdev->desc->linear_min_sel)
+ 		return -EINVAL;
+ 
+ 	return rdev->desc->volt_table[selector];
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/128-regulator-core-do-not-continue-if-selector-match.patch

@@ -0,0 +1,31 @@
+From 42b56e8bd343f34d5f2a601d8a8a05d8c861c08c Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Fri, 13 Nov 2020 19:56:04 +0200
+Subject: [PATCH 128/247] regulator: core: do not continue if selector match
+
+Do not continue if selector has already been located.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Mark Brown <[email protected]>
+---
+ drivers/regulator/core.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
+index dfdd42b9d773..0b7a23cdbcac 100644
+--- a/drivers/regulator/core.c
++++ b/drivers/regulator/core.c
+@@ -4063,6 +4063,9 @@ int regulator_set_voltage_time(struct regulator *regulator,
+ 		if (i < rdev->desc->linear_min_sel)
+ 			continue;
+ 
++		if (old_sel >= 0 && new_sel >= 0)
++			break;
++
+ 		voltage = regulator_list_voltage(regulator, i);
+ 		if (voltage < 0)
+ 			return -EINVAL;
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/129-regulator-core-return-zero-for-selectors-lower-than-.patch

@@ -0,0 +1,71 @@
+From 0e933ffc049a0e181b5a6c3af1933976d6959ba9 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Wed, 25 Nov 2020 19:25:47 +0200
+Subject: [PATCH 129/247] regulator: core: return zero for selectors lower than
+ linear_min_sel
+
+Selectors lower than linear_min_sel should not be considered invalid.
+Thus return zero in case _regulator_list_voltage(),
+regulator_list_hardware_vsel() or regulator_list_voltage_table()
+receives such selectors as argument.
+
+Fixes: bdcd1177578c ("regulator: core: validate selector against linear_min_sel")
+Reported-by: Jon Hunter <[email protected]>
+Signed-off-by: Claudiu Beznea <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Mark Brown <[email protected]>
+---
+ drivers/regulator/core.c    | 10 ++++++----
+ drivers/regulator/helpers.c |  5 +++--
+ 2 files changed, 9 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
+index 0b7a23cdbcac..65ecf872b4e0 100644
+--- a/drivers/regulator/core.c
++++ b/drivers/regulator/core.c
+@@ -2984,9 +2984,10 @@ static int _regulator_list_voltage(struct regulator_dev *rdev,
+ 		return rdev->desc->fixed_uV;
+ 
+ 	if (ops->list_voltage) {
+-		if (selector >= rdev->desc->n_voltages ||
+-		    selector < rdev->desc->linear_min_sel)
++		if (selector >= rdev->desc->n_voltages)
+ 			return -EINVAL;
++		if (selector < rdev->desc->linear_min_sel)
++			return 0;
+ 		if (lock)
+ 			regulator_lock(rdev);
+ 		ret = ops->list_voltage(rdev, selector);
+@@ -3136,9 +3137,10 @@ int regulator_list_hardware_vsel(struct regulator *regulator,
+ 	struct regulator_dev *rdev = regulator->rdev;
+ 	const struct regulator_ops *ops = rdev->desc->ops;
+ 
+-	if (selector >= rdev->desc->n_voltages ||
+-	    selector < rdev->desc->linear_min_sel)
++	if (selector >= rdev->desc->n_voltages)
+ 		return -EINVAL;
++	if (selector < rdev->desc->linear_min_sel)
++		return 0;
+ 	if (ops->set_voltage_sel != regulator_set_voltage_sel_regmap)
+ 		return -EOPNOTSUPP;
+ 
+diff --git a/drivers/regulator/helpers.c b/drivers/regulator/helpers.c
+index 974f1a63993d..f42b394a0c46 100644
+--- a/drivers/regulator/helpers.c
++++ b/drivers/regulator/helpers.c
+@@ -647,9 +647,10 @@ int regulator_list_voltage_table(struct regulator_dev *rdev,
+ 		return -EINVAL;
+ 	}
+ 
+-	if (selector >= rdev->desc->n_voltages ||
+-	    selector < rdev->desc->linear_min_sel)
++	if (selector >= rdev->desc->n_voltages)
+ 		return -EINVAL;
++	if (selector < rdev->desc->linear_min_sel)
++		return 0;
+ 
+ 	return rdev->desc->volt_table[selector];
+ }
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/130-regulator-mcp16502-lpm-pin-can-be-optional-on-some-p.patch

@@ -0,0 +1,35 @@
+From 763fe72f607d4e929d2c710c88e5c6978dd6ad97 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Thu, 7 Jan 2021 16:15:26 +0200
+Subject: [PATCH 130/247] regulator: mcp16502: lpm pin can be optional on some
+ platforms
+
+On some platform (e.g. SAMA7G5) LPM pin should be optional as it can
+be controlled explicitly (via shutdown controller registers) in the
+platform specific power saving code to decrease the power consumption
+while suspended as this SoC pin may be connected to other devices that
+could take power saving actions based on its value.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Mark Brown <[email protected]>
+---
+ drivers/regulator/mcp16502.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/regulator/mcp16502.c b/drivers/regulator/mcp16502.c
+index 74ad92dc664a..88c6bd5b6c78 100644
+--- a/drivers/regulator/mcp16502.c
++++ b/drivers/regulator/mcp16502.c
+@@ -550,7 +550,7 @@ static int mcp16502_probe(struct i2c_client *client,
+ 	config.regmap = rmap;
+ 	config.driver_data = mcp;
+ 
+-	mcp->lpm = devm_gpiod_get(dev, "lpm", GPIOD_OUT_LOW);
++	mcp->lpm = devm_gpiod_get_optional(dev, "lpm", GPIOD_OUT_LOW);
+ 	if (IS_ERR(mcp->lpm)) {
+ 		dev_err(dev, "failed to get lpm pin: %ld\n", PTR_ERR(mcp->lpm));
+ 		return PTR_ERR(mcp->lpm);
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/131-pinctrl-at91-pio4-add-support-for-fewer-lines-on-las.patch

@@ -0,0 +1,75 @@
+From 7cb1dad7a7dfe4cfe55ebe86930dd6aef0de66b4 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Fri, 13 Nov 2020 15:24:29 +0200
+Subject: [PATCH 131/247] pinctrl: at91-pio4: add support for fewer lines on
+ last PIO bank
+
+Some products, like sama7g5, do not have a full last bank of PIO lines.
+In this case for example, sama7g5 only has 8 lines for the PE bank.
+PA0-31, PB0-31, PC0-31, PD0-31, PE0-7, in total 136 lines.
+To cope with this situation, added a data attribute that is product dependent,
+to specify the number of lines of the last bank.
+In case this number is different from the macro ATMEL_PIO_NPINS_PER_BANK,
+adjust the total number of lines accordingly.
+This will avoid advertising 160 lines instead of the actual 136, as this
+product supports, and to avoid reading/writing to invalid register addresses.
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Acked-by: Ludovic Desroches <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Linus Walleij <[email protected]>
+---
+ drivers/pinctrl/pinctrl-at91-pio4.c | 18 ++++++++++++++++--
+ 1 file changed, 16 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c
+index 578b387100d9..d267367d94b9 100644
+--- a/drivers/pinctrl/pinctrl-at91-pio4.c
++++ b/drivers/pinctrl/pinctrl-at91-pio4.c
+@@ -71,8 +71,15 @@
+ /* Custom pinconf parameters */
+ #define ATMEL_PIN_CONFIG_DRIVE_STRENGTH	(PIN_CONFIG_END + 1)
+ 
++/**
++ * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
++ * @nbanks: number of PIO banks
++ * @last_bank_count: number of lines in the last bank (can be less than
++ *	the rest of the banks).
++ */
+ struct atmel_pioctrl_data {
+ 	unsigned nbanks;
++	unsigned last_bank_count;
+ };
+ 
+ struct atmel_group {
+@@ -980,11 +987,13 @@ static const struct dev_pm_ops atmel_pctrl_pm_ops = {
+  * We can have up to 16 banks.
+  */
+ static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
+-	.nbanks		= 4,
++	.nbanks			= 4,
++	.last_bank_count	= ATMEL_PIO_NPINS_PER_BANK,
+ };
+ 
+ static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
+-	.nbanks		= 5,
++	.nbanks			= 5,
++	.last_bank_count	= 8, /* sama7g5 has only PE0 to PE7 */
+ };
+ 
+ static const struct of_device_id atmel_pctrl_of_match[] = {
+@@ -1025,6 +1034,11 @@ static int atmel_pinctrl_probe(struct platform_device *pdev)
+ 	atmel_pioctrl_data = match->data;
+ 	atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
+ 	atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
++	/* if last bank has limited number of pins, adjust accordingly */
++	if (atmel_pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) {
++		atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK;
++		atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count;
++	}
+ 
+ 	atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
+ 	if (IS_ERR(atmel_pioctrl->reg_base))
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/132-dmaengine-at_xdmac-adapt-perid-for-mem2mem-operation.patch

@@ -0,0 +1,55 @@
+From 1dccaa4c1e99cd8bd27684a2c87ec806d426c088 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Fri, 16 Oct 2020 12:37:25 +0300
+Subject: [PATCH 132/247] dmaengine: at_xdmac: adapt perid for mem2mem
+ operations
+
+The PERID in the CC register for mem2mem operations must match an unused
+PERID.
+The PERID field is 7 bits, but the selected value is 0x3f.
+On later products we can have more reserved PERIDs for actual peripherals,
+thus this needs to be increased to maximum size.
+Changing the value to 0x7f, which is the maximum for 7 bits field.
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Reviewed-by: Tudor Ambarus <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Vinod Koul <[email protected]>
+---
+ drivers/dma/at_xdmac.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
+index 90afba0b36fe..85fe260ccd07 100644
+--- a/drivers/dma/at_xdmac.c
++++ b/drivers/dma/at_xdmac.c
+@@ -865,7 +865,7 @@ at_xdmac_interleaved_queue_desc(struct dma_chan *chan,
+ 	 * match the one of another channel. If not, it could lead to spurious
+ 	 * flag status.
+ 	 */
+-	u32			chan_cc = AT_XDMAC_CC_PERID(0x3f)
++	u32			chan_cc = AT_XDMAC_CC_PERID(0x7f)
+ 					| AT_XDMAC_CC_DIF(0)
+ 					| AT_XDMAC_CC_SIF(0)
+ 					| AT_XDMAC_CC_MBSIZE_SIXTEEN
+@@ -1047,7 +1047,7 @@ at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
+ 	 * match the one of another channel. If not, it could lead to spurious
+ 	 * flag status.
+ 	 */
+-	u32			chan_cc = AT_XDMAC_CC_PERID(0x3f)
++	u32			chan_cc = AT_XDMAC_CC_PERID(0x7f)
+ 					| AT_XDMAC_CC_DAM_INCREMENTED_AM
+ 					| AT_XDMAC_CC_SAM_INCREMENTED_AM
+ 					| AT_XDMAC_CC_DIF(0)
+@@ -1153,7 +1153,7 @@ static struct at_xdmac_desc *at_xdmac_memset_create_desc(struct dma_chan *chan,
+ 	 * match the one of another channel. If not, it could lead to spurious
+ 	 * flag status.
+ 	 */
+-	u32			chan_cc = AT_XDMAC_CC_PERID(0x3f)
++	u32			chan_cc = AT_XDMAC_CC_PERID(0x7f)
+ 					| AT_XDMAC_CC_DAM_UBS_AM
+ 					| AT_XDMAC_CC_SAM_INCREMENTED_AM
+ 					| AT_XDMAC_CC_DIF(0)
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/133-dmaengine-at_xdmac-add-support-for-sama7g5-based-at_.patch

@@ -0,0 +1,285 @@
+From 613af756b93fe005d9db11ea26fd0318f239d5a2 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Fri, 16 Oct 2020 12:38:50 +0300
+Subject: [PATCH 133/247] dmaengine: at_xdmac: add support for sama7g5 based
+ at_xdmac
+
+SAMA7G5 SoC uses a slightly different variant of the AT_XDMAC.
+Added support by a new compatible and a layout struct that copes
+to the specific version considering the compatible string.
+Only the differences in register map are present in the layout struct.
+I reworked the register access for this part that has the differences.
+Also the Source/Destination Interface bits are no longer valid for this
+variant of the XDMAC. Thus, the layout also has a bool for specifying
+whether these bits are required or not.
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Vinod Koul <[email protected]>
+---
+ drivers/dma/at_xdmac.c | 110 +++++++++++++++++++++++++++++++----------
+ 1 file changed, 84 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
+index 85fe260ccd07..2b096ea04018 100644
+--- a/drivers/dma/at_xdmac.c
++++ b/drivers/dma/at_xdmac.c
+@@ -38,13 +38,6 @@
+ #define AT_XDMAC_GE		0x1C	/* Global Channel Enable Register */
+ #define AT_XDMAC_GD		0x20	/* Global Channel Disable Register */
+ #define AT_XDMAC_GS		0x24	/* Global Channel Status Register */
+-#define AT_XDMAC_GRS		0x28	/* Global Channel Read Suspend Register */
+-#define AT_XDMAC_GWS		0x2C	/* Global Write Suspend Register */
+-#define AT_XDMAC_GRWS		0x30	/* Global Channel Read Write Suspend Register */
+-#define AT_XDMAC_GRWR		0x34	/* Global Channel Read Write Resume Register */
+-#define AT_XDMAC_GSWR		0x38	/* Global Channel Software Request Register */
+-#define AT_XDMAC_GSWS		0x3C	/* Global channel Software Request Status Register */
+-#define AT_XDMAC_GSWF		0x40	/* Global Channel Software Flush Request Register */
+ #define AT_XDMAC_VERSION	0xFFC	/* XDMAC Version Register */
+ 
+ /* Channel relative registers offsets */
+@@ -151,8 +144,6 @@
+ #define AT_XDMAC_CSUS		0x30	/* Channel Source Microblock Stride */
+ #define AT_XDMAC_CDUS		0x34	/* Channel Destination Microblock Stride */
+ 
+-#define AT_XDMAC_CHAN_REG_BASE	0x50	/* Channel registers base address */
+-
+ /* Microblock control members */
+ #define AT_XDMAC_MBR_UBC_UBLEN_MAX	0xFFFFFFUL	/* Maximum Microblock Length */
+ #define AT_XDMAC_MBR_UBC_NDE		(0x1 << 24)	/* Next Descriptor Enable */
+@@ -180,6 +171,27 @@ enum atc_status {
+ 	AT_XDMAC_CHAN_IS_PAUSED,
+ };
+ 
++struct at_xdmac_layout {
++	/* Global Channel Read Suspend Register */
++	u8				grs;
++	/* Global Write Suspend Register */
++	u8				gws;
++	/* Global Channel Read Write Suspend Register */
++	u8				grws;
++	/* Global Channel Read Write Resume Register */
++	u8				grwr;
++	/* Global Channel Software Request Register */
++	u8				gswr;
++	/* Global channel Software Request Status Register */
++	u8				gsws;
++	/* Global Channel Software Flush Request Register */
++	u8				gswf;
++	/* Channel reg base */
++	u8				chan_cc_reg_base;
++	/* Source/Destination Interface must be specified or not */
++	bool				sdif;
++};
++
+ /* ----- Channels ----- */
+ struct at_xdmac_chan {
+ 	struct dma_chan			chan;
+@@ -213,6 +225,7 @@ struct at_xdmac {
+ 	struct clk		*clk;
+ 	u32			save_gim;
+ 	struct dma_pool		*at_xdmac_desc_pool;
++	const struct at_xdmac_layout	*layout;
+ 	struct at_xdmac_chan	chan[];
+ };
+ 
+@@ -245,9 +258,33 @@ struct at_xdmac_desc {
+ 	struct list_head		xfer_node;
+ } __aligned(sizeof(u64));
+ 
++static const struct at_xdmac_layout at_xdmac_sama5d4_layout = {
++	.grs = 0x28,
++	.gws = 0x2C,
++	.grws = 0x30,
++	.grwr = 0x34,
++	.gswr = 0x38,
++	.gsws = 0x3C,
++	.gswf = 0x40,
++	.chan_cc_reg_base = 0x50,
++	.sdif = true,
++};
++
++static const struct at_xdmac_layout at_xdmac_sama7g5_layout = {
++	.grs = 0x30,
++	.gws = 0x38,
++	.grws = 0x40,
++	.grwr = 0x44,
++	.gswr = 0x48,
++	.gsws = 0x4C,
++	.gswf = 0x50,
++	.chan_cc_reg_base = 0x60,
++	.sdif = false,
++};
++
+ static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)
+ {
+-	return atxdmac->regs + (AT_XDMAC_CHAN_REG_BASE + chan_nb * 0x40);
++	return atxdmac->regs + (atxdmac->layout->chan_cc_reg_base + chan_nb * 0x40);
+ }
+ 
+ #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg))
+@@ -343,8 +380,10 @@ static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan,
+ 	first->active_xfer = true;
+ 
+ 	/* Tell xdmac where to get the first descriptor. */
+-	reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys)
+-	      | AT_XDMAC_CNDA_NDAIF(atchan->memif);
++	reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys);
++	if (atxdmac->layout->sdif)
++		reg |= AT_XDMAC_CNDA_NDAIF(atchan->memif);
++
+ 	at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg);
+ 
+ 	/*
+@@ -539,6 +578,7 @@ static int at_xdmac_compute_chan_conf(struct dma_chan *chan,
+ 				      enum dma_transfer_direction direction)
+ {
+ 	struct at_xdmac_chan	*atchan = to_at_xdmac_chan(chan);
++	struct at_xdmac		*atxdmac = to_at_xdmac(atchan->chan.device);
+ 	int			csize, dwidth;
+ 
+ 	if (direction == DMA_DEV_TO_MEM) {
+@@ -546,12 +586,14 @@ static int at_xdmac_compute_chan_conf(struct dma_chan *chan,
+ 			AT91_XDMAC_DT_PERID(atchan->perid)
+ 			| AT_XDMAC_CC_DAM_INCREMENTED_AM
+ 			| AT_XDMAC_CC_SAM_FIXED_AM
+-			| AT_XDMAC_CC_DIF(atchan->memif)
+-			| AT_XDMAC_CC_SIF(atchan->perif)
+ 			| AT_XDMAC_CC_SWREQ_HWR_CONNECTED
+ 			| AT_XDMAC_CC_DSYNC_PER2MEM
+ 			| AT_XDMAC_CC_MBSIZE_SIXTEEN
+ 			| AT_XDMAC_CC_TYPE_PER_TRAN;
++		if (atxdmac->layout->sdif)
++			atchan->cfg |= AT_XDMAC_CC_DIF(atchan->memif) |
++				       AT_XDMAC_CC_SIF(atchan->perif);
++
+ 		csize = ffs(atchan->sconfig.src_maxburst) - 1;
+ 		if (csize < 0) {
+ 			dev_err(chan2dev(chan), "invalid src maxburst value\n");
+@@ -569,12 +611,14 @@ static int at_xdmac_compute_chan_conf(struct dma_chan *chan,
+ 			AT91_XDMAC_DT_PERID(atchan->perid)
+ 			| AT_XDMAC_CC_DAM_FIXED_AM
+ 			| AT_XDMAC_CC_SAM_INCREMENTED_AM
+-			| AT_XDMAC_CC_DIF(atchan->perif)
+-			| AT_XDMAC_CC_SIF(atchan->memif)
+ 			| AT_XDMAC_CC_SWREQ_HWR_CONNECTED
+ 			| AT_XDMAC_CC_DSYNC_MEM2PER
+ 			| AT_XDMAC_CC_MBSIZE_SIXTEEN
+ 			| AT_XDMAC_CC_TYPE_PER_TRAN;
++		if (atxdmac->layout->sdif)
++			atchan->cfg |= AT_XDMAC_CC_DIF(atchan->perif) |
++				       AT_XDMAC_CC_SIF(atchan->memif);
++
+ 		csize = ffs(atchan->sconfig.dst_maxburst) - 1;
+ 		if (csize < 0) {
+ 			dev_err(chan2dev(chan), "invalid src maxburst value\n");
+@@ -864,10 +908,12 @@ at_xdmac_interleaved_queue_desc(struct dma_chan *chan,
+ 	 * ERRATA: Even if useless for memory transfers, the PERID has to not
+ 	 * match the one of another channel. If not, it could lead to spurious
+ 	 * flag status.
++	 * For SAMA7G5x case, the SIF and DIF fields are no longer used.
++	 * Thus, no need to have the SIF/DIF interfaces here.
++	 * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as
++	 * zero.
+ 	 */
+ 	u32			chan_cc = AT_XDMAC_CC_PERID(0x7f)
+-					| AT_XDMAC_CC_DIF(0)
+-					| AT_XDMAC_CC_SIF(0)
+ 					| AT_XDMAC_CC_MBSIZE_SIXTEEN
+ 					| AT_XDMAC_CC_TYPE_MEM_TRAN;
+ 
+@@ -1046,12 +1092,14 @@ at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
+ 	 * ERRATA: Even if useless for memory transfers, the PERID has to not
+ 	 * match the one of another channel. If not, it could lead to spurious
+ 	 * flag status.
++	 * For SAMA7G5x case, the SIF and DIF fields are no longer used.
++	 * Thus, no need to have the SIF/DIF interfaces here.
++	 * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as
++	 * zero.
+ 	 */
+ 	u32			chan_cc = AT_XDMAC_CC_PERID(0x7f)
+ 					| AT_XDMAC_CC_DAM_INCREMENTED_AM
+ 					| AT_XDMAC_CC_SAM_INCREMENTED_AM
+-					| AT_XDMAC_CC_DIF(0)
+-					| AT_XDMAC_CC_SIF(0)
+ 					| AT_XDMAC_CC_MBSIZE_SIXTEEN
+ 					| AT_XDMAC_CC_TYPE_MEM_TRAN;
+ 	unsigned long		irqflags;
+@@ -1152,12 +1200,14 @@ static struct at_xdmac_desc *at_xdmac_memset_create_desc(struct dma_chan *chan,
+ 	 * ERRATA: Even if useless for memory transfers, the PERID has to not
+ 	 * match the one of another channel. If not, it could lead to spurious
+ 	 * flag status.
++	 * For SAMA7G5x case, the SIF and DIF fields are no longer used.
++	 * Thus, no need to have the SIF/DIF interfaces here.
++	 * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as
++	 * zero.
+ 	 */
+ 	u32			chan_cc = AT_XDMAC_CC_PERID(0x7f)
+ 					| AT_XDMAC_CC_DAM_UBS_AM
+ 					| AT_XDMAC_CC_SAM_INCREMENTED_AM
+-					| AT_XDMAC_CC_DIF(0)
+-					| AT_XDMAC_CC_SIF(0)
+ 					| AT_XDMAC_CC_MBSIZE_SIXTEEN
+ 					| AT_XDMAC_CC_MEMSET_HW_MODE
+ 					| AT_XDMAC_CC_TYPE_MEM_TRAN;
+@@ -1436,7 +1486,7 @@ at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
+ 	mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC;
+ 	value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM;
+ 	if ((desc->lld.mbr_cfg & mask) == value) {
+-		at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);
++		at_xdmac_write(atxdmac, atxdmac->layout->gswf, atchan->mask);
+ 		while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
+ 			cpu_relax();
+ 	}
+@@ -1494,7 +1544,7 @@ at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
+ 	 * FIFO flush ensures that data are really written.
+ 	 */
+ 	if ((desc->lld.mbr_cfg & mask) == value) {
+-		at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);
++		at_xdmac_write(atxdmac, atxdmac->layout->gswf, atchan->mask);
+ 		while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
+ 			cpu_relax();
+ 	}
+@@ -1760,7 +1810,7 @@ static int at_xdmac_device_pause(struct dma_chan *chan)
+ 		return 0;
+ 
+ 	spin_lock_irqsave(&atchan->lock, flags);
+-	at_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask);
++	at_xdmac_write(atxdmac, atxdmac->layout->grws, atchan->mask);
+ 	while (at_xdmac_chan_read(atchan, AT_XDMAC_CC)
+ 	       & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP))
+ 		cpu_relax();
+@@ -1783,7 +1833,7 @@ static int at_xdmac_device_resume(struct dma_chan *chan)
+ 		return 0;
+ 	}
+ 
+-	at_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask);
++	at_xdmac_write(atxdmac, atxdmac->layout->grwr, atchan->mask);
+ 	clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
+ 	spin_unlock_irqrestore(&atchan->lock, flags);
+ 
+@@ -1985,6 +2035,10 @@ static int at_xdmac_probe(struct platform_device *pdev)
+ 	atxdmac->regs = base;
+ 	atxdmac->irq = irq;
+ 
++	atxdmac->layout = of_device_get_match_data(&pdev->dev);
++	if (!atxdmac->layout)
++		return -ENODEV;
++
+ 	atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk");
+ 	if (IS_ERR(atxdmac->clk)) {
+ 		dev_err(&pdev->dev, "can't get dma_clk\n");
+@@ -2127,6 +2181,10 @@ static const struct dev_pm_ops atmel_xdmac_dev_pm_ops = {
+ static const struct of_device_id atmel_xdmac_dt_ids[] = {
+ 	{
+ 		.compatible = "atmel,sama5d4-dma",
++		.data = &at_xdmac_sama5d4_layout,
++	}, {
++		.compatible = "microchip,sama7g5-dma",
++		.data = &at_xdmac_sama7g5_layout,
+ 	}, {
+ 		/* sentinel */
+ 	}
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/134-dmaengine-at_xdmac-add-AXI-priority-support-and-reco.patch

@@ -0,0 +1,118 @@
+From 4833d6ea13a6d2c44a91247991a82c3eb6c1613e Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Fri, 16 Oct 2020 12:39:18 +0300
+Subject: [PATCH 134/247] dmaengine: at_xdmac: add AXI priority support and
+ recommended settings
+
+The sama7g5 version of the XDMAC supports priority configuration and
+outstanding capabilities.
+Add defines for the specific registers for this configuration, together
+with recommended settings.
+However the settings are very different if the XDMAC is a mem2mem or a
+per2mem controller.
+Thus, we need to differentiate according to device tree property.
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Vinod Koul <[email protected]>
+---
+ drivers/dma/at_xdmac.c | 47 ++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 47 insertions(+)
+
+diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
+index 2b096ea04018..8ca86d09b255 100644
+--- a/drivers/dma/at_xdmac.c
++++ b/drivers/dma/at_xdmac.c
+@@ -30,7 +30,24 @@
+ #define		AT_XDMAC_FIFO_SZ(i)	(((i) >> 5) & 0x7FF)		/* Number of Bytes */
+ #define		AT_XDMAC_NB_REQ(i)	((((i) >> 16) & 0x3F) + 1)	/* Number of Peripheral Requests Minus One */
+ #define AT_XDMAC_GCFG		0x04	/* Global Configuration Register */
++#define		AT_XDMAC_WRHP(i)		(((i) & 0xF) << 4)
++#define		AT_XDMAC_WRMP(i)		(((i) & 0xF) << 8)
++#define		AT_XDMAC_WRLP(i)		(((i) & 0xF) << 12)
++#define		AT_XDMAC_RDHP(i)		(((i) & 0xF) << 16)
++#define		AT_XDMAC_RDMP(i)		(((i) & 0xF) << 20)
++#define		AT_XDMAC_RDLP(i)		(((i) & 0xF) << 24)
++#define		AT_XDMAC_RDSG(i)		(((i) & 0xF) << 28)
++#define AT_XDMAC_GCFG_M2M	(AT_XDMAC_RDLP(0xF) | AT_XDMAC_WRLP(0xF))
++#define AT_XDMAC_GCFG_P2M	(AT_XDMAC_RDSG(0x1) | AT_XDMAC_RDHP(0x3) | \
++				AT_XDMAC_WRHP(0x5))
+ #define AT_XDMAC_GWAC		0x08	/* Global Weighted Arbiter Configuration Register */
++#define		AT_XDMAC_PW0(i)		(((i) & 0xF) << 0)
++#define		AT_XDMAC_PW1(i)		(((i) & 0xF) << 4)
++#define		AT_XDMAC_PW2(i)		(((i) & 0xF) << 8)
++#define		AT_XDMAC_PW3(i)		(((i) & 0xF) << 12)
++#define AT_XDMAC_GWAC_M2M	0
++#define AT_XDMAC_GWAC_P2M	(AT_XDMAC_PW0(0xF) | AT_XDMAC_PW2(0xF))
++
+ #define AT_XDMAC_GIE		0x0C	/* Global Interrupt Enable Register */
+ #define AT_XDMAC_GID		0x10	/* Global Interrupt Disable Register */
+ #define AT_XDMAC_GIM		0x14	/* Global Interrupt Mask Register */
+@@ -190,6 +207,8 @@ struct at_xdmac_layout {
+ 	u8				chan_cc_reg_base;
+ 	/* Source/Destination Interface must be specified or not */
+ 	bool				sdif;
++	/* AXI queue priority configuration supported */
++	bool				axi_config;
+ };
+ 
+ /* ----- Channels ----- */
+@@ -268,6 +287,7 @@ static const struct at_xdmac_layout at_xdmac_sama5d4_layout = {
+ 	.gswf = 0x40,
+ 	.chan_cc_reg_base = 0x50,
+ 	.sdif = true,
++	.axi_config = false,
+ };
+ 
+ static const struct at_xdmac_layout at_xdmac_sama7g5_layout = {
+@@ -280,6 +300,7 @@ static const struct at_xdmac_layout at_xdmac_sama7g5_layout = {
+ 	.gswf = 0x50,
+ 	.chan_cc_reg_base = 0x60,
+ 	.sdif = false,
++	.axi_config = true,
+ };
+ 
+ static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)
+@@ -1996,6 +2017,30 @@ static int atmel_xdmac_resume(struct device *dev)
+ }
+ #endif /* CONFIG_PM_SLEEP */
+ 
++static void at_xdmac_axi_config(struct platform_device *pdev)
++{
++	struct at_xdmac	*atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev);
++	bool dev_m2m = false;
++	u32 dma_requests;
++
++	if (!atxdmac->layout->axi_config)
++		return; /* Not supported */
++
++	if (!of_property_read_u32(pdev->dev.of_node, "dma-requests",
++				  &dma_requests)) {
++		dev_info(&pdev->dev, "controller in mem2mem mode.\n");
++		dev_m2m = true;
++	}
++
++	if (dev_m2m) {
++		at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_M2M);
++		at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_M2M);
++	} else {
++		at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_P2M);
++		at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_P2M);
++	}
++}
++
+ static int at_xdmac_probe(struct platform_device *pdev)
+ {
+ 	struct at_xdmac	*atxdmac;
+@@ -2140,6 +2185,8 @@ static int at_xdmac_probe(struct platform_device *pdev)
+ 	dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n",
+ 		 nr_channels, atxdmac->regs);
+ 
++	at_xdmac_axi_config(pdev);
++
+ 	return 0;
+ 
+ err_dma_unregister:
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/135-net-macb-Correct-usage-of-MACB_CAPS_CLK_HW_CHG-flag.patch

@@ -0,0 +1,50 @@
+From 982347f757b85ef526afaf243867ddd515475e1b Mon Sep 17 00:00:00 2001
+From: Charles Keepax <[email protected]>
+Date: Mon, 4 Jan 2021 10:38:02 +0000
+Subject: [PATCH 135/247] net: macb: Correct usage of MACB_CAPS_CLK_HW_CHG flag
+
+A new flag MACB_CAPS_CLK_HW_CHG was added and all callers of
+macb_set_tx_clk were gated on the presence of this flag.
+
+-   if (!clk)
++ if (!bp->tx_clk || !(bp->caps & MACB_CAPS_CLK_HW_CHG))
+
+However the flag was not added to anything other than the new
+sama7g5_gem, turning that function call into a no op for all other
+systems. This breaks the networking on Zynq.
+
+The commit message adding this states: a new capability so that
+macb_set_tx_clock() to not be called for IPs having this
+capability
+
+This strongly implies that present of the flag was intended to skip
+the function not absence of the flag. Update the if statement to
+this effect, which repairs the existing users.
+
+Fixes: daafa1d33cc9 ("net: macb: add capability to not set the clock rate")
+Suggested-by: Andrew Lunn <[email protected]>
+Signed-off-by: Charles Keepax <[email protected]>
+Reviewed-by: Claudiu Beznea <[email protected]>
+Reviewed-by: Andrew Lunn <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Jakub Kicinski <[email protected]>
+---
+ drivers/net/ethernet/cadence/macb_main.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
+index 4ce302e03735..d5bd640d3fa4 100644
+--- a/drivers/net/ethernet/cadence/macb_main.c
++++ b/drivers/net/ethernet/cadence/macb_main.c
+@@ -464,7 +464,7 @@ static void macb_set_tx_clk(struct macb *bp, int speed)
+ {
+ 	long ferr, rate, rate_rounded;
+ 
+-	if (!bp->tx_clk || !(bp->caps & MACB_CAPS_CLK_HW_CHG))
++	if (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG))
+ 		return;
+ 
+ 	switch (speed) {
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/136-ARM-at91-sam9x60-SiP-types-added-to-soc-description.patch

@@ -0,0 +1,50 @@
+From a2eda4ef1e3d617cdd669e256e45e969fab62398 Mon Sep 17 00:00:00 2001
+From: Kai Stuhlemmer <[email protected]>
+Date: Thu, 8 Oct 2020 14:50:28 +0200
+Subject: [PATCH 136/247] ARM: at91: sam9x60 SiP types added to soc description
+
+Adding SAM9X60 SIP variants to the soc description list.
+
+Signed-off-by: Kai Stuhlemmer <[email protected]>
+Signed-off-by: Nicolas Ferre <[email protected]>
+Signed-off-by: Alexandre Belloni <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+---
+ drivers/soc/atmel/soc.c | 6 ++++++
+ drivers/soc/atmel/soc.h | 3 +++
+ 2 files changed, 9 insertions(+)
+
+diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c
+index 5d06ee70a36b..698d21f50516 100644
+--- a/drivers/soc/atmel/soc.c
++++ b/drivers/soc/atmel/soc.c
+@@ -69,6 +69,12 @@ static const struct at91_soc __initconst socs[] = {
+ #endif
+ #ifdef CONFIG_SOC_SAM9X60
+ 	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_EXID_MATCH, "sam9x60", "sam9x60"),
++	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D5M_EXID_MATCH,
++		 "sam9x60 64MiB DDR2 SiP", "sam9x60"),
++	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D1G_EXID_MATCH,
++		 "sam9x60 128MiB DDR2 SiP", "sam9x60"),
++	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D6K_EXID_MATCH,
++		 "sam9x60 8MiB SDRAM SiP", "sam9x60"),
+ #endif
+ #ifdef CONFIG_SOC_SAMA5
+ 	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH,
+diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h
+index ee652e4841a5..5849846a69d6 100644
+--- a/drivers/soc/atmel/soc.h
++++ b/drivers/soc/atmel/soc.h
+@@ -60,6 +60,9 @@ at91_soc_init(const struct at91_soc *socs);
+ #define AT91SAM9CN11_EXID_MATCH		0x00000009
+ 
+ #define SAM9X60_EXID_MATCH		0x00000000
++#define SAM9X60_D5M_EXID_MATCH		0x00000001
++#define SAM9X60_D1G_EXID_MATCH		0x00000010
++#define SAM9X60_D6K_EXID_MATCH		0x00000011
+ 
+ #define AT91SAM9XE128_CIDR_MATCH	0x329973a0
+ #define AT91SAM9XE256_CIDR_MATCH	0x329a93a0
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/137-drivers-soc-atmel-use-GENMASK.patch

@@ -0,0 +1,30 @@
+From 8d858d9c57a0210ca1ce9e5ba76fab8bdb4d7b39 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Fri, 22 Jan 2021 14:21:32 +0200
+Subject: [PATCH 137/247] drivers: soc: atmel: use GENMASK
+
+Use GENMASK() to define CIDR match mask.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Signed-off-by: Nicolas Ferre <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+---
+ drivers/soc/atmel/soc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c
+index 698d21f50516..c3f920ee5c6f 100644
+--- a/drivers/soc/atmel/soc.c
++++ b/drivers/soc/atmel/soc.c
+@@ -27,7 +27,7 @@
+ #define AT91_CHIPID_EXID		0x04
+ #define AT91_CIDR_VERSION(x)		((x) & 0x1f)
+ #define AT91_CIDR_EXT			BIT(31)
+-#define AT91_CIDR_MATCH_MASK		0x7fffffe0
++#define AT91_CIDR_MATCH_MASK		GENMASK(30, 5)
+ 
+ static const struct at91_soc __initconst socs[] = {
+ #ifdef CONFIG_SOC_AT91RM9200
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/138-drivers-soc-atmel-fix-__initconst-should-be-placed-a.patch

@@ -0,0 +1,31 @@
+From ed871f95827e9b6d4ee9f9eafec4e18b87fb1a56 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Fri, 22 Jan 2021 14:21:33 +0200
+Subject: [PATCH 138/247] drivers: soc: atmel: fix "__initconst should be
+ placed after socs[]" warning
+
+Fix checkpatch.pl warning: "__initconst should be placed after socs[]".
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Signed-off-by: Nicolas Ferre <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+---
+ drivers/soc/atmel/soc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c
+index c3f920ee5c6f..03f3c742716c 100644
+--- a/drivers/soc/atmel/soc.c
++++ b/drivers/soc/atmel/soc.c
+@@ -29,7 +29,7 @@
+ #define AT91_CIDR_EXT			BIT(31)
+ #define AT91_CIDR_MATCH_MASK		GENMASK(30, 5)
+ 
+-static const struct at91_soc __initconst socs[] = {
++static const struct at91_soc socs[] __initconst = {
+ #ifdef CONFIG_SOC_AT91RM9200
+ 	AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"),
+ #endif
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/139-drivers-soc-atmel-add-per-soc-id-and-version-match-m.patch

@@ -0,0 +1,355 @@
+From 8f6f7ef363268f417f1729bb0b234326dd1e8e2a Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Fri, 22 Jan 2021 14:21:35 +0200
+Subject: [PATCH 139/247] drivers: soc: atmel: add per soc id and version match
+ masks
+
+SAMA7G5 has different masks for chip ID and chip version on CIDR
+register compared to previous AT91 SoCs. For this the commit adapts
+the code for SAMA7G5 addition by introducing 2 new members in
+struct at91_soc and fill them properly and also preparing the
+parsing of proper DT binding.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Signed-off-by: Nicolas Ferre <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+---
+ drivers/soc/atmel/soc.c | 199 +++++++++++++++++++++++++++-------------
+ drivers/soc/atmel/soc.h |   7 +-
+ 2 files changed, 140 insertions(+), 66 deletions(-)
+
+diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c
+index 03f3c742716c..f9052f45cb3e 100644
+--- a/drivers/soc/atmel/soc.c
++++ b/drivers/soc/atmel/soc.c
+@@ -25,135 +25,200 @@
+ #define AT91_DBGU_EXID			0x44
+ #define AT91_CHIPID_CIDR		0x00
+ #define AT91_CHIPID_EXID		0x04
+-#define AT91_CIDR_VERSION(x)		((x) & 0x1f)
++#define AT91_CIDR_VERSION(x, m)		((x) & (m))
++#define AT91_CIDR_VERSION_MASK		GENMASK(4, 0)
+ #define AT91_CIDR_EXT			BIT(31)
+ #define AT91_CIDR_MATCH_MASK		GENMASK(30, 5)
+ 
+ static const struct at91_soc socs[] __initconst = {
+ #ifdef CONFIG_SOC_AT91RM9200
+-	AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"),
++	AT91_SOC(AT91RM9200_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, 0, "at91rm9200 BGA", "at91rm9200"),
+ #endif
+ #ifdef CONFIG_SOC_AT91SAM9
+-	AT91_SOC(AT91SAM9260_CIDR_MATCH, 0, "at91sam9260", NULL),
+-	AT91_SOC(AT91SAM9261_CIDR_MATCH, 0, "at91sam9261", NULL),
+-	AT91_SOC(AT91SAM9263_CIDR_MATCH, 0, "at91sam9263", NULL),
+-	AT91_SOC(AT91SAM9G20_CIDR_MATCH, 0, "at91sam9g20", NULL),
+-	AT91_SOC(AT91SAM9RL64_CIDR_MATCH, 0, "at91sam9rl64", NULL),
+-	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M11_EXID_MATCH,
++	AT91_SOC(AT91SAM9260_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, 0, "at91sam9260", NULL),
++	AT91_SOC(AT91SAM9261_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, 0, "at91sam9261", NULL),
++	AT91_SOC(AT91SAM9263_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, 0, "at91sam9263", NULL),
++	AT91_SOC(AT91SAM9G20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, 0, "at91sam9g20", NULL),
++	AT91_SOC(AT91SAM9RL64_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, 0, "at91sam9rl64", NULL),
++	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, AT91SAM9M11_EXID_MATCH,
+ 		 "at91sam9m11", "at91sam9g45"),
+-	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M10_EXID_MATCH,
++	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, AT91SAM9M10_EXID_MATCH,
+ 		 "at91sam9m10", "at91sam9g45"),
+-	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G46_EXID_MATCH,
++	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, AT91SAM9G46_EXID_MATCH,
+ 		 "at91sam9g46", "at91sam9g45"),
+-	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G45_EXID_MATCH,
++	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, AT91SAM9G45_EXID_MATCH,
+ 		 "at91sam9g45", "at91sam9g45"),
+-	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G15_EXID_MATCH,
++	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, AT91SAM9G15_EXID_MATCH,
+ 		 "at91sam9g15", "at91sam9x5"),
+-	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G35_EXID_MATCH,
++	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, AT91SAM9G35_EXID_MATCH,
+ 		 "at91sam9g35", "at91sam9x5"),
+-	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X35_EXID_MATCH,
++	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, AT91SAM9X35_EXID_MATCH,
+ 		 "at91sam9x35", "at91sam9x5"),
+-	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G25_EXID_MATCH,
++	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, AT91SAM9G25_EXID_MATCH,
+ 		 "at91sam9g25", "at91sam9x5"),
+-	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X25_EXID_MATCH,
++	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, AT91SAM9X25_EXID_MATCH,
+ 		 "at91sam9x25", "at91sam9x5"),
+-	AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN12_EXID_MATCH,
++	AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, AT91SAM9CN12_EXID_MATCH,
+ 		 "at91sam9cn12", "at91sam9n12"),
+-	AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9N12_EXID_MATCH,
++	AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, AT91SAM9N12_EXID_MATCH,
+ 		 "at91sam9n12", "at91sam9n12"),
+-	AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN11_EXID_MATCH,
++	AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, AT91SAM9CN11_EXID_MATCH,
+ 		 "at91sam9cn11", "at91sam9n12"),
+-	AT91_SOC(AT91SAM9XE128_CIDR_MATCH, 0, "at91sam9xe128", "at91sam9xe128"),
+-	AT91_SOC(AT91SAM9XE256_CIDR_MATCH, 0, "at91sam9xe256", "at91sam9xe256"),
+-	AT91_SOC(AT91SAM9XE512_CIDR_MATCH, 0, "at91sam9xe512", "at91sam9xe512"),
++	AT91_SOC(AT91SAM9XE128_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, 0, "at91sam9xe128", "at91sam9xe128"),
++	AT91_SOC(AT91SAM9XE256_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, 0, "at91sam9xe256", "at91sam9xe256"),
++	AT91_SOC(AT91SAM9XE512_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, 0, "at91sam9xe512", "at91sam9xe512"),
+ #endif
+ #ifdef CONFIG_SOC_SAM9X60
+-	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_EXID_MATCH, "sam9x60", "sam9x60"),
++	AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
++		 "sam9x60", "sam9x60"),
+ 	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D5M_EXID_MATCH,
++		 AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
+ 		 "sam9x60 64MiB DDR2 SiP", "sam9x60"),
+ 	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D1G_EXID_MATCH,
++		 AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
+ 		 "sam9x60 128MiB DDR2 SiP", "sam9x60"),
+ 	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D6K_EXID_MATCH,
++		 AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
+ 		 "sam9x60 8MiB SDRAM SiP", "sam9x60"),
+ #endif
+ #ifdef CONFIG_SOC_SAMA5
+-	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH,
++	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH,
+ 		 "sama5d21", "sama5d2"),
+-	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D22CU_EXID_MATCH,
++	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D22CU_EXID_MATCH,
+ 		 "sama5d22", "sama5d2"),
+-	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D225C_D1M_EXID_MATCH,
++	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D225C_D1M_EXID_MATCH,
+ 		 "sama5d225c 16MiB SiP", "sama5d2"),
+-	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D23CU_EXID_MATCH,
++	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D23CU_EXID_MATCH,
+ 		 "sama5d23", "sama5d2"),
+-	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CX_EXID_MATCH,
++	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D24CX_EXID_MATCH,
+ 		 "sama5d24", "sama5d2"),
+-	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CU_EXID_MATCH,
++	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D24CU_EXID_MATCH,
+ 		 "sama5d24", "sama5d2"),
+-	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D26CU_EXID_MATCH,
++	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D26CU_EXID_MATCH,
+ 		 "sama5d26", "sama5d2"),
+-	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CU_EXID_MATCH,
++	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D27CU_EXID_MATCH,
+ 		 "sama5d27", "sama5d2"),
+-	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CN_EXID_MATCH,
++	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D27CN_EXID_MATCH,
+ 		 "sama5d27", "sama5d2"),
+-	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D1G_EXID_MATCH,
++	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D27C_D1G_EXID_MATCH,
+ 		 "sama5d27c 128MiB SiP", "sama5d2"),
+-	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D5M_EXID_MATCH,
++	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D27C_D5M_EXID_MATCH,
+ 		 "sama5d27c 64MiB SiP", "sama5d2"),
+-	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD1G_EXID_MATCH,
++	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D27C_LD1G_EXID_MATCH,
+ 		 "sama5d27c 128MiB LPDDR2 SiP", "sama5d2"),
+-	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD2G_EXID_MATCH,
++	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D27C_LD2G_EXID_MATCH,
+ 		 "sama5d27c 256MiB LPDDR2 SiP", "sama5d2"),
+-	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CU_EXID_MATCH,
++	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D28CU_EXID_MATCH,
+ 		 "sama5d28", "sama5d2"),
+-	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CN_EXID_MATCH,
++	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D28CN_EXID_MATCH,
+ 		 "sama5d28", "sama5d2"),
+-	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_D1G_EXID_MATCH,
++	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D28C_D1G_EXID_MATCH,
+ 		 "sama5d28c 128MiB SiP", "sama5d2"),
+-	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD1G_EXID_MATCH,
++	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D28C_LD1G_EXID_MATCH,
+ 		 "sama5d28c 128MiB LPDDR2 SiP", "sama5d2"),
+-	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD2G_EXID_MATCH,
++	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D28C_LD2G_EXID_MATCH,
+ 		 "sama5d28c 256MiB LPDDR2 SiP", "sama5d2"),
+-	AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH,
++	AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D31_EXID_MATCH,
+ 		 "sama5d31", "sama5d3"),
+-	AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH,
++	AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D33_EXID_MATCH,
+ 		 "sama5d33", "sama5d3"),
+-	AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D34_EXID_MATCH,
++	AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D34_EXID_MATCH,
+ 		 "sama5d34", "sama5d3"),
+-	AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D35_EXID_MATCH,
++	AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D35_EXID_MATCH,
+ 		 "sama5d35", "sama5d3"),
+-	AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D36_EXID_MATCH,
++	AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D36_EXID_MATCH,
+ 		 "sama5d36", "sama5d3"),
+-	AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D41_EXID_MATCH,
++	AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D41_EXID_MATCH,
+ 		 "sama5d41", "sama5d4"),
+-	AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D42_EXID_MATCH,
++	AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D42_EXID_MATCH,
+ 		 "sama5d42", "sama5d4"),
+-	AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D43_EXID_MATCH,
++	AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D43_EXID_MATCH,
+ 		 "sama5d43", "sama5d4"),
+-	AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D44_EXID_MATCH,
++	AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMA5D44_EXID_MATCH,
+ 		 "sama5d44", "sama5d4"),
+ #endif
+ #ifdef CONFIG_SOC_SAMV7
+-	AT91_SOC(SAME70Q21_CIDR_MATCH, SAME70Q21_EXID_MATCH,
++	AT91_SOC(SAME70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAME70Q21_EXID_MATCH,
+ 		 "same70q21", "same7"),
+-	AT91_SOC(SAME70Q20_CIDR_MATCH, SAME70Q20_EXID_MATCH,
++	AT91_SOC(SAME70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAME70Q20_EXID_MATCH,
+ 		 "same70q20", "same7"),
+-	AT91_SOC(SAME70Q19_CIDR_MATCH, SAME70Q19_EXID_MATCH,
++	AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK
++		 AT91_CIDR_VERSION_MASK, SAME70Q19_EXID_MATCH,
+ 		 "same70q19", "same7"),
+-	AT91_SOC(SAMS70Q21_CIDR_MATCH, SAMS70Q21_EXID_MATCH,
++	AT91_SOC(SAMS70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMS70Q21_EXID_MATCH,
+ 		 "sams70q21", "sams7"),
+-	AT91_SOC(SAMS70Q20_CIDR_MATCH, SAMS70Q20_EXID_MATCH,
++	AT91_SOC(SAMS70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMS70Q20_EXID_MATCH,
+ 		 "sams70q20", "sams7"),
+-	AT91_SOC(SAMS70Q19_CIDR_MATCH, SAMS70Q19_EXID_MATCH,
++	AT91_SOC(SAMS70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMS70Q19_EXID_MATCH,
+ 		 "sams70q19", "sams7"),
+-	AT91_SOC(SAMV71Q21_CIDR_MATCH, SAMV71Q21_EXID_MATCH,
++	AT91_SOC(SAMV71Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMV71Q21_EXID_MATCH,
+ 		 "samv71q21", "samv7"),
+-	AT91_SOC(SAMV71Q20_CIDR_MATCH, SAMV71Q20_EXID_MATCH,
++	AT91_SOC(SAMV71Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMV71Q20_EXID_MATCH,
+ 		 "samv71q20", "samv7"),
+-	AT91_SOC(SAMV71Q19_CIDR_MATCH, SAMV71Q19_EXID_MATCH,
++	AT91_SOC(SAMV71Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMV71Q19_EXID_MATCH,
+ 		 "samv71q19", "samv7"),
+-	AT91_SOC(SAMV70Q20_CIDR_MATCH, SAMV70Q20_EXID_MATCH,
++	AT91_SOC(SAMV70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMV70Q20_EXID_MATCH,
+ 		 "samv70q20", "samv7"),
+-	AT91_SOC(SAMV70Q19_CIDR_MATCH, SAMV70Q19_EXID_MATCH,
++	AT91_SOC(SAMV70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH,
+ 		 "samv70q19", "samv7"),
+ #endif
+ 	{ /* sentinel */ },
+@@ -191,8 +256,12 @@ static int __init at91_get_cidr_exid_from_chipid(u32 *cidr, u32 *exid)
+ {
+ 	struct device_node *np;
+ 	void __iomem *regs;
++	static const struct of_device_id chipids[] = {
++		{ .compatible = "atmel,sama5d2-chipid" },
++		{ },
++	};
+ 
+-	np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-chipid");
++	np = of_find_matching_node(NULL, chipids);
+ 	if (!np)
+ 		return -ENODEV;
+ 
+@@ -235,7 +304,7 @@ struct soc_device * __init at91_soc_init(const struct at91_soc *socs)
+ 	}
+ 
+ 	for (soc = socs; soc->name; soc++) {
+-		if (soc->cidr_match != (cidr & AT91_CIDR_MATCH_MASK))
++		if (soc->cidr_match != (cidr & soc->cidr_mask))
+ 			continue;
+ 
+ 		if (!(cidr & AT91_CIDR_EXT) || soc->exid_match == exid)
+@@ -254,7 +323,7 @@ struct soc_device * __init at91_soc_init(const struct at91_soc *socs)
+ 	soc_dev_attr->family = soc->family;
+ 	soc_dev_attr->soc_id = soc->name;
+ 	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X",
+-					   AT91_CIDR_VERSION(cidr));
++					   AT91_CIDR_VERSION(cidr, soc->version_mask));
+ 	soc_dev = soc_device_register(soc_dev_attr);
+ 	if (IS_ERR(soc_dev)) {
+ 		kfree(soc_dev_attr->revision);
+@@ -266,7 +335,7 @@ struct soc_device * __init at91_soc_init(const struct at91_soc *socs)
+ 	if (soc->family)
+ 		pr_info("Detected SoC family: %s\n", soc->family);
+ 	pr_info("Detected SoC: %s, revision %X\n", soc->name,
+-		AT91_CIDR_VERSION(cidr));
++		AT91_CIDR_VERSION(cidr, soc->version_mask));
+ 
+ 	return soc_dev;
+ }
+diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h
+index 5849846a69d6..02198a4de22b 100644
+--- a/drivers/soc/atmel/soc.h
++++ b/drivers/soc/atmel/soc.h
+@@ -16,14 +16,19 @@
+ 
+ struct at91_soc {
+ 	u32 cidr_match;
++	u32 cidr_mask;
++	u32 version_mask;
+ 	u32 exid_match;
+ 	const char *name;
+ 	const char *family;
+ };
+ 
+-#define AT91_SOC(__cidr, __exid, __name, __family)		\
++#define AT91_SOC(__cidr, __cidr_mask, __version_mask, __exid,	\
++		 __name, __family)				\
+ 	{							\
+ 		.cidr_match = (__cidr),				\
++		.cidr_mask = (__cidr_mask),			\
++		.version_mask = (__version_mask),		\
+ 		.exid_match = (__exid),				\
+ 		.name = (__name),				\
+ 		.family = (__family),				\
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/140-drivers-soc-atmel-add-support-for-sama7g5.patch

@@ -0,0 +1,94 @@
+From e20bb57fc51741677a6fcae04e564797fd18921b Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Fri, 22 Jan 2021 14:21:37 +0200
+Subject: [PATCH 140/247] drivers: soc: atmel: add support for sama7g5
+
+Add support for SAMA7G5 SoCs.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Signed-off-by: Nicolas Ferre <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+---
+ drivers/soc/atmel/soc.c | 18 ++++++++++++++++++
+ drivers/soc/atmel/soc.h |  6 ++++++
+ 2 files changed, 24 insertions(+)
+
+diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c
+index f9052f45cb3e..bc8e72fd431a 100644
+--- a/drivers/soc/atmel/soc.c
++++ b/drivers/soc/atmel/soc.c
+@@ -27,8 +27,10 @@
+ #define AT91_CHIPID_EXID		0x04
+ #define AT91_CIDR_VERSION(x, m)		((x) & (m))
+ #define AT91_CIDR_VERSION_MASK		GENMASK(4, 0)
++#define AT91_CIDR_VERSION_MASK_SAMA7G5	GENMASK(3, 0)
+ #define AT91_CIDR_EXT			BIT(31)
+ #define AT91_CIDR_MATCH_MASK		GENMASK(30, 5)
++#define AT91_CIDR_MASK_SAMA7G5		GENMASK(27, 5)
+ 
+ static const struct at91_soc socs[] __initconst = {
+ #ifdef CONFIG_SOC_AT91RM9200
+@@ -220,6 +222,20 @@ static const struct at91_soc socs[] __initconst = {
+ 	AT91_SOC(SAMV70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
+ 		 AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH,
+ 		 "samv70q19", "samv7"),
++#endif
++#ifdef CONFIG_SOC_SAMA7
++	AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G51_EXID_MATCH,
++		 "sama7g51", "sama7g5"),
++	AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G52_EXID_MATCH,
++		 "sama7g52", "sama7g5"),
++	AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G53_EXID_MATCH,
++		 "sama7g53", "sama7g5"),
++	AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_EXID_MATCH,
++		 "sama7g54", "sama7g5"),
+ #endif
+ 	{ /* sentinel */ },
+ };
+@@ -258,6 +274,7 @@ static int __init at91_get_cidr_exid_from_chipid(u32 *cidr, u32 *exid)
+ 	void __iomem *regs;
+ 	static const struct of_device_id chipids[] = {
+ 		{ .compatible = "atmel,sama5d2-chipid" },
++		{ .compatible = "microchip,sama7g5-chipid" },
+ 		{ },
+ 	};
+ 
+@@ -345,6 +362,7 @@ static const struct of_device_id at91_soc_allowed_list[] __initconst = {
+ 	{ .compatible = "atmel,at91sam9", },
+ 	{ .compatible = "atmel,sama5", },
+ 	{ .compatible = "atmel,samv7", },
++	{ .compatible = "microchip,sama7g5", },
+ 	{ }
+ };
+ 
+diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h
+index 02198a4de22b..93c212533ff0 100644
+--- a/drivers/soc/atmel/soc.h
++++ b/drivers/soc/atmel/soc.h
+@@ -48,6 +48,7 @@ at91_soc_init(const struct at91_soc *socs);
+ #define AT91SAM9X5_CIDR_MATCH		0x019a05a0
+ #define AT91SAM9N12_CIDR_MATCH		0x019a07a0
+ #define SAM9X60_CIDR_MATCH		0x019b35a0
++#define SAMA7G5_CIDR_MATCH		0x00162100
+ 
+ #define AT91SAM9M11_EXID_MATCH		0x00000001
+ #define AT91SAM9M10_EXID_MATCH		0x00000002
+@@ -69,6 +70,11 @@ at91_soc_init(const struct at91_soc *socs);
+ #define SAM9X60_D1G_EXID_MATCH		0x00000010
+ #define SAM9X60_D6K_EXID_MATCH		0x00000011
+ 
++#define SAMA7G51_EXID_MATCH		0x3
++#define SAMA7G52_EXID_MATCH		0x2
++#define SAMA7G53_EXID_MATCH		0x1
++#define SAMA7G54_EXID_MATCH		0x0
++
+ #define AT91SAM9XE128_CIDR_MATCH	0x329973a0
+ #define AT91SAM9XE256_CIDR_MATCH	0x329a93a0
+ #define AT91SAM9XE512_CIDR_MATCH	0x329aa3a0
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/141-drivers-soc-atmel-add-spdx-license-identifier.patch

@@ -0,0 +1,56 @@
+From acd4816cfa7811b13ca2864645f2de41031ccf4d Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Tue, 26 Jan 2021 11:29:30 +0200
+Subject: [PATCH 141/247] drivers: soc: atmel: add spdx license identifier
+
+Add SPDX-License-Identifier.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+[[email protected]: remove license boilerplate now it's useless]
+Signed-off-by: Nicolas Ferre <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+---
+ drivers/soc/atmel/soc.c | 6 +-----
+ drivers/soc/atmel/soc.h | 6 +-----
+ 2 files changed, 2 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c
+index bc8e72fd431a..a2967846809f 100644
+--- a/drivers/soc/atmel/soc.c
++++ b/drivers/soc/atmel/soc.c
+@@ -1,13 +1,9 @@
++// SPDX-License-Identifier: GPL-2.0-only
+ /*
+  * Copyright (C) 2015 Atmel
+  *
+  * Alexandre Belloni <[email protected]
+  * Boris Brezillon <[email protected]
+- *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2.  This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
+- *
+  */
+ 
+ #define pr_fmt(fmt)	"AT91: " fmt
+diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h
+index 93c212533ff0..c3eb3c8f0834 100644
+--- a/drivers/soc/atmel/soc.h
++++ b/drivers/soc/atmel/soc.h
+@@ -1,12 +1,8 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
+ /*
+  * Copyright (C) 2015 Atmel
+  *
+  * Boris Brezillon <[email protected]
+- *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2.  This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
+- *
+  */
+ 
+ #ifndef __AT91_SOC_H
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/142-drivers-soc-atmel-fix-type-for-same7.patch

@@ -0,0 +1,33 @@
+From b105d1dfab46c13070b8bdea1ab28d223a9c1bee Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <[email protected]>
+Date: Thu, 4 Feb 2021 16:49:25 +0100
+Subject: [PATCH 142/247] drivers: soc: atmel: fix type for same7
+
+A missing comma caused a build failure:
+
+drivers/soc/atmel/soc.c:196:24: error: too few arguments provided to function-like macro invocation
+
+Fixes: af3a10513cd6 ("drivers: soc: atmel: add per soc id and version match masks")
+Signed-off-by: Arnd Bergmann <[email protected]>
+Acked-by: Alexandre Belloni <[email protected]>
+Signed-off-by: Arnd Bergmann <[email protected]>
+---
+ drivers/soc/atmel/soc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c
+index a2967846809f..a490ad7e090f 100644
+--- a/drivers/soc/atmel/soc.c
++++ b/drivers/soc/atmel/soc.c
+@@ -191,7 +191,7 @@ static const struct at91_soc socs[] __initconst = {
+ 	AT91_SOC(SAME70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
+ 		 AT91_CIDR_VERSION_MASK, SAME70Q20_EXID_MATCH,
+ 		 "same70q20", "same7"),
+-	AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK
++	AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
+ 		 AT91_CIDR_VERSION_MASK, SAME70Q19_EXID_MATCH,
+ 		 "same70q19", "same7"),
+ 	AT91_SOC(SAMS70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/143-clocksource-drivers-timer-microchip-pit64b-Add-clock.patch

@@ -0,0 +1,178 @@
+From 5f090a664d62ceeaf9a0f482426e35cab18d65a9 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Tue, 19 Jan 2021 14:59:25 +0200
+Subject: [PATCH 143/247] clocksource/drivers/timer-microchip-pit64b: Add
+ clocksource suspend/resume
+
+Add suspend/resume support for clocksource timer.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Signed-off-by: Daniel Lezcano <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+---
+ drivers/clocksource/timer-microchip-pit64b.c | 86 ++++++++++++++++----
+ 1 file changed, 71 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/clocksource/timer-microchip-pit64b.c b/drivers/clocksource/timer-microchip-pit64b.c
+index 59e11ca8ee73..ab623b25a47b 100644
+--- a/drivers/clocksource/timer-microchip-pit64b.c
++++ b/drivers/clocksource/timer-microchip-pit64b.c
+@@ -71,10 +71,24 @@ struct mchp_pit64b_clkevt {
+ 	struct clock_event_device	clkevt;
+ };
+ 
+-#define to_mchp_pit64b_timer(x) \
++#define clkevt_to_mchp_pit64b_timer(x) \
+ 	((struct mchp_pit64b_timer *)container_of(x,\
+ 		struct mchp_pit64b_clkevt, clkevt))
+ 
++/**
++ * mchp_pit64b_clksrc - PIT64B clocksource data structure
++ * @timer: PIT64B timer
++ * @clksrc: clocksource
++ */
++struct mchp_pit64b_clksrc {
++	struct mchp_pit64b_timer	timer;
++	struct clocksource		clksrc;
++};
++
++#define clksrc_to_mchp_pit64b_timer(x) \
++	((struct mchp_pit64b_timer *)container_of(x,\
++		struct mchp_pit64b_clksrc, clksrc))
++
+ /* Base address for clocksource timer. */
+ static void __iomem *mchp_pit64b_cs_base;
+ /* Default cycles for clockevent timer. */
+@@ -116,6 +130,36 @@ static inline void mchp_pit64b_reset(struct mchp_pit64b_timer *timer,
+ 	writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR);
+ }
+ 
++static void mchp_pit64b_suspend(struct mchp_pit64b_timer *timer)
++{
++	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
++	if (timer->mode & MCHP_PIT64B_MR_SGCLK)
++		clk_disable_unprepare(timer->gclk);
++	clk_disable_unprepare(timer->pclk);
++}
++
++static void mchp_pit64b_resume(struct mchp_pit64b_timer *timer)
++{
++	clk_prepare_enable(timer->pclk);
++	if (timer->mode & MCHP_PIT64B_MR_SGCLK)
++		clk_prepare_enable(timer->gclk);
++}
++
++static void mchp_pit64b_clksrc_suspend(struct clocksource *cs)
++{
++	struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs);
++
++	mchp_pit64b_suspend(timer);
++}
++
++static void mchp_pit64b_clksrc_resume(struct clocksource *cs)
++{
++	struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs);
++
++	mchp_pit64b_resume(timer);
++	mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);
++}
++
+ static u64 mchp_pit64b_clksrc_read(struct clocksource *cs)
+ {
+ 	return mchp_pit64b_cnt_read(mchp_pit64b_cs_base);
+@@ -128,7 +172,7 @@ static u64 mchp_pit64b_sched_read_clk(void)
+ 
+ static int mchp_pit64b_clkevt_shutdown(struct clock_event_device *cedev)
+ {
+-	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
++	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
+ 
+ 	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
+ 
+@@ -137,7 +181,7 @@ static int mchp_pit64b_clkevt_shutdown(struct clock_event_device *cedev)
+ 
+ static int mchp_pit64b_clkevt_set_periodic(struct clock_event_device *cedev)
+ {
+-	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
++	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
+ 
+ 	mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT,
+ 			  MCHP_PIT64B_IER_PERIOD);
+@@ -148,7 +192,7 @@ static int mchp_pit64b_clkevt_set_periodic(struct clock_event_device *cedev)
+ static int mchp_pit64b_clkevt_set_next_event(unsigned long evt,
+ 					     struct clock_event_device *cedev)
+ {
+-	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
++	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
+ 
+ 	mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT,
+ 			  MCHP_PIT64B_IER_PERIOD);
+@@ -158,21 +202,16 @@ static int mchp_pit64b_clkevt_set_next_event(unsigned long evt,
+ 
+ static void mchp_pit64b_clkevt_suspend(struct clock_event_device *cedev)
+ {
+-	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
++	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
+ 
+-	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
+-	if (timer->mode & MCHP_PIT64B_MR_SGCLK)
+-		clk_disable_unprepare(timer->gclk);
+-	clk_disable_unprepare(timer->pclk);
++	mchp_pit64b_suspend(timer);
+ }
+ 
+ static void mchp_pit64b_clkevt_resume(struct clock_event_device *cedev)
+ {
+-	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
++	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
+ 
+-	clk_prepare_enable(timer->pclk);
+-	if (timer->mode & MCHP_PIT64B_MR_SGCLK)
+-		clk_prepare_enable(timer->gclk);
++	mchp_pit64b_resume(timer);
+ }
+ 
+ static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id)
+@@ -296,20 +335,37 @@ static int __init mchp_pit64b_init_mode(struct mchp_pit64b_timer *timer,
+ static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer,
+ 					  u32 clk_rate)
+ {
++	struct mchp_pit64b_clksrc *cs;
+ 	int ret;
+ 
++	cs = kzalloc(sizeof(*cs), GFP_KERNEL);
++	if (!cs)
++		return -ENOMEM;
++
+ 	mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);
+ 
+ 	mchp_pit64b_cs_base = timer->base;
+ 
+-	ret = clocksource_mmio_init(timer->base, MCHP_PIT64B_NAME, clk_rate,
+-				    210, 64, mchp_pit64b_clksrc_read);
++	cs->timer.base = timer->base;
++	cs->timer.pclk = timer->pclk;
++	cs->timer.gclk = timer->gclk;
++	cs->timer.mode = timer->mode;
++	cs->clksrc.name = MCHP_PIT64B_NAME;
++	cs->clksrc.mask = CLOCKSOURCE_MASK(64);
++	cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
++	cs->clksrc.rating = 210;
++	cs->clksrc.read = mchp_pit64b_clksrc_read;
++	cs->clksrc.suspend = mchp_pit64b_clksrc_suspend;
++	cs->clksrc.resume = mchp_pit64b_clksrc_resume;
++
++	ret = clocksource_register_hz(&cs->clksrc, clk_rate);
+ 	if (ret) {
+ 		pr_debug("clksrc: Failed to register PIT64B clocksource!\n");
+ 
+ 		/* Stop timer. */
+ 		writel_relaxed(MCHP_PIT64B_CR_SWRST,
+ 			       timer->base + MCHP_PIT64B_CR);
++		kfree(cs);
+ 
+ 		return ret;
+ 	}
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/144-ASoC-atmel-pdc-Use-managed-DMA-buffer-allocation.patch

@@ -0,0 +1,140 @@
+From 0b20c174a17dcfa805ddac1301a5af7298877ec3 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <[email protected]>
+Date: Wed, 6 Jan 2021 14:36:48 +0100
+Subject: [PATCH 144/247] ASoC: atmel-pdc: Use managed DMA buffer allocation
+
+Instead of manually managing its DMA buffers using
+dma_{alloc,free}_coherent() lets the sound core take care of this using
+managed buffers.
+
+On one hand this reduces the amount of boiler plate code, but the main
+motivation for the change is to use the shared code where possible. This
+makes it easier to argue about correctness and that the code does not
+contain subtle bugs like data leakage or similar.
+
+Signed-off-by: Lars-Peter Clausen <[email protected]>
+Reviewed-by: Codrin Ciubotariu <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Mark Brown <[email protected]>
+---
+ sound/soc/atmel/atmel-pcm-pdc.c | 78 ++-------------------------------
+ 1 file changed, 4 insertions(+), 74 deletions(-)
+
+diff --git a/sound/soc/atmel/atmel-pcm-pdc.c b/sound/soc/atmel/atmel-pcm-pdc.c
+index 704f700013d3..3e7ea2021b46 100644
+--- a/sound/soc/atmel/atmel-pcm-pdc.c
++++ b/sound/soc/atmel/atmel-pcm-pdc.c
+@@ -34,86 +34,21 @@
+ #include "atmel-pcm.h"
+ 
+ 
+-static int atmel_pcm_preallocate_dma_buffer(struct snd_pcm *pcm,
+-	int stream)
+-{
+-	struct snd_pcm_substream *substream = pcm->streams[stream].substream;
+-	struct snd_dma_buffer *buf = &substream->dma_buffer;
+-	size_t size = ATMEL_SSC_DMABUF_SIZE;
+-
+-	buf->dev.type = SNDRV_DMA_TYPE_DEV;
+-	buf->dev.dev = pcm->card->dev;
+-	buf->private_data = NULL;
+-	buf->area = dma_alloc_coherent(pcm->card->dev, size,
+-			&buf->addr, GFP_KERNEL);
+-	pr_debug("atmel-pcm: alloc dma buffer: area=%p, addr=%p, size=%zu\n",
+-			(void *)buf->area, (void *)(long)buf->addr, size);
+-
+-	if (!buf->area)
+-		return -ENOMEM;
+-
+-	buf->bytes = size;
+-	return 0;
+-}
+-
+-static int atmel_pcm_mmap(struct snd_soc_component *component,
+-			  struct snd_pcm_substream *substream,
+-			  struct vm_area_struct *vma)
+-{
+-	return remap_pfn_range(vma, vma->vm_start,
+-		       substream->dma_buffer.addr >> PAGE_SHIFT,
+-		       vma->vm_end - vma->vm_start, vma->vm_page_prot);
+-}
+-
+ static int atmel_pcm_new(struct snd_soc_component *component,
+ 			 struct snd_soc_pcm_runtime *rtd)
+ {
+ 	struct snd_card *card = rtd->card->snd_card;
+-	struct snd_pcm *pcm = rtd->pcm;
+ 	int ret;
+ 
+ 	ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
+ 	if (ret)
+ 		return ret;
+ 
+-	if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
+-		pr_debug("atmel-pcm: allocating PCM playback DMA buffer\n");
+-		ret = atmel_pcm_preallocate_dma_buffer(pcm,
+-			SNDRV_PCM_STREAM_PLAYBACK);
+-		if (ret)
+-			goto out;
+-	}
++	snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
++				       card->dev, ATMEL_SSC_DMABUF_SIZE,
++				       ATMEL_SSC_DMABUF_SIZE);
+ 
+-	if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
+-		pr_debug("atmel-pcm: allocating PCM capture DMA buffer\n");
+-		ret = atmel_pcm_preallocate_dma_buffer(pcm,
+-			SNDRV_PCM_STREAM_CAPTURE);
+-		if (ret)
+-			goto out;
+-	}
+- out:
+-	return ret;
+-}
+-
+-static void atmel_pcm_free(struct snd_soc_component *component,
+-			   struct snd_pcm *pcm)
+-{
+-	struct snd_pcm_substream *substream;
+-	struct snd_dma_buffer *buf;
+-	int stream;
+-
+-	for (stream = 0; stream < 2; stream++) {
+-		substream = pcm->streams[stream].substream;
+-		if (!substream)
+-			continue;
+-
+-		buf = &substream->dma_buffer;
+-		if (!buf->area)
+-			continue;
+-		dma_free_coherent(pcm->card->dev, buf->bytes,
+-				  buf->area, buf->addr);
+-		buf->area = NULL;
+-	}
++	return 0;
+ }
+ 
+ /*--------------------------------------------------------------------------*\
+@@ -210,9 +145,6 @@ static int atmel_pcm_hw_params(struct snd_soc_component *component,
+ 	/* this may get called several times by oss emulation
+ 	 * with different params */
+ 
+-	snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
+-	runtime->dma_bytes = params_buffer_bytes(params);
+-
+ 	prtd->params = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
+ 	prtd->params->dma_intr_handler = atmel_pcm_dma_irq;
+ 
+@@ -384,9 +316,7 @@ static const struct snd_soc_component_driver atmel_soc_platform = {
+ 	.prepare	= atmel_pcm_prepare,
+ 	.trigger	= atmel_pcm_trigger,
+ 	.pointer	= atmel_pcm_pointer,
+-	.mmap		= atmel_pcm_mmap,
+ 	.pcm_construct	= atmel_pcm_new,
+-	.pcm_destruct	= atmel_pcm_free,
+ };
+ 
+ int atmel_pcm_pdc_platform_register(struct device *dev)
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/145-power-reset-at91-sama5d2_shdwc-add-support-for-sama7.patch

@@ -0,0 +1,146 @@
+From f39f2312a68ec0843adba08f9c9182ffa5624190 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Wed, 16 Dec 2020 14:57:33 +0200
+Subject: [PATCH 145/247] power: reset: at91-sama5d2_shdwc: add support for
+ sama7g5
+
+Add support for SAMA7G5 by adding proper struct reg_config structure
+and since SAMA7G5 is not currently on LPDDR setups the commit also
+avoid the mapping of DDR controller.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Signed-off-by: Sebastian Reichel <[email protected]>
+---
+ drivers/power/reset/at91-sama5d2_shdwc.c | 72 ++++++++++++++++++------
+ 1 file changed, 54 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c
+index d9cf91e5b06d..125e592af445 100644
+--- a/drivers/power/reset/at91-sama5d2_shdwc.c
++++ b/drivers/power/reset/at91-sama5d2_shdwc.c
+@@ -78,9 +78,15 @@ struct pmc_reg_config {
+ 	u8 mckr;
+ };
+ 
++struct ddrc_reg_config {
++	u32 type_offset;
++	u32 type_mask;
++};
++
+ struct reg_config {
+ 	struct shdwc_reg_config shdwc;
+ 	struct pmc_reg_config pmc;
++	struct ddrc_reg_config ddrc;
+ };
+ 
+ struct shdwc {
+@@ -262,6 +268,10 @@ static const struct reg_config sama5d2_reg_config = {
+ 	.pmc = {
+ 		.mckr		= 0x30,
+ 	},
++	.ddrc = {
++		.type_offset	= AT91_DDRSDRC_MDR,
++		.type_mask	= AT91_DDRSDRC_MD
++	},
+ };
+ 
+ static const struct reg_config sam9x60_reg_config = {
+@@ -275,6 +285,23 @@ static const struct reg_config sam9x60_reg_config = {
+ 	.pmc = {
+ 		.mckr		= 0x28,
+ 	},
++	.ddrc = {
++		.type_offset	= AT91_DDRSDRC_MDR,
++		.type_mask	= AT91_DDRSDRC_MD
++	},
++};
++
++static const struct reg_config sama7g5_reg_config = {
++	.shdwc = {
++		.wkup_pin_input = 0,
++		.mr_rtcwk_shift = 17,
++		.mr_rttwk_shift = 16,
++		.sr_rtcwk_shift = 5,
++		.sr_rttwk_shift = 4,
++	},
++	.pmc = {
++		.mckr		= 0x28,
++	},
+ };
+ 
+ static const struct of_device_id at91_shdwc_of_match[] = {
+@@ -285,6 +312,10 @@ static const struct of_device_id at91_shdwc_of_match[] = {
+ 	{
+ 		.compatible = "microchip,sam9x60-shdwc",
+ 		.data = &sam9x60_reg_config,
++	},
++	{
++		.compatible = "microchip,sama7g5-shdwc",
++		.data = &sama7g5_reg_config,
+ 	}, {
+ 		/*sentinel*/
+ 	}
+@@ -294,6 +325,7 @@ MODULE_DEVICE_TABLE(of, at91_shdwc_of_match);
+ static const struct of_device_id at91_pmc_ids[] = {
+ 	{ .compatible = "atmel,sama5d2-pmc" },
+ 	{ .compatible = "microchip,sam9x60-pmc" },
++	{ .compatible = "microchip,sama7g5-pmc" },
+ 	{ /* Sentinel. */ }
+ };
+ 
+@@ -355,30 +387,34 @@ static int __init at91_shdwc_probe(struct platform_device *pdev)
+ 		goto clk_disable;
+ 	}
+ 
+-	np = of_find_compatible_node(NULL, NULL, "atmel,sama5d3-ddramc");
+-	if (!np) {
+-		ret = -ENODEV;
+-		goto unmap;
+-	}
++	if (at91_shdwc->rcfg->ddrc.type_mask) {
++		np = of_find_compatible_node(NULL, NULL,
++					     "atmel,sama5d3-ddramc");
++		if (!np) {
++			ret = -ENODEV;
++			goto unmap;
++		}
+ 
+-	at91_shdwc->mpddrc_base = of_iomap(np, 0);
+-	of_node_put(np);
++		at91_shdwc->mpddrc_base = of_iomap(np, 0);
++		of_node_put(np);
+ 
+-	if (!at91_shdwc->mpddrc_base) {
+-		ret = -ENOMEM;
+-		goto unmap;
++		if (!at91_shdwc->mpddrc_base) {
++			ret = -ENOMEM;
++			goto unmap;
++		}
++
++		ddr_type = readl(at91_shdwc->mpddrc_base +
++				 at91_shdwc->rcfg->ddrc.type_offset) &
++				 at91_shdwc->rcfg->ddrc.type_mask;
++		if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 &&
++		    ddr_type != AT91_DDRSDRC_MD_LPDDR3) {
++			iounmap(at91_shdwc->mpddrc_base);
++			at91_shdwc->mpddrc_base = NULL;
++		}
+ 	}
+ 
+ 	pm_power_off = at91_poweroff;
+ 
+-	ddr_type = readl(at91_shdwc->mpddrc_base + AT91_DDRSDRC_MDR) &
+-			 AT91_DDRSDRC_MD;
+-	if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 &&
+-	    ddr_type != AT91_DDRSDRC_MD_LPDDR3) {
+-		iounmap(at91_shdwc->mpddrc_base);
+-		at91_shdwc->mpddrc_base = NULL;
+-	}
+-
+ 	return 0;
+ 
+ unmap:
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/146-pinctrl-at91-pio4-add-support-for-slew-rate.patch

@@ -0,0 +1,126 @@
+From bd819c78346012ae0627b1cd4f6ceb1b51162c71 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Wed, 27 Jan 2021 13:45:44 +0200
+Subject: [PATCH 146/247] pinctrl: at91-pio4: add support for slew-rate
+
+SAMA7G5 supports slew rate configuration. Adapt the driver for this.
+For output switching frequencies lower than 50MHz the slew rate needs to
+be enabled. Since most of the pins on SAMA7G5 fall into this category
+enabled the slew rate by default.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Acked-by: Ludovic Desroches <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Linus Walleij <[email protected]>
+---
+ drivers/pinctrl/pinctrl-at91-pio4.c | 27 +++++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c
+index d267367d94b9..f202cdb6dc3c 100644
+--- a/drivers/pinctrl/pinctrl-at91-pio4.c
++++ b/drivers/pinctrl/pinctrl-at91-pio4.c
+@@ -36,6 +36,7 @@
+ #define		ATMEL_PIO_DIR_MASK		BIT(8)
+ #define		ATMEL_PIO_PUEN_MASK		BIT(9)
+ #define		ATMEL_PIO_PDEN_MASK		BIT(10)
++#define		ATMEL_PIO_SR_MASK		BIT(11)
+ #define		ATMEL_PIO_IFEN_MASK		BIT(12)
+ #define		ATMEL_PIO_IFSCEN_MASK		BIT(13)
+ #define		ATMEL_PIO_OPD_MASK		BIT(14)
+@@ -76,10 +77,12 @@
+  * @nbanks: number of PIO banks
+  * @last_bank_count: number of lines in the last bank (can be less than
+  *	the rest of the banks).
++ * @slew_rate_support: slew rate support
+  */
+ struct atmel_pioctrl_data {
+ 	unsigned nbanks;
+ 	unsigned last_bank_count;
++	unsigned int slew_rate_support;
+ };
+ 
+ struct atmel_group {
+@@ -117,6 +120,7 @@ struct atmel_pin {
+  * @pm_suspend_backup: backup/restore register values on suspend/resume
+  * @dev: device entry for the Atmel PIO controller.
+  * @node: node of the Atmel PIO controller.
++ * @slew_rate_support: slew rate support
+  */
+ struct atmel_pioctrl {
+ 	void __iomem		*reg_base;
+@@ -138,6 +142,7 @@ struct atmel_pioctrl {
+ 	} *pm_suspend_backup;
+ 	struct device		*dev;
+ 	struct device_node	*node;
++	unsigned int		slew_rate_support;
+ };
+ 
+ static const char * const atmel_functions[] = {
+@@ -760,6 +765,13 @@ static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
+ 			return -EINVAL;
+ 		arg = 1;
+ 		break;
++	case PIN_CONFIG_SLEW_RATE:
++		if (!atmel_pioctrl->slew_rate_support)
++			return -EOPNOTSUPP;
++		if (!(res & ATMEL_PIO_SR_MASK))
++			return -EINVAL;
++		arg = 1;
++		break;
+ 	case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
+ 		if (!(res & ATMEL_PIO_DRVSTR_MASK))
+ 			return -EINVAL;
+@@ -793,6 +805,10 @@ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
+ 		dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
+ 			__func__, pin_id, configs[i]);
+ 
++		/* Keep slew rate enabled by default. */
++		if (atmel_pioctrl->slew_rate_support)
++			conf |= ATMEL_PIO_SR_MASK;
++
+ 		switch (param) {
+ 		case PIN_CONFIG_BIAS_DISABLE:
+ 			conf &= (~ATMEL_PIO_PUEN_MASK);
+@@ -850,6 +866,13 @@ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
+ 					ATMEL_PIO_SODR);
+ 			}
+ 			break;
++		case PIN_CONFIG_SLEW_RATE:
++			if (!atmel_pioctrl->slew_rate_support)
++				break;
++			/* And remove it if explicitly requested. */
++			if (arg == 0)
++				conf &= ~ATMEL_PIO_SR_MASK;
++			break;
+ 		case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
+ 			switch (arg) {
+ 			case ATMEL_PIO_DRVSTR_LO:
+@@ -901,6 +924,8 @@ static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
+ 		seq_printf(s, "%s ", "open-drain");
+ 	if (conf & ATMEL_PIO_SCHMITT_MASK)
+ 		seq_printf(s, "%s ", "schmitt");
++	if (atmel_pioctrl->slew_rate_support && (conf & ATMEL_PIO_SR_MASK))
++		seq_printf(s, "%s ", "slew-rate");
+ 	if (conf & ATMEL_PIO_DRVSTR_MASK) {
+ 		switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) {
+ 		case ATMEL_PIO_DRVSTR_ME:
+@@ -994,6 +1019,7 @@ static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
+ static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
+ 	.nbanks			= 5,
+ 	.last_bank_count	= 8, /* sama7g5 has only PE0 to PE7 */
++	.slew_rate_support	= 1,
+ };
+ 
+ static const struct of_device_id atmel_pctrl_of_match[] = {
+@@ -1039,6 +1065,7 @@ static int atmel_pinctrl_probe(struct platform_device *pdev)
+ 		atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK;
+ 		atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count;
+ 	}
++	atmel_pioctrl->slew_rate_support = atmel_pioctrl_data->slew_rate_support;
+ 
+ 	atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
+ 	if (IS_ERR(atmel_pioctrl->reg_base))
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/147-pinctrl-at91-pio4-fix-Prefer-unsigned-int-to-bare-us.patch

@@ -0,0 +1,345 @@
+From 99629d1ad7e4e03ac3324d36b703220555b65566 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Wed, 27 Jan 2021 13:45:45 +0200
+Subject: [PATCH 147/247] pinctrl: at91-pio4: fix "Prefer 'unsigned int' to
+ bare use of 'unsigned'"
+
+Fix "Prefer 'unsigned int' to bare use of 'unsigned'" checkpatch.pl
+warning.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Acked-by: Ludovic Desroches <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Linus Walleij <[email protected]>
+---
+ drivers/pinctrl/pinctrl-at91-pio4.c | 110 ++++++++++++++--------------
+ 1 file changed, 57 insertions(+), 53 deletions(-)
+
+diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c
+index f202cdb6dc3c..a5d328808e4c 100644
+--- a/drivers/pinctrl/pinctrl-at91-pio4.c
++++ b/drivers/pinctrl/pinctrl-at91-pio4.c
+@@ -80,8 +80,8 @@
+  * @slew_rate_support: slew rate support
+  */
+ struct atmel_pioctrl_data {
+-	unsigned nbanks;
+-	unsigned last_bank_count;
++	unsigned int nbanks;
++	unsigned int last_bank_count;
+ 	unsigned int slew_rate_support;
+ };
+ 
+@@ -91,11 +91,11 @@ struct atmel_group {
+ };
+ 
+ struct atmel_pin {
+-	unsigned pin_id;
+-	unsigned mux;
+-	unsigned ioset;
+-	unsigned bank;
+-	unsigned line;
++	unsigned int pin_id;
++	unsigned int mux;
++	unsigned int ioset;
++	unsigned int bank;
++	unsigned int line;
+ 	const char *device;
+ };
+ 
+@@ -125,16 +125,16 @@ struct atmel_pin {
+ struct atmel_pioctrl {
+ 	void __iomem		*reg_base;
+ 	struct clk		*clk;
+-	unsigned		nbanks;
++	unsigned int		nbanks;
+ 	struct pinctrl_dev	*pinctrl_dev;
+ 	struct atmel_group	*groups;
+ 	const char * const	*group_names;
+ 	struct atmel_pin	**pins;
+-	unsigned		npins;
++	unsigned int		npins;
+ 	struct gpio_chip	*gpio_chip;
+ 	struct irq_domain	*irq_domain;
+ 	int			*irqs;
+-	unsigned		*pm_wakeup_sources;
++	unsigned int		*pm_wakeup_sources;
+ 	struct {
+ 		u32		imr;
+ 		u32		odsr;
+@@ -177,11 +177,11 @@ static void atmel_gpio_irq_ack(struct irq_data *d)
+ 	 */
+ }
+ 
+-static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type)
++static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned int type)
+ {
+ 	struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
+ 	struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
+-	unsigned reg;
++	unsigned int reg;
+ 
+ 	atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
+ 			 BIT(pin->line));
+@@ -268,7 +268,7 @@ static struct irq_chip atmel_gpio_irq_chip = {
+ 	.irq_set_wake	= atmel_gpio_irq_set_wake,
+ };
+ 
+-static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
++static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
+ {
+ 	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
+ 
+@@ -316,11 +316,12 @@ static void atmel_gpio_irq_handler(struct irq_desc *desc)
+ 	chained_irq_exit(chip, desc);
+ }
+ 
+-static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
++static int atmel_gpio_direction_input(struct gpio_chip *chip,
++				      unsigned int offset)
+ {
+ 	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
+ 	struct atmel_pin *pin = atmel_pioctrl->pins[offset];
+-	unsigned reg;
++	unsigned int reg;
+ 
+ 	atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
+ 			 BIT(pin->line));
+@@ -331,11 +332,11 @@ static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+ 	return 0;
+ }
+ 
+-static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset)
++static int atmel_gpio_get(struct gpio_chip *chip, unsigned int offset)
+ {
+ 	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
+ 	struct atmel_pin *pin = atmel_pioctrl->pins[offset];
+-	unsigned reg;
++	unsigned int reg;
+ 
+ 	reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);
+ 
+@@ -369,12 +370,13 @@ static int atmel_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
+ 	return 0;
+ }
+ 
+-static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
++static int atmel_gpio_direction_output(struct gpio_chip *chip,
++				       unsigned int offset,
+ 				       int value)
+ {
+ 	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
+ 	struct atmel_pin *pin = atmel_pioctrl->pins[offset];
+-	unsigned reg;
++	unsigned int reg;
+ 
+ 	atmel_gpio_write(atmel_pioctrl, pin->bank,
+ 			 value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
+@@ -389,7 +391,7 @@ static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
+ 	return 0;
+ }
+ 
+-static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
++static void atmel_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
+ {
+ 	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
+ 	struct atmel_pin *pin = atmel_pioctrl->pins[offset];
+@@ -445,11 +447,11 @@ static struct gpio_chip atmel_gpio_chip = {
+ 
+ /* --- PINCTRL --- */
+ static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,
+-					  unsigned pin_id)
++					  unsigned int pin_id)
+ {
+ 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
+-	unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
+-	unsigned line = atmel_pioctrl->pins[pin_id]->line;
++	unsigned int bank = atmel_pioctrl->pins[pin_id]->bank;
++	unsigned int line = atmel_pioctrl->pins[pin_id]->line;
+ 	void __iomem *addr = atmel_pioctrl->reg_base
+ 			     + bank * ATMEL_PIO_BANK_OFFSET;
+ 
+@@ -461,11 +463,11 @@ static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,
+ }
+ 
+ static void atmel_pin_config_write(struct pinctrl_dev *pctldev,
+-				   unsigned pin_id, u32 conf)
++				   unsigned int pin_id, u32 conf)
+ {
+ 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
+-	unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
+-	unsigned line = atmel_pioctrl->pins[pin_id]->line;
++	unsigned int bank = atmel_pioctrl->pins[pin_id]->bank;
++	unsigned int line = atmel_pioctrl->pins[pin_id]->line;
+ 	void __iomem *addr = atmel_pioctrl->reg_base
+ 			     + bank * ATMEL_PIO_BANK_OFFSET;
+ 
+@@ -483,7 +485,7 @@ static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev)
+ }
+ 
+ static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,
+-					     unsigned selector)
++					     unsigned int selector)
+ {
+ 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
+ 
+@@ -491,19 +493,20 @@ static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,
+ }
+ 
+ static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,
+-				     unsigned selector, const unsigned **pins,
+-				     unsigned *num_pins)
++				     unsigned int selector,
++				     const unsigned int **pins,
++				     unsigned int *num_pins)
+ {
+ 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
+ 
+-	*pins = (unsigned *)&atmel_pioctrl->groups[selector].pin;
++	*pins = (unsigned int *)&atmel_pioctrl->groups[selector].pin;
+ 	*num_pins = 1;
+ 
+ 	return 0;
+ }
+ 
+ static struct atmel_group *
+-atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin)
++atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned int pin)
+ {
+ 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
+ 	int i;
+@@ -524,7 +527,7 @@ static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev,
+ 				    const char **func_name)
+ {
+ 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
+-	unsigned pin_id, func_id;
++	unsigned int pin_id, func_id;
+ 	struct atmel_group *grp;
+ 
+ 	pin_id = ATMEL_GET_PIN_NO(pinfunc);
+@@ -554,10 +557,10 @@ static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev,
+ static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
+ 					struct device_node *np,
+ 					struct pinctrl_map **map,
+-					unsigned *reserved_maps,
+-					unsigned *num_maps)
++					unsigned int *reserved_maps,
++					unsigned int *num_maps)
+ {
+-	unsigned num_pins, num_configs, reserve;
++	unsigned int num_pins, num_configs, reserve;
+ 	unsigned long *configs;
+ 	struct property	*pins;
+ 	u32 pinfunc;
+@@ -628,10 +631,10 @@ static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
+ static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
+ 				     struct device_node *np_config,
+ 				     struct pinctrl_map **map,
+-				     unsigned *num_maps)
++				     unsigned int *num_maps)
+ {
+ 	struct device_node *np;
+-	unsigned reserved_maps;
++	unsigned int reserved_maps;
+ 	int ret;
+ 
+ 	*map = NULL;
+@@ -679,13 +682,13 @@ static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev)
+ }
+ 
+ static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev,
+-					       unsigned selector)
++					       unsigned int selector)
+ {
+ 	return atmel_functions[selector];
+ }
+ 
+ static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,
+-					 unsigned selector,
++					 unsigned int selector,
+ 					 const char * const **groups,
+ 					 unsigned * const num_groups)
+ {
+@@ -698,11 +701,11 @@ static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,
+ }
+ 
+ static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,
+-			     unsigned function,
+-			     unsigned group)
++			     unsigned int function,
++			     unsigned int group)
+ {
+ 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
+-	unsigned pin;
++	unsigned int pin;
+ 	u32 conf;
+ 
+ 	dev_dbg(pctldev->dev, "enable function %s group %s\n",
+@@ -726,13 +729,13 @@ static const struct pinmux_ops atmel_pmxops = {
+ };
+ 
+ static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
+-					   unsigned group,
++					   unsigned int group,
+ 					   unsigned long *config)
+ {
+ 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
+-	unsigned param = pinconf_to_config_param(*config), arg = 0;
++	unsigned int param = pinconf_to_config_param(*config), arg = 0;
+ 	struct atmel_group *grp = atmel_pioctrl->groups + group;
+-	unsigned pin_id = grp->pin;
++	unsigned int pin_id = grp->pin;
+ 	u32 res;
+ 
+ 	res = atmel_pin_config_read(pctldev, pin_id);
+@@ -786,21 +789,21 @@ static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
+ }
+ 
+ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
+-					   unsigned group,
++					   unsigned int group,
+ 					   unsigned long *configs,
+-					   unsigned num_configs)
++					   unsigned int num_configs)
+ {
+ 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
+ 	struct atmel_group *grp = atmel_pioctrl->groups + group;
+-	unsigned bank, pin, pin_id = grp->pin;
++	unsigned int bank, pin, pin_id = grp->pin;
+ 	u32 mask, conf = 0;
+ 	int i;
+ 
+ 	conf = atmel_pin_config_read(pctldev, pin_id);
+ 
+ 	for (i = 0; i < num_configs; i++) {
+-		unsigned param = pinconf_to_config_param(configs[i]);
+-		unsigned arg = pinconf_to_config_argument(configs[i]);
++		unsigned int param = pinconf_to_config_param(configs[i]);
++		unsigned int arg = pinconf_to_config_argument(configs[i]);
+ 
+ 		dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
+ 			__func__, pin_id, configs[i]);
+@@ -900,7 +903,8 @@ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
+ }
+ 
+ static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
+-					   struct seq_file *s, unsigned pin_id)
++					   struct seq_file *s,
++					   unsigned int pin_id)
+ {
+ 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
+ 	u32 conf;
+@@ -1108,8 +1112,8 @@ static int atmel_pinctrl_probe(struct platform_device *pdev)
+ 		return -ENOMEM;
+ 	for (i = 0 ; i < atmel_pioctrl->npins; i++) {
+ 		struct atmel_group *group = atmel_pioctrl->groups + i;
+-		unsigned bank = ATMEL_PIO_BANK(i);
+-		unsigned line = ATMEL_PIO_LINE(i);
++		unsigned int bank = ATMEL_PIO_BANK(i);
++		unsigned int line = ATMEL_PIO_LINE(i);
+ 
+ 		atmel_pioctrl->pins[i] = devm_kzalloc(dev,
+ 				sizeof(**atmel_pioctrl->pins), GFP_KERNEL);
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/148-net-macb-Add-default-usrio-config-to-default-gem-con.patch

@@ -0,0 +1,63 @@
+From 096f58e564aed56936ef6de42a44c3101e9b8ed1 Mon Sep 17 00:00:00 2001
+From: Atish Patra <[email protected]>
+Date: Wed, 3 Mar 2021 11:55:49 -0800
+Subject: [PATCH 148/247] net: macb: Add default usrio config to default gem
+ config
+
+There is no usrio config defined for default gem config leading to
+a kernel panic devices that don't define a data. This issue can be
+reprdouced with microchip polar fire soc where compatible string
+is defined as "cdns,macb".
+
+Fixes: edac63861db7 ("add userio bits as platform configuration")
+
+Signed-off-by: Atish Patra <[email protected]>
+Acked-by: Nicolas Ferre <[email protected]>
+Signed-off-by: David S. Miller <[email protected]>
+---
+ drivers/net/ethernet/cadence/macb_main.c | 15 ++++++++-------
+ 1 file changed, 8 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
+index d5bd640d3fa4..a8d266d72779 100644
+--- a/drivers/net/ethernet/cadence/macb_main.c
++++ b/drivers/net/ethernet/cadence/macb_main.c
+@@ -3837,6 +3837,13 @@ static int macb_init(struct platform_device *pdev)
+ 	return 0;
+ }
+ 
++static const struct macb_usrio_config macb_default_usrio = {
++	.mii = MACB_BIT(MII),
++	.rmii = MACB_BIT(RMII),
++	.rgmii = GEM_BIT(RGMII),
++	.refclk = MACB_BIT(CLKEN),
++};
++
+ #if defined(CONFIG_OF)
+ /* 1518 rounded up */
+ #define AT91ETHER_MAX_RBUFF_SZ	0x600
+@@ -4352,13 +4359,6 @@ static int fu540_c000_init(struct platform_device *pdev)
+ 	return macb_init(pdev);
+ }
+ 
+-static const struct macb_usrio_config macb_default_usrio = {
+-	.mii = MACB_BIT(MII),
+-	.rmii = MACB_BIT(RMII),
+-	.rgmii = GEM_BIT(RGMII),
+-	.refclk = MACB_BIT(CLKEN),
+-};
+-
+ static const struct macb_usrio_config sama7g5_usrio = {
+ 	.mii = 0,
+ 	.rmii = 1,
+@@ -4507,6 +4507,7 @@ static const struct macb_config default_gem_config = {
+ 	.dma_burst_length = 16,
+ 	.clk_init = macb_clk_init,
+ 	.init = macb_init,
++	.usrio = &macb_default_usrio,
+ 	.jumbo_max_len = 10240,
+ };
+ 
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/149-ARM-at91-pm-Move-prototypes-to-mutually-included-hea.patch

@@ -0,0 +1,118 @@
+From 746aba88c64e409cbc3757a5f81fad5b5c74bbcc Mon Sep 17 00:00:00 2001
+From: Lee Jones <[email protected]>
+Date: Wed, 3 Mar 2021 12:41:49 +0000
+Subject: [PATCH 149/247] ARM: at91: pm: Move prototypes to mutually included
+ header
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Both the caller and the supplier's source file should have access to
+the include file containing the prototypes.
+
+Fixes the following W=1 kernel build warning(s):
+
+ drivers/pinctrl/pinctrl-at91.c:1637:6: warning: no previous prototype for ‘at91_pinctrl_gpio_suspend’ [-Wmissing-prototypes]
+ 1637 | void at91_pinctrl_gpio_suspend(void)
+ | ^~~~~~~~~~~~~~~~~~~~~~~~~
+ drivers/pinctrl/pinctrl-at91.c:1661:6: warning: no previous prototype for ‘at91_pinctrl_gpio_resume’ [-Wmissing-prototypes]
+ 1661 | void at91_pinctrl_gpio_resume(void)
+ | ^~~~~~~~~~~~~~~~~~~~~~~~
+
+Cc: Russell King <[email protected]>
+Cc: Nicolas Ferre <[email protected]>
+Cc: Alexandre Belloni <[email protected]>
+Cc: Ludovic Desroches <[email protected]>
+Signed-off-by: Lee Jones <[email protected]>
+Acked-by: Linus Walleij <[email protected]>
+Signed-off-by: Alexandre Belloni <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+---
+ arch/arm/mach-at91/pm.c        | 19 ++++++++-----------
+ drivers/pinctrl/pinctrl-at91.c |  2 ++
+ include/soc/at91/pm.h          | 16 ++++++++++++++++
+ 3 files changed, 26 insertions(+), 11 deletions(-)
+ create mode 100644 include/soc/at91/pm.h
+
+diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
+index 3f015cb6ec2b..2dee383f9050 100644
+--- a/arch/arm/mach-at91/pm.c
++++ b/arch/arm/mach-at91/pm.c
+@@ -17,6 +17,8 @@
+ #include <linux/clk/at91_pmc.h>
+ #include <linux/platform_data/atmel.h>
+ 
++#include <soc/at91/pm.h>
++
+ #include <asm/cacheflush.h>
+ #include <asm/fncpy.h>
+ #include <asm/system_misc.h>
+@@ -25,17 +27,6 @@
+ #include "generic.h"
+ #include "pm.h"
+ 
+-/*
+- * FIXME: this is needed to communicate between the pinctrl driver and
+- * the PM implementation in the machine. Possibly part of the PM
+- * implementation should be moved down into the pinctrl driver and get
+- * called as part of the generic suspend/resume path.
+- */
+-#ifdef CONFIG_PINCTRL_AT91
+-extern void at91_pinctrl_gpio_suspend(void);
+-extern void at91_pinctrl_gpio_resume(void);
+-#endif
+-
+ struct at91_soc_pm {
+ 	int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
+ 	int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
+@@ -326,6 +317,12 @@ static void at91_pm_suspend(suspend_state_t state)
+ static int at91_pm_enter(suspend_state_t state)
+ {
+ #ifdef CONFIG_PINCTRL_AT91
++	/*
++	 * FIXME: this is needed to communicate between the pinctrl driver and
++	 * the PM implementation in the machine. Possibly part of the PM
++	 * implementation should be moved down into the pinctrl driver and get
++	 * called as part of the generic suspend/resume path.
++	 */
+ 	at91_pinctrl_gpio_suspend();
+ #endif
+ 
+diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
+index 9015486e38c1..dcbb71fa1b2b 100644
+--- a/drivers/pinctrl/pinctrl-at91.c
++++ b/drivers/pinctrl/pinctrl-at91.c
+@@ -23,6 +23,8 @@
+ /* Since we request GPIOs from ourself */
+ #include <linux/pinctrl/consumer.h>
+ 
++#include <soc/at91/pm.h>
++
+ #include "pinctrl-at91.h"
+ #include "core.h"
+ 
+diff --git a/include/soc/at91/pm.h b/include/soc/at91/pm.h
+new file mode 100644
+index 000000000000..7a41e53a3ffa
+--- /dev/null
++++ b/include/soc/at91/pm.h
+@@ -0,0 +1,16 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++/*
++ * Atmel Power Management
++ *
++ * Copyright (C) 2020 Atmel
++ *
++ * Author: Lee Jones <[email protected]>
++ */
++
++#ifndef __SOC_ATMEL_PM_H
++#define __SOC_ATMEL_PM_H
++
++void at91_pinctrl_gpio_suspend(void);
++void at91_pinctrl_gpio_resume(void);
++
++#endif /* __SOC_ATMEL_PM_H */
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/150-ASoC-mchp-i2s-mcc-Add-compatible-for-SAMA7G5.patch

@@ -0,0 +1,53 @@
+From d6493e6f1c42f7ad350ea25e11f0e71fc32e6116 Mon Sep 17 00:00:00 2001
+From: Codrin Ciubotariu <[email protected]>
+Date: Mon, 1 Mar 2021 19:09:00 +0200
+Subject: [PATCH 150/247] ASoC: mchp-i2s-mcc: Add compatible for SAMA7G5
+
+Microchip's new SAMA7G5 includes an updated I2S-MCC compatible with the
+previous version found on SAM9X60. The new controller includes 8 (4 * 2)
+input and output data pins for up to 8 channels for I2S and Left-Justified
+formats.
+
+Signed-off-by: Codrin Ciubotariu <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Mark Brown <[email protected]>
+---
+ sound/soc/atmel/Kconfig        | 3 +++
+ sound/soc/atmel/mchp-i2s-mcc.c | 3 +++
+ 2 files changed, 6 insertions(+)
+
+diff --git a/sound/soc/atmel/Kconfig b/sound/soc/atmel/Kconfig
+index 89210048e6c2..802962935df0 100644
+--- a/sound/soc/atmel/Kconfig
++++ b/sound/soc/atmel/Kconfig
+@@ -126,10 +126,13 @@ config SND_MCHP_SOC_I2S_MCC
+ 	  Say Y or M if you want to add support for I2S Multi-Channel ASoC
+ 	  driver on the following Microchip platforms:
+ 	  - sam9x60
++	  - sama7g5
+ 
+ 	  The I2SMCC complies with the Inter-IC Sound (I2S) bus specification
+ 	  and supports a Time Division Multiplexed (TDM) interface with
+ 	  external multi-channel audio codecs.
++	  Starting with sama7g5, I2S and Left-Justified multi-channel is
++	  supported by using multiple data pins, output and input, without TDM.
+ 
+ config SND_MCHP_SOC_SPDIFTX
+ 	tristate "Microchip ASoC driver for boards using S/PDIF TX"
+diff --git a/sound/soc/atmel/mchp-i2s-mcc.c b/sound/soc/atmel/mchp-i2s-mcc.c
+index 04acc18f2d72..6a754cef9607 100644
+--- a/sound/soc/atmel/mchp-i2s-mcc.c
++++ b/sound/soc/atmel/mchp-i2s-mcc.c
+@@ -873,6 +873,9 @@ static const struct of_device_id mchp_i2s_mcc_dt_ids[] = {
+ 	{
+ 		.compatible = "microchip,sam9x60-i2smcc",
+ 	},
++	{
++		.compatible = "microchip,sama7g5-i2smcc",
++	},
+ 	{ /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, mchp_i2s_mcc_dt_ids);
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/151-ASoC-mchp-i2s-mcc-Add-multi-channel-support-for-I2S-.patch

@@ -0,0 +1,118 @@
+From 5bef4e8125d09443b5486971d5550ed285cde4b1 Mon Sep 17 00:00:00 2001
+From: Codrin Ciubotariu <[email protected]>
+Date: Mon, 1 Mar 2021 19:09:01 +0200
+Subject: [PATCH 151/247] ASoC: mchp-i2s-mcc: Add multi-channel support for I2S
+ and LEFT_J formats
+
+The latest I2S-MCC available in SAMA7G5 supports multi-channel for I2S and
+Left-Justified formats. For this, the new version uses 8 (4 * 2) input and
+output pins, with each pin being responsible for 2 channels. This sums up
+to a total of 8 channels for synchronous capture and playback.
+
+Signed-off-by: Codrin Ciubotariu <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Mark Brown <[email protected]>
+---
+ sound/soc/atmel/mchp-i2s-mcc.c | 38 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+
+diff --git a/sound/soc/atmel/mchp-i2s-mcc.c b/sound/soc/atmel/mchp-i2s-mcc.c
+index 6a754cef9607..dca4fd1e2dfd 100644
+--- a/sound/soc/atmel/mchp-i2s-mcc.c
++++ b/sound/soc/atmel/mchp-i2s-mcc.c
+@@ -16,6 +16,7 @@
+ #include <linux/clk.h>
+ #include <linux/mfd/syscon.h>
+ #include <linux/lcm.h>
++#include <linux/of_device.h>
+ 
+ #include <sound/core.h>
+ #include <sound/pcm.h>
+@@ -225,6 +226,10 @@ static const struct regmap_config mchp_i2s_mcc_regmap_config = {
+ 	.max_register = MCHP_I2SMCC_VERSION,
+ };
+ 
++struct mchp_i2s_mcc_soc_data {
++	unsigned int	data_pin_pair_num;
++};
++
+ struct mchp_i2s_mcc_dev {
+ 	struct wait_queue_head			wq_txrdy;
+ 	struct wait_queue_head			wq_rxrdy;
+@@ -232,6 +237,7 @@ struct mchp_i2s_mcc_dev {
+ 	struct regmap				*regmap;
+ 	struct clk				*pclk;
+ 	struct clk				*gclk;
++	const struct mchp_i2s_mcc_soc_data	*soc;
+ 	struct snd_dmaengine_dai_dma_data	playback;
+ 	struct snd_dmaengine_dai_dma_data	capture;
+ 	unsigned int				fmt;
+@@ -549,6 +555,17 @@ static int mchp_i2s_mcc_hw_params(struct snd_pcm_substream *substream,
+ 	}
+ 
+ 	if (dev->fmt & (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J)) {
++		/* for I2S and LEFT_J one pin is needed for every 2 channels */
++		if (channels > dev->soc->data_pin_pair_num * 2) {
++			dev_err(dev->dev,
++				"unsupported number of audio channels: %d\n",
++				channels);
++			return -EINVAL;
++		}
++
++		/* enable for interleaved format */
++		mrb |= MCHP_I2SMCC_MRB_CRAMODE_REGULAR;
++
+ 		switch (channels) {
+ 		case 1:
+ 			if (is_playback)
+@@ -558,6 +575,12 @@ static int mchp_i2s_mcc_hw_params(struct snd_pcm_substream *substream,
+ 			break;
+ 		case 2:
+ 			break;
++		case 4:
++			mra |= MCHP_I2SMCC_MRA_WIRECFG_I2S_2_TDM_1;
++			break;
++		case 8:
++			mra |= MCHP_I2SMCC_MRA_WIRECFG_I2S_4_TDM_2;
++			break;
+ 		default:
+ 			dev_err(dev->dev, "unsupported number of audio channels\n");
+ 			return -EINVAL;
+@@ -869,12 +892,22 @@ static const struct snd_soc_component_driver mchp_i2s_mcc_component = {
+ };
+ 
+ #ifdef CONFIG_OF
++static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sam9x60 = {
++	.data_pin_pair_num = 1,
++};
++
++static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sama7g5 = {
++	.data_pin_pair_num = 4,
++};
++
+ static const struct of_device_id mchp_i2s_mcc_dt_ids[] = {
+ 	{
+ 		.compatible = "microchip,sam9x60-i2smcc",
++		.data = &mchp_i2s_mcc_sam9x60,
+ 	},
+ 	{
+ 		.compatible = "microchip,sama7g5-i2smcc",
++		.data = &mchp_i2s_mcc_sama7g5,
+ 	},
+ 	{ /* sentinel */ }
+ };
+@@ -932,6 +965,11 @@ static int mchp_i2s_mcc_probe(struct platform_device *pdev)
+ 		dev->gclk = NULL;
+ 	}
+ 
++	dev->soc = of_device_get_match_data(&pdev->dev);
++	if (!dev->soc) {
++		dev_err(&pdev->dev, "failed to get soc data\n");
++		return -ENODEV;
++	}
+ 	dev->dev = &pdev->dev;
+ 	dev->regmap = regmap;
+ 	platform_set_drvdata(pdev, dev);
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/152-ASoC-mchp-i2s-mcc-Add-support-to-select-TDM-pins.patch

@@ -0,0 +1,113 @@
+From 2bbdc5b38603384996271a8817b0578a2360af2f Mon Sep 17 00:00:00 2001
+From: Codrin Ciubotariu <[email protected]>
+Date: Mon, 1 Mar 2021 19:09:03 +0200
+Subject: [PATCH 152/247] ASoC: mchp-i2s-mcc: Add support to select TDM pins
+
+SAMA7G5's I2S-MCC has 4 pairs of DIN/DOUT pins. Since TDM only uses a
+single pair of pins for synchronous capture and playback, the controller
+needs to be told which of the pair is connected. This can be mentioned
+using the "microchip,tdm-data-pair" property from DT. The property is
+optional, useful only if TDM is used. If it's missing, DIN/DOUT 0 pins
+will be used by default.
+
+Signed-off-by: Codrin Ciubotariu <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Mark Brown <[email protected]>
+---
+ sound/soc/atmel/mchp-i2s-mcc.c | 52 +++++++++++++++++++++++++++++++---
+ 1 file changed, 48 insertions(+), 4 deletions(-)
+
+diff --git a/sound/soc/atmel/mchp-i2s-mcc.c b/sound/soc/atmel/mchp-i2s-mcc.c
+index dca4fd1e2dfd..0818fa864f0e 100644
+--- a/sound/soc/atmel/mchp-i2s-mcc.c
++++ b/sound/soc/atmel/mchp-i2s-mcc.c
+@@ -100,6 +100,8 @@
+ #define MCHP_I2SMCC_MRA_DATALENGTH_8_BITS_COMPACT	(7 << 1)
+ 
+ #define MCHP_I2SMCC_MRA_WIRECFG_MASK		GENMASK(5, 4)
++#define MCHP_I2SMCC_MRA_WIRECFG_TDM(pin)	(((pin) << 4) & \
++						 MCHP_I2SMCC_MRA_WIRECFG_MASK)
+ #define MCHP_I2SMCC_MRA_WIRECFG_I2S_1_TDM_0	(0 << 4)
+ #define MCHP_I2SMCC_MRA_WIRECFG_I2S_2_TDM_1	(1 << 4)
+ #define MCHP_I2SMCC_MRA_WIRECFG_I2S_4_TDM_2	(2 << 4)
+@@ -245,6 +247,7 @@ struct mchp_i2s_mcc_dev {
+ 	unsigned int				frame_length;
+ 	int					tdm_slots;
+ 	int					channels;
++	u8					tdm_data_pair;
+ 	unsigned int				gclk_use:1;
+ 	unsigned int				gclk_running:1;
+ 	unsigned int				tx_rdy:1;
+@@ -589,6 +592,8 @@ static int mchp_i2s_mcc_hw_params(struct snd_pcm_substream *substream,
+ 		if (!frame_length)
+ 			frame_length = 2 * params_physical_width(params);
+ 	} else if (dev->fmt & SND_SOC_DAIFMT_DSP_A) {
++		mra |= MCHP_I2SMCC_MRA_WIRECFG_TDM(dev->tdm_data_pair);
++
+ 		if (dev->tdm_slots) {
+ 			if (channels % 2 && channels * 2 <= dev->tdm_slots) {
+ 				/*
+@@ -914,6 +919,45 @@ static const struct of_device_id mchp_i2s_mcc_dt_ids[] = {
+ MODULE_DEVICE_TABLE(of, mchp_i2s_mcc_dt_ids);
+ #endif
+ 
++static int mchp_i2s_mcc_soc_data_parse(struct platform_device *pdev,
++				       struct mchp_i2s_mcc_dev *dev)
++{
++	int err;
++
++	if (!dev->soc) {
++		dev_err(&pdev->dev, "failed to get soc data\n");
++		return -ENODEV;
++	}
++
++	if (dev->soc->data_pin_pair_num == 1)
++		return 0;
++
++	err = of_property_read_u8(pdev->dev.of_node, "microchip,tdm-data-pair",
++				  &dev->tdm_data_pair);
++	if (err < 0 && err != -EINVAL) {
++		dev_err(&pdev->dev,
++			"bad property data for 'microchip,tdm-data-pair': %d",
++			err);
++		return err;
++	}
++	if (err == -EINVAL) {
++		dev_info(&pdev->dev,
++			 "'microchip,tdm-data-pair' not found; assuming DIN/DOUT 0 for TDM\n");
++		dev->tdm_data_pair = 0;
++	} else {
++		if (dev->tdm_data_pair > dev->soc->data_pin_pair_num - 1) {
++			dev_err(&pdev->dev,
++				"invalid value for 'microchip,tdm-data-pair': %d\n",
++				dev->tdm_data_pair);
++			return -EINVAL;
++		}
++		dev_dbg(&pdev->dev, "TMD format on DIN/DOUT %d pins\n",
++			dev->tdm_data_pair);
++	}
++
++	return 0;
++}
++
+ static int mchp_i2s_mcc_probe(struct platform_device *pdev)
+ {
+ 	struct mchp_i2s_mcc_dev *dev;
+@@ -966,10 +1010,10 @@ static int mchp_i2s_mcc_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	dev->soc = of_device_get_match_data(&pdev->dev);
+-	if (!dev->soc) {
+-		dev_err(&pdev->dev, "failed to get soc data\n");
+-		return -ENODEV;
+-	}
++	err = mchp_i2s_mcc_soc_data_parse(pdev, dev);
++	if (err < 0)
++		return err;
++
+ 	dev->dev = &pdev->dev;
+ 	dev->regmap = regmap;
+ 	platform_set_drvdata(pdev, dev);
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/153-ASoC-mchp-i2s-mcc-Add-FIFOs-support.patch

@@ -0,0 +1,192 @@
+From 36bb4f0ab8e7ef69cc11d4d888aa898223b0e901 Mon Sep 17 00:00:00 2001
+From: Codrin Ciubotariu <[email protected]>
+Date: Mon, 1 Mar 2021 19:09:04 +0200
+Subject: [PATCH 153/247] ASoC: mchp-i2s-mcc: Add FIFOs support
+
+I2S-MCC found on SAMA7G5 includes 2 FIFOs (capture and playback). When
+FIFOs are enabled, bits I2SMCC_ISRA.TXLRDYx and I2SMCC_ISRA.TXRRDYx must
+not be used. Bits I2SMCC_ISRB.TXFFRDY and I2SMCC_ISRB.RXFFRDY must be used
+instead.
+
+Signed-off-by: Codrin Ciubotariu <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Mark Brown <[email protected]>
+---
+ sound/soc/atmel/mchp-i2s-mcc.c | 76 +++++++++++++++++++++++++---------
+ 1 file changed, 56 insertions(+), 20 deletions(-)
+
+diff --git a/sound/soc/atmel/mchp-i2s-mcc.c b/sound/soc/atmel/mchp-i2s-mcc.c
+index 0818fa864f0e..188484e84f94 100644
+--- a/sound/soc/atmel/mchp-i2s-mcc.c
++++ b/sound/soc/atmel/mchp-i2s-mcc.c
+@@ -176,7 +176,7 @@
+  */
+ #define MCHP_I2SMCC_MRB_CRAMODE_REGULAR		(1 << 0)
+ 
+-#define MCHP_I2SMCC_MRB_FIFOEN			BIT(1)
++#define MCHP_I2SMCC_MRB_FIFOEN			BIT(4)
+ 
+ #define MCHP_I2SMCC_MRB_DMACHUNK_MASK		GENMASK(9, 8)
+ #define MCHP_I2SMCC_MRB_DMACHUNK(no_words) \
+@@ -230,6 +230,7 @@ static const struct regmap_config mchp_i2s_mcc_regmap_config = {
+ 
+ struct mchp_i2s_mcc_soc_data {
+ 	unsigned int	data_pin_pair_num;
++	bool		has_fifo;
+ };
+ 
+ struct mchp_i2s_mcc_dev {
+@@ -257,7 +258,7 @@ struct mchp_i2s_mcc_dev {
+ static irqreturn_t mchp_i2s_mcc_interrupt(int irq, void *dev_id)
+ {
+ 	struct mchp_i2s_mcc_dev *dev = dev_id;
+-	u32 sra, imra, srb, imrb, pendinga, pendingb, idra = 0;
++	u32 sra, imra, srb, imrb, pendinga, pendingb, idra = 0, idrb = 0;
+ 	irqreturn_t ret = IRQ_NONE;
+ 
+ 	regmap_read(dev->regmap, MCHP_I2SMCC_IMRA, &imra);
+@@ -275,24 +276,36 @@ static irqreturn_t mchp_i2s_mcc_interrupt(int irq, void *dev_id)
+ 	 * Tx/Rx ready interrupts are enabled when stopping only, to assure
+ 	 * availability and to disable clocks if necessary
+ 	 */
+-	idra |= pendinga & (MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels) |
+-			    MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));
+-	if (idra)
++	if (dev->soc->has_fifo) {
++		idrb |= pendingb & (MCHP_I2SMCC_INT_TXFFRDY |
++				    MCHP_I2SMCC_INT_RXFFRDY);
++	} else {
++		idra |= pendinga & (MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels) |
++				    MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));
++	}
++	if (idra || idrb)
+ 		ret = IRQ_HANDLED;
+ 
+-	if ((imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) &&
+-	    (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) ==
+-	    (idra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels))) {
++	if ((!dev->soc->has_fifo &&
++	     (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) &&
++	     (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) ==
++	     (idra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels))) ||
++	    (dev->soc->has_fifo && imrb & MCHP_I2SMCC_INT_TXFFRDY)) {
+ 		dev->tx_rdy = 1;
+ 		wake_up_interruptible(&dev->wq_txrdy);
+ 	}
+-	if ((imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) &&
+-	    (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) ==
+-	    (idra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels))) {
++	if ((!dev->soc->has_fifo &&
++	     (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) &&
++	     (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) ==
++	     (idra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels))) ||
++	    (dev->soc->has_fifo && imrb & MCHP_I2SMCC_INT_RXFFRDY)) {
+ 		dev->rx_rdy = 1;
+ 		wake_up_interruptible(&dev->wq_rxrdy);
+ 	}
+-	regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, idra);
++	if (dev->soc->has_fifo)
++		regmap_write(dev->regmap, MCHP_I2SMCC_IDRB, idrb);
++	else
++		regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, idra);
+ 
+ 	return ret;
+ }
+@@ -664,6 +677,10 @@ static int mchp_i2s_mcc_hw_params(struct snd_pcm_substream *substream,
+ 		}
+ 	}
+ 
++	/* enable FIFO if available */
++	if (dev->soc->has_fifo)
++		mrb |= MCHP_I2SMCC_MRB_FIFOEN;
++
+ 	/*
+ 	 * If we are already running, the wanted setup must be
+ 	 * the same with the one that's currently ongoing
+@@ -726,8 +743,13 @@ static int mchp_i2s_mcc_hw_free(struct snd_pcm_substream *substream,
+ 		if (err == 0) {
+ 			dev_warn_once(dev->dev,
+ 				      "Timeout waiting for Tx ready\n");
+-			regmap_write(dev->regmap, MCHP_I2SMCC_IDRA,
+-				     MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels));
++			if (dev->soc->has_fifo)
++				regmap_write(dev->regmap, MCHP_I2SMCC_IDRB,
++					     MCHP_I2SMCC_INT_TXFFRDY);
++			else
++				regmap_write(dev->regmap, MCHP_I2SMCC_IDRA,
++					     MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels));
++
+ 			dev->tx_rdy = 1;
+ 		}
+ 	} else {
+@@ -737,8 +759,12 @@ static int mchp_i2s_mcc_hw_free(struct snd_pcm_substream *substream,
+ 		if (err == 0) {
+ 			dev_warn_once(dev->dev,
+ 				      "Timeout waiting for Rx ready\n");
+-			regmap_write(dev->regmap, MCHP_I2SMCC_IDRA,
+-				     MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));
++			if (dev->soc->has_fifo)
++				regmap_write(dev->regmap, MCHP_I2SMCC_IDRB,
++					     MCHP_I2SMCC_INT_RXFFRDY);
++			else
++				regmap_write(dev->regmap, MCHP_I2SMCC_IDRA,
++					     MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));
+ 			dev->rx_rdy = 1;
+ 		}
+ 	}
+@@ -765,7 +791,7 @@ static int mchp_i2s_mcc_trigger(struct snd_pcm_substream *substream, int cmd,
+ 	struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
+ 	bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
+ 	u32 cr = 0;
+-	u32 iera = 0;
++	u32 iera = 0, ierb = 0;
+ 	u32 sr;
+ 	int err;
+ 
+@@ -789,7 +815,10 @@ static int mchp_i2s_mcc_trigger(struct snd_pcm_substream *substream, int cmd,
+ 			 * Enable Tx Ready interrupts on all channels
+ 			 * to assure all data is sent
+ 			 */
+-			iera = MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels);
++			if (dev->soc->has_fifo)
++				ierb = MCHP_I2SMCC_INT_TXFFRDY;
++			else
++				iera = MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels);
+ 		} else if (!is_playback && (sr & MCHP_I2SMCC_SR_RXEN)) {
+ 			cr = MCHP_I2SMCC_CR_RXDIS;
+ 			dev->rx_rdy = 0;
+@@ -797,7 +826,10 @@ static int mchp_i2s_mcc_trigger(struct snd_pcm_substream *substream, int cmd,
+ 			 * Enable Rx Ready interrupts on all channels
+ 			 * to assure all data is received
+ 			 */
+-			iera = MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels);
++			if (dev->soc->has_fifo)
++				ierb = MCHP_I2SMCC_INT_RXFFRDY;
++			else
++				iera = MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels);
+ 		}
+ 		break;
+ 	default:
+@@ -815,7 +847,10 @@ static int mchp_i2s_mcc_trigger(struct snd_pcm_substream *substream, int cmd,
+ 		}
+ 	}
+ 
+-	regmap_write(dev->regmap, MCHP_I2SMCC_IERA, iera);
++	if (dev->soc->has_fifo)
++		regmap_write(dev->regmap, MCHP_I2SMCC_IERB, ierb);
++	else
++		regmap_write(dev->regmap, MCHP_I2SMCC_IERA, iera);
+ 	regmap_write(dev->regmap, MCHP_I2SMCC_CR, cr);
+ 
+ 	return 0;
+@@ -903,6 +938,7 @@ static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sam9x60 = {
+ 
+ static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sama7g5 = {
+ 	.data_pin_pair_num = 4,
++	.has_fifo = true,
+ };
+ 
+ static const struct of_device_id mchp_i2s_mcc_dt_ids[] = {
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/154-pinctrl-at91-pio4-Fix-slew-rate-disablement.patch

@@ -0,0 +1,54 @@
+From dc07cbae6e96843d26e8f10b16e901620bd16462 Mon Sep 17 00:00:00 2001
+From: Tudor Ambarus <[email protected]>
+Date: Fri, 9 Apr 2021 11:25:22 +0300
+Subject: [PATCH 154/247] pinctrl: at91-pio4: Fix slew rate disablement
+
+The slew rate was enabled by default for each configuration of the
+pin. In case the pin had more than one configuration, even if
+we set the slew rate as disabled in the device tree, the next pin
+configuration would set again the slew rate enabled by default,
+overwriting the slew rate disablement.
+Instead of enabling the slew rate by default for each pin configuration,
+enable the slew rate by default just once per pin, regardless of the
+number of configurations. This way the slew rate disablement will also
+work for cases where pins have multiple configurations.
+
+Fixes: c709135e576b ("pinctrl: at91-pio4: add support for slew-rate")
+Signed-off-by: Tudor Ambarus <[email protected]>
+Reviewed-by: Claudiu Beznea <[email protected]>
+Acked-by: Ludovic Desroches <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Linus Walleij <[email protected]>
+---
+ drivers/pinctrl/pinctrl-at91-pio4.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c
+index a5d328808e4c..4c01d8471ffa 100644
+--- a/drivers/pinctrl/pinctrl-at91-pio4.c
++++ b/drivers/pinctrl/pinctrl-at91-pio4.c
+@@ -801,6 +801,10 @@ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
+ 
+ 	conf = atmel_pin_config_read(pctldev, pin_id);
+ 
++	/* Keep slew rate enabled by default. */
++	if (atmel_pioctrl->slew_rate_support)
++		conf |= ATMEL_PIO_SR_MASK;
++
+ 	for (i = 0; i < num_configs; i++) {
+ 		unsigned int param = pinconf_to_config_param(configs[i]);
+ 		unsigned int arg = pinconf_to_config_argument(configs[i]);
+@@ -808,10 +812,6 @@ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
+ 		dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
+ 			__func__, pin_id, configs[i]);
+ 
+-		/* Keep slew rate enabled by default. */
+-		if (atmel_pioctrl->slew_rate_support)
+-			conf |= ATMEL_PIO_SR_MASK;
+-
+ 		switch (param) {
+ 		case PIN_CONFIG_BIAS_DISABLE:
+ 			conf &= (~ATMEL_PIO_PUEN_MASK);
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/155-media-atmel-properly-get-pm_runtime.patch

@@ -0,0 +1,166 @@
+From c7660cc977621c4a14d870d523918df067f0db39 Mon Sep 17 00:00:00 2001
+From: Mauro Carvalho Chehab <[email protected]>
+Date: Fri, 23 Apr 2021 16:47:42 +0200
+Subject: [PATCH 155/247] media: atmel: properly get pm_runtime
+
+There are several issues in the way the atmel driver handles
+pm_runtime_get_sync():
+
+- it doesn't check return codes;
+- it doesn't properly decrement the usage_count on all places;
+- it starts streaming even if pm_runtime_get_sync() fails.
+- while it tries to get pm_runtime at the clock enable logic,
+  it doesn't check if the operation was suceeded.
+
+Replace all occurrences of it to use the new kAPI:
+pm_runtime_resume_and_get(), which ensures that, if the
+return code is not negative, the usage_count was incremented.
+
+With that, add additional checks when this is called, in order
+to ensure that errors will be properly addressed.
+
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c | 30 ++++++++++++++-----
+ drivers/media/platform/atmel/atmel-isi.c      | 19 +++++++++---
+ 2 files changed, 38 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index fe3ec8d0eaee..ce8e1351fa53 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -294,9 +294,13 @@ static int isc_wait_clk_stable(struct clk_hw *hw)
+ static int isc_clk_prepare(struct clk_hw *hw)
+ {
+ 	struct isc_clk *isc_clk = to_isc_clk(hw);
++	int ret;
+ 
+-	if (isc_clk->id == ISC_ISPCK)
+-		pm_runtime_get_sync(isc_clk->dev);
++	if (isc_clk->id == ISC_ISPCK) {
++		ret = pm_runtime_resume_and_get(isc_clk->dev);
++		if (ret < 0)
++			return ret;
++	}
+ 
+ 	return isc_wait_clk_stable(hw);
+ }
+@@ -353,9 +357,13 @@ static int isc_clk_is_enabled(struct clk_hw *hw)
+ {
+ 	struct isc_clk *isc_clk = to_isc_clk(hw);
+ 	u32 status;
++	int ret;
+ 
+-	if (isc_clk->id == ISC_ISPCK)
+-		pm_runtime_get_sync(isc_clk->dev);
++	if (isc_clk->id == ISC_ISPCK) {
++		ret = pm_runtime_resume_and_get(isc_clk->dev);
++		if (ret < 0)
++			return 0;
++	}
+ 
+ 	regmap_read(isc_clk->regmap, ISC_CLKSR, &status);
+ 
+@@ -807,7 +815,12 @@ static int isc_start_streaming(struct vb2_queue *vq, unsigned int count)
+ 		goto err_start_stream;
+ 	}
+ 
+-	pm_runtime_get_sync(isc->dev);
++	ret = pm_runtime_resume_and_get(isc->dev);
++	if (ret < 0) {
++		v4l2_err(&isc->v4l2_dev, "RPM resume failed in subdev %d\n",
++			 ret);
++		goto err_pm_get;
++	}
+ 
+ 	ret = isc_configure(isc);
+ 	if (unlikely(ret))
+@@ -838,7 +851,7 @@ static int isc_start_streaming(struct vb2_queue *vq, unsigned int count)
+ 
+ err_configure:
+ 	pm_runtime_put_sync(isc->dev);
+-
++err_pm_get:
+ 	v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
+ 
+ err_start_stream:
+@@ -1809,6 +1822,7 @@ static void isc_awb_work(struct work_struct *w)
+ 	u32 baysel;
+ 	unsigned long flags;
+ 	u32 min, max;
++	int ret;
+ 
+ 	/* streaming is not active anymore */
+ 	if (isc->stop)
+@@ -1831,7 +1845,9 @@ static void isc_awb_work(struct work_struct *w)
+ 	ctrls->hist_id = hist_id;
+ 	baysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT;
+ 
+-	pm_runtime_get_sync(isc->dev);
++	ret = pm_runtime_resume_and_get(isc->dev);
++	if (ret < 0)
++		return;
+ 
+ 	/*
+ 	 * only update if we have all the required histograms and controls
+diff --git a/drivers/media/platform/atmel/atmel-isi.c b/drivers/media/platform/atmel/atmel-isi.c
+index d74aa73f26be..4ac5b7c19d0c 100644
+--- a/drivers/media/platform/atmel/atmel-isi.c
++++ b/drivers/media/platform/atmel/atmel-isi.c
+@@ -423,7 +423,9 @@ static int start_streaming(struct vb2_queue *vq, unsigned int count)
+ 	struct frame_buffer *buf, *node;
+ 	int ret;
+ 
+-	pm_runtime_get_sync(isi->dev);
++	ret = pm_runtime_resume_and_get(isi->dev);
++	if (ret < 0)
++		return ret;
+ 
+ 	/* Enable stream on the sub device */
+ 	ret = v4l2_subdev_call(isi->entity.subdev, video, s_stream, 1);
+@@ -783,9 +785,10 @@ static int isi_enum_frameintervals(struct file *file, void *fh,
+ 	return 0;
+ }
+ 
+-static void isi_camera_set_bus_param(struct atmel_isi *isi)
++static int isi_camera_set_bus_param(struct atmel_isi *isi)
+ {
+ 	u32 cfg1 = 0;
++	int ret;
+ 
+ 	/* set bus param for ISI */
+ 	if (isi->pdata.hsync_act_low)
+@@ -802,12 +805,16 @@ static void isi_camera_set_bus_param(struct atmel_isi *isi)
+ 	cfg1 |= ISI_CFG1_THMASK_BEATS_16;
+ 
+ 	/* Enable PM and peripheral clock before operate isi registers */
+-	pm_runtime_get_sync(isi->dev);
++	ret = pm_runtime_resume_and_get(isi->dev);
++	if (ret < 0)
++		return ret;
+ 
+ 	isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
+ 	isi_writel(isi, ISI_CFG1, cfg1);
+ 
+ 	pm_runtime_put(isi->dev);
++
++	return 0;
+ }
+ 
+ /* -----------------------------------------------------------------------*/
+@@ -1086,7 +1093,11 @@ static int isi_graph_notify_complete(struct v4l2_async_notifier *notifier)
+ 		dev_err(isi->dev, "No supported mediabus format found\n");
+ 		return ret;
+ 	}
+-	isi_camera_set_bus_param(isi);
++	ret = isi_camera_set_bus_param(isi);
++	if (ret) {
++		dev_err(isi->dev, "Can't wake up device\n");
++		return ret;
++	}
+ 
+ 	ret = isi_set_default_fmt(isi);
+ 	if (ret) {
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/156-media-atmel-atmel-isc-Remove-redundant-assignment-to.patch

@@ -0,0 +1,37 @@
+From b074b4695004b793a9199716295cb76da6c41686 Mon Sep 17 00:00:00 2001
+From: Jiapeng Chong <[email protected]>
+Date: Mon, 17 May 2021 12:07:48 +0200
+Subject: [PATCH 156/247] media: atmel: atmel-isc: Remove redundant assignment
+ to i
+
+Variable i is being assigned a value however the assignment is
+never read, so this redundant assignment can be removed.
+
+Clean up the following clang-analyzer warning:
+
+drivers/media/platform/atmel/atmel-isc-base.c:975:2: warning: Value
+stored to 'i' is never read [clang-analyzer-deadcode.DeadStores].
+
+Reported-by: Abaci Robot <[email protected]>
+Signed-off-by: Jiapeng Chong <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index ce8e1351fa53..a017572c870c 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -972,7 +972,6 @@ static int isc_enum_fmt_vid_cap(struct file *file, void *priv,
+ 
+ 	index -= ARRAY_SIZE(controller_formats);
+ 
+-	i = 0;
+ 	supported_index = 0;
+ 
+ 	for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/157-media-atmel-atmel-isc-specialize-gamma-table-into-pr.patch

@@ -0,0 +1,196 @@
+From c3f54d192dc7344c5216a3628b67c4bbccbf8c3c Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:56:59 +0200
+Subject: [PATCH 157/247] media: atmel: atmel-isc: specialize gamma table into
+ product specific
+
+Separate the gamma table from the isc base file into the specific sama5d2
+product file.
+Add a pointer to the gamma table and entries count inside the platform
+driver specific struct.
+
+[hverkuil: made isc_sama5d2_gamma_table static]
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c | 47 ++-----------------
+ drivers/media/platform/atmel/atmel-isc.h      | 11 +++--
+ .../media/platform/atmel/atmel-sama5d2-isc.c  | 45 ++++++++++++++++++
+ 3 files changed, 56 insertions(+), 47 deletions(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index a017572c870c..46d384332a58 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -176,48 +176,6 @@ struct isc_format formats_list[] = {
+ 
+ };
+ 
+-/* Gamma table with gamma 1/2.2 */
+-const u32 isc_gamma_table[GAMMA_MAX + 1][GAMMA_ENTRIES] = {
+-	/* 0 --> gamma 1/1.8 */
+-	{      0x65,  0x66002F,  0x950025,  0xBB0020,  0xDB001D,  0xF8001A,
+-	  0x1130018, 0x12B0017, 0x1420016, 0x1580014, 0x16D0013, 0x1810012,
+-	  0x1940012, 0x1A60012, 0x1B80011, 0x1C90010, 0x1DA0010, 0x1EA000F,
+-	  0x1FA000F, 0x209000F, 0x218000F, 0x227000E, 0x235000E, 0x243000E,
+-	  0x251000E, 0x25F000D, 0x26C000D, 0x279000D, 0x286000D, 0x293000C,
+-	  0x2A0000C, 0x2AC000C, 0x2B8000C, 0x2C4000C, 0x2D0000B, 0x2DC000B,
+-	  0x2E7000B, 0x2F3000B, 0x2FE000B, 0x309000B, 0x314000B, 0x31F000A,
+-	  0x32A000A, 0x334000B, 0x33F000A, 0x349000A, 0x354000A, 0x35E000A,
+-	  0x368000A, 0x372000A, 0x37C000A, 0x386000A, 0x3900009, 0x399000A,
+-	  0x3A30009, 0x3AD0009, 0x3B60009, 0x3BF000A, 0x3C90009, 0x3D20009,
+-	  0x3DB0009, 0x3E40009, 0x3ED0009, 0x3F60009 },
+-
+-	/* 1 --> gamma 1/2 */
+-	{      0x7F,  0x800034,  0xB50028,  0xDE0021, 0x100001E, 0x11E001B,
+-	  0x1390019, 0x1520017, 0x16A0015, 0x1800014, 0x1940014, 0x1A80013,
+-	  0x1BB0012, 0x1CD0011, 0x1DF0010, 0x1EF0010, 0x200000F, 0x20F000F,
+-	  0x21F000E, 0x22D000F, 0x23C000E, 0x24A000E, 0x258000D, 0x265000D,
+-	  0x273000C, 0x27F000D, 0x28C000C, 0x299000C, 0x2A5000C, 0x2B1000B,
+-	  0x2BC000C, 0x2C8000B, 0x2D3000C, 0x2DF000B, 0x2EA000A, 0x2F5000A,
+-	  0x2FF000B, 0x30A000A, 0x314000B, 0x31F000A, 0x329000A, 0x333000A,
+-	  0x33D0009, 0x3470009, 0x350000A, 0x35A0009, 0x363000A, 0x36D0009,
+-	  0x3760009, 0x37F0009, 0x3880009, 0x3910009, 0x39A0009, 0x3A30009,
+-	  0x3AC0008, 0x3B40009, 0x3BD0008, 0x3C60008, 0x3CE0008, 0x3D60009,
+-	  0x3DF0008, 0x3E70008, 0x3EF0008, 0x3F70008 },
+-
+-	/* 2 --> gamma 1/2.2 */
+-	{      0x99,  0x9B0038,  0xD4002A,  0xFF0023, 0x122001F, 0x141001B,
+-	  0x15D0019, 0x1760017, 0x18E0015, 0x1A30015, 0x1B80013, 0x1CC0012,
+-	  0x1DE0011, 0x1F00010, 0x2010010, 0x2110010, 0x221000F, 0x230000F,
+-	  0x23F000E, 0x24D000E, 0x25B000D, 0x269000C, 0x276000C, 0x283000C,
+-	  0x28F000C, 0x29B000C, 0x2A7000C, 0x2B3000B, 0x2BF000B, 0x2CA000B,
+-	  0x2D5000B, 0x2E0000A, 0x2EB000A, 0x2F5000A, 0x2FF000A, 0x30A000A,
+-	  0x3140009, 0x31E0009, 0x327000A, 0x3310009, 0x33A0009, 0x3440009,
+-	  0x34D0009, 0x3560009, 0x35F0009, 0x3680008, 0x3710008, 0x3790009,
+-	  0x3820008, 0x38A0008, 0x3930008, 0x39B0008, 0x3A30008, 0x3AB0008,
+-	  0x3B30008, 0x3BB0008, 0x3C30008, 0x3CB0007, 0x3D20008, 0x3DA0007,
+-	  0x3E20007, 0x3E90007, 0x3F00008, 0x3F80007 },
+-};
+-
+ #define ISC_IS_FORMAT_RAW(mbus_code) \
+ 	(((mbus_code) & 0xf000) == 0x3000)
+ 
+@@ -691,7 +649,7 @@ static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)
+ 
+ 	regmap_write(regmap, ISC_CFA_CFG, bay_cfg | ISC_CFA_CFG_EITPOL);
+ 
+-	gamma = &isc_gamma_table[ctrls->gamma_index][0];
++	gamma = &isc->gamma_table[ctrls->gamma_index][0];
+ 	regmap_bulk_write(regmap, ISC_GAM_BENTRY, gamma, GAMMA_ENTRIES);
+ 	regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES);
+ 	regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);
+@@ -2085,7 +2043,8 @@ static int isc_ctrl_init(struct isc_device *isc)
+ 
+ 	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0);
+ 	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256);
+-	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, GAMMA_MAX, 1, 2);
++	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1,
++			  isc->gamma_max);
+ 	isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
+ 					  V4L2_CID_AUTO_WHITE_BALANCE,
+ 					  0, 1, 1, 1);
+diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
+index 24b784b893d6..a85b99274e34 100644
+--- a/drivers/media/platform/atmel/atmel-isc.h
++++ b/drivers/media/platform/atmel/atmel-isc.h
+@@ -186,6 +186,10 @@ struct isc_ctrls {
+  *
+  * @current_subdev:	current subdevice: the sensor
+  * @subdev_entities:	list of subdevice entitites
++ *
++ * @gamma_table:	pointer to the table with gamma values, has
++ *			gamma_max sets of GAMMA_ENTRIES entries each
++ * @gamma_max:		maximum number of sets of inside the gamma_table
+  */
+ struct isc_device {
+ 	struct regmap		*regmap;
+@@ -244,16 +248,17 @@ struct isc_device {
+ 		struct v4l2_ctrl	*gr_off_ctrl;
+ 		struct v4l2_ctrl	*gb_off_ctrl;
+ 	};
+-};
+ 
+-#define GAMMA_MAX	2
+ #define GAMMA_ENTRIES	64
++	/* pointer to the defined gamma table */
++	const u32	(*gamma_table)[GAMMA_ENTRIES];
++	u32		gamma_max;
++};
+ 
+ #define ATMEL_ISC_NAME "atmel-isc"
+ 
+ extern struct isc_format formats_list[];
+ extern const struct isc_format controller_formats[];
+-extern const u32 isc_gamma_table[GAMMA_MAX + 1][GAMMA_ENTRIES];
+ extern const struct regmap_config isc_regmap_config;
+ extern const struct v4l2_async_notifier_operations isc_async_ops;
+ 
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index a3304f49e499..1b537cd1e09e 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -54,6 +54,48 @@
+ 
+ #define ISC_CLK_MAX_DIV		255
+ 
++/* Gamma table with gamma 1/2.2 */
++static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {
++	/* 0 --> gamma 1/1.8 */
++	{      0x65,  0x66002F,  0x950025,  0xBB0020,  0xDB001D,  0xF8001A,
++	  0x1130018, 0x12B0017, 0x1420016, 0x1580014, 0x16D0013, 0x1810012,
++	  0x1940012, 0x1A60012, 0x1B80011, 0x1C90010, 0x1DA0010, 0x1EA000F,
++	  0x1FA000F, 0x209000F, 0x218000F, 0x227000E, 0x235000E, 0x243000E,
++	  0x251000E, 0x25F000D, 0x26C000D, 0x279000D, 0x286000D, 0x293000C,
++	  0x2A0000C, 0x2AC000C, 0x2B8000C, 0x2C4000C, 0x2D0000B, 0x2DC000B,
++	  0x2E7000B, 0x2F3000B, 0x2FE000B, 0x309000B, 0x314000B, 0x31F000A,
++	  0x32A000A, 0x334000B, 0x33F000A, 0x349000A, 0x354000A, 0x35E000A,
++	  0x368000A, 0x372000A, 0x37C000A, 0x386000A, 0x3900009, 0x399000A,
++	  0x3A30009, 0x3AD0009, 0x3B60009, 0x3BF000A, 0x3C90009, 0x3D20009,
++	  0x3DB0009, 0x3E40009, 0x3ED0009, 0x3F60009 },
++
++	/* 1 --> gamma 1/2 */
++	{      0x7F,  0x800034,  0xB50028,  0xDE0021, 0x100001E, 0x11E001B,
++	  0x1390019, 0x1520017, 0x16A0015, 0x1800014, 0x1940014, 0x1A80013,
++	  0x1BB0012, 0x1CD0011, 0x1DF0010, 0x1EF0010, 0x200000F, 0x20F000F,
++	  0x21F000E, 0x22D000F, 0x23C000E, 0x24A000E, 0x258000D, 0x265000D,
++	  0x273000C, 0x27F000D, 0x28C000C, 0x299000C, 0x2A5000C, 0x2B1000B,
++	  0x2BC000C, 0x2C8000B, 0x2D3000C, 0x2DF000B, 0x2EA000A, 0x2F5000A,
++	  0x2FF000B, 0x30A000A, 0x314000B, 0x31F000A, 0x329000A, 0x333000A,
++	  0x33D0009, 0x3470009, 0x350000A, 0x35A0009, 0x363000A, 0x36D0009,
++	  0x3760009, 0x37F0009, 0x3880009, 0x3910009, 0x39A0009, 0x3A30009,
++	  0x3AC0008, 0x3B40009, 0x3BD0008, 0x3C60008, 0x3CE0008, 0x3D60009,
++	  0x3DF0008, 0x3E70008, 0x3EF0008, 0x3F70008 },
++
++	/* 2 --> gamma 1/2.2 */
++	{      0x99,  0x9B0038,  0xD4002A,  0xFF0023, 0x122001F, 0x141001B,
++	  0x15D0019, 0x1760017, 0x18E0015, 0x1A30015, 0x1B80013, 0x1CC0012,
++	  0x1DE0011, 0x1F00010, 0x2010010, 0x2110010, 0x221000F, 0x230000F,
++	  0x23F000E, 0x24D000E, 0x25B000D, 0x269000C, 0x276000C, 0x283000C,
++	  0x28F000C, 0x29B000C, 0x2A7000C, 0x2B3000B, 0x2BF000B, 0x2CA000B,
++	  0x2D5000B, 0x2E0000A, 0x2EB000A, 0x2F5000A, 0x2FF000A, 0x30A000A,
++	  0x3140009, 0x31E0009, 0x327000A, 0x3310009, 0x33A0009, 0x3440009,
++	  0x34D0009, 0x3560009, 0x35F0009, 0x3680008, 0x3710008, 0x3790009,
++	  0x3820008, 0x38A0008, 0x3930008, 0x39B0008, 0x3A30008, 0x3AB0008,
++	  0x3B30008, 0x3BB0008, 0x3C30008, 0x3CB0007, 0x3D20008, 0x3DA0007,
++	  0x3E20007, 0x3E90007, 0x3F00008, 0x3F80007 },
++};
++
+ static int isc_parse_dt(struct device *dev, struct isc_device *isc)
+ {
+ 	struct device_node *np = dev->of_node;
+@@ -171,6 +213,9 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 		return ret;
+ 	}
+ 
++	isc->gamma_table = isc_sama5d2_gamma_table;
++	isc->gamma_max = 2;
++
+ 	ret = isc_pipeline_init(isc);
+ 	if (ret)
+ 		return ret;
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/158-media-atmel-atmel-isc-specialize-driver-name-constan.patch

@@ -0,0 +1,79 @@
+From 0576e163d93d08a1ed112bd23f40478ef3fd323d Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:00 +0200
+Subject: [PATCH 158/247] media: atmel: atmel-isc: specialize driver name
+ constant
+
+The driver name constant must defined based on product driver, thus moving
+the constant directly where it's required. This will allow each ISC based
+product to define it's own name.
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c    | 4 ++--
+ drivers/media/platform/atmel/atmel-isc.h         | 2 --
+ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 4 ++--
+ 3 files changed, 4 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index 46d384332a58..d987a8891bd9 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -909,7 +909,7 @@ static int isc_querycap(struct file *file, void *priv,
+ {
+ 	struct isc_device *isc = video_drvdata(file);
+ 
+-	strscpy(cap->driver, ATMEL_ISC_NAME, sizeof(cap->driver));
++	strscpy(cap->driver, "microchip-isc", sizeof(cap->driver));
+ 	strscpy(cap->card, "Atmel Image Sensor Controller", sizeof(cap->card));
+ 	snprintf(cap->bus_info, sizeof(cap->bus_info),
+ 		 "platform:%s", isc->v4l2_dev.name);
+@@ -2261,7 +2261,7 @@ static int isc_async_complete(struct v4l2_async_notifier *notifier)
+ 	}
+ 
+ 	/* Register video device */
+-	strscpy(vdev->name, ATMEL_ISC_NAME, sizeof(vdev->name));
++	strscpy(vdev->name, "microchip-isc", sizeof(vdev->name));
+ 	vdev->release		= video_device_release_empty;
+ 	vdev->fops		= &isc_fops;
+ 	vdev->ioctl_ops		= &isc_ioctl_ops;
+diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
+index a85b99274e34..bb43d3a93052 100644
+--- a/drivers/media/platform/atmel/atmel-isc.h
++++ b/drivers/media/platform/atmel/atmel-isc.h
+@@ -255,8 +255,6 @@ struct isc_device {
+ 	u32		gamma_max;
+ };
+ 
+-#define ATMEL_ISC_NAME "atmel-isc"
+-
+ extern struct isc_format formats_list[];
+ extern const struct isc_format controller_formats[];
+ extern const struct regmap_config isc_regmap_config;
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index 1b537cd1e09e..cba6e6c8810b 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -206,7 +206,7 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 		return irq;
+ 
+ 	ret = devm_request_irq(dev, irq, isc_interrupt, 0,
+-			       ATMEL_ISC_NAME, isc);
++			       "atmel-sama5d2-isc", isc);
+ 	if (ret < 0) {
+ 		dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n",
+ 			irq, ret);
+@@ -378,7 +378,7 @@ static struct platform_driver atmel_isc_driver = {
+ 	.probe	= atmel_isc_probe,
+ 	.remove	= atmel_isc_remove,
+ 	.driver	= {
+-		.name		= ATMEL_ISC_NAME,
++		.name		= "atmel-sama5d2-isc",
+ 		.pm		= &atmel_isc_dev_pm_ops,
+ 		.of_match_table = of_match_ptr(atmel_isc_of_match),
+ 	},
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/159-media-atmel-atmel-isc-add-checks-for-limiting-frame-.patch

@@ -0,0 +1,50 @@
+From de8fa25cdf3726c83ac0d7b3b1e28bcb6334aadd Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:01 +0200
+Subject: [PATCH 159/247] media: atmel: atmel-isc: add checks for limiting
+ frame sizes
+
+When calling the subdev, certain subdev drivers will overwrite the
+frame size and adding sizes which are beyond the ISC's capabilities.
+Thus we need to ensure the frame size is cropped to the maximum caps.
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index d987a8891bd9..02f1d1c6b06e 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -1338,6 +1338,12 @@ static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f,
+ 
+ 	v4l2_fill_pix_format(pixfmt, &format.format);
+ 
++	/* Limit to Atmel ISC hardware capabilities */
++	if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH)
++		pixfmt->width = ISC_MAX_SUPPORT_WIDTH;
++	if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT)
++		pixfmt->height = ISC_MAX_SUPPORT_HEIGHT;
++
+ 	pixfmt->field = V4L2_FIELD_NONE;
+ 	pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp) >> 3;
+ 	pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height;
+@@ -1373,6 +1379,12 @@ static int isc_set_fmt(struct isc_device *isc, struct v4l2_format *f)
+ 	if (ret < 0)
+ 		return ret;
+ 
++	/* Limit to Atmel ISC hardware capabilities */
++	if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH)
++		pixfmt->width = ISC_MAX_SUPPORT_WIDTH;
++	if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT)
++		pixfmt->height = ISC_MAX_SUPPORT_HEIGHT;
++
+ 	isc->fmt = *f;
+ 
+ 	if (isc->try_config.sd_format && isc->config.sd_format &&
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/160-media-atmel-atmel-isc-specialize-max-width-and-max-h.patch

@@ -0,0 +1,140 @@
+From b51819e17260af2ecc152b7dcd61e63bcaa35edf Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:02 +0200
+Subject: [PATCH 160/247] media: atmel: atmel-isc: specialize max width and max
+ height
+
+Move the max width and max height constants to the product specific driver
+and have them in the device struct.
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c | 28 +++++++++----------
+ drivers/media/platform/atmel/atmel-isc.h      |  9 ++++--
+ .../media/platform/atmel/atmel-sama5d2-isc.c  |  7 +++--
+ 3 files changed, 25 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index 02f1d1c6b06e..ed0048e79f3b 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -1216,8 +1216,8 @@ static void isc_try_fse(struct isc_device *isc,
+ 	 * just use the maximum ISC can receive.
+ 	 */
+ 	if (ret) {
+-		pad_cfg->try_crop.width = ISC_MAX_SUPPORT_WIDTH;
+-		pad_cfg->try_crop.height = ISC_MAX_SUPPORT_HEIGHT;
++		pad_cfg->try_crop.width = isc->max_width;
++		pad_cfg->try_crop.height = isc->max_height;
+ 	} else {
+ 		pad_cfg->try_crop.width = fse.max_width;
+ 		pad_cfg->try_crop.height = fse.max_height;
+@@ -1294,10 +1294,10 @@ static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f,
+ 	isc->try_config.sd_format = sd_fmt;
+ 
+ 	/* Limit to Atmel ISC hardware capabilities */
+-	if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH)
+-		pixfmt->width = ISC_MAX_SUPPORT_WIDTH;
+-	if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT)
+-		pixfmt->height = ISC_MAX_SUPPORT_HEIGHT;
++	if (pixfmt->width > isc->max_width)
++		pixfmt->width = isc->max_width;
++	if (pixfmt->height > isc->max_height)
++		pixfmt->height = isc->max_height;
+ 
+ 	/*
+ 	 * The mbus format is the one the subdev outputs.
+@@ -1339,10 +1339,10 @@ static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f,
+ 	v4l2_fill_pix_format(pixfmt, &format.format);
+ 
+ 	/* Limit to Atmel ISC hardware capabilities */
+-	if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH)
+-		pixfmt->width = ISC_MAX_SUPPORT_WIDTH;
+-	if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT)
+-		pixfmt->height = ISC_MAX_SUPPORT_HEIGHT;
++	if (pixfmt->width > isc->max_width)
++		pixfmt->width = isc->max_width;
++	if (pixfmt->height > isc->max_height)
++		pixfmt->height = isc->max_height;
+ 
+ 	pixfmt->field = V4L2_FIELD_NONE;
+ 	pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp) >> 3;
+@@ -1380,10 +1380,10 @@ static int isc_set_fmt(struct isc_device *isc, struct v4l2_format *f)
+ 		return ret;
+ 
+ 	/* Limit to Atmel ISC hardware capabilities */
+-	if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH)
+-		pixfmt->width = ISC_MAX_SUPPORT_WIDTH;
+-	if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT)
+-		pixfmt->height = ISC_MAX_SUPPORT_HEIGHT;
++	if (f->fmt.pix.width > isc->max_width)
++		f->fmt.pix.width = isc->max_width;
++	if (f->fmt.pix.height > isc->max_height)
++		f->fmt.pix.height = isc->max_height;
+ 
+ 	isc->fmt = *f;
+ 
+diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
+index bb43d3a93052..f208fb691ac9 100644
+--- a/drivers/media/platform/atmel/atmel-isc.h
++++ b/drivers/media/platform/atmel/atmel-isc.h
+@@ -10,9 +10,6 @@
+  */
+ #ifndef _ATMEL_ISC_H_
+ 
+-#define ISC_MAX_SUPPORT_WIDTH   2592
+-#define ISC_MAX_SUPPORT_HEIGHT  1944
+-
+ #define ISC_CLK_MAX_DIV		255
+ 
+ enum isc_clk_id {
+@@ -190,6 +187,9 @@ struct isc_ctrls {
+  * @gamma_table:	pointer to the table with gamma values, has
+  *			gamma_max sets of GAMMA_ENTRIES entries each
+  * @gamma_max:		maximum number of sets of inside the gamma_table
++ *
++ * @max_width:		maximum frame width, dependent on the internal RAM
++ * @max_height:		maximum frame height, dependent on the internal RAM
+  */
+ struct isc_device {
+ 	struct regmap		*regmap;
+@@ -253,6 +253,9 @@ struct isc_device {
+ 	/* pointer to the defined gamma table */
+ 	const u32	(*gamma_table)[GAMMA_ENTRIES];
+ 	u32		gamma_max;
++
++	u32		max_width;
++	u32		max_height;
+ };
+ 
+ extern struct isc_format formats_list[];
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index cba6e6c8810b..39fc8d4f9bdc 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -49,8 +49,8 @@
+ #include "atmel-isc-regs.h"
+ #include "atmel-isc.h"
+ 
+-#define ISC_MAX_SUPPORT_WIDTH   2592
+-#define ISC_MAX_SUPPORT_HEIGHT  1944
++#define ISC_SAMA5D2_MAX_SUPPORT_WIDTH   2592
++#define ISC_SAMA5D2_MAX_SUPPORT_HEIGHT  1944
+ 
+ #define ISC_CLK_MAX_DIV		255
+ 
+@@ -216,6 +216,9 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 	isc->gamma_table = isc_sama5d2_gamma_table;
+ 	isc->gamma_max = 2;
+ 
++	isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH;
++	isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT;
++
+ 	ret = isc_pipeline_init(isc);
+ 	if (ret)
+ 		return ret;
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/161-media-atmel-atmel-isc-specialize-dma-cfg.patch

@@ -0,0 +1,69 @@
+From c42305f52560a1be6fc25a2f23579c7b323de654 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:03 +0200
+Subject: [PATCH 161/247] media: atmel: atmel-isc: specialize dma cfg
+
+The dma configuration (DCFG) is specific to the product.
+Move this configuration in the product specific driver, and add the
+field inside the driver struct.
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c    | 3 +--
+ drivers/media/platform/atmel/atmel-isc.h         | 2 ++
+ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 3 +++
+ 3 files changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index ed0048e79f3b..07ba439eb7e9 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -724,8 +724,7 @@ static int isc_configure(struct isc_device *isc)
+ 	rlp_mode = isc->config.rlp_cfg_mode;
+ 	pipeline = isc->config.bits_pipeline;
+ 
+-	dcfg = isc->config.dcfg_imode |
+-		       ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
++	dcfg = isc->config.dcfg_imode | isc->dcfg;
+ 
+ 	pfe_cfg0  |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE;
+ 	mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |
+diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
+index f208fb691ac9..88ec4268de11 100644
+--- a/drivers/media/platform/atmel/atmel-isc.h
++++ b/drivers/media/platform/atmel/atmel-isc.h
+@@ -149,6 +149,7 @@ struct isc_ctrls {
+  * @hclock:		Hclock clock input (refer datasheet)
+  * @ispck:		iscpck clock (refer datasheet)
+  * @isc_clks:		ISC clocks
++ * @dcfg:		DMA master configuration, architecture dependent
+  *
+  * @dev:		Registered device driver
+  * @v4l2_dev:		v4l2 registered device
+@@ -196,6 +197,7 @@ struct isc_device {
+ 	struct clk		*hclock;
+ 	struct clk		*ispck;
+ 	struct isc_clk		isc_clks[2];
++	u32			dcfg;
+ 
+ 	struct device		*dev;
+ 	struct v4l2_device	v4l2_dev;
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index 39fc8d4f9bdc..12edeb07b618 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -219,6 +219,9 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 	isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH;
+ 	isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT;
+ 
++	/* sama5d2-isc - 8 bits per beat */
++	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
++
+ 	ret = isc_pipeline_init(isc);
+ 	if (ret)
+ 		return ret;
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/162-media-atmel-atmel-isc-extract-CSC-submodule-config-i.patch

@@ -0,0 +1,103 @@
+From 6ccda3cf6a102ac4f6e21386d0dd0fedfb066525 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:04 +0200
+Subject: [PATCH 162/247] media: atmel: atmel-isc: extract CSC submodule config
+ into separate function
+
+The CSC submodule is a part of the atmel-isc pipeline, and stands for
+Color Space Conversion. It is used to apply a matrix transformation to
+RGB pixels to convert them to the YUV components.
+The CSC submodule should be initialized in the product specific driver
+as it's product specific. Other products can implement it differently.
+
+[hverkuil: made isc_sama5d2_config_csc static]
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c    |  8 +-------
+ drivers/media/platform/atmel/atmel-isc.h         |  7 +++++++
+ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 15 +++++++++++++++
+ 3 files changed, 23 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index 07ba439eb7e9..6c709f6a408c 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -654,13 +654,7 @@ static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)
+ 	regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES);
+ 	regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);
+ 
+-	/* Convert RGB to YUV */
+-	regmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16));
+-	regmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16));
+-	regmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16));
+-	regmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16));
+-	regmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16));
+-	regmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16));
++	isc->config_csc(isc);
+ 
+ 	regmap_write(regmap, ISC_CBC_BRIGHT, ctrls->brightness);
+ 	regmap_write(regmap, ISC_CBC_CONTRAST, ctrls->contrast);
+diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
+index 88ec4268de11..ebdb9ed791a7 100644
+--- a/drivers/media/platform/atmel/atmel-isc.h
++++ b/drivers/media/platform/atmel/atmel-isc.h
+@@ -191,6 +191,9 @@ struct isc_ctrls {
+  *
+  * @max_width:		maximum frame width, dependent on the internal RAM
+  * @max_height:		maximum frame height, dependent on the internal RAM
++ *
++ * @config_csc:		pointer to a function that initializes product
++ *			specific CSC module
+  */
+ struct isc_device {
+ 	struct regmap		*regmap;
+@@ -258,6 +261,10 @@ struct isc_device {
+ 
+ 	u32		max_width;
+ 	u32		max_height;
++
++	struct {
++		void (*config_csc)(struct isc_device *isc);
++	};
+ };
+ 
+ extern struct isc_format formats_list[];
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index 12edeb07b618..19d0f750636c 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -54,6 +54,19 @@
+ 
+ #define ISC_CLK_MAX_DIV		255
+ 
++static void isc_sama5d2_config_csc(struct isc_device *isc)
++{
++	struct regmap *regmap = isc->regmap;
++
++	/* Convert RGB to YUV */
++	regmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16));
++	regmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16));
++	regmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16));
++	regmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16));
++	regmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16));
++	regmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16));
++}
++
+ /* Gamma table with gamma 1/2.2 */
+ static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {
+ 	/* 0 --> gamma 1/1.8 */
+@@ -219,6 +232,8 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 	isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH;
+ 	isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT;
+ 
++	isc->config_csc = isc_sama5d2_config_csc;
++
+ 	/* sama5d2-isc - 8 bits per beat */
+ 	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
+ 
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/163-media-atmel-atmel-isc-base-add-id-to-clock-debug-mes.patch

@@ -0,0 +1,33 @@
+From 19dd7c72c6c457c147133a7dad8ab28d35538f99 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:05 +0200
+Subject: [PATCH 163/247] media: atmel: atmel-isc-base: add id to clock debug
+ message
+
+Add the clock id to the debug message regarding clock setup
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index 6c709f6a408c..f9190fccb482 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -281,8 +281,8 @@ static int isc_clk_enable(struct clk_hw *hw)
+ 	unsigned long flags;
+ 	unsigned int status;
+ 
+-	dev_dbg(isc_clk->dev, "ISC CLK: %s, div = %d, parent id = %d\n",
+-		__func__, isc_clk->div, isc_clk->parent_id);
++	dev_dbg(isc_clk->dev, "ISC CLK: %s, id = %d, div = %d, parent id = %d\n",
++		__func__, id, isc_clk->div, isc_clk->parent_id);
+ 
+ 	spin_lock_irqsave(&isc_clk->lock, flags);
+ 	regmap_update_bits(regmap, ISC_CLKCFG,
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/164-media-atmel-atmel-isc-create-register-offsets-struct.patch

@@ -0,0 +1,126 @@
+From 7a1b082cd81a2496e2687cee7ea1ef04a3020f48 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:06 +0200
+Subject: [PATCH 164/247] media: atmel: atmel-isc: create register offsets
+ struct
+
+Create a struct that holds register offsets that are product specific.
+Add initially the CSC register.
+This allows each product that contains a variant of the ISC to add their
+own register offset.
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c |  2 +-
+ drivers/media/platform/atmel/atmel-isc-regs.h |  3 +++
+ drivers/media/platform/atmel/atmel-isc.h      | 12 +++++++++++
+ .../media/platform/atmel/atmel-sama5d2-isc.c  | 20 +++++++++++++------
+ 4 files changed, 30 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index f9190fccb482..18136e58a754 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -2326,7 +2326,7 @@ int isc_pipeline_init(struct isc_device *isc)
+ 		REG_FIELD(ISC_GAM_CTRL, 1, 1),
+ 		REG_FIELD(ISC_GAM_CTRL, 2, 2),
+ 		REG_FIELD(ISC_GAM_CTRL, 3, 3),
+-		REG_FIELD(ISC_CSC_CTRL, 0, 0),
++		REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),
+ 		REG_FIELD(ISC_CBC_CTRL, 0, 0),
+ 		REG_FIELD(ISC_SUB422_CTRL, 0, 0),
+ 		REG_FIELD(ISC_SUB420_CTRL, 0, 0),
+diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h
+index f1e160ed4351..5a65600c5f88 100644
+--- a/drivers/media/platform/atmel/atmel-isc-regs.h
++++ b/drivers/media/platform/atmel/atmel-isc-regs.h
+@@ -153,6 +153,9 @@
+ /* ISC_Gamma Correction Green Entry Register */
+ #define ISC_GAM_RENTRY	0x00000298
+ 
++/* Offset for CSC register specific to sama5d2 product */
++#define ISC_SAMA5D2_CSC_OFFSET	0
++
+ /* Color Space Conversion Control Register */
+ #define ISC_CSC_CTRL    0x00000398
+ 
+diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
+index ebdb9ed791a7..db6b4d469dff 100644
+--- a/drivers/media/platform/atmel/atmel-isc.h
++++ b/drivers/media/platform/atmel/atmel-isc.h
+@@ -143,6 +143,14 @@ struct isc_ctrls {
+ 
+ #define ISC_PIPE_LINE_NODE_NUM	11
+ 
++/*
++ * struct isc_reg_offsets - ISC device register offsets
++ * @csc:		Offset for the CSC register
++ */
++struct isc_reg_offsets {
++	u32 csc;
++};
++
+ /*
+  * struct isc_device - ISC device driver data/config struct
+  * @regmap:		Register map
+@@ -194,6 +202,8 @@ struct isc_ctrls {
+  *
+  * @config_csc:		pointer to a function that initializes product
+  *			specific CSC module
++ *
++ * @offsets:		struct holding the product specific register offsets
+  */
+ struct isc_device {
+ 	struct regmap		*regmap;
+@@ -265,6 +275,8 @@ struct isc_device {
+ 	struct {
+ 		void (*config_csc)(struct isc_device *isc);
+ 	};
++
++	struct isc_reg_offsets		offsets;
+ };
+ 
+ extern struct isc_format formats_list[];
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index 19d0f750636c..2ad6227aa2f5 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -59,12 +59,18 @@ static void isc_sama5d2_config_csc(struct isc_device *isc)
+ 	struct regmap *regmap = isc->regmap;
+ 
+ 	/* Convert RGB to YUV */
+-	regmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16));
+-	regmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16));
+-	regmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16));
+-	regmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16));
+-	regmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16));
+-	regmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16));
++	regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc,
++		     0x42 | (0x81 << 16));
++	regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc,
++		     0x19 | (0x10 << 16));
++	regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc,
++		     0xFDA | (0xFB6 << 16));
++	regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc,
++		     0x70 | (0x80 << 16));
++	regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc,
++		     0x70 | (0xFA2 << 16));
++	regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc,
++		     0xFEE | (0x80 << 16));
+ }
+ 
+ /* Gamma table with gamma 1/2.2 */
+@@ -234,6 +240,8 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 
+ 	isc->config_csc = isc_sama5d2_config_csc;
+ 
++	isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;
++
+ 	/* sama5d2-isc - 8 bits per beat */
+ 	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
+ 
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/165-media-atmel-atmel-isc-extract-CBC-submodule-config-i.patch

@@ -0,0 +1,89 @@
+From aa31e58d80d233385fa3b972e6b85f293e2a9093 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:07 +0200
+Subject: [PATCH 165/247] media: atmel: atmel-isc: extract CBC submodule config
+ into separate function
+
+The CBC submodule is a part of the atmel-isc pipeline, and stands for
+Contrast Brightness Control. It is used to apply gains and offsets to the
+luma (Y) and chroma (U, V) components of the YUV elements.
+The CBC submodule should be initialized in the product specific driver
+as it's product specific. Other products can implement it differently
+
+[hverkuil: made isc_sama5d2_config_cbc static]
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c    | 4 +---
+ drivers/media/platform/atmel/atmel-isc.h         | 3 +++
+ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 9 +++++++++
+ 3 files changed, 13 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index 18136e58a754..865410e10e70 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -655,9 +655,7 @@ static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)
+ 	regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);
+ 
+ 	isc->config_csc(isc);
+-
+-	regmap_write(regmap, ISC_CBC_BRIGHT, ctrls->brightness);
+-	regmap_write(regmap, ISC_CBC_CONTRAST, ctrls->contrast);
++	isc->config_cbc(isc);
+ }
+ 
+ static int isc_update_profile(struct isc_device *isc)
+diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
+index db6b4d469dff..65c3059afb8e 100644
+--- a/drivers/media/platform/atmel/atmel-isc.h
++++ b/drivers/media/platform/atmel/atmel-isc.h
+@@ -202,6 +202,8 @@ struct isc_reg_offsets {
+  *
+  * @config_csc:		pointer to a function that initializes product
+  *			specific CSC module
++ * @config_cbc:		pointer to a function that initializes product
++ *			specific CBC module
+  *
+  * @offsets:		struct holding the product specific register offsets
+  */
+@@ -274,6 +276,7 @@ struct isc_device {
+ 
+ 	struct {
+ 		void (*config_csc)(struct isc_device *isc);
++		void (*config_cbc)(struct isc_device *isc);
+ 	};
+ 
+ 	struct isc_reg_offsets		offsets;
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index 2ad6227aa2f5..770d62b483d0 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -73,6 +73,14 @@ static void isc_sama5d2_config_csc(struct isc_device *isc)
+ 		     0xFEE | (0x80 << 16));
+ }
+ 
++static void isc_sama5d2_config_cbc(struct isc_device *isc)
++{
++	struct regmap *regmap = isc->regmap;
++
++	regmap_write(regmap, ISC_CBC_BRIGHT, isc->ctrls.brightness);
++	regmap_write(regmap, ISC_CBC_CONTRAST, isc->ctrls.contrast);
++}
++
+ /* Gamma table with gamma 1/2.2 */
+ static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {
+ 	/* 0 --> gamma 1/1.8 */
+@@ -239,6 +247,7 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 	isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT;
+ 
+ 	isc->config_csc = isc_sama5d2_config_csc;
++	isc->config_cbc = isc_sama5d2_config_cbc;
+ 
+ 	isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;
+ 
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/166-media-atmel-atmel-isc-add-CBC-to-the-reg-offsets-str.patch

@@ -0,0 +1,93 @@
+From 52e4b779ae1af3e322d0c673375dcd51315739d4 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:08 +0200
+Subject: [PATCH 166/247] media: atmel: atmel-isc: add CBC to the reg offsets
+ struct
+
+The CBC submodule is a part of the atmel-isc pipeline, and stands for
+Contrast Brightness Control. It is used to apply gains and offsets to the
+luma (Y) and chroma (U, V) components of the YUV elements.
+Add cbc to the reg offsets struct. This will allow different products
+to have a different reg offset for this particular module.
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c    | 2 +-
+ drivers/media/platform/atmel/atmel-isc-regs.h    | 3 +++
+ drivers/media/platform/atmel/atmel-isc.h         | 2 ++
+ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 7 +++++--
+ 4 files changed, 11 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index 865410e10e70..b7728914fda8 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -2325,7 +2325,7 @@ int isc_pipeline_init(struct isc_device *isc)
+ 		REG_FIELD(ISC_GAM_CTRL, 2, 2),
+ 		REG_FIELD(ISC_GAM_CTRL, 3, 3),
+ 		REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),
+-		REG_FIELD(ISC_CBC_CTRL, 0, 0),
++		REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0),
+ 		REG_FIELD(ISC_SUB422_CTRL, 0, 0),
+ 		REG_FIELD(ISC_SUB420_CTRL, 0, 0),
+ 	};
+diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h
+index 5a65600c5f88..a5e2fe01ba9f 100644
+--- a/drivers/media/platform/atmel/atmel-isc-regs.h
++++ b/drivers/media/platform/atmel/atmel-isc-regs.h
+@@ -177,6 +177,9 @@
+ /* Color Space Conversion CRB OCR Register */
+ #define ISC_CSC_CRB_OCR	0x000003b0
+ 
++/* Offset for CBC register specific to sama5d2 product */
++#define ISC_SAMA5D2_CBC_OFFSET	0
++
+ /* Contrast And Brightness Control Register */
+ #define ISC_CBC_CTRL    0x000003b4
+ 
+diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
+index 65c3059afb8e..d8b4b1959b94 100644
+--- a/drivers/media/platform/atmel/atmel-isc.h
++++ b/drivers/media/platform/atmel/atmel-isc.h
+@@ -146,9 +146,11 @@ struct isc_ctrls {
+ /*
+  * struct isc_reg_offsets - ISC device register offsets
+  * @csc:		Offset for the CSC register
++ * @cbc:		Offset for the CBC register
+  */
+ struct isc_reg_offsets {
+ 	u32 csc;
++	u32 cbc;
+ };
+ 
+ /*
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index 770d62b483d0..bb9362093efe 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -77,8 +77,10 @@ static void isc_sama5d2_config_cbc(struct isc_device *isc)
+ {
+ 	struct regmap *regmap = isc->regmap;
+ 
+-	regmap_write(regmap, ISC_CBC_BRIGHT, isc->ctrls.brightness);
+-	regmap_write(regmap, ISC_CBC_CONTRAST, isc->ctrls.contrast);
++	regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc,
++		     isc->ctrls.brightness);
++	regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc,
++		     isc->ctrls.contrast);
+ }
+ 
+ /* Gamma table with gamma 1/2.2 */
+@@ -250,6 +252,7 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 	isc->config_cbc = isc_sama5d2_config_cbc;
+ 
+ 	isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;
++	isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET;
+ 
+ 	/* sama5d2-isc - 8 bits per beat */
+ 	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/167-media-atmel-atmel-isc-add-SUB422-and-SUB420-to-regis.patch

@@ -0,0 +1,91 @@
+From aebb741058a63c3493f4139d11d6f290d5691e9b Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:09 +0200
+Subject: [PATCH 167/247] media: atmel: atmel-isc: add SUB422 and SUB420 to
+ register offsets
+
+The SUB submodules are a part of the atmel-isc pipeline, and stand for
+Subsampling. They are used to subsample the original YUV 4:4:4 pixel ratio
+aspect to either 4:2:2 or 4:2:0.
+Add sub420 and sub422 to the reg offsets struct.
+This will allow different products to have a different reg offset for these
+particular modules.
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c    | 4 ++--
+ drivers/media/platform/atmel/atmel-isc-regs.h    | 4 ++++
+ drivers/media/platform/atmel/atmel-isc.h         | 4 ++++
+ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 2 ++
+ 4 files changed, 12 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index b7728914fda8..b398cdfdc2c9 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -2326,8 +2326,8 @@ int isc_pipeline_init(struct isc_device *isc)
+ 		REG_FIELD(ISC_GAM_CTRL, 3, 3),
+ 		REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),
+ 		REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0),
+-		REG_FIELD(ISC_SUB422_CTRL, 0, 0),
+-		REG_FIELD(ISC_SUB420_CTRL, 0, 0),
++		REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0),
++		REG_FIELD(ISC_SUB420_CTRL + isc->offsets.sub420, 0, 0),
+ 	};
+ 
+ 	for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
+diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h
+index a5e2fe01ba9f..04839def6ef6 100644
+--- a/drivers/media/platform/atmel/atmel-isc-regs.h
++++ b/drivers/media/platform/atmel/atmel-isc-regs.h
+@@ -194,9 +194,13 @@
+ #define ISC_CBC_CONTRAST	0x000003c0
+ #define ISC_CBC_CONTRAST_MASK	GENMASK(11, 0)
+ 
++/* Offset for SUB422 register specific to sama5d2 product */
++#define ISC_SAMA5D2_SUB422_OFFSET	0
+ /* Subsampling 4:4:4 to 4:2:2 Control Register */
+ #define ISC_SUB422_CTRL 0x000003c4
+ 
++/* Offset for SUB420 register specific to sama5d2 product */
++#define ISC_SAMA5D2_SUB420_OFFSET	0
+ /* Subsampling 4:2:2 to 4:2:0 Control Register */
+ #define ISC_SUB420_CTRL 0x000003cc
+ 
+diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
+index d8b4b1959b94..9eb85540d89d 100644
+--- a/drivers/media/platform/atmel/atmel-isc.h
++++ b/drivers/media/platform/atmel/atmel-isc.h
+@@ -147,10 +147,14 @@ struct isc_ctrls {
+  * struct isc_reg_offsets - ISC device register offsets
+  * @csc:		Offset for the CSC register
+  * @cbc:		Offset for the CBC register
++ * @sub422:		Offset for the SUB422 register
++ * @sub420:		Offset for the SUB420 register
+  */
+ struct isc_reg_offsets {
+ 	u32 csc;
+ 	u32 cbc;
++	u32 sub422;
++	u32 sub420;
+ };
+ 
+ /*
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index bb9362093efe..57ea1ae50c44 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -253,6 +253,8 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 
+ 	isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;
+ 	isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET;
++	isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET;
++	isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET;
+ 
+ 	/* sama5d2-isc - 8 bits per beat */
+ 	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/168-media-atmel-atmel-isc-add-RLP-to-register-offsets.patch

@@ -0,0 +1,85 @@
+From b432a8b0fc88de5b49236482053d8d372c68ee55 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:10 +0200
+Subject: [PATCH 168/247] media: atmel: atmel-isc: add RLP to register offsets
+
+The RLP submodule is a part of the atmel-isc pipeline, and stands for
+Rounding,Limiting and Packaging. It used to extract specific data from the
+ISC pipeline. For example if we want to output greyscale 8 bit, we would
+use limiting to 8 bits, and packaging to Luma component only.
+Add rlp to the reg offsets struct.
+This will allow different products to have a different reg offset for this
+particular module.
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c    | 4 ++--
+ drivers/media/platform/atmel/atmel-isc-regs.h    | 2 ++
+ drivers/media/platform/atmel/atmel-isc.h         | 2 ++
+ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 1 +
+ 4 files changed, 7 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index b398cdfdc2c9..25c90b821067 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -726,8 +726,8 @@ static int isc_configure(struct isc_device *isc)
+ 
+ 	regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);
+ 
+-	regmap_update_bits(regmap, ISC_RLP_CFG, ISC_RLP_CFG_MODE_MASK,
+-			   rlp_mode);
++	regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,
++			   ISC_RLP_CFG_MODE_MASK, rlp_mode);
+ 
+ 	regmap_write(regmap, ISC_DCFG, dcfg);
+ 
+diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h
+index 04839def6ef6..2205484e04fc 100644
+--- a/drivers/media/platform/atmel/atmel-isc-regs.h
++++ b/drivers/media/platform/atmel/atmel-isc-regs.h
+@@ -204,6 +204,8 @@
+ /* Subsampling 4:2:2 to 4:2:0 Control Register */
+ #define ISC_SUB420_CTRL 0x000003cc
+ 
++/* Offset for RLP register specific to sama5d2 product */
++#define ISC_SAMA5D2_RLP_OFFSET	0
+ /* Rounding, Limiting and Packing Configuration Register */
+ #define ISC_RLP_CFG     0x000003d0
+ 
+diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
+index 9eb85540d89d..4a5293c66f49 100644
+--- a/drivers/media/platform/atmel/atmel-isc.h
++++ b/drivers/media/platform/atmel/atmel-isc.h
+@@ -149,12 +149,14 @@ struct isc_ctrls {
+  * @cbc:		Offset for the CBC register
+  * @sub422:		Offset for the SUB422 register
+  * @sub420:		Offset for the SUB420 register
++ * @rlp:		Offset for the RLP register
+  */
+ struct isc_reg_offsets {
+ 	u32 csc;
+ 	u32 cbc;
+ 	u32 sub422;
+ 	u32 sub420;
++	u32 rlp;
+ };
+ 
+ /*
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index 57ea1ae50c44..b01b5b9f229b 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -255,6 +255,7 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 	isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET;
+ 	isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET;
+ 	isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET;
++	isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET;
+ 
+ 	/* sama5d2-isc - 8 bits per beat */
+ 	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/169-media-atmel-atmel-isc-add-HIS-to-register-offsets.patch

@@ -0,0 +1,110 @@
+From 8c19aa14b8303a0e7c4bae42f3f00f9a2a65b0db Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:11 +0200
+Subject: [PATCH 169/247] media: atmel: atmel-isc: add HIS to register offsets
+
+The HIS submodule is a part of the atmel-isc pipeline, and stands for
+Histogram. This module performs a color histogram that can be read and used
+by the main processor.
+Add his to the reg offsets struct.
+This will allow different products to have a different reg offset for this
+particular module.
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c    | 11 +++++++----
+ drivers/media/platform/atmel/atmel-isc-regs.h    |  2 ++
+ drivers/media/platform/atmel/atmel-isc.h         |  2 ++
+ drivers/media/platform/atmel/atmel-sama5d2-isc.c |  1 +
+ 4 files changed, 12 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index 25c90b821067..5c95aa45cf6c 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -686,12 +686,13 @@ static void isc_set_histogram(struct isc_device *isc, bool enable)
+ 	struct isc_ctrls *ctrls = &isc->ctrls;
+ 
+ 	if (enable) {
+-		regmap_write(regmap, ISC_HIS_CFG,
++		regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,
+ 			     ISC_HIS_CFG_MODE_GR |
+ 			     (isc->config.sd_format->cfa_baycfg
+ 					<< ISC_HIS_CFG_BAYSEL_SHIFT) |
+ 					ISC_HIS_CFG_RAR);
+-		regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_EN);
++		regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,
++			     ISC_HIS_CTRL_EN);
+ 		regmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE);
+ 		ctrls->hist_id = ISC_HIS_CFG_MODE_GR;
+ 		isc_update_profile(isc);
+@@ -700,7 +701,8 @@ static void isc_set_histogram(struct isc_device *isc, bool enable)
+ 		ctrls->hist_stat = HIST_ENABLED;
+ 	} else {
+ 		regmap_write(regmap, ISC_INTDIS, ISC_INT_HISDONE);
+-		regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_DIS);
++		regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,
++			     ISC_HIS_CTRL_DIS);
+ 
+ 		ctrls->hist_stat = HIST_DISABLED;
+ 	}
+@@ -1836,7 +1838,8 @@ static void isc_awb_work(struct work_struct *w)
+ 			ctrls->awb = ISC_WB_NONE;
+ 		}
+ 	}
+-	regmap_write(regmap, ISC_HIS_CFG, hist_id | baysel | ISC_HIS_CFG_RAR);
++	regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,
++		     hist_id | baysel | ISC_HIS_CFG_RAR);
+ 	isc_update_profile(isc);
+ 	/* if awb has been disabled, we don't need to start another histogram */
+ 	if (ctrls->awb)
+diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h
+index 2205484e04fc..0ab280ab59ec 100644
+--- a/drivers/media/platform/atmel/atmel-isc-regs.h
++++ b/drivers/media/platform/atmel/atmel-isc-regs.h
+@@ -224,6 +224,8 @@
+ #define ISC_RLP_CFG_MODE_YYCC_LIMITED   0xc
+ #define ISC_RLP_CFG_MODE_MASK           GENMASK(3, 0)
+ 
++/* Offset for HIS register specific to sama5d2 product */
++#define ISC_SAMA5D2_HIS_OFFSET	0
+ /* Histogram Control Register */
+ #define ISC_HIS_CTRL	0x000003d4
+ 
+diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
+index 4a5293c66f49..97ec4c58297e 100644
+--- a/drivers/media/platform/atmel/atmel-isc.h
++++ b/drivers/media/platform/atmel/atmel-isc.h
+@@ -150,6 +150,7 @@ struct isc_ctrls {
+  * @sub422:		Offset for the SUB422 register
+  * @sub420:		Offset for the SUB420 register
+  * @rlp:		Offset for the RLP register
++ * @his:		Offset for the HIS related registers
+  */
+ struct isc_reg_offsets {
+ 	u32 csc;
+@@ -157,6 +158,7 @@ struct isc_reg_offsets {
+ 	u32 sub422;
+ 	u32 sub420;
+ 	u32 rlp;
++	u32 his;
+ };
+ 
+ /*
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index b01b5b9f229b..db93cb76c08b 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -256,6 +256,7 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 	isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET;
+ 	isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET;
+ 	isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET;
++	isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET;
+ 
+ 	/* sama5d2-isc - 8 bits per beat */
+ 	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/170-media-atmel-atmel-isc-add-DMA-to-register-offsets.patch

@@ -0,0 +1,121 @@
+From 7173e54070a9b530c8c16e0a507be71385133abd Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:12 +0200
+Subject: [PATCH 170/247] media: atmel: atmel-isc: add DMA to register offsets
+
+The DMA submodule is a part of the atmel-isc pipeline, and stands for
+Direct Memory Access. It acts like a master on the AXI bus of the SoC, and
+can directly write the RAM area with the pixel data from the ISC internal
+sram.
+Add dma to the reg offsets struct.
+This will allow different products to have a different reg offset for this
+particular module.
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c | 19 ++++++++++++-------
+ drivers/media/platform/atmel/atmel-isc-regs.h |  3 +++
+ drivers/media/platform/atmel/atmel-isc.h      |  2 ++
+ .../media/platform/atmel/atmel-sama5d2-isc.c  |  1 +
+ 4 files changed, 18 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index 5c95aa45cf6c..e010429fc44d 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -601,16 +601,20 @@ static void isc_start_dma(struct isc_device *isc)
+ 			   ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN);
+ 
+ 	addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0);
+-	regmap_write(regmap, ISC_DAD0, addr0);
++	regmap_write(regmap, ISC_DAD0 + isc->offsets.dma, addr0);
+ 
+ 	switch (isc->config.fourcc) {
+ 	case V4L2_PIX_FMT_YUV420:
+-		regmap_write(regmap, ISC_DAD1, addr0 + (sizeimage * 2) / 3);
+-		regmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 5) / 6);
++		regmap_write(regmap, ISC_DAD1 + isc->offsets.dma,
++			     addr0 + (sizeimage * 2) / 3);
++		regmap_write(regmap, ISC_DAD2 + isc->offsets.dma,
++			     addr0 + (sizeimage * 5) / 6);
+ 		break;
+ 	case V4L2_PIX_FMT_YUV422P:
+-		regmap_write(regmap, ISC_DAD1, addr0 + sizeimage / 2);
+-		regmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 3) / 4);
++		regmap_write(regmap, ISC_DAD1 + isc->offsets.dma,
++			     addr0 + sizeimage / 2);
++		regmap_write(regmap, ISC_DAD2 + isc->offsets.dma,
++			     addr0 + (sizeimage * 3) / 4);
+ 		break;
+ 	default:
+ 		break;
+@@ -618,7 +622,8 @@ static void isc_start_dma(struct isc_device *isc)
+ 
+ 	dctrl_dview = isc->config.dctrl_dview;
+ 
+-	regmap_write(regmap, ISC_DCTRL, dctrl_dview | ISC_DCTRL_IE_IS);
++	regmap_write(regmap, ISC_DCTRL + isc->offsets.dma,
++		     dctrl_dview | ISC_DCTRL_IE_IS);
+ 	spin_lock(&isc->awb_lock);
+ 	regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE);
+ 	spin_unlock(&isc->awb_lock);
+@@ -731,7 +736,7 @@ static int isc_configure(struct isc_device *isc)
+ 	regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,
+ 			   ISC_RLP_CFG_MODE_MASK, rlp_mode);
+ 
+-	regmap_write(regmap, ISC_DCFG, dcfg);
++	regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg);
+ 
+ 	/* Set the pipeline */
+ 	isc_set_pipeline(isc, pipeline);
+diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h
+index 0ab280ab59ec..4940998c82a2 100644
+--- a/drivers/media/platform/atmel/atmel-isc-regs.h
++++ b/drivers/media/platform/atmel/atmel-isc-regs.h
+@@ -247,6 +247,9 @@
+ 
+ #define ISC_HIS_CFG_RAR			BIT(8)
+ 
++/* Offset for DMA register specific to sama5d2 product */
++#define ISC_SAMA5D2_DMA_OFFSET	0
++
+ /* DMA Configuration Register */
+ #define ISC_DCFG        0x000003e0
+ #define ISC_DCFG_IMODE_PACKED8          0x0
+diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
+index 97ec4c58297e..bea545327d3d 100644
+--- a/drivers/media/platform/atmel/atmel-isc.h
++++ b/drivers/media/platform/atmel/atmel-isc.h
+@@ -151,6 +151,7 @@ struct isc_ctrls {
+  * @sub420:		Offset for the SUB420 register
+  * @rlp:		Offset for the RLP register
+  * @his:		Offset for the HIS related registers
++ * @dma:		Offset for the DMA related registers
+  */
+ struct isc_reg_offsets {
+ 	u32 csc;
+@@ -159,6 +160,7 @@ struct isc_reg_offsets {
+ 	u32 sub420;
+ 	u32 rlp;
+ 	u32 his;
++	u32 dma;
+ };
+ 
+ /*
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index db93cb76c08b..bfd56ac5c921 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -257,6 +257,7 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 	isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET;
+ 	isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET;
+ 	isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET;
++	isc->offsets.dma = ISC_SAMA5D2_DMA_OFFSET;
+ 
+ 	/* sama5d2-isc - 8 bits per beat */
+ 	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/171-media-atmel-atmel-isc-add-support-for-version-regist.patch

@@ -0,0 +1,86 @@
+From 0939b0a92acca11a5a3b0de5dd70434e17e40ed3 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:13 +0200
+Subject: [PATCH 171/247] media: atmel: atmel-isc: add support for version
+ register
+
+Add support for version register and print it at probe time.
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-regs.h    | 5 +++++
+ drivers/media/platform/atmel/atmel-isc.h         | 2 ++
+ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 5 +++++
+ 3 files changed, 12 insertions(+)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h
+index 4940998c82a2..344668dcfcf4 100644
+--- a/drivers/media/platform/atmel/atmel-isc-regs.h
++++ b/drivers/media/platform/atmel/atmel-isc-regs.h
+@@ -295,6 +295,11 @@
+ /* DMA Address 2 Register */
+ #define ISC_DAD2        0x000003fc
+ 
++/* Offset for version register specific to sama5d2 product */
++#define ISC_SAMA5D2_VERSION_OFFSET	0
++/* Version Register */
++#define ISC_VERSION	0x0000040c
++
+ /* Histogram Entry */
+ #define ISC_HIS_ENTRY	0x00000410
+ 
+diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
+index bea545327d3d..13ee19d99c2e 100644
+--- a/drivers/media/platform/atmel/atmel-isc.h
++++ b/drivers/media/platform/atmel/atmel-isc.h
+@@ -152,6 +152,7 @@ struct isc_ctrls {
+  * @rlp:		Offset for the RLP register
+  * @his:		Offset for the HIS related registers
+  * @dma:		Offset for the DMA related registers
++ * @version:		Offset for the version register
+  */
+ struct isc_reg_offsets {
+ 	u32 csc;
+@@ -161,6 +162,7 @@ struct isc_reg_offsets {
+ 	u32 rlp;
+ 	u32 his;
+ 	u32 dma;
++	u32 version;
+ };
+ 
+ /*
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index bfd56ac5c921..aebf38dde2d2 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -210,6 +210,7 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 	struct isc_subdev_entity *subdev_entity;
+ 	int irq;
+ 	int ret;
++	u32 ver;
+ 
+ 	isc = devm_kzalloc(dev, sizeof(*isc), GFP_KERNEL);
+ 	if (!isc)
+@@ -258,6 +259,7 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 	isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET;
+ 	isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET;
+ 	isc->offsets.dma = ISC_SAMA5D2_DMA_OFFSET;
++	isc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET;
+ 
+ 	/* sama5d2-isc - 8 bits per beat */
+ 	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
+@@ -346,6 +348,9 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 	pm_runtime_enable(dev);
+ 	pm_request_idle(dev);
+ 
++	regmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver);
++	dev_info(dev, "Microchip ISC version %x\n", ver);
++
+ 	return 0;
+ 
+ cleanup_subdev:
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/172-media-atmel-atmel-isc-add-his_entry-to-register-offs.patch

@@ -0,0 +1,82 @@
+From bce46a8a620a796ca3cfe5bff61baf6744074986 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:14 +0200
+Subject: [PATCH 172/247] media: atmel: atmel-isc: add his_entry to register
+ offsets
+
+Add his_entry to the reg offsets struct.
+This will allow different products to have a different reg offset for this
+particular module.
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c    | 3 ++-
+ drivers/media/platform/atmel/atmel-isc-regs.h    | 2 ++
+ drivers/media/platform/atmel/atmel-isc.h         | 2 ++
+ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 1 +
+ 4 files changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index e010429fc44d..cfe60b2882ac 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -1684,7 +1684,8 @@ static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max)
+ 	*min = 0;
+ 	*max = HIST_ENTRIES;
+ 
+-	regmap_bulk_read(regmap, ISC_HIS_ENTRY, hist_entry, HIST_ENTRIES);
++	regmap_bulk_read(regmap, ISC_HIS_ENTRY + isc->offsets.his_entry,
++			 hist_entry, HIST_ENTRIES);
+ 
+ 	*hist_count = 0;
+ 	/*
+diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h
+index 344668dcfcf4..a15c13e1a833 100644
+--- a/drivers/media/platform/atmel/atmel-isc-regs.h
++++ b/drivers/media/platform/atmel/atmel-isc-regs.h
+@@ -300,6 +300,8 @@
+ /* Version Register */
+ #define ISC_VERSION	0x0000040c
+ 
++/* Offset for version register specific to sama5d2 product */
++#define ISC_SAMA5D2_HIS_ENTRY_OFFSET	0
+ /* Histogram Entry */
+ #define ISC_HIS_ENTRY	0x00000410
+ 
+diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
+index 13ee19d99c2e..513b2b920b1f 100644
+--- a/drivers/media/platform/atmel/atmel-isc.h
++++ b/drivers/media/platform/atmel/atmel-isc.h
+@@ -153,6 +153,7 @@ struct isc_ctrls {
+  * @his:		Offset for the HIS related registers
+  * @dma:		Offset for the DMA related registers
+  * @version:		Offset for the version register
++ * @his_entry:		Offset for the HIS entries registers
+  */
+ struct isc_reg_offsets {
+ 	u32 csc;
+@@ -163,6 +164,7 @@ struct isc_reg_offsets {
+ 	u32 his;
+ 	u32 dma;
+ 	u32 version;
++	u32 his_entry;
+ };
+ 
+ /*
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index aebf38dde2d2..ed575eb3726d 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -260,6 +260,7 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 	isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET;
+ 	isc->offsets.dma = ISC_SAMA5D2_DMA_OFFSET;
+ 	isc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET;
++	isc->offsets.his_entry = ISC_SAMA5D2_HIS_ENTRY_OFFSET;
+ 
+ 	/* sama5d2-isc - 8 bits per beat */
+ 	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/173-media-atmel-atmel-isc-add-register-description-for-a.patch

@@ -0,0 +1,104 @@
+From 87b581b1197df5f77bd65819d0428f2404c6b764 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:15 +0200
+Subject: [PATCH 173/247] media: atmel: atmel-isc: add register description for
+ additional modules
+
+Add register description for additional pipeline modules: the
+Defective Pixel Correction (DPC) and the Vertical and Horizontal Scaler(VHXS)
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-regs.h | 67 +++++++++++++++++++
+ 1 file changed, 67 insertions(+)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h
+index a15c13e1a833..457eed74cda9 100644
+--- a/drivers/media/platform/atmel/atmel-isc-regs.h
++++ b/drivers/media/platform/atmel/atmel-isc-regs.h
+@@ -90,6 +90,46 @@
+ #define ISC_INT_DDONE		BIT(8)
+ #define ISC_INT_HISDONE		BIT(12)
+ 
++/* ISC DPC Control Register */
++#define ISC_DPC_CTRL	0x40
++
++#define ISC_DPC_CTRL_DPCEN	BIT(0)
++#define ISC_DPC_CTRL_GDCEN	BIT(1)
++#define ISC_DPC_CTRL_BLCEN	BIT(2)
++
++/* ISC DPC Config Register */
++#define ISC_DPC_CFG	0x44
++
++#define ISC_DPC_CFG_BAYSEL_SHIFT	0
++
++#define ISC_DPC_CFG_EITPOL		BIT(4)
++
++#define ISC_DPC_CFG_TA_ENABLE		BIT(14)
++#define ISC_DPC_CFG_TC_ENABLE		BIT(13)
++#define ISC_DPC_CFG_TM_ENABLE		BIT(12)
++
++#define ISC_DPC_CFG_RE_MODE		BIT(17)
++
++#define ISC_DPC_CFG_GDCCLP_SHIFT	20
++#define ISC_DPC_CFG_GDCCLP_MASK		GENMASK(22, 20)
++
++#define ISC_DPC_CFG_BLOFF_SHIFT		24
++#define ISC_DPC_CFG_BLOFF_MASK		GENMASK(31, 24)
++
++#define ISC_DPC_CFG_BAYCFG_SHIFT	0
++#define ISC_DPC_CFG_BAYCFG_MASK		GENMASK(1, 0)
++/* ISC DPC Threshold Median Register */
++#define ISC_DPC_THRESHM	0x48
++
++/* ISC DPC Threshold Closest Register */
++#define ISC_DPC_THRESHC	0x4C
++
++/* ISC DPC Threshold Average Register */
++#define ISC_DPC_THRESHA	0x50
++
++/* ISC DPC STatus Register */
++#define ISC_DPC_SR	0x54
++
+ /* ISC White Balance Control Register */
+ #define ISC_WB_CTRL     0x00000058
+ 
+@@ -153,6 +193,33 @@
+ /* ISC_Gamma Correction Green Entry Register */
+ #define ISC_GAM_RENTRY	0x00000298
+ 
++/* ISC VHXS Control Register */
++#define ISC_VHXS_CTRL	0x398
++
++/* ISC VHXS Source Size Register */
++#define ISC_VHXS_SS	0x39C
++
++/* ISC VHXS Destination Size Register */
++#define ISC_VHXS_DS	0x3A0
++
++/* ISC Vertical Factor Register */
++#define ISC_VXS_FACT	0x3a4
++
++/* ISC Horizontal Factor Register */
++#define ISC_HXS_FACT	0x3a8
++
++/* ISC Vertical Config Register */
++#define ISC_VXS_CFG	0x3ac
++
++/* ISC Horizontal Config Register */
++#define ISC_HXS_CFG	0x3b0
++
++/* ISC Vertical Tap Register */
++#define ISC_VXS_TAP	0x3b4
++
++/* ISC Horizontal Tap Register */
++#define ISC_HXS_TAP	0x434
++
+ /* Offset for CSC register specific to sama5d2 product */
+ #define ISC_SAMA5D2_CSC_OFFSET	0
+ 
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/174-media-atmel-atmel-isc-extend-pipeline-with-extra-mod.patch

@@ -0,0 +1,111 @@
+From 58a6cc3c7eecd16208cd16b92b4eaf8385e69696 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:16 +0200
+Subject: [PATCH 174/247] media: atmel: atmel-isc: extend pipeline with extra
+ modules
+
+Newer ISC pipelines have the additional modules of
+Defective Pixel Correction -> DPC itself,
+Defective Pixel Correction -> Green Disparity Correction (DPC_GDC)
+Defective Pixel Correction -> Black Level Correction (DPC_BLC)
+Vertical and Horizontal Scaler -> VHXS
+
+Some products have this full pipeline (sama7g5), other products do not (sama5d2)
+
+Add the modules to the isc base, and also extend the register range to include
+the modules.
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c | 11 ++++++--
+ drivers/media/platform/atmel/atmel-isc.h      | 28 +++++++++++--------
+ 2 files changed, 25 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index cfe60b2882ac..a6b62e009c38 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -2324,8 +2324,14 @@ int isc_pipeline_init(struct isc_device *isc)
+ 	struct regmap_field *regs;
+ 	unsigned int i;
+ 
+-	/* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */
++	/*
++	 * DPCEN-->GDCEN-->BLCEN-->WB-->CFA-->CC-->
++	 * GAM-->VHXS-->CSC-->CBC-->SUB422-->SUB420
++	 */
+ 	const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = {
++		REG_FIELD(ISC_DPC_CTRL, 0, 0),
++		REG_FIELD(ISC_DPC_CTRL, 1, 1),
++		REG_FIELD(ISC_DPC_CTRL, 2, 2),
+ 		REG_FIELD(ISC_WB_CTRL, 0, 0),
+ 		REG_FIELD(ISC_CFA_CTRL, 0, 0),
+ 		REG_FIELD(ISC_CC_CTRL, 0, 0),
+@@ -2333,6 +2339,7 @@ int isc_pipeline_init(struct isc_device *isc)
+ 		REG_FIELD(ISC_GAM_CTRL, 1, 1),
+ 		REG_FIELD(ISC_GAM_CTRL, 2, 2),
+ 		REG_FIELD(ISC_GAM_CTRL, 3, 3),
++		REG_FIELD(ISC_VHXS_CTRL, 0, 0),
+ 		REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),
+ 		REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0),
+ 		REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0),
+@@ -2351,7 +2358,7 @@ int isc_pipeline_init(struct isc_device *isc)
+ }
+ 
+ /* regmap configuration */
+-#define ATMEL_ISC_REG_MAX    0xbfc
++#define ATMEL_ISC_REG_MAX    0xd5c
+ const struct regmap_config isc_regmap_config = {
+ 	.reg_bits       = 32,
+ 	.reg_stride     = 4,
+diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
+index 513b2b920b1f..86edeea2d5cd 100644
+--- a/drivers/media/platform/atmel/atmel-isc.h
++++ b/drivers/media/platform/atmel/atmel-isc.h
+@@ -67,17 +67,21 @@ struct isc_format {
+ };
+ 
+ /* Pipeline bitmap */
+-#define WB_ENABLE	BIT(0)
+-#define CFA_ENABLE	BIT(1)
+-#define CC_ENABLE	BIT(2)
+-#define GAM_ENABLE	BIT(3)
+-#define GAM_BENABLE	BIT(4)
+-#define GAM_GENABLE	BIT(5)
+-#define GAM_RENABLE	BIT(6)
+-#define CSC_ENABLE	BIT(7)
+-#define CBC_ENABLE	BIT(8)
+-#define SUB422_ENABLE	BIT(9)
+-#define SUB420_ENABLE	BIT(10)
++#define DPC_DPCENABLE	BIT(0)
++#define DPC_GDCENABLE	BIT(1)
++#define DPC_BLCENABLE	BIT(2)
++#define WB_ENABLE	BIT(3)
++#define CFA_ENABLE	BIT(4)
++#define CC_ENABLE	BIT(5)
++#define GAM_ENABLE	BIT(6)
++#define GAM_BENABLE	BIT(7)
++#define GAM_GENABLE	BIT(8)
++#define GAM_RENABLE	BIT(9)
++#define VHXS_ENABLE	BIT(10)
++#define CSC_ENABLE	BIT(11)
++#define CBC_ENABLE	BIT(12)
++#define SUB422_ENABLE	BIT(13)
++#define SUB420_ENABLE	BIT(14)
+ 
+ #define GAM_ENABLES	(GAM_RENABLE | GAM_GENABLE | GAM_BENABLE | GAM_ENABLE)
+ 
+@@ -141,7 +145,7 @@ struct isc_ctrls {
+ 	u32 hist_minmax[HIST_BAYER][2];
+ };
+ 
+-#define ISC_PIPE_LINE_NODE_NUM	11
++#define ISC_PIPE_LINE_NODE_NUM	15
+ 
+ /*
+  * struct isc_reg_offsets - ISC device register offsets
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/175-media-atmel-atmel-isc-add-CC-initialization-function.patch

@@ -0,0 +1,92 @@
+From 0db91d2a803221c313c9f2cd1d71050d7c5a7b5b Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:17 +0200
+Subject: [PATCH 175/247] media: atmel: atmel-isc: add CC initialization
+ function
+
+The CC submodule is a part of the atmel-isc pipeline, and stands for
+Color Correction. It is used to apply gains and offsets to the
+chroma (U, V) components of the YUV elements.
+Implement the CC submodule initialization, as a product
+specific function, which currently configures the neutral point in color
+correction.
+
+[hverkuil: made isc_sama5d2_config_cc static]
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c    |  1 +
+ drivers/media/platform/atmel/atmel-isc.h         |  3 +++
+ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 14 ++++++++++++++
+ 3 files changed, 18 insertions(+)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index a6b62e009c38..ffce8de2cf4d 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -661,6 +661,7 @@ static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)
+ 
+ 	isc->config_csc(isc);
+ 	isc->config_cbc(isc);
++	isc->config_cc(isc);
+ }
+ 
+ static int isc_update_profile(struct isc_device *isc)
+diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
+index 86edeea2d5cd..293746664cef 100644
+--- a/drivers/media/platform/atmel/atmel-isc.h
++++ b/drivers/media/platform/atmel/atmel-isc.h
+@@ -224,6 +224,8 @@ struct isc_reg_offsets {
+  *			specific CSC module
+  * @config_cbc:		pointer to a function that initializes product
+  *			specific CBC module
++ * @config_cc:		pointer to a function that initializes product
++ *			specific CC module
+  *
+  * @offsets:		struct holding the product specific register offsets
+  */
+@@ -297,6 +299,7 @@ struct isc_device {
+ 	struct {
+ 		void (*config_csc)(struct isc_device *isc);
+ 		void (*config_cbc)(struct isc_device *isc);
++		void (*config_cc)(struct isc_device *isc);
+ 	};
+ 
+ 	struct isc_reg_offsets		offsets;
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index ed575eb3726d..903920b74965 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -83,6 +83,19 @@ static void isc_sama5d2_config_cbc(struct isc_device *isc)
+ 		     isc->ctrls.contrast);
+ }
+ 
++static void isc_sama5d2_config_cc(struct isc_device *isc)
++{
++	struct regmap *regmap = isc->regmap;
++
++	/* Configure each register at the neutral fixed point 1.0 or 0.0 */
++	regmap_write(regmap, ISC_CC_RR_RG, (1 << 8));
++	regmap_write(regmap, ISC_CC_RB_OR, 0);
++	regmap_write(regmap, ISC_CC_GR_GG, (1 << 8) << 16);
++	regmap_write(regmap, ISC_CC_GB_OG, 0);
++	regmap_write(regmap, ISC_CC_BR_BG, 0);
++	regmap_write(regmap, ISC_CC_BB_OB, (1 << 8));
++}
++
+ /* Gamma table with gamma 1/2.2 */
+ static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {
+ 	/* 0 --> gamma 1/1.8 */
+@@ -251,6 +264,7 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 
+ 	isc->config_csc = isc_sama5d2_config_csc;
+ 	isc->config_cbc = isc_sama5d2_config_cbc;
++	isc->config_cc = isc_sama5d2_config_cc;
+ 
+ 	isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;
+ 	isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET;
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/176-media-atmel-atmel-isc-create-product-specific-v4l2-c.patch

@@ -0,0 +1,95 @@
+From 0a75c502eac4f2ef71b6c3e0b3a01db1b3c37ba9 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:18 +0200
+Subject: [PATCH 176/247] media: atmel: atmel-isc: create product specific v4l2
+ controls config
+
+Create product specific callback for initializing v4l2 controls.
+Call this from v4l2 controls init function.
+
+[hverkuil: made isc_sama5d2_config_ctrls static]
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c    |  5 +++--
+ drivers/media/platform/atmel/atmel-isc.h         |  5 +++++
+ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 12 ++++++++++++
+ 3 files changed, 20 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index ffce8de2cf4d..8ed8b8a4840c 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -2051,11 +2051,12 @@ static int isc_ctrl_init(struct isc_device *isc)
+ 	if (ret < 0)
+ 		return ret;
+ 
++	/* Initialize product specific controls. For example, contrast */
++	isc->config_ctrls(isc, ops);
++
+ 	ctrls->brightness = 0;
+-	ctrls->contrast = 256;
+ 
+ 	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0);
+-	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256);
+ 	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1,
+ 			  isc->gamma_max);
+ 	isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
+diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
+index 293746664cef..428419d5a07d 100644
+--- a/drivers/media/platform/atmel/atmel-isc.h
++++ b/drivers/media/platform/atmel/atmel-isc.h
+@@ -226,6 +226,8 @@ struct isc_reg_offsets {
+  *			specific CBC module
+  * @config_cc:		pointer to a function that initializes product
+  *			specific CC module
++ * @config_ctrls:	pointer to a functoin that initializes product
++ *			specific v4l2 controls.
+  *
+  * @offsets:		struct holding the product specific register offsets
+  */
+@@ -300,6 +302,9 @@ struct isc_device {
+ 		void (*config_csc)(struct isc_device *isc);
+ 		void (*config_cbc)(struct isc_device *isc);
+ 		void (*config_cc)(struct isc_device *isc);
++
++		void (*config_ctrls)(struct isc_device *isc,
++				     const struct v4l2_ctrl_ops *ops);
+ 	};
+ 
+ 	struct isc_reg_offsets		offsets;
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index 903920b74965..7512012cd9f3 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -96,6 +96,17 @@ static void isc_sama5d2_config_cc(struct isc_device *isc)
+ 	regmap_write(regmap, ISC_CC_BB_OB, (1 << 8));
+ }
+ 
++static void isc_sama5d2_config_ctrls(struct isc_device *isc,
++				     const struct v4l2_ctrl_ops *ops)
++{
++	struct isc_ctrls *ctrls = &isc->ctrls;
++	struct v4l2_ctrl_handler *hdl = &ctrls->handler;
++
++	ctrls->contrast = 256;
++
++	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256);
++}
++
+ /* Gamma table with gamma 1/2.2 */
+ static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {
+ 	/* 0 --> gamma 1/1.8 */
+@@ -265,6 +276,7 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 	isc->config_csc = isc_sama5d2_config_csc;
+ 	isc->config_cbc = isc_sama5d2_config_cbc;
+ 	isc->config_cc = isc_sama5d2_config_cc;
++	isc->config_ctrls = isc_sama5d2_config_ctrls;
+ 
+ 	isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;
+ 	isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET;
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/177-media-atmel-atmel-isc-create-callback-for-DPC-submod.patch

@@ -0,0 +1,84 @@
+From d53eb90044c19ba22b51978fcb007d9b5200b83a Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:19 +0200
+Subject: [PATCH 177/247] media: atmel: atmel-isc: create callback for DPC
+ submodule product specific
+
+The DPC submodule is a part of the atmel-isc pipeline, and stands for
+Defective Pixel Correction. Its purpose is to detect defective pixels and
+correct them if possible with the help of adjacent pixels.
+Create a product specific callback for initializing the DPC submodule
+of the pipeline.
+For sama5d2 product, this module does not exist, thus this function is a noop.
+
+[hverkuil: made isc_sama5d2_config_dpc static]
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c    | 1 +
+ drivers/media/platform/atmel/atmel-isc.h         | 3 +++
+ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 6 ++++++
+ 3 files changed, 10 insertions(+)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index 8ed8b8a4840c..777a5dc19d6e 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -659,6 +659,7 @@ static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)
+ 	regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES);
+ 	regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);
+ 
++	isc->config_dpc(isc);
+ 	isc->config_csc(isc);
+ 	isc->config_cbc(isc);
+ 	isc->config_cc(isc);
+diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
+index 428419d5a07d..2f093dc968cd 100644
+--- a/drivers/media/platform/atmel/atmel-isc.h
++++ b/drivers/media/platform/atmel/atmel-isc.h
+@@ -220,6 +220,8 @@ struct isc_reg_offsets {
+  * @max_width:		maximum frame width, dependent on the internal RAM
+  * @max_height:		maximum frame height, dependent on the internal RAM
+  *
++ * @config_dpc:		pointer to a function that initializes product
++ *			specific DPC module
+  * @config_csc:		pointer to a function that initializes product
+  *			specific CSC module
+  * @config_cbc:		pointer to a function that initializes product
+@@ -299,6 +301,7 @@ struct isc_device {
+ 	u32		max_height;
+ 
+ 	struct {
++		void (*config_dpc)(struct isc_device *isc);
+ 		void (*config_csc)(struct isc_device *isc);
+ 		void (*config_cbc)(struct isc_device *isc);
+ 		void (*config_cc)(struct isc_device *isc);
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index 7512012cd9f3..84d1bf3305f2 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -107,6 +107,11 @@ static void isc_sama5d2_config_ctrls(struct isc_device *isc,
+ 	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256);
+ }
+ 
++static void isc_sama5d2_config_dpc(struct isc_device *isc)
++{
++	/* This module is not present on sama5d2 pipeline */
++}
++
+ /* Gamma table with gamma 1/2.2 */
+ static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {
+ 	/* 0 --> gamma 1/1.8 */
+@@ -273,6 +278,7 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 	isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH;
+ 	isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT;
+ 
++	isc->config_dpc = isc_sama5d2_config_dpc;
+ 	isc->config_csc = isc_sama5d2_config_csc;
+ 	isc->config_cbc = isc_sama5d2_config_cbc;
+ 	isc->config_cc = isc_sama5d2_config_cc;
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/178-media-atmel-atmel-isc-create-callback-for-GAM-submod.patch

@@ -0,0 +1,84 @@
+From 96936a6753a13dea5a8f66de949e6594dd82ce22 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:20 +0200
+Subject: [PATCH 178/247] media: atmel: atmel-isc: create callback for GAM
+ submodule product specific
+
+The GAM submodule is a part of the atmel-isc pipeline, and stands for
+Gamma Correction. It is used to apply the gamma curve to the incoming pixels.
+Create a product specific callback for initializing the GAM submodule
+of the pipeline.
+For sama5d2 product, there is no special configuration at this moment,
+thus this function is a noop.
+
+[hverkuil: made isc_sama5d2_config_gam static]
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c    | 1 +
+ drivers/media/platform/atmel/atmel-isc.h         | 3 +++
+ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 6 ++++++
+ 3 files changed, 10 insertions(+)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index 777a5dc19d6e..aef0d6570d39 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -663,6 +663,7 @@ static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)
+ 	isc->config_csc(isc);
+ 	isc->config_cbc(isc);
+ 	isc->config_cc(isc);
++	isc->config_gam(isc);
+ }
+ 
+ static int isc_update_profile(struct isc_device *isc)
+diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
+index 2f093dc968cd..151997c11f56 100644
+--- a/drivers/media/platform/atmel/atmel-isc.h
++++ b/drivers/media/platform/atmel/atmel-isc.h
+@@ -228,6 +228,8 @@ struct isc_reg_offsets {
+  *			specific CBC module
+  * @config_cc:		pointer to a function that initializes product
+  *			specific CC module
++ * @config_gam:		pointer to a function that initializes product
++ *			specific GAMMA module
+  * @config_ctrls:	pointer to a functoin that initializes product
+  *			specific v4l2 controls.
+  *
+@@ -305,6 +307,7 @@ struct isc_device {
+ 		void (*config_csc)(struct isc_device *isc);
+ 		void (*config_cbc)(struct isc_device *isc);
+ 		void (*config_cc)(struct isc_device *isc);
++		void (*config_gam)(struct isc_device *isc);
+ 
+ 		void (*config_ctrls)(struct isc_device *isc,
+ 				     const struct v4l2_ctrl_ops *ops);
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index 84d1bf3305f2..b99849ecb8a1 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -112,6 +112,11 @@ static void isc_sama5d2_config_dpc(struct isc_device *isc)
+ 	/* This module is not present on sama5d2 pipeline */
+ }
+ 
++static void isc_sama5d2_config_gam(struct isc_device *isc)
++{
++	/* No specific gamma configuration */
++}
++
+ /* Gamma table with gamma 1/2.2 */
+ static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {
+ 	/* 0 --> gamma 1/1.8 */
+@@ -282,6 +287,7 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 	isc->config_csc = isc_sama5d2_config_csc;
+ 	isc->config_cbc = isc_sama5d2_config_cbc;
+ 	isc->config_cc = isc_sama5d2_config_cc;
++	isc->config_gam = isc_sama5d2_config_gam;
+ 	isc->config_ctrls = isc_sama5d2_config_ctrls;
+ 
+ 	isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/179-media-atmel-atmel-isc-create-callback-for-RLP-submod.patch

@@ -0,0 +1,104 @@
+From ece1d7059731e31875e6eb464da4fb4a16465305 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:21 +0200
+Subject: [PATCH 179/247] media: atmel: atmel-isc: create callback for RLP
+ submodule product specific
+
+The RLP submodule is a part of the atmel-isc pipeline, and stands for
+Rounding,Limiting and Packaging. It used to extract specific data from the
+ISC pipeline. For example if we want to output greyscale 8 bit, we would
+use limiting to 8 bits, and packaging to Luma component only.
+
+Create a product specific callback for initializing the RLP submodule
+of the pipeline
+
+[hverkuil: made isc_sama5d2_config_rlp static]
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c    |  6 ++----
+ drivers/media/platform/atmel/atmel-isc.h         |  3 +++
+ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 10 ++++++++++
+ 3 files changed, 15 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index aef0d6570d39..67c16ca17672 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -719,11 +719,10 @@ static void isc_set_histogram(struct isc_device *isc, bool enable)
+ static int isc_configure(struct isc_device *isc)
+ {
+ 	struct regmap *regmap = isc->regmap;
+-	u32 pfe_cfg0, rlp_mode, dcfg, mask, pipeline;
++	u32 pfe_cfg0, dcfg, mask, pipeline;
+ 	struct isc_subdev_entity *subdev = isc->current_subdev;
+ 
+ 	pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps;
+-	rlp_mode = isc->config.rlp_cfg_mode;
+ 	pipeline = isc->config.bits_pipeline;
+ 
+ 	dcfg = isc->config.dcfg_imode | isc->dcfg;
+@@ -736,8 +735,7 @@ static int isc_configure(struct isc_device *isc)
+ 
+ 	regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);
+ 
+-	regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,
+-			   ISC_RLP_CFG_MODE_MASK, rlp_mode);
++	isc->config_rlp(isc);
+ 
+ 	regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg);
+ 
+diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
+index 151997c11f56..24006327c5e4 100644
+--- a/drivers/media/platform/atmel/atmel-isc.h
++++ b/drivers/media/platform/atmel/atmel-isc.h
+@@ -230,6 +230,8 @@ struct isc_reg_offsets {
+  *			specific CC module
+  * @config_gam:		pointer to a function that initializes product
+  *			specific GAMMA module
++ * @config_rlp:		pointer to a function that initializes product
++ *			specific RLP module
+  * @config_ctrls:	pointer to a functoin that initializes product
+  *			specific v4l2 controls.
+  *
+@@ -308,6 +310,7 @@ struct isc_device {
+ 		void (*config_cbc)(struct isc_device *isc);
+ 		void (*config_cc)(struct isc_device *isc);
+ 		void (*config_gam)(struct isc_device *isc);
++		void (*config_rlp)(struct isc_device *isc);
+ 
+ 		void (*config_ctrls)(struct isc_device *isc,
+ 				     const struct v4l2_ctrl_ops *ops);
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index b99849ecb8a1..86704a1a24b9 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -117,6 +117,15 @@ static void isc_sama5d2_config_gam(struct isc_device *isc)
+ 	/* No specific gamma configuration */
+ }
+ 
++static void isc_sama5d2_config_rlp(struct isc_device *isc)
++{
++	struct regmap *regmap = isc->regmap;
++	u32 rlp_mode = isc->config.rlp_cfg_mode;
++
++	regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,
++			   ISC_RLP_CFG_MODE_MASK, rlp_mode);
++}
++
+ /* Gamma table with gamma 1/2.2 */
+ static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {
+ 	/* 0 --> gamma 1/1.8 */
+@@ -288,6 +297,7 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 	isc->config_cbc = isc_sama5d2_config_cbc;
+ 	isc->config_cc = isc_sama5d2_config_cc;
+ 	isc->config_gam = isc_sama5d2_config_gam;
++	isc->config_rlp = isc_sama5d2_config_rlp;
+ 	isc->config_ctrls = isc_sama5d2_config_ctrls;
+ 
+ 	isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/180-media-atmel-atmel-isc-move-the-formats-list-into-pro.patch

@@ -0,0 +1,449 @@
+From dda51aa2e4524914d25022864466fa9d8713a5e9 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:22 +0200
+Subject: [PATCH 180/247] media: atmel: atmel-isc: move the formats list into
+ product specific code
+
+The list of input and output formats has to be product specific.
+Move this list into the product specific code.
+Have pointers to these arrays inside the device struct.
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c | 167 ++----------------
+ drivers/media/platform/atmel/atmel-isc.h      |  12 +-
+ .../media/platform/atmel/atmel-sama5d2-isc.c  | 136 ++++++++++++++
+ 3 files changed, 165 insertions(+), 150 deletions(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index 67c16ca17672..90a62d43fdb1 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -45,137 +45,6 @@ module_param(sensor_preferred, uint, 0644);
+ MODULE_PARM_DESC(sensor_preferred,
+ 		 "Sensor is preferred to output the specified format (1-on 0-off), default 1");
+ 
+-/* This is a list of the formats that the ISC can *output* */
+-const struct isc_format controller_formats[] = {
+-	{
+-		.fourcc		= V4L2_PIX_FMT_ARGB444,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_ARGB555,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_RGB565,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_ABGR32,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_XBGR32,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_YUV420,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_YUYV,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_YUV422P,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_GREY,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_Y10,
+-	},
+-};
+-
+-/* This is a list of formats that the ISC can receive as *input* */
+-struct isc_format formats_list[] = {
+-	{
+-		.fourcc		= V4L2_PIX_FMT_SBGGR8,
+-		.mbus_code	= MEDIA_BUS_FMT_SBGGR8_1X8,
+-		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
+-		.cfa_baycfg	= ISC_BAY_CFG_BGBG,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_SGBRG8,
+-		.mbus_code	= MEDIA_BUS_FMT_SGBRG8_1X8,
+-		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
+-		.cfa_baycfg	= ISC_BAY_CFG_GBGB,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_SGRBG8,
+-		.mbus_code	= MEDIA_BUS_FMT_SGRBG8_1X8,
+-		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
+-		.cfa_baycfg	= ISC_BAY_CFG_GRGR,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_SRGGB8,
+-		.mbus_code	= MEDIA_BUS_FMT_SRGGB8_1X8,
+-		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
+-		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_SBGGR10,
+-		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
+-		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
+-		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_SGBRG10,
+-		.mbus_code	= MEDIA_BUS_FMT_SGBRG10_1X10,
+-		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
+-		.cfa_baycfg	= ISC_BAY_CFG_GBGB,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_SGRBG10,
+-		.mbus_code	= MEDIA_BUS_FMT_SGRBG10_1X10,
+-		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
+-		.cfa_baycfg	= ISC_BAY_CFG_GRGR,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_SRGGB10,
+-		.mbus_code	= MEDIA_BUS_FMT_SRGGB10_1X10,
+-		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
+-		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_SBGGR12,
+-		.mbus_code	= MEDIA_BUS_FMT_SBGGR12_1X12,
+-		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
+-		.cfa_baycfg	= ISC_BAY_CFG_BGBG,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_SGBRG12,
+-		.mbus_code	= MEDIA_BUS_FMT_SGBRG12_1X12,
+-		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
+-		.cfa_baycfg	= ISC_BAY_CFG_GBGB,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_SGRBG12,
+-		.mbus_code	= MEDIA_BUS_FMT_SGRBG12_1X12,
+-		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
+-		.cfa_baycfg	= ISC_BAY_CFG_GRGR,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_SRGGB12,
+-		.mbus_code	= MEDIA_BUS_FMT_SRGGB12_1X12,
+-		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
+-		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_GREY,
+-		.mbus_code	= MEDIA_BUS_FMT_Y8_1X8,
+-		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_YUYV,
+-		.mbus_code	= MEDIA_BUS_FMT_YUYV8_2X8,
+-		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_RGB565,
+-		.mbus_code	= MEDIA_BUS_FMT_RGB565_2X8_LE,
+-		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
+-	},
+-	{
+-		.fourcc		= V4L2_PIX_FMT_Y10,
+-		.mbus_code	= MEDIA_BUS_FMT_Y10_1X10,
+-		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
+-	},
+-
+-};
+-
+ #define ISC_IS_FORMAT_RAW(mbus_code) \
+ 	(((mbus_code) & 0xf000) == 0x3000)
+ 
+@@ -919,24 +788,25 @@ static int isc_querycap(struct file *file, void *priv,
+ static int isc_enum_fmt_vid_cap(struct file *file, void *priv,
+ 				 struct v4l2_fmtdesc *f)
+ {
++	struct isc_device *isc = video_drvdata(file);
+ 	u32 index = f->index;
+ 	u32 i, supported_index;
+ 
+-	if (index < ARRAY_SIZE(controller_formats)) {
+-		f->pixelformat = controller_formats[index].fourcc;
++	if (index < isc->controller_formats_size) {
++		f->pixelformat = isc->controller_formats[index].fourcc;
+ 		return 0;
+ 	}
+ 
+-	index -= ARRAY_SIZE(controller_formats);
++	index -= isc->controller_formats_size;
+ 
+ 	supported_index = 0;
+ 
+-	for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
+-		if (!ISC_IS_FORMAT_RAW(formats_list[i].mbus_code) ||
+-		    !formats_list[i].sd_support)
++	for (i = 0; i < isc->formats_list_size; i++) {
++		if (!ISC_IS_FORMAT_RAW(isc->formats_list[i].mbus_code) ||
++		    !isc->formats_list[i].sd_support)
+ 			continue;
+ 		if (supported_index == index) {
+-			f->pixelformat = formats_list[i].fourcc;
++			f->pixelformat = isc->formats_list[i].fourcc;
+ 			return 0;
+ 		}
+ 		supported_index++;
+@@ -1477,8 +1347,8 @@ static int isc_enum_framesizes(struct file *file, void *fh,
+ 		if (isc->user_formats[i]->fourcc == fsize->pixel_format)
+ 			ret = 0;
+ 
+-	for (i = 0; i < ARRAY_SIZE(controller_formats); i++)
+-		if (controller_formats[i].fourcc == fsize->pixel_format)
++	for (i = 0; i < isc->controller_formats_size; i++)
++		if (isc->controller_formats[i].fourcc == fsize->pixel_format)
+ 			ret = 0;
+ 
+ 	if (ret)
+@@ -1514,8 +1384,8 @@ static int isc_enum_frameintervals(struct file *file, void *fh,
+ 		if (isc->user_formats[i]->fourcc == fival->pixel_format)
+ 			ret = 0;
+ 
+-	for (i = 0; i < ARRAY_SIZE(controller_formats); i++)
+-		if (controller_formats[i].fourcc == fival->pixel_format)
++	for (i = 0; i < isc->controller_formats_size; i++)
++		if (isc->controller_formats[i].fourcc == fival->pixel_format)
+ 			ret = 0;
+ 
+ 	if (ret)
+@@ -2126,12 +1996,13 @@ static void isc_async_unbind(struct v4l2_async_notifier *notifier,
+ 	v4l2_ctrl_handler_free(&isc->ctrls.handler);
+ }
+ 
+-static struct isc_format *find_format_by_code(unsigned int code, int *index)
++static struct isc_format *find_format_by_code(struct isc_device *isc,
++					      unsigned int code, int *index)
+ {
+-	struct isc_format *fmt = &formats_list[0];
++	struct isc_format *fmt = &isc->formats_list[0];
+ 	unsigned int i;
+ 
+-	for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
++	for (i = 0; i < isc->formats_list_size; i++) {
+ 		if (fmt->mbus_code == code) {
+ 			*index = i;
+ 			return fmt;
+@@ -2148,7 +2019,7 @@ static int isc_formats_init(struct isc_device *isc)
+ 	struct isc_format *fmt;
+ 	struct v4l2_subdev *subdev = isc->current_subdev->sd;
+ 	unsigned int num_fmts, i, j;
+-	u32 list_size = ARRAY_SIZE(formats_list);
++	u32 list_size = isc->formats_list_size;
+ 	struct v4l2_subdev_mbus_code_enum mbus_code = {
+ 		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ 	};
+@@ -2158,7 +2029,7 @@ static int isc_formats_init(struct isc_device *isc)
+ 	       NULL, &mbus_code)) {
+ 		mbus_code.index++;
+ 
+-		fmt = find_format_by_code(mbus_code.code, &i);
++		fmt = find_format_by_code(isc, mbus_code.code, &i);
+ 		if (!fmt) {
+ 			v4l2_warn(&isc->v4l2_dev, "Mbus code %x not supported\n",
+ 				  mbus_code.code);
+@@ -2179,7 +2050,7 @@ static int isc_formats_init(struct isc_device *isc)
+ 	if (!isc->user_formats)
+ 		return -ENOMEM;
+ 
+-	fmt = &formats_list[0];
++	fmt = &isc->formats_list[0];
+ 	for (i = 0, j = 0; i < list_size; i++) {
+ 		if (fmt->sd_support)
+ 			isc->user_formats[j++] = fmt;
+diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
+index 24006327c5e4..b34737c09a5b 100644
+--- a/drivers/media/platform/atmel/atmel-isc.h
++++ b/drivers/media/platform/atmel/atmel-isc.h
+@@ -236,6 +236,12 @@ struct isc_reg_offsets {
+  *			specific v4l2 controls.
+  *
+  * @offsets:		struct holding the product specific register offsets
++ * @controller_formats:	pointer to the array of possible formats that the
++ *			controller can output
++ * @formats_list:	pointer to the array of possible formats that can
++ *			be used as an input to the controller
++ * @controller_formats_size:	size of controller_formats array
++ * @formats_list_size:	size of formats_list array
+  */
+ struct isc_device {
+ 	struct regmap		*regmap;
+@@ -317,10 +323,12 @@ struct isc_device {
+ 	};
+ 
+ 	struct isc_reg_offsets		offsets;
++	const struct isc_format		*controller_formats;
++	struct isc_format		*formats_list;
++	u32				controller_formats_size;
++	u32				formats_list_size;
+ };
+ 
+-extern struct isc_format formats_list[];
+-extern const struct isc_format controller_formats[];
+ extern const struct regmap_config isc_regmap_config;
+ extern const struct v4l2_async_notifier_operations isc_async_ops;
+ 
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index 86704a1a24b9..b8c1b57ed820 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -54,6 +54,137 @@
+ 
+ #define ISC_CLK_MAX_DIV		255
+ 
++/* This is a list of the formats that the ISC can *output* */
++static const struct isc_format sama5d2_controller_formats[] = {
++	{
++		.fourcc		= V4L2_PIX_FMT_ARGB444,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_ARGB555,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_RGB565,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_ABGR32,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_XBGR32,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_YUV420,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_YUYV,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_YUV422P,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_GREY,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_Y10,
++	},
++};
++
++/* This is a list of formats that the ISC can receive as *input* */
++static struct isc_format sama5d2_formats_list[] = {
++	{
++		.fourcc		= V4L2_PIX_FMT_SBGGR8,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR8_1X8,
++		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
++		.cfa_baycfg	= ISC_BAY_CFG_BGBG,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_SGBRG8,
++		.mbus_code	= MEDIA_BUS_FMT_SGBRG8_1X8,
++		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
++		.cfa_baycfg	= ISC_BAY_CFG_GBGB,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_SGRBG8,
++		.mbus_code	= MEDIA_BUS_FMT_SGRBG8_1X8,
++		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
++		.cfa_baycfg	= ISC_BAY_CFG_GRGR,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_SRGGB8,
++		.mbus_code	= MEDIA_BUS_FMT_SRGGB8_1X8,
++		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
++		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_SBGGR10,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
++		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_SGBRG10,
++		.mbus_code	= MEDIA_BUS_FMT_SGBRG10_1X10,
++		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
++		.cfa_baycfg	= ISC_BAY_CFG_GBGB,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_SGRBG10,
++		.mbus_code	= MEDIA_BUS_FMT_SGRBG10_1X10,
++		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
++		.cfa_baycfg	= ISC_BAY_CFG_GRGR,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_SRGGB10,
++		.mbus_code	= MEDIA_BUS_FMT_SRGGB10_1X10,
++		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
++		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_SBGGR12,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR12_1X12,
++		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
++		.cfa_baycfg	= ISC_BAY_CFG_BGBG,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_SGBRG12,
++		.mbus_code	= MEDIA_BUS_FMT_SGBRG12_1X12,
++		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
++		.cfa_baycfg	= ISC_BAY_CFG_GBGB,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_SGRBG12,
++		.mbus_code	= MEDIA_BUS_FMT_SGRBG12_1X12,
++		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
++		.cfa_baycfg	= ISC_BAY_CFG_GRGR,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_SRGGB12,
++		.mbus_code	= MEDIA_BUS_FMT_SRGGB12_1X12,
++		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
++		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_GREY,
++		.mbus_code	= MEDIA_BUS_FMT_Y8_1X8,
++		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_YUYV,
++		.mbus_code	= MEDIA_BUS_FMT_YUYV8_2X8,
++		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_RGB565,
++		.mbus_code	= MEDIA_BUS_FMT_RGB565_2X8_LE,
++		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_Y10,
++		.mbus_code	= MEDIA_BUS_FMT_Y10_1X10,
++		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
++	},
++
++};
++
+ static void isc_sama5d2_config_csc(struct isc_device *isc)
+ {
+ 	struct regmap *regmap = isc->regmap;
+@@ -310,6 +441,11 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 	isc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET;
+ 	isc->offsets.his_entry = ISC_SAMA5D2_HIS_ENTRY_OFFSET;
+ 
++	isc->controller_formats = sama5d2_controller_formats;
++	isc->controller_formats_size = ARRAY_SIZE(sama5d2_controller_formats);
++	isc->formats_list = sama5d2_formats_list;
++	isc->formats_list_size = ARRAY_SIZE(sama5d2_formats_list);
++
+ 	/* sama5d2-isc - 8 bits per beat */
+ 	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
+ 
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/181-media-atmel-atmel-isc-create-an-adapt-pipeline-callb.patch

@@ -0,0 +1,98 @@
+From 8601f1fc0a9a22788bfa6369fbbf83b3828a5b42 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:23 +0200
+Subject: [PATCH 181/247] media: atmel: atmel-isc: create an adapt pipeline
+ callback for product specific
+
+Once the pipeline is set in the base code, create a callback that will adapt
+the ISC pipeline to each product.
+Create the adapt_pipeline callback that will be used in this fashion.
+
+[hverkuil: made isc_sama5d2_adapt_pipeline static]
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c    |  4 ++++
+ drivers/media/platform/atmel/atmel-isc.h         |  5 +++++
+ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 11 +++++++++++
+ 3 files changed, 20 insertions(+)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index 90a62d43fdb1..7862d6bf850d 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -1059,6 +1059,10 @@ static int isc_try_configure_pipeline(struct isc_device *isc)
+ 	default:
+ 		isc->try_config.bits_pipeline = 0x0;
+ 	}
++
++	/* Tune the pipeline to product specific */
++	isc->adapt_pipeline(isc);
++
+ 	return 0;
+ }
+ 
+diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
+index b34737c09a5b..f59b2426ae74 100644
+--- a/drivers/media/platform/atmel/atmel-isc.h
++++ b/drivers/media/platform/atmel/atmel-isc.h
+@@ -235,6 +235,9 @@ struct isc_reg_offsets {
+  * @config_ctrls:	pointer to a functoin that initializes product
+  *			specific v4l2 controls.
+  *
++ * @adapt_pipeline:	pointer to a function that adapts the pipeline bits
++ *			to the product specific pipeline
++ *
+  * @offsets:		struct holding the product specific register offsets
+  * @controller_formats:	pointer to the array of possible formats that the
+  *			controller can output
+@@ -320,6 +323,8 @@ struct isc_device {
+ 
+ 		void (*config_ctrls)(struct isc_device *isc,
+ 				     const struct v4l2_ctrl_ops *ops);
++
++		void (*adapt_pipeline)(struct isc_device *isc);
+ 	};
+ 
+ 	struct isc_reg_offsets		offsets;
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index b8c1b57ed820..26c971a380ca 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -54,6 +54,10 @@
+ 
+ #define ISC_CLK_MAX_DIV		255
+ 
++#define ISC_SAMA5D2_PIPELINE \
++	(WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \
++	CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE)
++
+ /* This is a list of the formats that the ISC can *output* */
+ static const struct isc_format sama5d2_controller_formats[] = {
+ 	{
+@@ -257,6 +261,11 @@ static void isc_sama5d2_config_rlp(struct isc_device *isc)
+ 			   ISC_RLP_CFG_MODE_MASK, rlp_mode);
+ }
+ 
++static void isc_sama5d2_adapt_pipeline(struct isc_device *isc)
++{
++	isc->try_config.bits_pipeline &= ISC_SAMA5D2_PIPELINE;
++}
++
+ /* Gamma table with gamma 1/2.2 */
+ static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {
+ 	/* 0 --> gamma 1/1.8 */
+@@ -431,6 +440,8 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 	isc->config_rlp = isc_sama5d2_config_rlp;
+ 	isc->config_ctrls = isc_sama5d2_config_ctrls;
+ 
++	isc->adapt_pipeline = isc_sama5d2_adapt_pipeline;
++
+ 	isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;
+ 	isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET;
+ 	isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET;
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/182-media-atmel-atmel-isc-regs-add-additional-fields-for.patch

@@ -0,0 +1,60 @@
+From bf032d1a0105939b90072914d88181fbe6187f43 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:24 +0200
+Subject: [PATCH 182/247] media: atmel: atmel-isc-regs: add additional fields
+ for sama7g5 type pipeline
+
+Add additional fields for registers present in sama7g5 type pipeline.
+Extend register masks for additional bits in sama7g5 type pipeline registers.
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-regs.h | 16 ++++++++++++++--
+ 1 file changed, 14 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h
+index 457eed74cda9..5f99bf7717c1 100644
+--- a/drivers/media/platform/atmel/atmel-isc-regs.h
++++ b/drivers/media/platform/atmel/atmel-isc-regs.h
+@@ -289,8 +289,18 @@
+ #define ISC_RLP_CFG_MODE_ARGB32         0xa
+ #define ISC_RLP_CFG_MODE_YYCC           0xb
+ #define ISC_RLP_CFG_MODE_YYCC_LIMITED   0xc
++#define ISC_RLP_CFG_MODE_YCYC           0xd
+ #define ISC_RLP_CFG_MODE_MASK           GENMASK(3, 0)
+ 
++#define ISC_RLP_CFG_LSH			BIT(5)
++
++#define ISC_RLP_CFG_YMODE_YUYV		(3 << 6)
++#define ISC_RLP_CFG_YMODE_YVYU		(2 << 6)
++#define ISC_RLP_CFG_YMODE_VYUY		(0 << 6)
++#define ISC_RLP_CFG_YMODE_UYVY		(1 << 6)
++
++#define ISC_RLP_CFG_YMODE_MASK		GENMASK(7, 6)
++
+ /* Offset for HIS register specific to sama5d2 product */
+ #define ISC_SAMA5D2_HIS_OFFSET	0
+ /* Histogram Control Register */
+@@ -332,13 +342,15 @@
+ #define ISC_DCFG_YMBSIZE_BEATS4         (0x1 << 4)
+ #define ISC_DCFG_YMBSIZE_BEATS8         (0x2 << 4)
+ #define ISC_DCFG_YMBSIZE_BEATS16        (0x3 << 4)
+-#define ISC_DCFG_YMBSIZE_MASK           GENMASK(5, 4)
++#define ISC_DCFG_YMBSIZE_BEATS32        (0x4 << 4)
++#define ISC_DCFG_YMBSIZE_MASK           GENMASK(6, 4)
+ 
+ #define ISC_DCFG_CMBSIZE_SINGLE         (0x0 << 8)
+ #define ISC_DCFG_CMBSIZE_BEATS4         (0x1 << 8)
+ #define ISC_DCFG_CMBSIZE_BEATS8         (0x2 << 8)
+ #define ISC_DCFG_CMBSIZE_BEATS16        (0x3 << 8)
+-#define ISC_DCFG_CMBSIZE_MASK           GENMASK(9, 8)
++#define ISC_DCFG_CMBSIZE_BEATS32        (0x4 << 8)
++#define ISC_DCFG_CMBSIZE_MASK           GENMASK(10, 8)
+ 
+ /* DMA Control Register */
+ #define ISC_DCTRL       0x000003e4
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/183-media-atmel-atmel-isc-base-add-support-for-more-form.patch

@@ -0,0 +1,150 @@
+From fa9e6cd8f3ba4a277c06e4c1fb01cd69b3a57234 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:25 +0200
+Subject: [PATCH 183/247] media: atmel: atmel-isc-base: add support for more
+ formats and additional pipeline modules
+
+Add support for additional formats supported by newer pipelines, and for
+additional pipeline modules.
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-isc-base.c | 48 +++++++++++++++----
+ 1 file changed, 38 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index 7862d6bf850d..dcb321ad10b8 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -855,6 +855,8 @@ static int isc_try_validate_formats(struct isc_device *isc)
+ 	case V4L2_PIX_FMT_YUV420:
+ 	case V4L2_PIX_FMT_YUV422P:
+ 	case V4L2_PIX_FMT_YUYV:
++	case V4L2_PIX_FMT_UYVY:
++	case V4L2_PIX_FMT_VYUY:
+ 		ret = 0;
+ 		yuv = true;
+ 		break;
+@@ -869,6 +871,7 @@ static int isc_try_validate_formats(struct isc_device *isc)
+ 		break;
+ 	case V4L2_PIX_FMT_GREY:
+ 	case V4L2_PIX_FMT_Y10:
++	case V4L2_PIX_FMT_Y16:
+ 		ret = 0;
+ 		grey = true;
+ 		break;
+@@ -899,6 +902,8 @@ static int isc_try_validate_formats(struct isc_device *isc)
+  */
+ static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump)
+ {
++	isc->try_config.rlp_cfg_mode = 0;
++
+ 	switch (isc->try_config.fourcc) {
+ 	case V4L2_PIX_FMT_SBGGR8:
+ 	case V4L2_PIX_FMT_SGBRG8:
+@@ -965,7 +970,19 @@ static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump)
+ 		isc->try_config.bpp = 16;
+ 		break;
+ 	case V4L2_PIX_FMT_YUYV:
+-		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
++		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_YUYV;
++		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
++		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
++		isc->try_config.bpp = 16;
++		break;
++	case V4L2_PIX_FMT_UYVY:
++		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_UYVY;
++		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
++		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
++		isc->try_config.bpp = 16;
++		break;
++	case V4L2_PIX_FMT_VYUY:
++		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_VYUY;
+ 		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
+ 		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
+ 		isc->try_config.bpp = 16;
+@@ -976,8 +993,11 @@ static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump)
+ 		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
+ 		isc->try_config.bpp = 8;
+ 		break;
++	case V4L2_PIX_FMT_Y16:
++		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10 | ISC_RLP_CFG_LSH;
++		fallthrough;
+ 	case V4L2_PIX_FMT_Y10:
+-		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10;
++		isc->try_config.rlp_cfg_mode |= ISC_RLP_CFG_MODE_DATY10;
+ 		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
+ 		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
+ 		isc->try_config.bpp = 16;
+@@ -1011,7 +1031,8 @@ static int isc_try_configure_pipeline(struct isc_device *isc)
+ 		/* if sensor format is RAW, we convert inside ISC */
+ 		if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
+ 			isc->try_config.bits_pipeline = CFA_ENABLE |
+-				WB_ENABLE | GAM_ENABLES;
++				WB_ENABLE | GAM_ENABLES | DPC_BLCENABLE |
++				CC_ENABLE;
+ 		} else {
+ 			isc->try_config.bits_pipeline = 0x0;
+ 		}
+@@ -1020,8 +1041,9 @@ static int isc_try_configure_pipeline(struct isc_device *isc)
+ 		/* if sensor format is RAW, we convert inside ISC */
+ 		if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
+ 			isc->try_config.bits_pipeline = CFA_ENABLE |
+-				CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
+-				SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE;
++				CSC_ENABLE | GAM_ENABLES | WB_ENABLE |
++				SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE |
++				DPC_BLCENABLE;
+ 		} else {
+ 			isc->try_config.bits_pipeline = 0x0;
+ 		}
+@@ -1031,33 +1053,39 @@ static int isc_try_configure_pipeline(struct isc_device *isc)
+ 		if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
+ 			isc->try_config.bits_pipeline = CFA_ENABLE |
+ 				CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
+-				SUB422_ENABLE | CBC_ENABLE;
++				SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE;
+ 		} else {
+ 			isc->try_config.bits_pipeline = 0x0;
+ 		}
+ 		break;
+ 	case V4L2_PIX_FMT_YUYV:
++	case V4L2_PIX_FMT_UYVY:
++	case V4L2_PIX_FMT_VYUY:
+ 		/* if sensor format is RAW, we convert inside ISC */
+ 		if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
+ 			isc->try_config.bits_pipeline = CFA_ENABLE |
+ 				CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
+-				SUB422_ENABLE | CBC_ENABLE;
++				SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE;
+ 		} else {
+ 			isc->try_config.bits_pipeline = 0x0;
+ 		}
+ 		break;
+ 	case V4L2_PIX_FMT_GREY:
+-		if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
++	case V4L2_PIX_FMT_Y16:
+ 		/* if sensor format is RAW, we convert inside ISC */
++		if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
+ 			isc->try_config.bits_pipeline = CFA_ENABLE |
+ 				CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
+-				CBC_ENABLE;
++				CBC_ENABLE | DPC_BLCENABLE;
+ 		} else {
+ 			isc->try_config.bits_pipeline = 0x0;
+ 		}
+ 		break;
+ 	default:
+-		isc->try_config.bits_pipeline = 0x0;
++		if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code))
++			isc->try_config.bits_pipeline = WB_ENABLE | DPC_BLCENABLE;
++		else
++			isc->try_config.bits_pipeline = 0x0;
+ 	}
+ 
+ 	/* Tune the pipeline to product specific */
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/184-media-atmel-atmel-isc-sama5d2-remove-duplicate-defin.patch

@@ -0,0 +1,31 @@
+From b36d11efc134f9f1e2804270d08b9dbefdee4a0d Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:26 +0200
+Subject: [PATCH 184/247] media: atmel: atmel-isc-sama5d2: remove duplicate
+ define
+
+Remove a duplicate definition of clock max divider
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index 26c971a380ca..d6fd22b127fd 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -52,8 +52,6 @@
+ #define ISC_SAMA5D2_MAX_SUPPORT_WIDTH   2592
+ #define ISC_SAMA5D2_MAX_SUPPORT_HEIGHT  1944
+ 
+-#define ISC_CLK_MAX_DIV		255
+-
+ #define ISC_SAMA5D2_PIPELINE \
+ 	(WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \
+ 	CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE)
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/185-media-atmel-atmel-isc-add-microchip-xisc-driver.patch

@@ -0,0 +1,826 @@
+From 74fd7ea680cb1a3a43b51a7279aea45efdf9ec42 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Tue, 13 Apr 2021 12:57:29 +0200
+Subject: [PATCH 185/247] media: atmel: atmel-isc: add microchip-xisc driver
+
+Add driver for the extended variant of the isc, the microchip XISC
+present on sama7g5 product.
+
+[hverkuil: drop MODULE_SUPPORTED_DEVICE, no longer exists]
+[hverkuil: made isc_sama7g5_config_csc et al static]
+[hverkuil: made sama7g5_controller_formats et al static]
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/Makefile               |   1 +
+ drivers/media/platform/atmel/Kconfig          |  11 +
+ drivers/media/platform/atmel/Makefile         |   2 +
+ drivers/media/platform/atmel/atmel-isc-base.c |   2 +-
+ drivers/media/platform/atmel/atmel-isc-regs.h |  26 +
+ .../media/platform/atmel/atmel-sama7g5-isc.c  | 630 ++++++++++++++++++
+ 6 files changed, 671 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/media/platform/atmel/atmel-sama7g5-isc.c
+
+diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
+index 62b6cdc8c730..fd15c76402c9 100644
+--- a/drivers/media/platform/Makefile
++++ b/drivers/media/platform/Makefile
+@@ -64,6 +64,7 @@ obj-$(CONFIG_VIDEO_RCAR_VIN)		+= rcar-vin/
+ 
+ obj-$(CONFIG_VIDEO_ATMEL_ISC)		+= atmel/
+ obj-$(CONFIG_VIDEO_ATMEL_ISI)		+= atmel/
++obj-$(CONFIG_VIDEO_ATMEL_XISC)		+= atmel/
+ 
+ obj-$(CONFIG_VIDEO_STM32_DCMI)		+= stm32/
+ 
+diff --git a/drivers/media/platform/atmel/Kconfig b/drivers/media/platform/atmel/Kconfig
+index 1850fe7f9360..99b51213f871 100644
+--- a/drivers/media/platform/atmel/Kconfig
++++ b/drivers/media/platform/atmel/Kconfig
+@@ -12,6 +12,17 @@ config VIDEO_ATMEL_ISC
+ 	   This module makes the ATMEL Image Sensor Controller available
+ 	   as a v4l2 device.
+ 
++config VIDEO_ATMEL_XISC
++	tristate "ATMEL eXtended Image Sensor Controller (XISC) support"
++	depends on VIDEO_V4L2 && COMMON_CLK && VIDEO_V4L2_SUBDEV_API
++	depends on ARCH_AT91 || COMPILE_TEST
++	select VIDEOBUF2_DMA_CONTIG
++	select REGMAP_MMIO
++	select V4L2_FWNODE
++	help
++	   This module makes the ATMEL eXtended Image Sensor Controller
++	   available as a v4l2 device.
++
+ config VIDEO_ATMEL_ISI
+ 	tristate "ATMEL Image Sensor Interface (ISI) support"
+ 	depends on VIDEO_V4L2 && OF
+diff --git a/drivers/media/platform/atmel/Makefile b/drivers/media/platform/atmel/Makefile
+index 2dba38994a70..c5c01556c653 100644
+--- a/drivers/media/platform/atmel/Makefile
++++ b/drivers/media/platform/atmel/Makefile
+@@ -1,5 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+ atmel-isc-objs = atmel-sama5d2-isc.o atmel-isc-base.o
++atmel-xisc-objs = atmel-sama7g5-isc.o atmel-isc-base.o
+ 
+ obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel-isi.o
+ obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel-isc.o
++obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel-xisc.o
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index dcb321ad10b8..46c6e3e20f33 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -600,7 +600,7 @@ static int isc_configure(struct isc_device *isc)
+ 	mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |
+ 	       ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW |
+ 	       ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC |
+-		   ISC_PFE_CFG0_CCIR656;
++	       ISC_PFE_CFG0_CCIR656 | ISC_PFE_CFG0_MIPI;
+ 
+ 	regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);
+ 
+diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h
+index 5f99bf7717c1..d06b72228d4f 100644
+--- a/drivers/media/platform/atmel/atmel-isc-regs.h
++++ b/drivers/media/platform/atmel/atmel-isc-regs.h
+@@ -26,6 +26,7 @@
+ #define ISC_PFE_CFG0_PPOL_LOW   BIT(2)
+ #define ISC_PFE_CFG0_CCIR656    BIT(9)
+ #define ISC_PFE_CFG0_CCIR_CRC   BIT(10)
++#define ISC_PFE_CFG0_MIPI	BIT(14)
+ 
+ #define ISC_PFE_CFG0_MODE_PROGRESSIVE   (0x0 << 4)
+ #define ISC_PFE_CFG0_MODE_MASK          GENMASK(6, 4)
+@@ -184,6 +185,8 @@
+ /* ISC Gamma Correction Control Register */
+ #define ISC_GAM_CTRL    0x00000094
+ 
++#define ISC_GAM_CTRL_BIPART	BIT(4)
++
+ /* ISC_Gamma Correction Blue Entry Register */
+ #define ISC_GAM_BENTRY	0x00000098
+ 
+@@ -222,6 +225,8 @@
+ 
+ /* Offset for CSC register specific to sama5d2 product */
+ #define ISC_SAMA5D2_CSC_OFFSET	0
++/* Offset for CSC register specific to sama7g5 product */
++#define ISC_SAMA7G5_CSC_OFFSET	0x11c
+ 
+ /* Color Space Conversion Control Register */
+ #define ISC_CSC_CTRL    0x00000398
+@@ -246,6 +251,8 @@
+ 
+ /* Offset for CBC register specific to sama5d2 product */
+ #define ISC_SAMA5D2_CBC_OFFSET	0
++/* Offset for CBC register specific to sama7g5 product */
++#define ISC_SAMA7G5_CBC_OFFSET	0x11c
+ 
+ /* Contrast And Brightness Control Register */
+ #define ISC_CBC_CTRL    0x000003b4
+@@ -261,18 +268,30 @@
+ #define ISC_CBC_CONTRAST	0x000003c0
+ #define ISC_CBC_CONTRAST_MASK	GENMASK(11, 0)
+ 
++/* Hue Register */
++#define ISC_CBCHS_HUE	0x4e0
++/* Saturation Register */
++#define ISC_CBCHS_SAT	0x4e4
++
+ /* Offset for SUB422 register specific to sama5d2 product */
+ #define ISC_SAMA5D2_SUB422_OFFSET	0
++/* Offset for SUB422 register specific to sama7g5 product */
++#define ISC_SAMA7G5_SUB422_OFFSET	0x124
++
+ /* Subsampling 4:4:4 to 4:2:2 Control Register */
+ #define ISC_SUB422_CTRL 0x000003c4
+ 
+ /* Offset for SUB420 register specific to sama5d2 product */
+ #define ISC_SAMA5D2_SUB420_OFFSET	0
++/* Offset for SUB420 register specific to sama7g5 product */
++#define ISC_SAMA7G5_SUB420_OFFSET	0x124
+ /* Subsampling 4:2:2 to 4:2:0 Control Register */
+ #define ISC_SUB420_CTRL 0x000003cc
+ 
+ /* Offset for RLP register specific to sama5d2 product */
+ #define ISC_SAMA5D2_RLP_OFFSET	0
++/* Offset for RLP register specific to sama7g5 product */
++#define ISC_SAMA7G5_RLP_OFFSET	0x124
+ /* Rounding, Limiting and Packing Configuration Register */
+ #define ISC_RLP_CFG     0x000003d0
+ 
+@@ -303,6 +322,8 @@
+ 
+ /* Offset for HIS register specific to sama5d2 product */
+ #define ISC_SAMA5D2_HIS_OFFSET	0
++/* Offset for HIS register specific to sama7g5 product */
++#define ISC_SAMA7G5_HIS_OFFSET	0x124
+ /* Histogram Control Register */
+ #define ISC_HIS_CTRL	0x000003d4
+ 
+@@ -326,6 +347,8 @@
+ 
+ /* Offset for DMA register specific to sama5d2 product */
+ #define ISC_SAMA5D2_DMA_OFFSET	0
++/* Offset for DMA register specific to sama7g5 product */
++#define ISC_SAMA7G5_DMA_OFFSET	0x13c
+ 
+ /* DMA Configuration Register */
+ #define ISC_DCFG        0x000003e0
+@@ -376,11 +399,14 @@
+ 
+ /* Offset for version register specific to sama5d2 product */
+ #define ISC_SAMA5D2_VERSION_OFFSET	0
++#define ISC_SAMA7G5_VERSION_OFFSET	0x13c
+ /* Version Register */
+ #define ISC_VERSION	0x0000040c
+ 
+ /* Offset for version register specific to sama5d2 product */
+ #define ISC_SAMA5D2_HIS_ENTRY_OFFSET	0
++/* Offset for version register specific to sama7g5 product */
++#define ISC_SAMA7G5_HIS_ENTRY_OFFSET	0x14c
+ /* Histogram Entry */
+ #define ISC_HIS_ENTRY	0x00000410
+ 
+diff --git a/drivers/media/platform/atmel/atmel-sama7g5-isc.c b/drivers/media/platform/atmel/atmel-sama7g5-isc.c
+new file mode 100644
+index 000000000000..f2785131ff56
+--- /dev/null
++++ b/drivers/media/platform/atmel/atmel-sama7g5-isc.c
+@@ -0,0 +1,630 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Microchip eXtended Image Sensor Controller (XISC) driver
++ *
++ * Copyright (C) 2019-2021 Microchip Technology, Inc. and its subsidiaries
++ *
++ * Author: Eugen Hristev <[email protected]>
++ *
++ * Sensor-->PFE-->DPC-->WB-->CFA-->CC-->GAM-->VHXS-->CSC-->CBHS-->SUB-->RLP-->DMA-->HIS
++ *
++ * ISC video pipeline integrates the following submodules:
++ * PFE: Parallel Front End to sample the camera sensor input stream
++ * DPC: Defective Pixel Correction with black offset correction, green disparity
++ *      correction and defective pixel correction (3 modules total)
++ *  WB: Programmable white balance in the Bayer domain
++ * CFA: Color filter array interpolation module
++ *  CC: Programmable color correction
++ * GAM: Gamma correction
++ *VHXS: Vertical and Horizontal Scaler
++ * CSC: Programmable color space conversion
++ *CBHS: Contrast Brightness Hue and Saturation control
++ * SUB: This module performs YCbCr444 to YCbCr420 chrominance subsampling
++ * RLP: This module performs rounding, range limiting
++ *      and packing of the incoming data
++ * DMA: This module performs DMA master accesses to write frames to external RAM
++ * HIS: Histogram module performs statistic counters on the frames
++ */
++
++#include <linux/clk.h>
++#include <linux/clkdev.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/math64.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_graph.h>
++#include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++#include <linux/regmap.h>
++#include <linux/videodev2.h>
++
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-event.h>
++#include <media/v4l2-image-sizes.h>
++#include <media/v4l2-ioctl.h>
++#include <media/v4l2-fwnode.h>
++#include <media/v4l2-subdev.h>
++#include <media/videobuf2-dma-contig.h>
++
++#include "atmel-isc-regs.h"
++#include "atmel-isc.h"
++
++#define ISC_SAMA7G5_MAX_SUPPORT_WIDTH   3264
++#define ISC_SAMA7G5_MAX_SUPPORT_HEIGHT  2464
++
++#define ISC_SAMA7G5_PIPELINE \
++	(WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \
++	CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE)
++
++/* This is a list of the formats that the ISC can *output* */
++static const struct isc_format sama7g5_controller_formats[] = {
++	{
++		.fourcc		= V4L2_PIX_FMT_ARGB444,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_ARGB555,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_RGB565,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_ABGR32,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_XBGR32,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_YUV420,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_UYVY,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_VYUY,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_YUYV,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_YUV422P,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_GREY,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_Y10,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_Y16,
++	},
++};
++
++/* This is a list of formats that the ISC can receive as *input* */
++static struct isc_format sama7g5_formats_list[] = {
++	{
++		.fourcc		= V4L2_PIX_FMT_SBGGR8,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR8_1X8,
++		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
++		.cfa_baycfg	= ISC_BAY_CFG_BGBG,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_SGBRG8,
++		.mbus_code	= MEDIA_BUS_FMT_SGBRG8_1X8,
++		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
++		.cfa_baycfg	= ISC_BAY_CFG_GBGB,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_SGRBG8,
++		.mbus_code	= MEDIA_BUS_FMT_SGRBG8_1X8,
++		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
++		.cfa_baycfg	= ISC_BAY_CFG_GRGR,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_SRGGB8,
++		.mbus_code	= MEDIA_BUS_FMT_SRGGB8_1X8,
++		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
++		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_SBGGR10,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
++		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_SGBRG10,
++		.mbus_code	= MEDIA_BUS_FMT_SGBRG10_1X10,
++		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
++		.cfa_baycfg	= ISC_BAY_CFG_GBGB,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_SGRBG10,
++		.mbus_code	= MEDIA_BUS_FMT_SGRBG10_1X10,
++		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
++		.cfa_baycfg	= ISC_BAY_CFG_GRGR,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_SRGGB10,
++		.mbus_code	= MEDIA_BUS_FMT_SRGGB10_1X10,
++		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
++		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_SBGGR12,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR12_1X12,
++		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
++		.cfa_baycfg	= ISC_BAY_CFG_BGBG,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_SGBRG12,
++		.mbus_code	= MEDIA_BUS_FMT_SGBRG12_1X12,
++		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
++		.cfa_baycfg	= ISC_BAY_CFG_GBGB,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_SGRBG12,
++		.mbus_code	= MEDIA_BUS_FMT_SGRBG12_1X12,
++		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
++		.cfa_baycfg	= ISC_BAY_CFG_GRGR,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_SRGGB12,
++		.mbus_code	= MEDIA_BUS_FMT_SRGGB12_1X12,
++		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
++		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_GREY,
++		.mbus_code	= MEDIA_BUS_FMT_Y8_1X8,
++		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_YUYV,
++		.mbus_code	= MEDIA_BUS_FMT_YUYV8_2X8,
++		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_UYVY,
++		.mbus_code	= MEDIA_BUS_FMT_YUYV8_2X8,
++		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_RGB565,
++		.mbus_code	= MEDIA_BUS_FMT_RGB565_2X8_LE,
++		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
++	},
++	{
++		.fourcc		= V4L2_PIX_FMT_Y10,
++		.mbus_code	= MEDIA_BUS_FMT_Y10_1X10,
++		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
++	},
++
++};
++
++static void isc_sama7g5_config_csc(struct isc_device *isc)
++{
++	struct regmap *regmap = isc->regmap;
++
++	/* Convert RGB to YUV */
++	regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc,
++		     0x42 | (0x81 << 16));
++	regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc,
++		     0x19 | (0x10 << 16));
++	regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc,
++		     0xFDA | (0xFB6 << 16));
++	regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc,
++		     0x70 | (0x80 << 16));
++	regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc,
++		     0x70 | (0xFA2 << 16));
++	regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc,
++		     0xFEE | (0x80 << 16));
++}
++
++static void isc_sama7g5_config_cbc(struct isc_device *isc)
++{
++	struct regmap *regmap = isc->regmap;
++
++	/* Configure what is set via v4l2 ctrls */
++	regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc, isc->ctrls.brightness);
++	regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc, isc->ctrls.contrast);
++	/* Configure Hue and Saturation as neutral midpoint */
++	regmap_write(regmap, ISC_CBCHS_HUE, 0);
++	regmap_write(regmap, ISC_CBCHS_SAT, (1 << 4));
++}
++
++static void isc_sama7g5_config_cc(struct isc_device *isc)
++{
++	struct regmap *regmap = isc->regmap;
++
++	/* Configure each register at the neutral fixed point 1.0 or 0.0 */
++	regmap_write(regmap, ISC_CC_RR_RG, (1 << 8));
++	regmap_write(regmap, ISC_CC_RB_OR, 0);
++	regmap_write(regmap, ISC_CC_GR_GG, (1 << 8) << 16);
++	regmap_write(regmap, ISC_CC_GB_OG, 0);
++	regmap_write(regmap, ISC_CC_BR_BG, 0);
++	regmap_write(regmap, ISC_CC_BB_OB, (1 << 8));
++}
++
++static void isc_sama7g5_config_ctrls(struct isc_device *isc,
++				     const struct v4l2_ctrl_ops *ops)
++{
++	struct isc_ctrls *ctrls = &isc->ctrls;
++	struct v4l2_ctrl_handler *hdl = &ctrls->handler;
++
++	ctrls->contrast = 16;
++
++	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 16);
++}
++
++static void isc_sama7g5_config_dpc(struct isc_device *isc)
++{
++	u32 bay_cfg = isc->config.sd_format->cfa_baycfg;
++	struct regmap *regmap = isc->regmap;
++
++	regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BLOFF_MASK,
++			   (64 << ISC_DPC_CFG_BLOFF_SHIFT));
++	regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BAYCFG_MASK,
++			   (bay_cfg << ISC_DPC_CFG_BAYCFG_SHIFT));
++}
++
++static void isc_sama7g5_config_gam(struct isc_device *isc)
++{
++	struct regmap *regmap = isc->regmap;
++
++	regmap_update_bits(regmap, ISC_GAM_CTRL, ISC_GAM_CTRL_BIPART,
++			   ISC_GAM_CTRL_BIPART);
++}
++
++static void isc_sama7g5_config_rlp(struct isc_device *isc)
++{
++	struct regmap *regmap = isc->regmap;
++	u32 rlp_mode = isc->config.rlp_cfg_mode;
++
++	regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,
++			   ISC_RLP_CFG_MODE_MASK | ISC_RLP_CFG_LSH |
++			   ISC_RLP_CFG_YMODE_MASK, rlp_mode);
++}
++
++static void isc_sama7g5_adapt_pipeline(struct isc_device *isc)
++{
++	isc->try_config.bits_pipeline &= ISC_SAMA7G5_PIPELINE;
++}
++
++/* Gamma table with gamma 1/2.2 */
++static const u32 isc_sama7g5_gamma_table[][GAMMA_ENTRIES] = {
++	/* index 0 --> gamma bipartite */
++	{
++	      0x980,  0x4c0320,  0x650260,  0x7801e0,  0x8701a0,  0x940180,
++	   0xa00160,  0xab0120,  0xb40120,  0xbd0120,  0xc60100,  0xce0100,
++	   0xd600e0,  0xdd00e0,  0xe400e0,  0xeb00c0,  0xf100c0,  0xf700c0,
++	   0xfd00c0, 0x10300a0, 0x10800c0, 0x10e00a0, 0x11300a0, 0x11800a0,
++	  0x11d00a0, 0x12200a0, 0x12700a0, 0x12c0080, 0x13000a0, 0x1350080,
++	  0x13900a0, 0x13e0080, 0x1420076, 0x17d0062, 0x1ae0054, 0x1d8004a,
++	  0x1fd0044, 0x21f003e, 0x23e003a, 0x25b0036, 0x2760032, 0x28f0030,
++	  0x2a7002e, 0x2be002c, 0x2d4002c, 0x2ea0028, 0x2fe0028, 0x3120026,
++	  0x3250024, 0x3370024, 0x3490022, 0x35a0022, 0x36b0020, 0x37b0020,
++	  0x38b0020, 0x39b001e, 0x3aa001e, 0x3b9001c, 0x3c7001c, 0x3d5001c,
++	  0x3e3001c, 0x3f1001c, 0x3ff001a, 0x40c001a },
++};
++
++static int xisc_parse_dt(struct device *dev, struct isc_device *isc)
++{
++	struct device_node *np = dev->of_node;
++	struct device_node *epn = NULL;
++	struct isc_subdev_entity *subdev_entity;
++	unsigned int flags;
++	int ret;
++	bool mipi_mode;
++
++	INIT_LIST_HEAD(&isc->subdev_entities);
++
++	mipi_mode = of_property_read_bool(np, "microchip,mipi-mode");
++
++	while (1) {
++		struct v4l2_fwnode_endpoint v4l2_epn = { .bus_type = 0 };
++
++		epn = of_graph_get_next_endpoint(np, epn);
++		if (!epn)
++			return 0;
++
++		ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(epn),
++						 &v4l2_epn);
++		if (ret) {
++			ret = -EINVAL;
++			dev_err(dev, "Could not parse the endpoint\n");
++			break;
++		}
++
++		subdev_entity = devm_kzalloc(dev, sizeof(*subdev_entity),
++					     GFP_KERNEL);
++		if (!subdev_entity) {
++			ret = -ENOMEM;
++			break;
++		}
++		subdev_entity->epn = epn;
++
++		flags = v4l2_epn.bus.parallel.flags;
++
++		if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
++			subdev_entity->pfe_cfg0 = ISC_PFE_CFG0_HPOL_LOW;
++
++		if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
++			subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_VPOL_LOW;
++
++		if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
++			subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_PPOL_LOW;
++
++		if (v4l2_epn.bus_type == V4L2_MBUS_BT656)
++			subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_CCIR_CRC |
++					ISC_PFE_CFG0_CCIR656;
++
++		if (mipi_mode)
++			subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_MIPI;
++
++		list_add_tail(&subdev_entity->list, &isc->subdev_entities);
++	}
++	of_node_put(epn);
++
++	return ret;
++}
++
++static int microchip_xisc_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct isc_device *isc;
++	struct resource *res;
++	void __iomem *io_base;
++	struct isc_subdev_entity *subdev_entity;
++	int irq;
++	int ret;
++	u32 ver;
++
++	isc = devm_kzalloc(dev, sizeof(*isc), GFP_KERNEL);
++	if (!isc)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, isc);
++	isc->dev = dev;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	io_base = devm_ioremap_resource(dev, res);
++	if (IS_ERR(io_base))
++		return PTR_ERR(io_base);
++
++	isc->regmap = devm_regmap_init_mmio(dev, io_base, &isc_regmap_config);
++	if (IS_ERR(isc->regmap)) {
++		ret = PTR_ERR(isc->regmap);
++		dev_err(dev, "failed to init register map: %d\n", ret);
++		return ret;
++	}
++
++	irq = platform_get_irq(pdev, 0);
++	if (irq < 0)
++		return irq;
++
++	ret = devm_request_irq(dev, irq, isc_interrupt, 0,
++			       "microchip-sama7g5-xisc", isc);
++	if (ret < 0) {
++		dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n",
++			irq, ret);
++		return ret;
++	}
++
++	isc->gamma_table = isc_sama7g5_gamma_table;
++	isc->gamma_max = 0;
++
++	isc->max_width = ISC_SAMA7G5_MAX_SUPPORT_WIDTH;
++	isc->max_height = ISC_SAMA7G5_MAX_SUPPORT_HEIGHT;
++
++	isc->config_dpc = isc_sama7g5_config_dpc;
++	isc->config_csc = isc_sama7g5_config_csc;
++	isc->config_cbc = isc_sama7g5_config_cbc;
++	isc->config_cc = isc_sama7g5_config_cc;
++	isc->config_gam = isc_sama7g5_config_gam;
++	isc->config_rlp = isc_sama7g5_config_rlp;
++	isc->config_ctrls = isc_sama7g5_config_ctrls;
++
++	isc->adapt_pipeline = isc_sama7g5_adapt_pipeline;
++
++	isc->offsets.csc = ISC_SAMA7G5_CSC_OFFSET;
++	isc->offsets.cbc = ISC_SAMA7G5_CBC_OFFSET;
++	isc->offsets.sub422 = ISC_SAMA7G5_SUB422_OFFSET;
++	isc->offsets.sub420 = ISC_SAMA7G5_SUB420_OFFSET;
++	isc->offsets.rlp = ISC_SAMA7G5_RLP_OFFSET;
++	isc->offsets.his = ISC_SAMA7G5_HIS_OFFSET;
++	isc->offsets.dma = ISC_SAMA7G5_DMA_OFFSET;
++	isc->offsets.version = ISC_SAMA7G5_VERSION_OFFSET;
++	isc->offsets.his_entry = ISC_SAMA7G5_HIS_ENTRY_OFFSET;
++
++	isc->controller_formats = sama7g5_controller_formats;
++	isc->controller_formats_size = ARRAY_SIZE(sama7g5_controller_formats);
++	isc->formats_list = sama7g5_formats_list;
++	isc->formats_list_size = ARRAY_SIZE(sama7g5_formats_list);
++
++	/* sama7g5-isc RAM access port is full AXI4 - 32 bits per beat */
++	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS32 | ISC_DCFG_CMBSIZE_BEATS32;
++
++	ret = isc_pipeline_init(isc);
++	if (ret)
++		return ret;
++
++	isc->hclock = devm_clk_get(dev, "hclock");
++	if (IS_ERR(isc->hclock)) {
++		ret = PTR_ERR(isc->hclock);
++		dev_err(dev, "failed to get hclock: %d\n", ret);
++		return ret;
++	}
++
++	ret = clk_prepare_enable(isc->hclock);
++	if (ret) {
++		dev_err(dev, "failed to enable hclock: %d\n", ret);
++		return ret;
++	}
++
++	ret = isc_clk_init(isc);
++	if (ret) {
++		dev_err(dev, "failed to init isc clock: %d\n", ret);
++		goto unprepare_hclk;
++	}
++
++	isc->ispck = isc->isc_clks[ISC_ISPCK].clk;
++
++	ret = clk_prepare_enable(isc->ispck);
++	if (ret) {
++		dev_err(dev, "failed to enable ispck: %d\n", ret);
++		goto unprepare_hclk;
++	}
++
++	/* ispck should be greater or equal to hclock */
++	ret = clk_set_rate(isc->ispck, clk_get_rate(isc->hclock));
++	if (ret) {
++		dev_err(dev, "failed to set ispck rate: %d\n", ret);
++		goto unprepare_clk;
++	}
++
++	ret = v4l2_device_register(dev, &isc->v4l2_dev);
++	if (ret) {
++		dev_err(dev, "unable to register v4l2 device.\n");
++		goto unprepare_clk;
++	}
++
++	ret = xisc_parse_dt(dev, isc);
++	if (ret) {
++		dev_err(dev, "fail to parse device tree\n");
++		goto unregister_v4l2_device;
++	}
++
++	if (list_empty(&isc->subdev_entities)) {
++		dev_err(dev, "no subdev found\n");
++		ret = -ENODEV;
++		goto unregister_v4l2_device;
++	}
++
++	list_for_each_entry(subdev_entity, &isc->subdev_entities, list) {
++		struct v4l2_async_subdev *asd;
++
++		v4l2_async_notifier_init(&subdev_entity->notifier);
++
++		asd = v4l2_async_notifier_add_fwnode_remote_subdev(
++					&subdev_entity->notifier,
++					of_fwnode_handle(subdev_entity->epn),
++					struct v4l2_async_subdev);
++
++		of_node_put(subdev_entity->epn);
++		subdev_entity->epn = NULL;
++
++		if (IS_ERR(asd)) {
++			ret = PTR_ERR(asd);
++			goto cleanup_subdev;
++		}
++
++		subdev_entity->notifier.ops = &isc_async_ops;
++
++		ret = v4l2_async_notifier_register(&isc->v4l2_dev,
++						   &subdev_entity->notifier);
++		if (ret) {
++			dev_err(dev, "fail to register async notifier\n");
++			goto cleanup_subdev;
++		}
++
++		if (video_is_registered(&isc->video_dev))
++			break;
++	}
++
++	pm_runtime_set_active(dev);
++	pm_runtime_enable(dev);
++	pm_request_idle(dev);
++
++	regmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver);
++	dev_info(dev, "Microchip XISC version %x\n", ver);
++
++	return 0;
++
++cleanup_subdev:
++	isc_subdev_cleanup(isc);
++
++unregister_v4l2_device:
++	v4l2_device_unregister(&isc->v4l2_dev);
++
++unprepare_clk:
++	clk_disable_unprepare(isc->ispck);
++unprepare_hclk:
++	clk_disable_unprepare(isc->hclock);
++
++	isc_clk_cleanup(isc);
++
++	return ret;
++}
++
++static int microchip_xisc_remove(struct platform_device *pdev)
++{
++	struct isc_device *isc = platform_get_drvdata(pdev);
++
++	pm_runtime_disable(&pdev->dev);
++
++	isc_subdev_cleanup(isc);
++
++	v4l2_device_unregister(&isc->v4l2_dev);
++
++	clk_disable_unprepare(isc->ispck);
++	clk_disable_unprepare(isc->hclock);
++
++	isc_clk_cleanup(isc);
++
++	return 0;
++}
++
++static int __maybe_unused xisc_runtime_suspend(struct device *dev)
++{
++	struct isc_device *isc = dev_get_drvdata(dev);
++
++	clk_disable_unprepare(isc->ispck);
++	clk_disable_unprepare(isc->hclock);
++
++	return 0;
++}
++
++static int __maybe_unused xisc_runtime_resume(struct device *dev)
++{
++	struct isc_device *isc = dev_get_drvdata(dev);
++	int ret;
++
++	ret = clk_prepare_enable(isc->hclock);
++	if (ret)
++		return ret;
++
++	ret = clk_prepare_enable(isc->ispck);
++	if (ret)
++		clk_disable_unprepare(isc->hclock);
++
++	return ret;
++}
++
++static const struct dev_pm_ops microchip_xisc_dev_pm_ops = {
++	SET_RUNTIME_PM_OPS(xisc_runtime_suspend, xisc_runtime_resume, NULL)
++};
++
++static const struct of_device_id microchip_xisc_of_match[] = {
++	{ .compatible = "microchip,sama7g5-isc" },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, microchip_xisc_of_match);
++
++static struct platform_driver microchip_xisc_driver = {
++	.probe	= microchip_xisc_probe,
++	.remove	= microchip_xisc_remove,
++	.driver	= {
++		.name		= "microchip-sama7g5-xisc",
++		.pm		= &microchip_xisc_dev_pm_ops,
++		.of_match_table = of_match_ptr(microchip_xisc_of_match),
++	},
++};
++
++module_platform_driver(microchip_xisc_driver);
++
++MODULE_AUTHOR("Eugen Hristev <[email protected]>");
++MODULE_DESCRIPTION("The V4L2 driver for Microchip-XISC");
++MODULE_LICENSE("GPL v2");
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/186-ASoC-atmel-fix-shadowed-variable.patch

@@ -0,0 +1,53 @@
+From 1b41c69264d7233a3e9a0aa36333ee22a5a049e9 Mon Sep 17 00:00:00 2001
+From: Pierre-Louis Bossart <[email protected]>
+Date: Fri, 26 Mar 2021 16:59:12 -0500
+Subject: [PATCH 186/247] ASoC: atmel: fix shadowed variable
+
+Fix cppcheck warning:
+
+sound/soc/atmel/atmel-classd.c:51:14: style: Local variable 'pwm_type'
+shadows outer variable [shadowVariable]
+ const char *pwm_type;
+             ^
+sound/soc/atmel/atmel-classd.c:226:27: note: Shadowed declaration
+static const char * const pwm_type[] = {
+                          ^
+sound/soc/atmel/atmel-classd.c:51:14: note: Shadow variable
+ const char *pwm_type;
+             ^
+
+Signed-off-by: Pierre-Louis Bossart <[email protected]>
+Reviewed-by: Codrin Ciubotariu <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Mark Brown <[email protected]>
+---
+ sound/soc/atmel/atmel-classd.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/sound/soc/atmel/atmel-classd.c b/sound/soc/atmel/atmel-classd.c
+index b1a28a9382fb..6023369e0f1a 100644
+--- a/sound/soc/atmel/atmel-classd.c
++++ b/sound/soc/atmel/atmel-classd.c
+@@ -48,7 +48,7 @@ static struct atmel_classd_pdata *atmel_classd_dt_init(struct device *dev)
+ {
+ 	struct device_node *np = dev->of_node;
+ 	struct atmel_classd_pdata *pdata;
+-	const char *pwm_type;
++	const char *pwm_type_s;
+ 	int ret;
+ 
+ 	if (!np) {
+@@ -60,8 +60,8 @@ static struct atmel_classd_pdata *atmel_classd_dt_init(struct device *dev)
+ 	if (!pdata)
+ 		return ERR_PTR(-ENOMEM);
+ 
+-	ret = of_property_read_string(np, "atmel,pwm-type", &pwm_type);
+-	if ((ret == 0) && (strcmp(pwm_type, "diff") == 0))
++	ret = of_property_read_string(np, "atmel,pwm-type", &pwm_type_s);
++	if ((ret == 0) && (strcmp(pwm_type_s, "diff") == 0))
+ 		pdata->pwm_type = CLASSD_MR_PWMTYP_DIFF;
+ 	else
+ 		pdata->pwm_type = CLASSD_MR_PWMTYP_SINGLE;
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/187-ASoC-atmel-atmel-i2s-remove-useless-initialization.patch

@@ -0,0 +1,41 @@
+From e53725fe0c7e6b52927280272f49fe5f4b4ef317 Mon Sep 17 00:00:00 2001
+From: Pierre-Louis Bossart <[email protected]>
+Date: Fri, 26 Mar 2021 16:59:13 -0500
+Subject: [PATCH 187/247] ASoC: atmel: atmel-i2s: remove useless initialization
+
+Cppcheck complains:
+
+sound/soc/atmel/atmel-i2s.c:628:6: style: Redundant initialization for 'err'. The initialized value is overwritten before it is read. [redundantInitialization]
+ err = devm_request_irq(&pdev->dev, irq, atmel_i2s_interrupt, 0,
+     ^
+sound/soc/atmel/atmel-i2s.c:598:10: note: err is initialized
+ int err = -ENXIO;
+         ^
+sound/soc/atmel/atmel-i2s.c:628:6: note: err is overwritten
+ err = devm_request_irq(&pdev->dev, irq, atmel_i2s_interrupt, 0,
+     ^
+
+Signed-off-by: Pierre-Louis Bossart <[email protected]>
+Reviewed-by: Codrin Ciubotariu <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Mark Brown <[email protected]>
+---
+ sound/soc/atmel/atmel-i2s.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/sound/soc/atmel/atmel-i2s.c b/sound/soc/atmel/atmel-i2s.c
+index 7483c474ccd7..e7169c63becd 100644
+--- a/sound/soc/atmel/atmel-i2s.c
++++ b/sound/soc/atmel/atmel-i2s.c
+@@ -613,7 +613,7 @@ static int atmel_i2s_probe(struct platform_device *pdev)
+ 	struct regmap *regmap;
+ 	void __iomem *base;
+ 	int irq;
+-	int err = -ENXIO;
++	int err;
+ 	unsigned int pcm_flags = 0;
+ 	unsigned int version;
+ 
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/188-ASoC-atmel-i2s-Set-symmetric-sample-bits.patch

@@ -0,0 +1,31 @@
+From a6f337fdf68294cfae233724567cbeea0ae5148f Mon Sep 17 00:00:00 2001
+From: Codrin Ciubotariu <[email protected]>
+Date: Fri, 18 Jun 2021 18:07:40 +0300
+Subject: [PATCH 188/247] ASoC: atmel-i2s: Set symmetric sample bits
+
+The I2S needs to have the same sample bits for both capture and playback
+streams.
+
+Fixes: b543e467d1a9 ("ASoC: atmel-i2s: add driver for the new Atmel I2S controller")
+Signed-off-by: Codrin Ciubotariu <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Mark Brown <[email protected]>
+---
+ sound/soc/atmel/atmel-i2s.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/sound/soc/atmel/atmel-i2s.c b/sound/soc/atmel/atmel-i2s.c
+index e7169c63becd..2a5bc7a54e6c 100644
+--- a/sound/soc/atmel/atmel-i2s.c
++++ b/sound/soc/atmel/atmel-i2s.c
+@@ -560,6 +560,7 @@ static struct snd_soc_dai_driver atmel_i2s_dai = {
+ 	},
+ 	.ops = &atmel_i2s_dai_ops,
+ 	.symmetric_rates = 1,
++	.symmetric_samplebits = 1,
+ };
+ 
+ static const struct snd_soc_component_driver atmel_i2s_component = {
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/189-watchdog-sama5d4_wdt-add-support-for-sama7g5-wdt.patch

@@ -0,0 +1,51 @@
+From ff83cc9f95aaba75991210312061b7fe52aaa400 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Thu, 27 May 2021 13:01:19 +0300
+Subject: [PATCH 189/247] watchdog: sama5d4_wdt: add support for sama7g5-wdt
+
+Add support for compatible sama7g5-wdt.
+The sama7g5 wdt is the same hardware block as on sam9x60.
+Adapt the driver to use the sam9x60/sama7g5 variant if either
+of the two compatibles are selected (sam9x60-wdt/sama7g5-wdt).
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Acked-by: Nicolas Ferre <[email protected]>
+Reviewed-by: Guenter Roeck <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Guenter Roeck <[email protected]>
+Signed-off-by: Wim Van Sebroeck <[email protected]>
+---
+ drivers/watchdog/sama5d4_wdt.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/watchdog/sama5d4_wdt.c b/drivers/watchdog/sama5d4_wdt.c
+index e5d11d6a2600..ec20ad4e534f 100644
+--- a/drivers/watchdog/sama5d4_wdt.c
++++ b/drivers/watchdog/sama5d4_wdt.c
+@@ -268,8 +268,10 @@ static int sama5d4_wdt_probe(struct platform_device *pdev)
+ 	wdd->min_timeout = MIN_WDT_TIMEOUT;
+ 	wdd->max_timeout = MAX_WDT_TIMEOUT;
+ 	wdt->last_ping = jiffies;
+-	wdt->sam9x60_support = of_device_is_compatible(dev->of_node,
+-						       "microchip,sam9x60-wdt");
++
++	if (of_device_is_compatible(dev->of_node, "microchip,sam9x60-wdt") ||
++	    of_device_is_compatible(dev->of_node, "microchip,sama7g5-wdt"))
++		wdt->sam9x60_support = true;
+ 
+ 	watchdog_set_drvdata(wdd, wdt);
+ 
+@@ -329,6 +331,10 @@ static const struct of_device_id sama5d4_wdt_of_match[] = {
+ 	{
+ 		.compatible = "microchip,sam9x60-wdt",
+ 	},
++	{
++		.compatible = "microchip,sama7g5-wdt",
++	},
++
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, sama5d4_wdt_of_match);
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/190-media-atmel-fix-build-when-ISC-m-and-XISC-y.patch

@@ -0,0 +1,144 @@
+From dfcc0395f5e838c0b5c3fb93c9335b6a8892178a Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Mon, 5 Jul 2021 14:57:08 +0200
+Subject: [PATCH 190/247] media: atmel: fix build when ISC=m and XISC=y
+
+Building VIDEO_ATMEL_ISC as module and VIDEO_ATMEL_XISC as built-in
+(or viceversa) causes build errors:
+
+ or1k-linux-ld: drivers/media/platform/atmel/atmel-isc-base.o: in function `isc_async_complete':
+ atmel-isc-base.c:(.text+0x40d0): undefined reference to `__this_module'
+ or1k-linux-ld: atmel-isc-base.c:(.text+0x40f0): undefined reference to `__this_module'
+ or1k-linux-ld: drivers/media/platform/atmel/atmel-isc-base.o:(.rodata+0x390): undefined reference to `__this_module'
+ or1k-linux-ld: drivers/media/platform/atmel/atmel-isc-base.o:(__param+0x4): undefined reference to `__this_module'
+ or1k-linux-ld: drivers/media/platform/atmel/atmel-isc-base.o:(__param+0x18): undefined reference to `__this_module'
+
+This is caused by the file atmel-isc-base.c which is common code between
+the two drivers.
+
+The solution is to create another Kconfig symbol that is automatically
+selected and generates the module atmel-isc-base.ko. This module can be
+loaded when both drivers are modules, or built-in when at least one of them
+is built-in.
+
+Reported-by: kernel test robot <[email protected]>
+Fixes: c9aa973884a1 ("media: atmel: atmel-isc: add microchip-xisc driver")
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ drivers/media/platform/atmel/Kconfig          |  8 ++++++++
+ drivers/media/platform/atmel/Makefile         |  5 +++--
+ drivers/media/platform/atmel/atmel-isc-base.c | 11 +++++++++++
+ 3 files changed, 22 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/platform/atmel/Kconfig b/drivers/media/platform/atmel/Kconfig
+index 99b51213f871..dda2f27da317 100644
+--- a/drivers/media/platform/atmel/Kconfig
++++ b/drivers/media/platform/atmel/Kconfig
+@@ -8,6 +8,7 @@ config VIDEO_ATMEL_ISC
+ 	select VIDEOBUF2_DMA_CONTIG
+ 	select REGMAP_MMIO
+ 	select V4L2_FWNODE
++	select VIDEO_ATMEL_ISC_BASE
+ 	help
+ 	   This module makes the ATMEL Image Sensor Controller available
+ 	   as a v4l2 device.
+@@ -19,10 +20,17 @@ config VIDEO_ATMEL_XISC
+ 	select VIDEOBUF2_DMA_CONTIG
+ 	select REGMAP_MMIO
+ 	select V4L2_FWNODE
++	select VIDEO_ATMEL_ISC_BASE
+ 	help
+ 	   This module makes the ATMEL eXtended Image Sensor Controller
+ 	   available as a v4l2 device.
+ 
++config VIDEO_ATMEL_ISC_BASE
++	tristate
++	default n
++	help
++	  ATMEL ISC and XISC common code base.
++
+ config VIDEO_ATMEL_ISI
+ 	tristate "ATMEL Image Sensor Interface (ISI) support"
+ 	depends on VIDEO_V4L2 && OF
+diff --git a/drivers/media/platform/atmel/Makefile b/drivers/media/platform/atmel/Makefile
+index c5c01556c653..46d264ab7948 100644
+--- a/drivers/media/platform/atmel/Makefile
++++ b/drivers/media/platform/atmel/Makefile
+@@ -1,7 +1,8 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+-atmel-isc-objs = atmel-sama5d2-isc.o atmel-isc-base.o
+-atmel-xisc-objs = atmel-sama7g5-isc.o atmel-isc-base.o
++atmel-isc-objs = atmel-sama5d2-isc.o
++atmel-xisc-objs = atmel-sama7g5-isc.o
+ 
+ obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel-isi.o
++obj-$(CONFIG_VIDEO_ATMEL_ISC_BASE) += atmel-isc-base.o
+ obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel-isc.o
+ obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel-xisc.o
+diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
+index 46c6e3e20f33..54168b72fd2f 100644
+--- a/drivers/media/platform/atmel/atmel-isc-base.c
++++ b/drivers/media/platform/atmel/atmel-isc-base.c
+@@ -378,6 +378,7 @@ int isc_clk_init(struct isc_device *isc)
+ 
+ 	return 0;
+ }
++EXPORT_SYMBOL_GPL(isc_clk_init);
+ 
+ void isc_clk_cleanup(struct isc_device *isc)
+ {
+@@ -392,6 +393,7 @@ void isc_clk_cleanup(struct isc_device *isc)
+ 			clk_unregister(isc_clk->clk);
+ 	}
+ }
++EXPORT_SYMBOL_GPL(isc_clk_cleanup);
+ 
+ static int isc_queue_setup(struct vb2_queue *vq,
+ 			    unsigned int *nbuffers, unsigned int *nplanes,
+@@ -1575,6 +1577,7 @@ irqreturn_t isc_interrupt(int irq, void *dev_id)
+ 
+ 	return ret;
+ }
++EXPORT_SYMBOL_GPL(isc_interrupt);
+ 
+ static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max)
+ {
+@@ -2209,6 +2212,7 @@ const struct v4l2_async_notifier_operations isc_async_ops = {
+ 	.unbind = isc_async_unbind,
+ 	.complete = isc_async_complete,
+ };
++EXPORT_SYMBOL_GPL(isc_async_ops);
+ 
+ void isc_subdev_cleanup(struct isc_device *isc)
+ {
+@@ -2221,6 +2225,7 @@ void isc_subdev_cleanup(struct isc_device *isc)
+ 
+ 	INIT_LIST_HEAD(&isc->subdev_entities);
+ }
++EXPORT_SYMBOL_GPL(isc_subdev_cleanup);
+ 
+ int isc_pipeline_init(struct isc_device *isc)
+ {
+@@ -2261,6 +2266,7 @@ int isc_pipeline_init(struct isc_device *isc)
+ 
+ 	return 0;
+ }
++EXPORT_SYMBOL_GPL(isc_pipeline_init);
+ 
+ /* regmap configuration */
+ #define ATMEL_ISC_REG_MAX    0xd5c
+@@ -2270,4 +2276,9 @@ const struct regmap_config isc_regmap_config = {
+ 	.val_bits       = 32,
+ 	.max_register	= ATMEL_ISC_REG_MAX,
+ };
++EXPORT_SYMBOL_GPL(isc_regmap_config);
+ 
++MODULE_AUTHOR("Songjun Wu");
++MODULE_AUTHOR("Eugen Hristev");
++MODULE_DESCRIPTION("Atmel ISC common code base");
++MODULE_LICENSE("GPL v2");
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/191-i2c-at91-remove-define-CONFIG_PM.patch

@@ -0,0 +1,81 @@
+From 023a6b46536dce41f2c5a7425826fc4da4509b8f Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Mon, 5 Jul 2021 15:15:16 +0300
+Subject: [PATCH 191/247] i2c: at91: remove #define CONFIG_PM
+
+Remove #define CONFIG_PM and use __maybe_unused for PM functions and
+pm_ptr() for PM ops.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Reviewed-by: Codrin Ciubotariu <[email protected]>
+Signed-off-by: Wolfram Sang <[email protected]>
+---
+ drivers/i2c/busses/i2c-at91-core.c | 17 +++++------------
+ 1 file changed, 5 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-at91-core.c b/drivers/i2c/busses/i2c-at91-core.c
+index e14edd236108..9f3c3e8e8011 100644
+--- a/drivers/i2c/busses/i2c-at91-core.c
++++ b/drivers/i2c/busses/i2c-at91-core.c
+@@ -286,9 +286,7 @@ static int at91_twi_remove(struct platform_device *pdev)
+ 	return 0;
+ }
+ 
+-#ifdef CONFIG_PM
+-
+-static int at91_twi_runtime_suspend(struct device *dev)
++static int __maybe_unused at91_twi_runtime_suspend(struct device *dev)
+ {
+ 	struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
+ 
+@@ -299,7 +297,7 @@ static int at91_twi_runtime_suspend(struct device *dev)
+ 	return 0;
+ }
+ 
+-static int at91_twi_runtime_resume(struct device *dev)
++static int __maybe_unused at91_twi_runtime_resume(struct device *dev)
+ {
+ 	struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
+ 
+@@ -308,7 +306,7 @@ static int at91_twi_runtime_resume(struct device *dev)
+ 	return clk_prepare_enable(twi_dev->clk);
+ }
+ 
+-static int at91_twi_suspend_noirq(struct device *dev)
++static int __maybe_unused at91_twi_suspend_noirq(struct device *dev)
+ {
+ 	if (!pm_runtime_status_suspended(dev))
+ 		at91_twi_runtime_suspend(dev);
+@@ -316,7 +314,7 @@ static int at91_twi_suspend_noirq(struct device *dev)
+ 	return 0;
+ }
+ 
+-static int at91_twi_resume_noirq(struct device *dev)
++static int __maybe_unused at91_twi_resume_noirq(struct device *dev)
+ {
+ 	struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
+ 	int ret;
+@@ -342,11 +340,6 @@ static const struct dev_pm_ops at91_twi_pm = {
+ 	.runtime_resume		= at91_twi_runtime_resume,
+ };
+ 
+-#define at91_twi_pm_ops (&at91_twi_pm)
+-#else
+-#define at91_twi_pm_ops NULL
+-#endif
+-
+ static struct platform_driver at91_twi_driver = {
+ 	.probe		= at91_twi_probe,
+ 	.remove		= at91_twi_remove,
+@@ -354,7 +347,7 @@ static struct platform_driver at91_twi_driver = {
+ 	.driver		= {
+ 		.name	= "at91_i2c",
+ 		.of_match_table = of_match_ptr(atmel_twi_dt_ids),
+-		.pm	= at91_twi_pm_ops,
++		.pm	= pm_ptr(&at91_twi_pm),
+ 	},
+ };
+ 
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/192-ASoC-codecs-ad193x-add-support-for-96kHz-and-192kHz-.patch

@@ -0,0 +1,98 @@
+From 1c906a59a60887e1b997ebab63f19f33a1c69a3e Mon Sep 17 00:00:00 2001
+From: Codrin Ciubotariu <[email protected]>
+Date: Tue, 3 Aug 2021 13:48:25 +0300
+Subject: [PATCH 192/247] ASoC: codecs: ad193x: add support for 96kHz and
+ 192kHz playback rates
+
+ad193x devices support 96KHz and 192KHz sampling rates, when PLL/MCLK is
+referenced to 48kHz.
+Tested on ad1934.
+
+Signed-off-by: Codrin Ciubotariu <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Mark Brown <[email protected]>
+---
+ sound/soc/codecs/ad193x.c | 30 ++++++++++++++++++++++++++++--
+ sound/soc/codecs/ad193x.h |  4 ++++
+ 2 files changed, 32 insertions(+), 2 deletions(-)
+
+diff --git a/sound/soc/codecs/ad193x.c b/sound/soc/codecs/ad193x.c
+index f37ab7eda615..278a55af158b 100644
+--- a/sound/soc/codecs/ad193x.c
++++ b/sound/soc/codecs/ad193x.c
+@@ -316,6 +316,13 @@ static int ad193x_hw_params(struct snd_pcm_substream *substream,
+ 	int word_len = 0, master_rate = 0;
+ 	struct snd_soc_component *component = dai->component;
+ 	struct ad193x_priv *ad193x = snd_soc_component_get_drvdata(component);
++	bool is_playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
++	u8 dacc0;
++
++	dev_dbg(dai->dev, "%s() rate=%u format=%#x width=%u channels=%u\n",
++		__func__, params_rate(params), params_format(params),
++		params_width(params), params_channels(params));
++
+ 
+ 	/* bit size */
+ 	switch (params_width(params)) {
+@@ -346,6 +353,25 @@ static int ad193x_hw_params(struct snd_pcm_substream *substream,
+ 		break;
+ 	}
+ 
++	if (is_playback) {
++		switch (params_rate(params)) {
++		case 48000:
++			dacc0 = AD193X_DAC_SR_48;
++			break;
++		case 96000:
++			dacc0 = AD193X_DAC_SR_96;
++			break;
++		case 192000:
++			dacc0 = AD193X_DAC_SR_192;
++			break;
++		default:
++			dev_err(dai->dev, "invalid sampling rate: %d\n", params_rate(params));
++			return -EINVAL;
++		}
++
++		regmap_update_bits(ad193x->regmap, AD193X_DAC_CTRL0, AD193X_DAC_SR_MASK, dacc0);
++	}
++
+ 	regmap_update_bits(ad193x->regmap, AD193X_PLL_CLK_CTRL0,
+ 			    AD193X_PLL_INPUT_MASK, master_rate);
+ 
+@@ -385,7 +411,7 @@ static struct snd_soc_dai_driver ad193x_dai = {
+ 		.stream_name = "Playback",
+ 		.channels_min = 2,
+ 		.channels_max = 8,
+-		.rates = SNDRV_PCM_RATE_48000,
++		.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
+ 		.formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S16_LE |
+ 			SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE,
+ 	},
+@@ -407,7 +433,7 @@ static struct snd_soc_dai_driver ad193x_no_adc_dai = {
+ 		.stream_name = "Playback",
+ 		.channels_min = 2,
+ 		.channels_max = 8,
+-		.rates = SNDRV_PCM_RATE_48000,
++		.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
+ 		.formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S16_LE |
+ 			SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE,
+ 	},
+diff --git a/sound/soc/codecs/ad193x.h b/sound/soc/codecs/ad193x.h
+index 377854712c20..61f4648861d5 100644
+--- a/sound/soc/codecs/ad193x.h
++++ b/sound/soc/codecs/ad193x.h
+@@ -37,6 +37,10 @@ int ad193x_probe(struct device *dev, struct regmap *regmap,
+ #define AD193X_PLL_CLK_SRC_MCLK	(1 << 1)
+ #define AD193X_DAC_CTRL0        0x02
+ #define AD193X_DAC_POWERDOWN           0x01
++#define AD193X_DAC_SR_MASK           0x06
++#define AD193X_DAC_SR_48	(0 << 1)
++#define AD193X_DAC_SR_96	(1 << 1)
++#define AD193X_DAC_SR_192	(2 << 1)
+ #define AD193X_DAC_SERFMT_MASK		0xC0
+ #define AD193X_DAC_SERFMT_STEREO	(0 << 6)
+ #define AD193X_DAC_SERFMT_TDM		(1 << 6)
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/193-media-atmel-atmel-sama5d2-isc-fix-YUYV-format.patch

@@ -0,0 +1,53 @@
+From 21261e30679118b96ed537d1cdf9e12682fc1b29 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Wed, 9 Jun 2021 15:00:28 +0200
+Subject: [PATCH 193/247] media: atmel: atmel-sama5d2-isc: fix YUYV format
+
+SAMA5D2 does not have the YCYC field for the RLP (rounding, limiting,
+packaging) module.
+The YCYC field is supposed to work with interleaved YUV formats like YUYV.
+In SAMA5D2, we have to use YYCC field, which is used for both planar
+formats like YUV420 and interleaved formats like YUYV.
+Fix the according rlp callback to replace the generic YCYC field (which
+makes more sense from a logical point of view) with the required YYCC
+field.
+
+Fixes: debfa496871c ("media: atmel: atmel-isc-base: add support for more formats and additional pipeline modules")
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Hans Verkuil <[email protected]>
+Signed-off-by: Mauro Carvalho Chehab <[email protected]>
+---
+ .../media/platform/atmel/atmel-sama5d2-isc.c    | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+index d6fd22b127fd..4f09db71d152 100644
+--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
+@@ -255,6 +255,23 @@ static void isc_sama5d2_config_rlp(struct isc_device *isc)
+ 	struct regmap *regmap = isc->regmap;
+ 	u32 rlp_mode = isc->config.rlp_cfg_mode;
+ 
++	/*
++	 * In sama5d2, the YUV planar modes and the YUYV modes are treated
++	 * in the same way in RLP register.
++	 * Normally, YYCC mode should be Luma(n) - Color B(n) - Color R (n)
++	 * and YCYC should be Luma(n + 1) - Color B (n) - Luma (n) - Color R (n)
++	 * but in sama5d2, the YCYC mode does not exist, and YYCC must be
++	 * selected for both planar and interleaved modes, as in fact
++	 * both modes are supported.
++	 *
++	 * Thus, if the YCYC mode is selected, replace it with the
++	 * sama5d2-compliant mode which is YYCC .
++	 */
++	if ((rlp_mode & ISC_RLP_CFG_MODE_YCYC) == ISC_RLP_CFG_MODE_YCYC) {
++		rlp_mode &= ~ISC_RLP_CFG_MODE_MASK;
++		rlp_mode |= ISC_RLP_CFG_MODE_YYCC;
++	}
++
+ 	regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,
+ 			   ISC_RLP_CFG_MODE_MASK, rlp_mode);
+ }
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/194-clk-at91-add-register-definition-for-sama7g5-s-maste.patch

@@ -0,0 +1,56 @@
+From 602f85ff15d45bd313f8f6600d72202a50fd83a9 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Mon, 19 Jul 2021 11:03:17 +0300
+Subject: [PATCH 194/247] clk: at91: add register definition for sama7g5's
+ master clock
+
+Add register definitions for SAMA7G5's master clock. These would be
+also used by architecture specific power saving code.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Signed-off-by: Nicolas Ferre <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+---
+ include/linux/clk/at91_pmc.h | 26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
+index a4f82e836a7c..ccb3f034bfa9 100644
+--- a/include/linux/clk/at91_pmc.h
++++ b/include/linux/clk/at91_pmc.h
+@@ -137,6 +137,32 @@
+ #define			AT91_PMC_PLLADIV2_ON		(1 << 12)
+ #define		AT91_PMC_H32MXDIV	BIT(24)
+ 
++#define	AT91_PMC_MCR_V2		0x30				/* Master Clock Register [SAMA7G5 only] */
++#define		AT91_PMC_MCR_V2_ID_MSK	(0xF)
++#define			AT91_PMC_MCR_V2_ID(_id)		((_id) & AT91_PMC_MCR_V2_ID_MSK)
++#define		AT91_PMC_MCR_V2_CMD	(1 << 7)
++#define		AT91_PMC_MCR_V2_DIV	(7 << 8)
++#define			AT91_PMC_MCR_V2_DIV1		(0 << 8)
++#define			AT91_PMC_MCR_V2_DIV2		(1 << 8)
++#define			AT91_PMC_MCR_V2_DIV4		(2 << 8)
++#define			AT91_PMC_MCR_V2_DIV8		(3 << 8)
++#define			AT91_PMC_MCR_V2_DIV16		(4 << 8)
++#define			AT91_PMC_MCR_V2_DIV32		(5 << 8)
++#define			AT91_PMC_MCR_V2_DIV64		(6 << 8)
++#define			AT91_PMC_MCR_V2_DIV3		(7 << 8)
++#define		AT91_PMC_MCR_V2_CSS	(0x1F << 16)
++#define			AT91_PMC_MCR_V2_CSS_MD_SLCK	(0 << 16)
++#define			AT91_PMC_MCR_V2_CSS_TD_SLCK	(1 << 16)
++#define			AT91_PMC_MCR_V2_CSS_MAINCK	(2 << 16)
++#define			AT91_PMC_MCR_V2_CSS_MCK0	(3 << 16)
++#define			AT91_PMC_MCR_V2_CSS_SYSPLL	(5 << 16)
++#define			AT91_PMC_MCR_V2_CSS_DDRPLL	(6 << 16)
++#define			AT91_PMC_MCR_V2_CSS_IMGPLL	(7 << 16)
++#define			AT91_PMC_MCR_V2_CSS_BAUDPLL	(8 << 16)
++#define			AT91_PMC_MCR_V2_CSS_AUDIOPLL	(9 << 16)
++#define			AT91_PMC_MCR_V2_CSS_ETHPLL	(10 << 16)
++#define		AT91_PMC_MCR_V2_EN	(1 << 28)
++
+ #define AT91_PMC_XTALF		0x34			/* Main XTAL Frequency Register [SAMA7G5 only] */
+ 
+ #define	AT91_PMC_USB		0x38			/* USB Clock Register [some SAM9 only] */
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/195-ARM-at91-add-new-SoC-sama7g5.patch

@@ -0,0 +1,54 @@
+From 32bac6971d0572f67758f9a8c8af7bf4592f1675 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Fri, 9 Apr 2021 14:31:15 +0300
+Subject: [PATCH 195/247] ARM: at91: add new SoC sama7g5
+
+Add new SoC from at91 family : sama7g5
+
+Signed-off-by: Eugen Hristev <[email protected]>
+[[email protected]: Select PLL, generic clock and UTMI support, add PM configs]
+Signed-off-by: Claudiu Beznea <[email protected]>
+Signed-off-by: Nicolas Ferre <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Link: https://lore.kernel.org/r/[email protected]
+---
+ arch/arm/mach-at91/Kconfig | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
+index ccd7e80ce943..b09bb2279f7f 100644
+--- a/arch/arm/mach-at91/Kconfig
++++ b/arch/arm/mach-at91/Kconfig
+@@ -57,6 +57,16 @@ config SOC_SAMA5D4
+ 	help
+ 	  Select this if you are using one of Microchip's SAMA5D4 family SoC.
+ 
++config SOC_SAMA7G5
++	bool "SAMA7G5 family"
++	depends on ARCH_MULTI_V7
++	select HAVE_AT91_GENERATED_CLK
++	select HAVE_AT91_SAM9X60_PLL
++	select HAVE_AT91_UTMI
++	select SOC_SAMA7
++	help
++	  Select this if you are using one of Microchip's SAMA7G5 family SoC.
++
+ config SOC_AT91RM9200
+ 	bool "AT91RM9200"
+ 	depends on ARCH_MULTI_V4T
+@@ -191,4 +201,12 @@ config SOC_SAMA5
+ config ATMEL_PM
+ 	bool
+ 
++config SOC_SAMA7
++	bool
++	select ARM_GIC
++	select ATMEL_PM if PM
++	select ATMEL_SDRAMC
++	select MEMORY
++	select SOC_SAM_V7
++	select SRAM if PM
+ endif
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/196-ARM-at91-debug-add-sama7g5-low-level-debug-uart.patch

@@ -0,0 +1,55 @@
+From 3de4879bf59b46a966ea226a67df70b88f43a23e Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <[email protected]>
+Date: Fri, 9 Apr 2021 14:31:16 +0300
+Subject: [PATCH 196/247] ARM: at91: debug: add sama7g5 low level debug uart
+
+Add sama7g5 SoC debug uart on Flexcom3. This is the UART that the
+ROM bootloader uses.
+
+Signed-off-by: Eugen Hristev <[email protected]>
+Signed-off-by: Nicolas Ferre <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+[claudiu.beznea: adapt to v5.10.27]
+Signed-off-by: Claudiu Beznea <[email protected]>
+---
+ arch/arm/Kconfig.debug | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
+index dd1cf7035398..09901118e3fb 100644
+--- a/arch/arm/Kconfig.debug
++++ b/arch/arm/Kconfig.debug
+@@ -191,6 +191,14 @@ choice
+ 		  their output to the USART1 port on SAMV7 based
+ 		  machines.
+ 
++	config DEBUG_AT91_SAMA7G5_FLEXCOM3
++		bool "Kernel low-level debugging on SAMA7G5 FLEXCOM3"
++		select DEBUG_AT91_UART
++		depends on SOC_SAMA7G5
++		help
++		  Say Y here if you want kernel low-level debugging support
++		  on the FLEXCOM3 port of SAMA7G5.
++
+ 	config DEBUG_BCM2835
+ 		bool "Kernel low-level debugging on BCM2835 PL011 UART"
+ 		depends on ARCH_BCM2835 && ARCH_MULTI_V6
+@@ -1731,6 +1739,7 @@ config DEBUG_UART_PHYS
+ 	default 0xd4017000 if DEBUG_MMP_UART2
+ 	default 0xd4018000 if DEBUG_MMP_UART3
+ 	default 0xe0000000 if DEBUG_SPEAR13XX
++	default 0xe1824200 if DEBUG_AT91_SAMA7G5_FLEXCOM3
+ 	default 0xe4007000 if DEBUG_HIP04_UART
+ 	default 0xe6c40000 if DEBUG_RMOBILE_SCIFA0
+ 	default 0xe6c50000 if DEBUG_RMOBILE_SCIFA1
+@@ -1791,6 +1800,7 @@ config DEBUG_UART_VIRT
+ 	default 0xc8912000 if DEBUG_RV1108_UART0
+ 	default 0xe0010fe0 if ARCH_RPC
+ 	default 0xf0000be0 if ARCH_EBSA110
++	default 0xe0824200 if DEBUG_AT91_SAMA7G5_FLEXCOM3
+ 	default 0xf0010000 if DEBUG_ASM9260_UART
+ 	default 0xf0100000 if DEBUG_DIGICOLOR_UA0
+ 	default 0xf01fb000 if DEBUG_NOMADIK_UART
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/197-ARM-at91-pm-move-pm_bu-to-soc_pm-data-structure.patch

@@ -0,0 +1,92 @@
+From e41d00bdaa31b36fd314e927104082615aa4643a Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Thu, 15 Apr 2021 13:49:47 +0300
+Subject: [PATCH 197/247] ARM: at91: pm: move pm_bu to soc_pm data structure
+
+Move pm_bu to soc_pm data structure.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Signed-off-by: Nicolas Ferre <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+---
+ arch/arm/mach-at91/pm.c | 34 +++++++++++++++++++++-------------
+ 1 file changed, 21 insertions(+), 13 deletions(-)
+
+diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
+index 2dee383f9050..3fa223c21618 100644
+--- a/arch/arm/mach-at91/pm.c
++++ b/arch/arm/mach-at91/pm.c
+@@ -27,10 +27,25 @@
+ #include "generic.h"
+ #include "pm.h"
+ 
++/**
++ * struct at91_pm_bu - AT91 power management backup unit data structure
++ * @suspended: true if suspended to backup mode
++ * @reserved: reserved
++ * @canary: canary data for memory checking after exit from backup mode
++ * @resume: resume API
++ */
++struct at91_pm_bu {
++	int suspended;
++	unsigned long reserved;
++	phys_addr_t canary;
++	phys_addr_t resume;
++};
++
+ struct at91_soc_pm {
+ 	int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
+ 	int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
+ 	const struct of_device_id *ws_ids;
++	struct at91_pm_bu *bu;
+ 	struct at91_pm_data data;
+ };
+ 
+@@ -71,13 +86,6 @@ static int at91_pm_valid_state(suspend_state_t state)
+ 
+ static int canary = 0xA5A5A5A5;
+ 
+-static struct at91_pm_bu {
+-	int suspended;
+-	unsigned long reserved;
+-	phys_addr_t canary;
+-	phys_addr_t resume;
+-} *pm_bu;
+-
+ struct wakeup_source_info {
+ 	unsigned int pmc_fsmr_bit;
+ 	unsigned int shdwc_mr_bit;
+@@ -288,7 +296,7 @@ static int at91_suspend_finish(unsigned long val)
+ static void at91_pm_suspend(suspend_state_t state)
+ {
+ 	if (soc_pm.data.mode == AT91_PM_BACKUP) {
+-		pm_bu->suspended = 1;
++		soc_pm.bu->suspended = 1;
+ 
+ 		cpu_suspend(0, at91_suspend_finish);
+ 
+@@ -672,16 +680,16 @@ static int __init at91_pm_backup_init(void)
+ 		goto securam_fail;
+ 	}
+ 
+-	pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
+-	if (!pm_bu) {
++	soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
++	if (!soc_pm.bu) {
+ 		pr_warn("%s: unable to alloc securam!\n", __func__);
+ 		ret = -ENOMEM;
+ 		goto securam_fail;
+ 	}
+ 
+-	pm_bu->suspended = 0;
+-	pm_bu->canary = __pa_symbol(&canary);
+-	pm_bu->resume = __pa_symbol(cpu_resume);
++	soc_pm.bu->suspended = 0;
++	soc_pm.bu->canary = __pa_symbol(&canary);
++	soc_pm.bu->resume = __pa_symbol(cpu_resume);
+ 
+ 	return 0;
+ 
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/198-ARM-at91-pm-move-the-setup-of-soc_pm.bu-suspended.patch

@@ -0,0 +1,60 @@
+From c8f2a8aaae41fa0a40ad88855ae82696098230d7 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Thu, 15 Apr 2021 13:49:48 +0300
+Subject: [PATCH 198/247] ARM: at91: pm: move the setup of soc_pm.bu->suspended
+
+Move the setup of soc_pm.bu->suspended in platform_suspend::begin
+function so that the PMC code in charge with clocks suspend/resume
+to differentiate b/w standard PM mode and backup mode.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Reviewed-by: Alexandre Belloni <[email protected]>
+Signed-off-by: Nicolas Ferre <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+---
+ arch/arm/mach-at91/pm.c | 15 ++++++++++++---
+ 1 file changed, 12 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
+index 3fa223c21618..f182d8bf6f82 100644
+--- a/arch/arm/mach-at91/pm.c
++++ b/arch/arm/mach-at91/pm.c
+@@ -214,6 +214,8 @@ static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
+  */
+ static int at91_pm_begin(suspend_state_t state)
+ {
++	int ret;
++
+ 	switch (state) {
+ 	case PM_SUSPEND_MEM:
+ 		soc_pm.data.mode = soc_pm.data.suspend_mode;
+@@ -227,7 +229,16 @@ static int at91_pm_begin(suspend_state_t state)
+ 		soc_pm.data.mode = -1;
+ 	}
+ 
+-	return at91_pm_config_ws(soc_pm.data.mode, true);
++	ret = at91_pm_config_ws(soc_pm.data.mode, true);
++	if (ret)
++		return ret;
++
++	if (soc_pm.data.mode == AT91_PM_BACKUP)
++		soc_pm.bu->suspended = 1;
++	else if (soc_pm.bu)
++		soc_pm.bu->suspended = 0;
++
++	return 0;
+ }
+ 
+ /*
+@@ -296,8 +307,6 @@ static int at91_suspend_finish(unsigned long val)
+ static void at91_pm_suspend(suspend_state_t state)
+ {
+ 	if (soc_pm.data.mode == AT91_PM_BACKUP) {
+-		soc_pm.bu->suspended = 1;
+-
+ 		cpu_suspend(0, at91_suspend_finish);
+ 
+ 		/* The SRAM is lost between suspend cycles */
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/199-ARM-at91-pm-document-at91_soc_pm-structure.patch

@@ -0,0 +1,36 @@
+From 59a4b3b9381b727f416d9cc52e60d0bc7d93ecae Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Thu, 15 Apr 2021 13:49:49 +0300
+Subject: [PATCH 199/247] ARM: at91: pm: document at91_soc_pm structure
+
+Document at91_soc_pm structure.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Signed-off-by: Nicolas Ferre <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+---
+ arch/arm/mach-at91/pm.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
+index f182d8bf6f82..a060bec77f20 100644
+--- a/arch/arm/mach-at91/pm.c
++++ b/arch/arm/mach-at91/pm.c
+@@ -41,6 +41,14 @@ struct at91_pm_bu {
+ 	phys_addr_t resume;
+ };
+ 
++/**
++ * struct at91_soc_pm - AT91 SoC power management data structure
++ * @config_shdwc_ws: wakeup sources configuration function for SHDWC
++ * @config_pmc_ws: wakeup srouces configuration function for PMC
++ * @ws_ids: wakup sources of_device_id array
++ * @data: PM data to be used on last phase of suspend
++ * @bu: backup unit mapped data (for backup mode)
++ */
+ struct at91_soc_pm {
+ 	int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
+ 	int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
+-- 
+2.32.0
+

target/linux/at91/patches-5.10/200-ARM-at91-pm-check-for-different-controllers-in-at91_.patch

@@ -0,0 +1,243 @@
+From 0c4cbd38a705bdeab11de4c84ad0ce8c3de8a81d Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <[email protected]>
+Date: Thu, 15 Apr 2021 13:49:50 +0300
+Subject: [PATCH 200/247] ARM: at91: pm: check for different controllers in
+ at91_pm_modes_init()
+
+at91_pm_modes_init() checks for proper nodes in device tree and maps
+them accordingly. Up to SAMA7G5 all AT91 SoCs had the same mapping
+b/w power saving modes and different controllers needed in the
+final/first steps of suspend/resume. SAMA7G5 is not aligned with the
+old SoCs thus the code is adapted for this. This patch prepares
+the field for next commits.
+
+Signed-off-by: Claudiu Beznea <[email protected]>
+Signed-off-by: Nicolas Ferre <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+---
+ arch/arm/mach-at91/pm.c | 143 +++++++++++++++++++++++++---------------
+ 1 file changed, 91 insertions(+), 52 deletions(-)
+
+diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
+index a060bec77f20..e9f9fb410761 100644
+--- a/arch/arm/mach-at91/pm.c
++++ b/arch/arm/mach-at91/pm.c
+@@ -57,6 +57,18 @@ struct at91_soc_pm {
+ 	struct at91_pm_data data;
+ };
+ 
++/**
++ * enum at91_pm_iomaps:	IOs that needs to be mapped for different PM modes
++ * @AT91_PM_IOMAP_SHDWC:	SHDWC controller
++ * @AT91_PM_IOMAP_SFRBU:	SFRBU controller
++ */
++enum at91_pm_iomaps {
++	AT91_PM_IOMAP_SHDWC,
++	AT91_PM_IOMAP_SFRBU,
++};
++
++#define AT91_PM_IOMAP(name)	BIT(AT91_PM_IOMAP_##name)
++
+ static struct at91_soc_pm soc_pm = {
+ 	.data = {
+ 		.standby_mode = AT91_PM_STANDBY,
+@@ -671,24 +683,15 @@ static int __init at91_pm_backup_init(void)
+ 	if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
+ 		return 0;
+ 
+-	np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
+-	if (!np) {
+-		pr_warn("%s: failed to find sfrbu!\n", __func__);
+-		return ret;
+-	}
+-
+-	soc_pm.data.sfrbu = of_iomap(np, 0);
+-	of_node_put(np);
+-
+ 	np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
+ 	if (!np)
+-		goto securam_fail_no_ref_dev;
++		return ret;
+ 
+ 	pdev = of_find_device_by_node(np);
+ 	of_node_put(np);
+ 	if (!pdev) {
+ 		pr_warn("%s: failed to find securam device!\n", __func__);
+-		goto securam_fail_no_ref_dev;
++		return ret;
+ 	}
+ 
+ 	sram_pool = gen_pool_get(&pdev->dev, NULL);
+@@ -712,64 +715,92 @@ static int __init at91_pm_backup_init(void)
+ 
+ securam_fail:
+ 	put_device(&pdev->dev);
+-securam_fail_no_ref_dev:
+-	iounmap(soc_pm.data.sfrbu);
+-	soc_pm.data.sfrbu = NULL;
+ 	return ret;
+ }
+ 
+-static void __init at91_pm_use_default_mode(int pm_mode)
+-{
+-	if (pm_mode != AT91_PM_ULP1 && pm_mode != AT91_PM_BACKUP)
+-		return;
+-
+-	if (soc_pm.data.standby_mode == pm_mode)
+-		soc_pm.data.standby_mode = AT91_PM_ULP0;
+-	if (soc_pm.data.suspend_mode == pm_mode)
+-		soc_pm.data.suspend_mode = AT91_PM_ULP0;
+-}
+-
+ static const struct of_device_id atmel_shdwc_ids[] = {
+ 	{ .compatible = "atmel,sama5d2-shdwc" },
+ 	{ .compatible = "microchip,sam9x60-shdwc" },
+ 	{ /* sentinel. */ }
+ };
+ 
+-static void __init at91_pm_modes_init(void)
++static void __init at91_pm_modes_init(const u32 *maps, int len)
+ {
+ 	struct device_node *np;
+-	int ret;
++	int ret, mode;
+ 
+-	if (!at91_is_pm_mode_active(AT91_PM_BACKUP) &&
+-	    !at91_is_pm_mode_active(AT91_PM_ULP1))
+-		return;
++	ret = at91_pm_backup_init();
++	if (ret) {
++		if (soc_pm.data.standby_mode == AT91_PM_BACKUP)
++			soc_pm.data.standby_mode = AT91_PM_ULP0;
++		if (soc_pm.data.suspend_mode == AT91_PM_BACKUP)
++			soc_pm.data.suspend_mode = AT91_PM_ULP0;
++	}
+ 
+-	np = of_find_matching_node(NULL, atmel_shdwc_ids);
+-	if (!np) {
+-		pr_warn("%s: failed to find shdwc!\n", __func__);
+-		goto ulp1_default;
++	if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
++	    maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) {
++		np = of_find_matching_node(NULL, atmel_shdwc_ids);
++		if (!np) {
++			pr_warn("%s: failed to find shdwc!\n", __func__);
++
++			/* Use ULP0 if it doesn't needs SHDWC.*/
++			if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)))
++				mode = AT91_PM_ULP0;
++			else
++				mode = AT91_PM_STANDBY;
++
++			if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC))
++				soc_pm.data.standby_mode = mode;
++			if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))
++				soc_pm.data.suspend_mode = mode;
++		} else {
++			soc_pm.data.shdwc = of_iomap(np, 0);
++			of_node_put(np);
++		}
+ 	}
+ 
+-	soc_pm.data.shdwc = of_iomap(np, 0);
+-	of_node_put(np);
++	if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
++	    maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) {
++		np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
++		if (!np) {
++			pr_warn("%s: failed to find sfrbu!\n", __func__);
++
++			/*
++			 * Use ULP0 if it doesn't need SHDWC or if SHDWC
++			 * was already located.
++			 */
++			if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)) ||
++			    soc_pm.data.shdwc)
++				mode = AT91_PM_ULP0;
++			else
++				mode = AT91_PM_STANDBY;
++
++			if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU))
++				soc_pm.data.standby_mode = mode;
++			if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))
++				soc_pm.data.suspend_mode = mode;
++		} else {
++			soc_pm.data.sfrbu = of_iomap(np, 0);
++			of_node_put(np);
++		}
++	}
+ 
+-	ret = at91_pm_backup_init();
+-	if (ret) {
+-		if (!at91_is_pm_mode_active(AT91_PM_ULP1))
+-			goto unmap;
+-		else
+-			goto backup_default;
++	/* Unmap all unnecessary. */
++	if (soc_pm.data.shdwc &&
++	    !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
++	      maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) {
++		iounmap(soc_pm.data.shdwc);
++		soc_pm.data.shdwc = NULL;
+ 	}
+ 
+-	return;
++	if (soc_pm.data.sfrbu &&
++	    !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
++	      maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) {
++		iounmap(soc_pm.data.sfrbu);
++		soc_pm.data.sfrbu = NULL;
++	}
+ 
+-unmap:
+-	iounmap(soc_pm.data.shdwc);
+-	soc_pm.data.shdwc = NULL;
+-ulp1_default:
+-	at91_pm_use_default_mode(AT91_PM_ULP1);
+-backup_default:
+-	at91_pm_use_default_mode(AT91_PM_BACKUP);
++	return;
+ }
+ 
+ struct pmc_info {
+@@ -936,13 +967,16 @@ void __init sam9x60_pm_init(void)
+ 	static const int modes[] __initconst = {
+ 		AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
+ 	};
++	static const int iomaps[] __initconst = {
++		[AT91_PM_ULP1]		= AT91_PM_IOMAP(SHDWC),
++	};
+ 	int ret;
+ 
+ 	if (!IS_ENABLED(CONFIG_SOC_SAM9X60))
+ 		return;
+ 
+ 	at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
+-	at91_pm_modes_init();
++	at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
+ 	ret = at91_dt_ramc();
+ 	if (ret)
+ 		return;
+@@ -999,13 +1033,18 @@ void __init sama5d2_pm_init(void)
+ 		AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
+ 		AT91_PM_BACKUP,
+ 	};
++	static const u32 iomaps[] __initconst = {
++		[AT91_PM_ULP1]		= AT91_PM_IOMAP(SHDWC),
++		[AT91_PM_BACKUP]	= AT91_PM_IOMAP(SHDWC) |
++					  AT91_PM_IOMAP(SFRBU),
++	};
+ 	int ret;
+ 
+ 	if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
+ 		return;
+ 
+ 	at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
+-	at91_pm_modes_init();
++	at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
+ 	ret = at91_dt_ramc();
+ 	if (ret)
+ 		return;
+-- 
+2.32.0
+